1 /* $Id: hfc_2bds0.c,v 1.18.2.6 2004/02/11 13:21:33 keil Exp $
3 * specific routines for CCD's HFC 2BDS0
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
13 #include <linux/init.h>
14 #include <linux/sched.h>
16 #include "hfc_2bds0.h"
18 #include <linux/interrupt.h>
24 #define byteout(addr,val) outb(val,addr)
25 #define bytein(addr) inb(addr)
28 dummyf(struct IsdnCardState *cs, u_char * data, int size)
30 printk(KERN_WARNING "HiSax: hfcd dummy fifo called\n");
34 ReadReg(struct IsdnCardState *cs, int data, u_char reg)
39 if (cs->hw.hfcD.cip != reg) {
40 cs->hw.hfcD.cip = reg;
41 byteout(cs->hw.hfcD.addr | 1, reg);
43 ret = bytein(cs->hw.hfcD.addr);
45 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2))
46 debugl1(cs, "t3c RD %02x %02x", reg, ret);
49 ret = bytein(cs->hw.hfcD.addr | 1);
54 WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value)
56 if (cs->hw.hfcD.cip != reg) {
57 cs->hw.hfcD.cip = reg;
58 byteout(cs->hw.hfcD.addr | 1, reg);
61 byteout(cs->hw.hfcD.addr, value);
63 if (cs->debug & L1_DEB_HSCX_FIFO && (data != HFCD_DATA_NODEB))
64 debugl1(cs, "t3c W%c %02x %02x", data ? 'D' : 'C', reg, value);
68 /* Interface functions */
71 readreghfcd(struct IsdnCardState *cs, u_char offset)
73 return(ReadReg(cs, HFCD_DATA, offset));
77 writereghfcd(struct IsdnCardState *cs, u_char offset, u_char value)
79 WriteReg(cs, HFCD_DATA, offset, value);
83 WaitForBusy(struct IsdnCardState *cs)
87 while (!(ReadReg(cs, HFCD_DATA, HFCD_STAT) & HFCD_BUSY) && to) {
92 printk(KERN_WARNING "HiSax: WaitForBusy timeout\n");
97 WaitNoBusy(struct IsdnCardState *cs)
101 while ((ReadReg(cs, HFCD_STATUS, HFCD_STATUS) & HFCD_BUSY) && to) {
106 printk(KERN_WARNING "HiSax: WaitNoBusy timeout\n");
111 SelFiFo(struct IsdnCardState *cs, u_char FiFo)
115 if (cs->hw.hfcD.fifo == FiFo)
118 case 0: cip = HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_B1;
120 case 1: cip = HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_B1;
122 case 2: cip = HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_B2;
124 case 3: cip = HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_B2;
126 case 4: cip = HFCD_FIFO | HFCD_Z1 | HFCD_SEND;
128 case 5: cip = HFCD_FIFO | HFCD_Z1 | HFCD_REC;
131 debugl1(cs, "SelFiFo Error");
134 cs->hw.hfcD.fifo = FiFo;
136 cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0);
142 GetFreeFifoBytes_B(struct BCState *bcs)
146 if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
147 return (bcs->cs->hw.hfcD.bfifosize);
148 s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
150 s += bcs->cs->hw.hfcD.bfifosize;
151 s = bcs->cs->hw.hfcD.bfifosize - s;
156 GetFreeFifoBytes_D(struct IsdnCardState *cs)
160 if (cs->hw.hfcD.f1 == cs->hw.hfcD.f2)
161 return (cs->hw.hfcD.dfifosize);
162 s = cs->hw.hfcD.send[cs->hw.hfcD.f1] - cs->hw.hfcD.send[cs->hw.hfcD.f2];
164 s += cs->hw.hfcD.dfifosize;
165 s = cs->hw.hfcD.dfifosize - s;
170 ReadZReg(struct IsdnCardState *cs, u_char reg)
175 val = 256 * ReadReg(cs, HFCD_DATA, reg | HFCB_Z_HIGH);
177 val += ReadReg(cs, HFCD_DATA, reg | HFCB_Z_LOW);
181 static struct sk_buff
182 *hfc_empty_fifo(struct BCState *bcs, int count)
186 struct IsdnCardState *cs = bcs->cs;
191 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
192 debugl1(cs, "hfc_empty_fifo");
194 if (count > HSCX_BUFMAX + 3) {
195 if (cs->debug & L1_DEB_WARN)
196 debugl1(cs, "hfc_empty_fifo: incoming packet too large");
197 cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
198 while (idx++ < count) {
200 ReadReg(cs, HFCD_DATA_NODEB, cip);
203 } else if (count < 4) {
204 if (cs->debug & L1_DEB_WARN)
205 debugl1(cs, "hfc_empty_fifo: incoming packet too small");
206 cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
207 #ifdef ERROR_STATISTIC
210 while ((idx++ < count) && WaitNoBusy(cs))
211 ReadReg(cs, HFCD_DATA_NODEB, cip);
213 } else if (!(skb = dev_alloc_skb(count - 3)))
214 printk(KERN_WARNING "HFC: receive out of memory\n");
216 ptr = skb_put(skb, count - 3);
218 cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
219 while (idx < (count - 3)) {
222 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip);
226 if (idx != count - 3) {
227 debugl1(cs, "RFIFO BUSY error");
228 printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
229 dev_kfree_skb_irq(skb);
233 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);
235 chksum += ReadReg(cs, HFCD_DATA, cip);
237 stat = ReadReg(cs, HFCD_DATA, cip);
238 if (cs->debug & L1_DEB_HSCX)
239 debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x",
240 bcs->channel, chksum, stat);
242 debugl1(cs, "FIFO CRC error");
243 dev_kfree_skb_irq(skb);
245 #ifdef ERROR_STATISTIC
253 stat = ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F2_INC |
254 HFCB_REC | HFCB_CHANNEL(bcs->channel));
260 hfc_fill_fifo(struct BCState *bcs)
262 struct IsdnCardState *cs = bcs->cs;
269 if (bcs->tx_skb->len <= 0)
271 SelFiFo(cs, HFCB_SEND | HFCB_CHANNEL(bcs->channel));
272 cip = HFCB_FIFO | HFCB_F1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
274 bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip);
276 cip = HFCB_FIFO | HFCB_F2 | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
278 bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip);
279 bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
280 if (cs->debug & L1_DEB_HSCX)
281 debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
282 bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
283 bcs->hw.hfc.send[bcs->hw.hfc.f1]);
284 fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
288 if (cs->debug & L1_DEB_HSCX)
289 debugl1(cs, "hfc_fill_fifo more as 30 frames");
292 count = GetFreeFifoBytes_B(bcs);
293 if (cs->debug & L1_DEB_HSCX)
294 debugl1(cs, "hfc_fill_fifo %d count(%ld/%d),%lx",
295 bcs->channel, bcs->tx_skb->len,
296 count, current->state);
297 if (count < bcs->tx_skb->len) {
298 if (cs->debug & L1_DEB_HSCX)
299 debugl1(cs, "hfc_fill_fifo no fifo mem");
302 cip = HFCB_FIFO | HFCB_FIFO_IN | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
306 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
307 while (idx < bcs->tx_skb->len) {
310 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx]);
313 if (idx != bcs->tx_skb->len) {
314 debugl1(cs, "FIFO Send BUSY error");
315 printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
317 bcs->tx_cnt -= bcs->tx_skb->len;
318 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
319 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
321 spin_lock_irqsave(&bcs->aclock, flags);
322 bcs->ackcnt += bcs->tx_skb->len;
323 spin_unlock_irqrestore(&bcs->aclock, flags);
324 schedule_event(bcs, B_ACKPENDING);
326 dev_kfree_skb_any(bcs->tx_skb);
331 ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
333 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
338 hfc_send_data(struct BCState *bcs)
340 struct IsdnCardState *cs = bcs->cs;
342 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
344 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
346 debugl1(cs,"send_data %d blocked", bcs->channel);
350 main_rec_2bds0(struct BCState *bcs)
352 struct IsdnCardState *cs = bcs->cs;
355 int receive, count = 5;
360 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
361 debugl1(cs,"rec_data %d blocked", bcs->channel);
364 SelFiFo(cs, HFCB_REC | HFCB_CHANNEL(bcs->channel));
365 cip = HFCB_FIFO | HFCB_F1 | HFCB_REC | HFCB_CHANNEL(bcs->channel);
367 f1 = ReadReg(cs, HFCD_DATA, cip);
368 cip = HFCB_FIFO | HFCB_F2 | HFCB_REC | HFCB_CHANNEL(bcs->channel);
370 f2 = ReadReg(cs, HFCD_DATA, cip);
372 if (cs->debug & L1_DEB_HSCX)
373 debugl1(cs, "hfc rec %d f1(%d) f2(%d)",
374 bcs->channel, f1, f2);
375 z1 = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
376 z2 = ReadZReg(cs, HFCB_FIFO | HFCB_Z2 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
379 rcnt += cs->hw.hfcD.bfifosize;
381 if (cs->debug & L1_DEB_HSCX)
382 debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
383 bcs->channel, z1, z2, rcnt);
384 if ((skb = hfc_empty_fifo(bcs, rcnt))) {
385 skb_queue_tail(&bcs->rqueue, skb);
386 schedule_event(bcs, B_RCVBUFREADY);
397 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
398 if (count && receive)
404 mode_2bs0(struct BCState *bcs, int mode, int bc)
406 struct IsdnCardState *cs = bcs->cs;
408 if (cs->debug & L1_DEB_HSCX)
409 debugl1(cs, "HFCD bchannel mode %d bchan %d/%d",
410 mode, bc, bcs->channel);
416 cs->hw.hfcD.conn |= 0x18;
417 cs->hw.hfcD.sctrl &= ~SCTRL_B2_ENA;
419 cs->hw.hfcD.conn |= 0x3;
420 cs->hw.hfcD.sctrl &= ~SCTRL_B1_ENA;
423 case (L1_MODE_TRANS):
425 cs->hw.hfcD.ctmt |= 2;
426 cs->hw.hfcD.conn &= ~0x18;
427 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA;
429 cs->hw.hfcD.ctmt |= 1;
430 cs->hw.hfcD.conn &= ~0x3;
431 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA;
436 cs->hw.hfcD.ctmt &= ~2;
437 cs->hw.hfcD.conn &= ~0x18;
438 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA;
440 cs->hw.hfcD.ctmt &= ~1;
441 cs->hw.hfcD.conn &= ~0x3;
442 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA;
446 WriteReg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl);
447 WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);
448 WriteReg(cs, HFCD_DATA, HFCD_CONN, cs->hw.hfcD.conn);
452 hfc_l2l1(struct PStack *st, int pr, void *arg)
454 struct BCState *bcs = st->l1.bcs;
455 struct sk_buff *skb = arg;
459 case (PH_DATA | REQUEST):
460 spin_lock_irqsave(&bcs->cs->lock, flags);
462 skb_queue_tail(&bcs->squeue, skb);
465 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
466 bcs->cs->BC_Send_Data(bcs);
468 spin_unlock_irqrestore(&bcs->cs->lock, flags);
470 case (PH_PULL | INDICATION):
471 spin_lock_irqsave(&bcs->cs->lock, flags);
473 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
475 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
477 bcs->cs->BC_Send_Data(bcs);
479 spin_unlock_irqrestore(&bcs->cs->lock, flags);
481 case (PH_PULL | REQUEST):
483 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
484 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
486 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
488 case (PH_ACTIVATE | REQUEST):
489 spin_lock_irqsave(&bcs->cs->lock, flags);
490 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
491 mode_2bs0(bcs, st->l1.mode, st->l1.bc);
492 spin_unlock_irqrestore(&bcs->cs->lock, flags);
493 l1_msg_b(st, pr, arg);
495 case (PH_DEACTIVATE | REQUEST):
496 l1_msg_b(st, pr, arg);
498 case (PH_DEACTIVATE | CONFIRM):
499 spin_lock_irqsave(&bcs->cs->lock, flags);
500 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
501 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
502 mode_2bs0(bcs, 0, st->l1.bc);
503 spin_unlock_irqrestore(&bcs->cs->lock, flags);
504 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
510 close_2bs0(struct BCState *bcs)
512 mode_2bs0(bcs, 0, bcs->channel);
513 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
514 skb_queue_purge(&bcs->rqueue);
515 skb_queue_purge(&bcs->squeue);
517 dev_kfree_skb_any(bcs->tx_skb);
519 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
525 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
527 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
528 skb_queue_head_init(&bcs->rqueue);
529 skb_queue_head_init(&bcs->squeue);
532 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
539 setstack_2b(struct PStack *st, struct BCState *bcs)
541 bcs->channel = st->l1.bc;
542 if (open_hfcstate(st->l1.hardware, bcs))
545 st->l2.l2l1 = hfc_l2l1;
546 setstack_manager(st);
553 hfcd_bh(struct work_struct *work)
555 struct IsdnCardState *cs =
556 container_of(work, struct IsdnCardState, tqueue);
558 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
559 switch (cs->dc.hfcd.ph_state) {
561 l1_msg(cs, HW_RESET | INDICATION, NULL);
564 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
567 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
570 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
573 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
579 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
580 DChannel_proc_rcv(cs);
581 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
582 DChannel_proc_xmt(cs);
586 int receive_dmsg(struct IsdnCardState *cs)
591 u_char stat, cip, f1, f2;
596 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
597 debugl1(cs, "rec_dmsg blocked");
600 SelFiFo(cs, 4 | HFCD_REC);
601 cip = HFCD_FIFO | HFCD_F1 | HFCD_REC;
603 f1 = cs->readisac(cs, cip) & 0xf;
604 cip = HFCD_FIFO | HFCD_F2 | HFCD_REC;
606 f2 = cs->readisac(cs, cip) & 0xf;
607 while ((f1 != f2) && count--) {
608 z1 = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_REC);
609 z2 = ReadZReg(cs, HFCD_FIFO | HFCD_Z2 | HFCD_REC);
612 rcnt += cs->hw.hfcD.dfifosize;
614 if (cs->debug & L1_DEB_ISAC)
615 debugl1(cs, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
616 f1, f2, z1, z2, rcnt);
618 cip = HFCD_FIFO | HFCD_FIFO_OUT | HFCD_REC;
619 if (rcnt > MAX_DFRAME_LEN + 3) {
620 if (cs->debug & L1_DEB_WARN)
621 debugl1(cs, "empty_fifo d: incoming packet too large");
623 if (!(WaitNoBusy(cs)))
625 ReadReg(cs, HFCD_DATA_NODEB, cip);
628 } else if (rcnt < 4) {
629 if (cs->debug & L1_DEB_WARN)
630 debugl1(cs, "empty_fifo d: incoming packet too small");
631 while ((idx++ < rcnt) && WaitNoBusy(cs))
632 ReadReg(cs, HFCD_DATA_NODEB, cip);
633 } else if ((skb = dev_alloc_skb(rcnt - 3))) {
634 ptr = skb_put(skb, rcnt - 3);
635 while (idx < (rcnt - 3)) {
636 if (!(WaitNoBusy(cs)))
638 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip);
642 if (idx != (rcnt - 3)) {
643 debugl1(cs, "RFIFO D BUSY error");
644 printk(KERN_WARNING "HFC DFIFO channel BUSY Error\n");
645 dev_kfree_skb_irq(skb);
647 #ifdef ERROR_STATISTIC
652 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);
654 chksum += ReadReg(cs, HFCD_DATA, cip);
656 stat = ReadReg(cs, HFCD_DATA, cip);
657 if (cs->debug & L1_DEB_ISAC)
658 debugl1(cs, "empty_dfifo chksum %x stat %x",
661 debugl1(cs, "FIFO CRC error");
662 dev_kfree_skb_irq(skb);
664 #ifdef ERROR_STATISTIC
668 skb_queue_tail(&cs->rq, skb);
669 schedule_event(cs, D_RCVBUFREADY);
673 printk(KERN_WARNING "HFC: D receive out of memory\n");
675 cip = HFCD_FIFO | HFCD_F2_INC | HFCD_REC;
677 stat = ReadReg(cs, HFCD_DATA, cip);
679 cip = HFCD_FIFO | HFCD_F2 | HFCD_REC;
681 f2 = cs->readisac(cs, cip) & 0xf;
683 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
688 hfc_fill_dfifo(struct IsdnCardState *cs)
696 if (cs->tx_skb->len <= 0)
699 SelFiFo(cs, 4 | HFCD_SEND);
700 cip = HFCD_FIFO | HFCD_F1 | HFCD_SEND;
702 cs->hw.hfcD.f1 = ReadReg(cs, HFCD_DATA, cip) & 0xf;
704 cip = HFCD_FIFO | HFCD_F2 | HFCD_SEND;
705 cs->hw.hfcD.f2 = ReadReg(cs, HFCD_DATA, cip) & 0xf;
706 cs->hw.hfcD.send[cs->hw.hfcD.f1] = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_SEND);
707 if (cs->debug & L1_DEB_ISAC)
708 debugl1(cs, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)",
709 cs->hw.hfcD.f1, cs->hw.hfcD.f2,
710 cs->hw.hfcD.send[cs->hw.hfcD.f1]);
711 fcnt = cs->hw.hfcD.f1 - cs->hw.hfcD.f2;
715 if (cs->debug & L1_DEB_HSCX)
716 debugl1(cs, "hfc_fill_Dfifo more as 14 frames");
719 count = GetFreeFifoBytes_D(cs);
720 if (cs->debug & L1_DEB_ISAC)
721 debugl1(cs, "hfc_fill_Dfifo count(%ld/%d)",
722 cs->tx_skb->len, count);
723 if (count < cs->tx_skb->len) {
724 if (cs->debug & L1_DEB_ISAC)
725 debugl1(cs, "hfc_fill_Dfifo no fifo mem");
728 cip = HFCD_FIFO | HFCD_FIFO_IN | HFCD_SEND;
732 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx++]);
733 while (idx < cs->tx_skb->len) {
734 if (!(WaitNoBusy(cs)))
736 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx]);
739 if (idx != cs->tx_skb->len) {
740 debugl1(cs, "DFIFO Send BUSY error");
741 printk(KERN_WARNING "HFC S DFIFO channel BUSY Error\n");
745 ReadReg(cs, HFCD_DATA, HFCD_FIFO | HFCD_F1_INC | HFCD_SEND);
746 dev_kfree_skb_any(cs->tx_skb);
753 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
755 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
757 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
764 hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val)
770 if (cs->debug & L1_DEB_ISAC)
771 debugl1(cs, "HFCD irq %x %s", val,
772 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
773 "locked" : "unlocked");
774 val &= cs->hw.hfcD.int_m1;
775 if (val & 0x40) { /* TE state machine irq */
776 exval = cs->readisac(cs, HFCD_STATES) & 0xf;
777 if (cs->debug & L1_DEB_ISAC)
778 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcd.ph_state,
780 cs->dc.hfcd.ph_state = exval;
781 schedule_event(cs, D_L1STATECHANGE);
785 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
786 cs->hw.hfcD.int_s1 |= val;
789 if (cs->hw.hfcD.int_s1 & 0x18) {
791 val = cs->hw.hfcD.int_s1;
792 cs->hw.hfcD.int_s1 = exval;
795 if (!(bcs=Sel_BCS(cs, 0))) {
797 debugl1(cs, "hfcd spurious 0x08 IRQ");
802 if (!(bcs=Sel_BCS(cs, 1))) {
804 debugl1(cs, "hfcd spurious 0x10 IRQ");
809 if (!(bcs=Sel_BCS(cs, 0))) {
811 debugl1(cs, "hfcd spurious 0x01 IRQ");
814 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
816 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
818 debugl1(cs,"fill_data %d blocked", bcs->channel);
820 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
821 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
823 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
825 debugl1(cs,"fill_data %d blocked", bcs->channel);
827 schedule_event(bcs, B_XMTBUFREADY);
833 if (!(bcs=Sel_BCS(cs, 1))) {
835 debugl1(cs, "hfcd spurious 0x02 IRQ");
838 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
840 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
842 debugl1(cs,"fill_data %d blocked", bcs->channel);
844 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
845 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
847 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
849 debugl1(cs,"fill_data %d blocked", bcs->channel);
851 schedule_event(bcs, B_XMTBUFREADY);
856 if (val & 0x20) { /* receive dframe */
859 if (val & 0x04) { /* dframe transmitted */
860 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
861 del_timer(&cs->dbusytimer);
862 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
863 schedule_event(cs, D_CLEARBUSY);
865 if (cs->tx_skb->len) {
866 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
868 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
870 debugl1(cs, "hfc_fill_dfifo irq blocked");
874 dev_kfree_skb_irq(cs->tx_skb);
879 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
881 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
883 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
885 debugl1(cs, "hfc_fill_dfifo irq blocked");
888 schedule_event(cs, D_XMTBUFREADY);
891 if (cs->hw.hfcD.int_s1 && count--) {
892 val = cs->hw.hfcD.int_s1;
893 cs->hw.hfcD.int_s1 = 0;
894 if (cs->debug & L1_DEB_ISAC)
895 debugl1(cs, "HFCD irq %x loop %d", val, 15-count);
902 HFCD_l1hw(struct PStack *st, int pr, void *arg)
904 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
905 struct sk_buff *skb = arg;
909 case (PH_DATA | REQUEST):
910 if (cs->debug & DEB_DLOG_HEX)
911 LogFrame(cs, skb->data, skb->len);
912 if (cs->debug & DEB_DLOG_VERBOSE)
913 dlogframe(cs, skb, 0);
914 spin_lock_irqsave(&cs->lock, flags);
916 skb_queue_tail(&cs->sq, skb);
917 #ifdef L2FRAME_DEBUG /* psa */
918 if (cs->debug & L1_DEB_LAPD)
919 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
924 #ifdef L2FRAME_DEBUG /* psa */
925 if (cs->debug & L1_DEB_LAPD)
926 Logl2Frame(cs, skb, "PH_DATA", 0);
928 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
930 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
932 debugl1(cs, "hfc_fill_dfifo blocked");
935 spin_unlock_irqrestore(&cs->lock, flags);
937 case (PH_PULL | INDICATION):
938 spin_lock_irqsave(&cs->lock, flags);
940 if (cs->debug & L1_DEB_WARN)
941 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
942 skb_queue_tail(&cs->sq, skb);
943 spin_unlock_irqrestore(&cs->lock, flags);
946 if (cs->debug & DEB_DLOG_HEX)
947 LogFrame(cs, skb->data, skb->len);
948 if (cs->debug & DEB_DLOG_VERBOSE)
949 dlogframe(cs, skb, 0);
952 #ifdef L2FRAME_DEBUG /* psa */
953 if (cs->debug & L1_DEB_LAPD)
954 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
956 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
958 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
960 debugl1(cs, "hfc_fill_dfifo blocked");
961 spin_unlock_irqrestore(&cs->lock, flags);
963 case (PH_PULL | REQUEST):
964 #ifdef L2FRAME_DEBUG /* psa */
965 if (cs->debug & L1_DEB_LAPD)
966 debugl1(cs, "-> PH_REQUEST_PULL");
969 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
970 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
972 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
974 case (HW_RESET | REQUEST):
975 spin_lock_irqsave(&cs->lock, flags);
976 cs->writeisac(cs, HFCD_STATES, HFCD_LOAD_STATE | 3); /* HFC ST 3 */
978 cs->writeisac(cs, HFCD_STATES, 3); /* HFC ST 2 */
979 cs->hw.hfcD.mst_m |= HFCD_MASTER;
980 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
981 cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
982 spin_unlock_irqrestore(&cs->lock, flags);
983 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
985 case (HW_ENABLE | REQUEST):
986 spin_lock_irqsave(&cs->lock, flags);
987 cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
988 spin_unlock_irqrestore(&cs->lock, flags);
990 case (HW_DEACTIVATE | REQUEST):
991 spin_lock_irqsave(&cs->lock, flags);
992 cs->hw.hfcD.mst_m &= ~HFCD_MASTER;
993 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
994 spin_unlock_irqrestore(&cs->lock, flags);
996 case (HW_INFO3 | REQUEST):
997 spin_lock_irqsave(&cs->lock, flags);
998 cs->hw.hfcD.mst_m |= HFCD_MASTER;
999 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
1000 spin_unlock_irqrestore(&cs->lock, flags);
1003 if (cs->debug & L1_DEB_WARN)
1004 debugl1(cs, "hfcd_l1hw unknown pr %4x", pr);
1010 setstack_hfcd(struct PStack *st, struct IsdnCardState *cs)
1012 st->l1.l1hw = HFCD_l1hw;
1016 hfc_dbusy_timer(struct IsdnCardState *cs)
1021 *init_send_hfcd(int cnt)
1026 if (!(send = kmalloc(cnt * sizeof(unsigned int), GFP_ATOMIC))) {
1028 "HiSax: No memory for hfcd.send\n");
1031 for (i = 0; i < cnt; i++)
1037 init2bds0(struct IsdnCardState *cs)
1039 cs->setstack_d = setstack_hfcd;
1040 if (!cs->hw.hfcD.send)
1041 cs->hw.hfcD.send = init_send_hfcd(16);
1042 if (!cs->bcs[0].hw.hfc.send)
1043 cs->bcs[0].hw.hfc.send = init_send_hfcd(32);
1044 if (!cs->bcs[1].hw.hfc.send)
1045 cs->bcs[1].hw.hfc.send = init_send_hfcd(32);
1046 cs->BC_Send_Data = &hfc_send_data;
1047 cs->bcs[0].BC_SetStack = setstack_2b;
1048 cs->bcs[1].BC_SetStack = setstack_2b;
1049 cs->bcs[0].BC_Close = close_2bs0;
1050 cs->bcs[1].BC_Close = close_2bs0;
1051 mode_2bs0(cs->bcs, 0, 0);
1052 mode_2bs0(cs->bcs + 1, 0, 1);
1056 release2bds0(struct IsdnCardState *cs)
1058 kfree(cs->bcs[0].hw.hfc.send);
1059 cs->bcs[0].hw.hfc.send = NULL;
1060 kfree(cs->bcs[1].hw.hfc.send);
1061 cs->bcs[1].hw.hfc.send = NULL;
1062 kfree(cs->hw.hfcD.send);
1063 cs->hw.hfcD.send = NULL;
1067 set_cs_func(struct IsdnCardState *cs)
1069 cs->readisac = &readreghfcd;
1070 cs->writeisac = &writereghfcd;
1071 cs->readisacfifo = &dummyf;
1072 cs->writeisacfifo = &dummyf;
1073 cs->BC_Read_Reg = &ReadReg;
1074 cs->BC_Write_Reg = &WriteReg;
1075 cs->dbusytimer.function = (void *) hfc_dbusy_timer;
1076 cs->dbusytimer.data = (long) cs;
1077 init_timer(&cs->dbusytimer);
1078 INIT_WORK(&cs->tqueue, hfcd_bh);