1 /* $Id: hfc_2bs0.c,v 1.20.2.6 2004/02/11 13:21:33 keil Exp $
3 * specific routines for CCD's HFC 2BS0
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
13 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
22 WaitForBusy(struct IsdnCardState *cs)
27 while (!(cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
28 val = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2 |
29 (cs->hw.hfc.cip & 3));
34 printk(KERN_WARNING "HiSax: waitforBusy timeout\n");
41 WaitNoBusy(struct IsdnCardState *cs)
45 while ((cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
50 printk(KERN_WARNING "HiSax: waitforBusy timeout\n");
57 GetFreeFifoBytes(struct BCState *bcs)
61 if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
62 return (bcs->cs->hw.hfc.fifosize);
63 s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
65 s += bcs->cs->hw.hfc.fifosize;
66 s = bcs->cs->hw.hfc.fifosize - s;
71 ReadZReg(struct BCState *bcs, u_char reg)
76 val = 256 * bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_HIGH);
78 val += bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_LOW);
83 hfc_clear_fifo(struct BCState *bcs)
85 struct IsdnCardState *cs = bcs->cs;
90 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
91 debugl1(cs, "hfc_clear_fifo");
92 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
93 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
94 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
98 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
99 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
101 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
102 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
103 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
105 while (((f1 != f2) || (z1 != z2)) && cnt--) {
106 if (cs->debug & L1_DEB_HSCX)
107 debugl1(cs, "hfc clear %d f1(%d) f2(%d)",
108 bcs->channel, f1, f2);
111 rcnt += cs->hw.hfc.fifosize;
114 if (cs->debug & L1_DEB_HSCX)
115 debugl1(cs, "hfc clear %d z1(%x) z2(%x) cnt(%d)",
116 bcs->channel, z1, z2, rcnt);
117 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
119 while ((idx < rcnt) && WaitNoBusy(cs)) {
120 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
125 cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
126 HFC_CHANNEL(bcs->channel));
129 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
131 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
132 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
134 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
135 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
136 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
142 static struct sk_buff
144 hfc_empty_fifo(struct BCState *bcs, int count)
148 struct IsdnCardState *cs = bcs->cs;
153 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
154 debugl1(cs, "hfc_empty_fifo");
156 if (count > HSCX_BUFMAX + 3) {
157 if (cs->debug & L1_DEB_WARN)
158 debugl1(cs, "hfc_empty_fifo: incoming packet too large");
159 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
160 while ((idx++ < count) && WaitNoBusy(cs))
161 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
163 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
164 HFC_CHANNEL(bcs->channel));
168 if ((count < 4) && (bcs->mode != L1_MODE_TRANS)) {
169 if (cs->debug & L1_DEB_WARN)
170 debugl1(cs, "hfc_empty_fifo: incoming packet too small");
171 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
172 while ((idx++ < count) && WaitNoBusy(cs))
173 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
175 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
176 HFC_CHANNEL(bcs->channel));
178 #ifdef ERROR_STATISTIC
183 if (bcs->mode == L1_MODE_TRANS)
187 if (!(skb = dev_alloc_skb(count)))
188 printk(KERN_WARNING "HFC: receive out of memory\n");
190 ptr = skb_put(skb, count);
192 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
193 while ((idx < count) && WaitNoBusy(cs)) {
194 *ptr++ = cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
198 debugl1(cs, "RFIFO BUSY error");
199 printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
200 dev_kfree_skb_any(skb);
201 if (bcs->mode != L1_MODE_TRANS) {
203 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
204 HFC_CHANNEL(bcs->channel));
209 if (bcs->mode != L1_MODE_TRANS) {
211 chksum = (cs->BC_Read_Reg(cs, HFC_DATA, cip) << 8);
213 chksum += cs->BC_Read_Reg(cs, HFC_DATA, cip);
215 stat = cs->BC_Read_Reg(cs, HFC_DATA, cip);
216 if (cs->debug & L1_DEB_HSCX)
217 debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x",
218 bcs->channel, chksum, stat);
220 debugl1(cs, "FIFO CRC error");
221 dev_kfree_skb_any(skb);
223 #ifdef ERROR_STATISTIC
228 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
229 HFC_CHANNEL(bcs->channel));
237 hfc_fill_fifo(struct BCState *bcs)
239 struct IsdnCardState *cs = bcs->cs;
247 if (bcs->tx_skb->len <= 0)
250 cip = HFC_CIP | HFC_F1 | HFC_SEND | HFC_CHANNEL(bcs->channel);
251 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
252 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
256 if (bcs->mode != L1_MODE_TRANS) {
257 bcs->hw.hfc.f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
258 cip = HFC_CIP | HFC_F2 | HFC_SEND | HFC_CHANNEL(bcs->channel);
260 bcs->hw.hfc.f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
261 bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(bcs, HFC_Z1 | HFC_SEND | HFC_CHANNEL(bcs->channel));
262 if (cs->debug & L1_DEB_HSCX)
263 debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
264 bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
265 bcs->hw.hfc.send[bcs->hw.hfc.f1]);
266 fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
270 if (cs->debug & L1_DEB_HSCX)
271 debugl1(cs, "hfc_fill_fifo more as 30 frames");
274 count = GetFreeFifoBytes(bcs);
278 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
279 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
282 count += cs->hw.hfc.fifosize;
283 } /* L1_MODE_TRANS */
284 if (cs->debug & L1_DEB_HSCX)
285 debugl1(cs, "hfc_fill_fifo %d count(%u/%d)",
286 bcs->channel, bcs->tx_skb->len,
288 if (count < bcs->tx_skb->len) {
289 if (cs->debug & L1_DEB_HSCX)
290 debugl1(cs, "hfc_fill_fifo no fifo mem");
293 cip = HFC_CIP | HFC_FIFO_IN | HFC_SEND | HFC_CHANNEL(bcs->channel);
295 while ((idx < bcs->tx_skb->len) && WaitNoBusy(cs))
296 cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
297 if (idx != bcs->tx_skb->len) {
298 debugl1(cs, "FIFO Send BUSY error");
299 printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
301 count = bcs->tx_skb->len;
302 bcs->tx_cnt -= count;
303 if (PACKET_NOACK == bcs->tx_skb->pkt_type)
305 dev_kfree_skb_any(bcs->tx_skb);
307 if (bcs->mode != L1_MODE_TRANS) {
310 cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F1_INC | HFC_SEND | HFC_CHANNEL(bcs->channel));
312 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
315 spin_lock_irqsave(&bcs->aclock, flags);
316 bcs->ackcnt += count;
317 spin_unlock_irqrestore(&bcs->aclock, flags);
318 schedule_event(bcs, B_ACKPENDING);
320 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
326 main_irq_hfc(struct BCState *bcs)
328 struct IsdnCardState *cs = bcs->cs;
331 int receive, transmit, count = 5;
336 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
337 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
338 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
343 if (bcs->mode == L1_MODE_HDLC) {
344 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
345 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
347 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
349 if (cs->debug & L1_DEB_HSCX)
350 debugl1(cs, "hfc rec %d f1(%d) f2(%d)",
351 bcs->channel, f1, f2);
355 if (receive || (bcs->mode == L1_MODE_TRANS)) {
357 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
358 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
361 rcnt += cs->hw.hfc.fifosize;
362 if ((bcs->mode == L1_MODE_HDLC) || (rcnt)) {
364 if (cs->debug & L1_DEB_HSCX)
365 debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
366 bcs->channel, z1, z2, rcnt);
368 if ((skb = hfc_empty_fifo(bcs, rcnt))) {
369 skb_queue_tail(&bcs->rqueue, skb);
370 schedule_event(bcs, B_RCVBUFREADY);
377 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
379 if (test_bit(BC_FLG_BUSY, &bcs->Flag))
382 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
384 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
386 if (test_bit(BC_FLG_BUSY, &bcs->Flag))
390 schedule_event(bcs, B_XMTBUFREADY);
393 if ((receive || transmit) && count)
399 mode_hfc(struct BCState *bcs, int mode, int bc)
401 struct IsdnCardState *cs = bcs->cs;
403 if (cs->debug & L1_DEB_HSCX)
404 debugl1(cs, "HFC 2BS0 mode %d bchan %d/%d",
405 mode, bc, bcs->channel);
412 cs->hw.hfc.ctmt &= ~1;
413 cs->hw.hfc.isac_spcr &= ~0x03;
416 cs->hw.hfc.ctmt &= ~2;
417 cs->hw.hfc.isac_spcr &= ~0x0c;
420 case (L1_MODE_TRANS):
421 cs->hw.hfc.ctmt &= ~(1 << bc); /* set HDLC mode */
422 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
423 hfc_clear_fifo(bcs); /* complete fifo clear */
425 cs->hw.hfc.ctmt |= 1;
426 cs->hw.hfc.isac_spcr &= ~0x03;
427 cs->hw.hfc.isac_spcr |= 0x02;
429 cs->hw.hfc.ctmt |= 2;
430 cs->hw.hfc.isac_spcr &= ~0x0c;
431 cs->hw.hfc.isac_spcr |= 0x08;
436 cs->hw.hfc.ctmt &= ~1;
437 cs->hw.hfc.isac_spcr &= ~0x03;
438 cs->hw.hfc.isac_spcr |= 0x02;
440 cs->hw.hfc.ctmt &= ~2;
441 cs->hw.hfc.isac_spcr &= ~0x0c;
442 cs->hw.hfc.isac_spcr |= 0x08;
446 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
447 cs->writeisac(cs, ISAC_SPCR, cs->hw.hfc.isac_spcr);
448 if (mode == L1_MODE_HDLC)
453 hfc_l2l1(struct PStack *st, int pr, void *arg)
455 struct BCState *bcs = st->l1.bcs;
456 struct sk_buff *skb = arg;
460 case (PH_DATA | REQUEST):
461 spin_lock_irqsave(&bcs->cs->lock, flags);
463 skb_queue_tail(&bcs->squeue, skb);
466 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
467 bcs->cs->BC_Send_Data(bcs);
469 spin_unlock_irqrestore(&bcs->cs->lock, flags);
471 case (PH_PULL | INDICATION):
472 spin_lock_irqsave(&bcs->cs->lock, flags);
474 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
476 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
478 bcs->cs->BC_Send_Data(bcs);
480 spin_unlock_irqrestore(&bcs->cs->lock, flags);
482 case (PH_PULL | REQUEST):
484 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
485 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
487 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
489 case (PH_ACTIVATE | REQUEST):
490 spin_lock_irqsave(&bcs->cs->lock, flags);
491 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
492 mode_hfc(bcs, st->l1.mode, st->l1.bc);
493 spin_unlock_irqrestore(&bcs->cs->lock, flags);
494 l1_msg_b(st, pr, arg);
496 case (PH_DEACTIVATE | REQUEST):
497 l1_msg_b(st, pr, arg);
499 case (PH_DEACTIVATE | CONFIRM):
500 spin_lock_irqsave(&bcs->cs->lock, flags);
501 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
502 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
503 mode_hfc(bcs, 0, st->l1.bc);
504 spin_unlock_irqrestore(&bcs->cs->lock, flags);
505 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
512 close_hfcstate(struct BCState *bcs)
514 mode_hfc(bcs, 0, bcs->channel);
515 if (test_bit(BC_FLG_INIT, &bcs->Flag)) {
516 skb_queue_purge(&bcs->rqueue);
517 skb_queue_purge(&bcs->squeue);
519 dev_kfree_skb_any(bcs->tx_skb);
521 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
524 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
528 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
530 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
531 skb_queue_head_init(&bcs->rqueue);
532 skb_queue_head_init(&bcs->squeue);
535 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
542 setstack_hfc(struct PStack *st, struct BCState *bcs)
544 bcs->channel = st->l1.bc;
545 if (open_hfcstate(st->l1.hardware, bcs))
548 st->l2.l2l1 = hfc_l2l1;
549 setstack_manager(st);
556 init_send(struct BCState *bcs)
560 if (!(bcs->hw.hfc.send = kmalloc(32 * sizeof(unsigned int), GFP_ATOMIC))) {
562 "HiSax: No memory for hfc.send\n");
565 for (i = 0; i < 32; i++)
566 bcs->hw.hfc.send[i] = 0x1fff;
570 inithfc(struct IsdnCardState *cs)
572 init_send(&cs->bcs[0]);
573 init_send(&cs->bcs[1]);
574 cs->BC_Send_Data = &hfc_fill_fifo;
575 cs->bcs[0].BC_SetStack = setstack_hfc;
576 cs->bcs[1].BC_SetStack = setstack_hfc;
577 cs->bcs[0].BC_Close = close_hfcstate;
578 cs->bcs[1].BC_Close = close_hfcstate;
579 mode_hfc(cs->bcs, 0, 0);
580 mode_hfc(cs->bcs + 1, 0, 0);
584 releasehfc(struct IsdnCardState *cs)
586 kfree(cs->bcs[0].hw.hfc.send);
587 cs->bcs[0].hw.hfc.send = NULL;
588 kfree(cs->bcs[1].hw.hfc.send);
589 cs->bcs[1].hw.hfc.send = NULL;