2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
18 #include "x86_emulate.h"
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/vmalloc.h>
24 #include <linux/highmem.h>
25 #include <linux/profile.h>
26 #include <linux/sched.h>
30 MODULE_AUTHOR("Qumranet");
31 MODULE_LICENSE("GPL");
33 #define IOPM_ALLOC_ORDER 2
34 #define MSRPM_ALLOC_ORDER 1
40 #define DR7_GD_MASK (1 << 13)
41 #define DR6_BD_MASK (1 << 13)
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
46 #define KVM_EFER_LMA (1 << 10)
47 #define KVM_EFER_LME (1 << 8)
49 #define SVM_FEATURE_NPT (1 << 0)
50 #define SVM_FEATURE_LBRV (1 << 1)
51 #define SVM_DEATURE_SVML (1 << 2)
53 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
55 return container_of(vcpu, struct vcpu_svm, vcpu);
58 unsigned long iopm_base;
59 unsigned long msrpm_base;
61 struct kvm_ldttss_desc {
64 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
65 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
68 } __attribute__((packed));
76 struct kvm_ldttss_desc *tss_desc;
78 struct page *save_area;
81 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
82 static uint32_t svm_features;
84 struct svm_init_data {
89 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
91 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
92 #define MSRS_RANGE_SIZE 2048
93 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
95 #define MAX_INST_SIZE 15
97 static inline u32 svm_has(u32 feat)
99 return svm_features & feat;
102 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
104 int word_index = __ffs(vcpu->irq_summary);
105 int bit_index = __ffs(vcpu->irq_pending[word_index]);
106 int irq = word_index * BITS_PER_LONG + bit_index;
108 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
109 if (!vcpu->irq_pending[word_index])
110 clear_bit(word_index, &vcpu->irq_summary);
114 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
116 set_bit(irq, vcpu->irq_pending);
117 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
120 static inline void clgi(void)
122 asm volatile (SVM_CLGI);
125 static inline void stgi(void)
127 asm volatile (SVM_STGI);
130 static inline void invlpga(unsigned long addr, u32 asid)
132 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
135 static inline unsigned long kvm_read_cr2(void)
139 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
143 static inline void kvm_write_cr2(unsigned long val)
145 asm volatile ("mov %0, %%cr2" :: "r" (val));
148 static inline unsigned long read_dr6(void)
152 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
156 static inline void write_dr6(unsigned long val)
158 asm volatile ("mov %0, %%dr6" :: "r" (val));
161 static inline unsigned long read_dr7(void)
165 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
169 static inline void write_dr7(unsigned long val)
171 asm volatile ("mov %0, %%dr7" :: "r" (val));
174 static inline void force_new_asid(struct kvm_vcpu *vcpu)
176 to_svm(vcpu)->asid_generation--;
179 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
181 force_new_asid(vcpu);
184 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
186 if (!(efer & KVM_EFER_LMA))
187 efer &= ~KVM_EFER_LME;
189 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
190 vcpu->shadow_efer = efer;
193 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
195 struct vcpu_svm *svm = to_svm(vcpu);
197 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
198 SVM_EVTINJ_VALID_ERR |
199 SVM_EVTINJ_TYPE_EXEPT |
201 svm->vmcb->control.event_inj_err = error_code;
204 static void inject_ud(struct kvm_vcpu *vcpu)
206 to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
207 SVM_EVTINJ_TYPE_EXEPT |
211 static int is_page_fault(uint32_t info)
213 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
214 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
217 static int is_external_interrupt(u32 info)
219 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
220 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
223 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
225 struct vcpu_svm *svm = to_svm(vcpu);
227 if (!svm->next_rip) {
228 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
231 if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) {
232 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
238 vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
239 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
241 vcpu->interrupt_window_open = 1;
244 static int has_svm(void)
246 uint32_t eax, ebx, ecx, edx;
248 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
249 printk(KERN_INFO "has_svm: not amd\n");
253 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
254 if (eax < SVM_CPUID_FUNC) {
255 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
259 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
260 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
261 printk(KERN_DEBUG "has_svm: svm not available\n");
267 static void svm_hardware_disable(void *garbage)
269 struct svm_cpu_data *svm_data
270 = per_cpu(svm_data, raw_smp_processor_id());
275 wrmsrl(MSR_VM_HSAVE_PA, 0);
276 rdmsrl(MSR_EFER, efer);
277 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
278 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
279 __free_page(svm_data->save_area);
284 static void svm_hardware_enable(void *garbage)
287 struct svm_cpu_data *svm_data;
290 struct desc_ptr gdt_descr;
292 struct Xgt_desc_struct gdt_descr;
294 struct desc_struct *gdt;
295 int me = raw_smp_processor_id();
298 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
301 svm_data = per_cpu(svm_data, me);
304 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
309 svm_data->asid_generation = 1;
310 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
311 svm_data->next_asid = svm_data->max_asid + 1;
312 svm_features = cpuid_edx(SVM_CPUID_FUNC);
314 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
315 gdt = (struct desc_struct *)gdt_descr.address;
316 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
318 rdmsrl(MSR_EFER, efer);
319 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
321 wrmsrl(MSR_VM_HSAVE_PA,
322 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
325 static int svm_cpu_init(int cpu)
327 struct svm_cpu_data *svm_data;
330 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
334 svm_data->save_area = alloc_page(GFP_KERNEL);
336 if (!svm_data->save_area)
339 per_cpu(svm_data, cpu) = svm_data;
349 static void set_msr_interception(u32 *msrpm, unsigned msr,
354 for (i = 0; i < NUM_MSR_MAPS; i++) {
355 if (msr >= msrpm_ranges[i] &&
356 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
357 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
358 msrpm_ranges[i]) * 2;
360 u32 *base = msrpm + (msr_offset / 32);
361 u32 msr_shift = msr_offset % 32;
362 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
363 *base = (*base & ~(0x3 << msr_shift)) |
371 static __init int svm_hardware_setup(void)
374 struct page *iopm_pages;
375 struct page *msrpm_pages;
376 void *iopm_va, *msrpm_va;
379 kvm_emulator_want_group7_invlpg();
381 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
386 iopm_va = page_address(iopm_pages);
387 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
388 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
389 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
392 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
398 msrpm_va = page_address(msrpm_pages);
399 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
400 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
403 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
404 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
405 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
406 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
407 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
408 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
410 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
411 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
412 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
413 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
415 for_each_online_cpu(cpu) {
416 r = svm_cpu_init(cpu);
423 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
426 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
431 static __exit void svm_hardware_unsetup(void)
433 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
434 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
435 iopm_base = msrpm_base = 0;
438 static void init_seg(struct vmcb_seg *seg)
441 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
442 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
447 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
450 seg->attrib = SVM_SELECTOR_P_MASK | type;
455 static void init_vmcb(struct vmcb *vmcb)
457 struct vmcb_control_area *control = &vmcb->control;
458 struct vmcb_save_area *save = &vmcb->save;
460 control->intercept_cr_read = INTERCEPT_CR0_MASK |
464 control->intercept_cr_write = INTERCEPT_CR0_MASK |
468 control->intercept_dr_read = INTERCEPT_DR0_MASK |
473 control->intercept_dr_write = INTERCEPT_DR0_MASK |
480 control->intercept_exceptions = 1 << PF_VECTOR;
483 control->intercept = (1ULL << INTERCEPT_INTR) |
484 (1ULL << INTERCEPT_NMI) |
485 (1ULL << INTERCEPT_SMI) |
487 * selective cr0 intercept bug?
488 * 0: 0f 22 d8 mov %eax,%cr3
489 * 3: 0f 20 c0 mov %cr0,%eax
490 * 6: 0d 00 00 00 80 or $0x80000000,%eax
491 * b: 0f 22 c0 mov %eax,%cr0
492 * set cr3 ->interception
493 * get cr0 ->interception
494 * set cr0 -> no interception
496 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
497 (1ULL << INTERCEPT_CPUID) |
498 (1ULL << INTERCEPT_HLT) |
499 (1ULL << INTERCEPT_INVLPGA) |
500 (1ULL << INTERCEPT_IOIO_PROT) |
501 (1ULL << INTERCEPT_MSR_PROT) |
502 (1ULL << INTERCEPT_TASK_SWITCH) |
503 (1ULL << INTERCEPT_SHUTDOWN) |
504 (1ULL << INTERCEPT_VMRUN) |
505 (1ULL << INTERCEPT_VMMCALL) |
506 (1ULL << INTERCEPT_VMLOAD) |
507 (1ULL << INTERCEPT_VMSAVE) |
508 (1ULL << INTERCEPT_STGI) |
509 (1ULL << INTERCEPT_CLGI) |
510 (1ULL << INTERCEPT_SKINIT) |
511 (1ULL << INTERCEPT_MONITOR) |
512 (1ULL << INTERCEPT_MWAIT);
514 control->iopm_base_pa = iopm_base;
515 control->msrpm_base_pa = msrpm_base;
516 control->tsc_offset = 0;
517 control->int_ctl = V_INTR_MASKING_MASK;
525 save->cs.selector = 0xf000;
526 /* Executable/Readable Code Segment */
527 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
528 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
529 save->cs.limit = 0xffff;
531 * cs.base should really be 0xffff0000, but vmx can't handle that, so
532 * be consistent with it.
534 * Replace when we have real mode working for vmx.
536 save->cs.base = 0xf0000;
538 save->gdtr.limit = 0xffff;
539 save->idtr.limit = 0xffff;
541 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
542 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
544 save->efer = MSR_EFER_SVME_MASK;
546 save->dr6 = 0xffff0ff0;
549 save->rip = 0x0000fff0;
552 * cr0 val on cpu init should be 0x60000010, we enable cpu
553 * cache by default. the orderly way is to enable cache in bios.
555 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
556 save->cr4 = X86_CR4_PAE;
560 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
562 struct vcpu_svm *svm;
566 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
572 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
576 page = alloc_page(GFP_KERNEL);
582 svm->vmcb = page_address(page);
583 clear_page(svm->vmcb);
584 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
585 svm->asid_generation = 0;
586 memset(svm->db_regs, 0, sizeof(svm->db_regs));
587 init_vmcb(svm->vmcb);
590 svm->vcpu.fpu_active = 1;
591 svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
592 if (svm->vcpu.vcpu_id == 0)
593 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
598 kvm_vcpu_uninit(&svm->vcpu);
600 kmem_cache_free(kvm_vcpu_cache, svm);
605 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
607 struct vcpu_svm *svm = to_svm(vcpu);
609 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
610 kvm_vcpu_uninit(vcpu);
611 kmem_cache_free(kvm_vcpu_cache, svm);
614 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
616 struct vcpu_svm *svm = to_svm(vcpu);
619 if (unlikely(cpu != vcpu->cpu)) {
623 * Make sure that the guest sees a monotonically
627 delta = vcpu->host_tsc - tsc_this;
628 svm->vmcb->control.tsc_offset += delta;
632 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
633 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
636 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
638 struct vcpu_svm *svm = to_svm(vcpu);
641 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
642 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
644 rdtscll(vcpu->host_tsc);
647 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
651 static void svm_cache_regs(struct kvm_vcpu *vcpu)
653 struct vcpu_svm *svm = to_svm(vcpu);
655 vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
656 vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
657 vcpu->rip = svm->vmcb->save.rip;
660 static void svm_decache_regs(struct kvm_vcpu *vcpu)
662 struct vcpu_svm *svm = to_svm(vcpu);
663 svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
664 svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
665 svm->vmcb->save.rip = vcpu->rip;
668 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
670 return to_svm(vcpu)->vmcb->save.rflags;
673 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
675 to_svm(vcpu)->vmcb->save.rflags = rflags;
678 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
680 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
683 case VCPU_SREG_CS: return &save->cs;
684 case VCPU_SREG_DS: return &save->ds;
685 case VCPU_SREG_ES: return &save->es;
686 case VCPU_SREG_FS: return &save->fs;
687 case VCPU_SREG_GS: return &save->gs;
688 case VCPU_SREG_SS: return &save->ss;
689 case VCPU_SREG_TR: return &save->tr;
690 case VCPU_SREG_LDTR: return &save->ldtr;
696 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
698 struct vmcb_seg *s = svm_seg(vcpu, seg);
703 static void svm_get_segment(struct kvm_vcpu *vcpu,
704 struct kvm_segment *var, int seg)
706 struct vmcb_seg *s = svm_seg(vcpu, seg);
709 var->limit = s->limit;
710 var->selector = s->selector;
711 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
712 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
713 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
714 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
715 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
716 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
717 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
718 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
719 var->unusable = !var->present;
722 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
724 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
726 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
727 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
730 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
732 struct vcpu_svm *svm = to_svm(vcpu);
734 dt->limit = svm->vmcb->save.idtr.limit;
735 dt->base = svm->vmcb->save.idtr.base;
738 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
740 struct vcpu_svm *svm = to_svm(vcpu);
742 svm->vmcb->save.idtr.limit = dt->limit;
743 svm->vmcb->save.idtr.base = dt->base ;
746 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
748 struct vcpu_svm *svm = to_svm(vcpu);
750 dt->limit = svm->vmcb->save.gdtr.limit;
751 dt->base = svm->vmcb->save.gdtr.base;
754 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
756 struct vcpu_svm *svm = to_svm(vcpu);
758 svm->vmcb->save.gdtr.limit = dt->limit;
759 svm->vmcb->save.gdtr.base = dt->base ;
762 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
766 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
768 struct vcpu_svm *svm = to_svm(vcpu);
771 if (vcpu->shadow_efer & KVM_EFER_LME) {
772 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
773 vcpu->shadow_efer |= KVM_EFER_LMA;
774 svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
777 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
778 vcpu->shadow_efer &= ~KVM_EFER_LMA;
779 svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
783 if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
784 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
785 vcpu->fpu_active = 1;
789 cr0 |= X86_CR0_PG | X86_CR0_WP;
790 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
791 svm->vmcb->save.cr0 = cr0;
794 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
797 to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
800 static void svm_set_segment(struct kvm_vcpu *vcpu,
801 struct kvm_segment *var, int seg)
803 struct vcpu_svm *svm = to_svm(vcpu);
804 struct vmcb_seg *s = svm_seg(vcpu, seg);
807 s->limit = var->limit;
808 s->selector = var->selector;
812 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
813 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
814 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
815 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
816 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
817 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
818 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
819 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
821 if (seg == VCPU_SREG_CS)
823 = (svm->vmcb->save.cs.attrib
824 >> SVM_SELECTOR_DPL_SHIFT) & 3;
830 svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
831 svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
835 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
840 static void load_host_msrs(struct kvm_vcpu *vcpu)
843 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
847 static void save_host_msrs(struct kvm_vcpu *vcpu)
850 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
854 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
856 if (svm_data->next_asid > svm_data->max_asid) {
857 ++svm_data->asid_generation;
858 svm_data->next_asid = 1;
859 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
862 svm->vcpu.cpu = svm_data->cpu;
863 svm->asid_generation = svm_data->asid_generation;
864 svm->vmcb->control.asid = svm_data->next_asid++;
867 static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
869 invlpga(address, to_svm(vcpu)->vmcb->control.asid); // is needed?
872 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
874 return to_svm(vcpu)->db_regs[dr];
877 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
880 struct vcpu_svm *svm = to_svm(vcpu);
884 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
885 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
886 svm->vmcb->save.dr6 |= DR6_BD_MASK;
887 *exception = DB_VECTOR;
893 svm->db_regs[dr] = value;
896 if (vcpu->cr4 & X86_CR4_DE) {
897 *exception = UD_VECTOR;
901 if (value & ~((1ULL << 32) - 1)) {
902 *exception = GP_VECTOR;
905 svm->vmcb->save.dr7 = value;
909 printk(KERN_DEBUG "%s: unexpected dr %u\n",
911 *exception = UD_VECTOR;
916 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
918 u32 exit_int_info = svm->vmcb->control.exit_int_info;
919 struct kvm *kvm = svm->vcpu.kvm;
922 enum emulation_result er;
925 if (!irqchip_in_kernel(kvm) &&
926 is_external_interrupt(exit_int_info))
927 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
929 mutex_lock(&kvm->lock);
931 fault_address = svm->vmcb->control.exit_info_2;
932 error_code = svm->vmcb->control.exit_info_1;
933 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
935 mutex_unlock(&kvm->lock);
939 mutex_unlock(&kvm->lock);
942 er = emulate_instruction(&svm->vcpu, kvm_run, fault_address,
944 mutex_unlock(&kvm->lock);
949 case EMULATE_DO_MMIO:
950 ++svm->vcpu.stat.mmio_exits;
953 vcpu_printf(&svm->vcpu, "%s: emulate fail\n", __FUNCTION__);
959 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
963 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
965 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
966 if (!(svm->vcpu.cr0 & X86_CR0_TS))
967 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
968 svm->vcpu.fpu_active = 1;
973 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
976 * VMCB is undefined after a SHUTDOWN intercept
977 * so reinitialize it.
979 clear_page(svm->vmcb);
980 init_vmcb(svm->vmcb);
982 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
986 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
988 u32 io_info = svm->vmcb->control.exit_info_1; //address size bug?
989 int size, down, in, string, rep;
992 ++svm->vcpu.stat.io_exits;
994 svm->next_rip = svm->vmcb->control.exit_info_2;
996 string = (io_info & SVM_IOIO_STR_MASK) != 0;
999 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1004 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1005 port = io_info >> 16;
1006 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1007 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1008 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1010 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1013 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1018 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1020 svm->next_rip = svm->vmcb->save.rip + 1;
1021 skip_emulated_instruction(&svm->vcpu);
1022 return kvm_emulate_halt(&svm->vcpu);
1025 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1027 svm->next_rip = svm->vmcb->save.rip + 3;
1028 skip_emulated_instruction(&svm->vcpu);
1029 return kvm_hypercall(&svm->vcpu, kvm_run);
1032 static int invalid_op_interception(struct vcpu_svm *svm,
1033 struct kvm_run *kvm_run)
1035 inject_ud(&svm->vcpu);
1039 static int task_switch_interception(struct vcpu_svm *svm,
1040 struct kvm_run *kvm_run)
1042 pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1043 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1047 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1049 svm->next_rip = svm->vmcb->save.rip + 2;
1050 kvm_emulate_cpuid(&svm->vcpu);
1054 static int emulate_on_interception(struct vcpu_svm *svm,
1055 struct kvm_run *kvm_run)
1057 if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE)
1058 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1062 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1064 struct vcpu_svm *svm = to_svm(vcpu);
1067 case MSR_IA32_TIME_STAMP_COUNTER: {
1071 *data = svm->vmcb->control.tsc_offset + tsc;
1075 *data = svm->vmcb->save.star;
1077 #ifdef CONFIG_X86_64
1079 *data = svm->vmcb->save.lstar;
1082 *data = svm->vmcb->save.cstar;
1084 case MSR_KERNEL_GS_BASE:
1085 *data = svm->vmcb->save.kernel_gs_base;
1087 case MSR_SYSCALL_MASK:
1088 *data = svm->vmcb->save.sfmask;
1091 case MSR_IA32_SYSENTER_CS:
1092 *data = svm->vmcb->save.sysenter_cs;
1094 case MSR_IA32_SYSENTER_EIP:
1095 *data = svm->vmcb->save.sysenter_eip;
1097 case MSR_IA32_SYSENTER_ESP:
1098 *data = svm->vmcb->save.sysenter_esp;
1101 return kvm_get_msr_common(vcpu, ecx, data);
1106 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1108 u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1111 if (svm_get_msr(&svm->vcpu, ecx, &data))
1112 svm_inject_gp(&svm->vcpu, 0);
1114 svm->vmcb->save.rax = data & 0xffffffff;
1115 svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1116 svm->next_rip = svm->vmcb->save.rip + 2;
1117 skip_emulated_instruction(&svm->vcpu);
1122 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1124 struct vcpu_svm *svm = to_svm(vcpu);
1127 case MSR_IA32_TIME_STAMP_COUNTER: {
1131 svm->vmcb->control.tsc_offset = data - tsc;
1135 svm->vmcb->save.star = data;
1137 #ifdef CONFIG_X86_64
1139 svm->vmcb->save.lstar = data;
1142 svm->vmcb->save.cstar = data;
1144 case MSR_KERNEL_GS_BASE:
1145 svm->vmcb->save.kernel_gs_base = data;
1147 case MSR_SYSCALL_MASK:
1148 svm->vmcb->save.sfmask = data;
1151 case MSR_IA32_SYSENTER_CS:
1152 svm->vmcb->save.sysenter_cs = data;
1154 case MSR_IA32_SYSENTER_EIP:
1155 svm->vmcb->save.sysenter_eip = data;
1157 case MSR_IA32_SYSENTER_ESP:
1158 svm->vmcb->save.sysenter_esp = data;
1161 return kvm_set_msr_common(vcpu, ecx, data);
1166 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1168 u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1169 u64 data = (svm->vmcb->save.rax & -1u)
1170 | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1171 svm->next_rip = svm->vmcb->save.rip + 2;
1172 if (svm_set_msr(&svm->vcpu, ecx, data))
1173 svm_inject_gp(&svm->vcpu, 0);
1175 skip_emulated_instruction(&svm->vcpu);
1179 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1181 if (svm->vmcb->control.exit_info_1)
1182 return wrmsr_interception(svm, kvm_run);
1184 return rdmsr_interception(svm, kvm_run);
1187 static int interrupt_window_interception(struct vcpu_svm *svm,
1188 struct kvm_run *kvm_run)
1190 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1191 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1193 * If the user space waits to inject interrupts, exit as soon as
1196 if (kvm_run->request_interrupt_window &&
1197 !svm->vcpu.irq_summary) {
1198 ++svm->vcpu.stat.irq_window_exits;
1199 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1206 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1207 struct kvm_run *kvm_run) = {
1208 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1209 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1210 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1212 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1213 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1214 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1215 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1216 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1217 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1218 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1219 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1220 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1221 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1222 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1223 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1224 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1225 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1226 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1227 [SVM_EXIT_INTR] = nop_on_interception,
1228 [SVM_EXIT_NMI] = nop_on_interception,
1229 [SVM_EXIT_SMI] = nop_on_interception,
1230 [SVM_EXIT_INIT] = nop_on_interception,
1231 [SVM_EXIT_VINTR] = interrupt_window_interception,
1232 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1233 [SVM_EXIT_CPUID] = cpuid_interception,
1234 [SVM_EXIT_HLT] = halt_interception,
1235 [SVM_EXIT_INVLPG] = emulate_on_interception,
1236 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1237 [SVM_EXIT_IOIO] = io_interception,
1238 [SVM_EXIT_MSR] = msr_interception,
1239 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1240 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1241 [SVM_EXIT_VMRUN] = invalid_op_interception,
1242 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1243 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1244 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1245 [SVM_EXIT_STGI] = invalid_op_interception,
1246 [SVM_EXIT_CLGI] = invalid_op_interception,
1247 [SVM_EXIT_SKINIT] = invalid_op_interception,
1248 [SVM_EXIT_MONITOR] = invalid_op_interception,
1249 [SVM_EXIT_MWAIT] = invalid_op_interception,
1253 static int handle_exit(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1255 u32 exit_code = svm->vmcb->control.exit_code;
1257 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1258 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1259 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1261 __FUNCTION__, svm->vmcb->control.exit_int_info,
1264 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1265 || svm_exit_handlers[exit_code] == 0) {
1266 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1267 kvm_run->hw.hardware_exit_reason = exit_code;
1271 return svm_exit_handlers[exit_code](svm, kvm_run);
1274 static void reload_tss(struct kvm_vcpu *vcpu)
1276 int cpu = raw_smp_processor_id();
1278 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1279 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1283 static void pre_svm_run(struct vcpu_svm *svm)
1285 int cpu = raw_smp_processor_id();
1287 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1289 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1290 if (svm->vcpu.cpu != cpu ||
1291 svm->asid_generation != svm_data->asid_generation)
1292 new_asid(svm, svm_data);
1296 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1298 struct vmcb_control_area *control;
1300 control = &svm->vmcb->control;
1301 control->int_vector = irq;
1302 control->int_ctl &= ~V_INTR_PRIO_MASK;
1303 control->int_ctl |= V_IRQ_MASK |
1304 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1307 static void svm_intr_assist(struct vcpu_svm *svm)
1309 struct vmcb *vmcb = svm->vmcb;
1310 int intr_vector = -1;
1312 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1313 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1314 intr_vector = vmcb->control.exit_int_info &
1315 SVM_EVTINJ_VEC_MASK;
1316 vmcb->control.exit_int_info = 0;
1317 svm_inject_irq(svm, intr_vector);
1321 if (vmcb->control.int_ctl & V_IRQ_MASK)
1324 if (!kvm_cpu_has_interrupt(&svm->vcpu))
1327 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1328 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1329 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1330 /* unable to deliver irq, set pending irq */
1331 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1332 svm_inject_irq(svm, 0x0);
1335 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1336 intr_vector = kvm_cpu_get_interrupt(&svm->vcpu);
1337 svm_inject_irq(svm, intr_vector);
1340 static void kvm_reput_irq(struct vcpu_svm *svm)
1342 struct kvm_vcpu *vcpu = &svm->vcpu;
1343 struct vmcb_control_area *control = &svm->vmcb->control;
1345 if ((control->int_ctl & V_IRQ_MASK) && !irqchip_in_kernel(vcpu->kvm)) {
1346 control->int_ctl &= ~V_IRQ_MASK;
1347 push_irq(&svm->vcpu, control->int_vector);
1350 svm->vcpu.interrupt_window_open =
1351 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1354 static void svm_do_inject_vector(struct vcpu_svm *svm)
1356 struct kvm_vcpu *vcpu = &svm->vcpu;
1357 int word_index = __ffs(vcpu->irq_summary);
1358 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1359 int irq = word_index * BITS_PER_LONG + bit_index;
1361 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1362 if (!vcpu->irq_pending[word_index])
1363 clear_bit(word_index, &vcpu->irq_summary);
1364 svm_inject_irq(svm, irq);
1367 static void do_interrupt_requests(struct vcpu_svm *svm,
1368 struct kvm_run *kvm_run)
1370 struct vmcb_control_area *control = &svm->vmcb->control;
1372 svm->vcpu.interrupt_window_open =
1373 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1374 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1376 if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1378 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1380 svm_do_inject_vector(svm);
1383 * Interrupts blocked. Wait for unblock.
1385 if (!svm->vcpu.interrupt_window_open &&
1386 (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) {
1387 control->intercept |= 1ULL << INTERCEPT_VINTR;
1389 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1392 static void post_kvm_run_save(struct vcpu_svm *svm,
1393 struct kvm_run *kvm_run)
1395 kvm_run->ready_for_interrupt_injection
1396 = (svm->vcpu.interrupt_window_open &&
1397 svm->vcpu.irq_summary == 0);
1398 kvm_run->if_flag = (svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1399 kvm_run->cr8 = svm->vcpu.cr8;
1400 kvm_run->apic_base = svm->vcpu.apic_base;
1404 * Check if userspace requested an interrupt window, and that the
1405 * interrupt window is open.
1407 * No need to exit to userspace if we already have an interrupt queued.
1409 static int dm_request_for_irq_injection(struct vcpu_svm *svm,
1410 struct kvm_run *kvm_run)
1412 return (!svm->vcpu.irq_summary &&
1413 kvm_run->request_interrupt_window &&
1414 svm->vcpu.interrupt_window_open &&
1415 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1418 static void save_db_regs(unsigned long *db_regs)
1420 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1421 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1422 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1423 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1426 static void load_db_regs(unsigned long *db_regs)
1428 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1429 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1430 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1431 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1434 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1436 force_new_asid(vcpu);
1439 static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1441 struct vcpu_svm *svm = to_svm(vcpu);
1448 r = kvm_mmu_reload(vcpu);
1454 if (signal_pending(current)) {
1456 ++vcpu->stat.signal_exits;
1457 post_kvm_run_save(svm, kvm_run);
1458 kvm_run->exit_reason = KVM_EXIT_INTR;
1462 if (irqchip_in_kernel(vcpu->kvm))
1463 svm_intr_assist(svm);
1464 else if (!vcpu->mmio_read_completed)
1465 do_interrupt_requests(svm, kvm_run);
1467 vcpu->guest_mode = 1;
1469 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
1470 svm_flush_tlb(vcpu);
1474 save_host_msrs(vcpu);
1475 fs_selector = read_fs();
1476 gs_selector = read_gs();
1477 ldt_selector = read_ldt();
1478 svm->host_cr2 = kvm_read_cr2();
1479 svm->host_dr6 = read_dr6();
1480 svm->host_dr7 = read_dr7();
1481 svm->vmcb->save.cr2 = vcpu->cr2;
1483 if (svm->vmcb->save.dr7 & 0xff) {
1485 save_db_regs(svm->host_db_regs);
1486 load_db_regs(svm->db_regs);
1489 if (vcpu->fpu_active) {
1490 fx_save(&vcpu->host_fx_image);
1491 fx_restore(&vcpu->guest_fx_image);
1495 #ifdef CONFIG_X86_64
1496 "push %%rbx; push %%rcx; push %%rdx;"
1497 "push %%rsi; push %%rdi; push %%rbp;"
1498 "push %%r8; push %%r9; push %%r10; push %%r11;"
1499 "push %%r12; push %%r13; push %%r14; push %%r15;"
1501 "push %%ebx; push %%ecx; push %%edx;"
1502 "push %%esi; push %%edi; push %%ebp;"
1505 #ifdef CONFIG_X86_64
1506 "mov %c[rbx](%[svm]), %%rbx \n\t"
1507 "mov %c[rcx](%[svm]), %%rcx \n\t"
1508 "mov %c[rdx](%[svm]), %%rdx \n\t"
1509 "mov %c[rsi](%[svm]), %%rsi \n\t"
1510 "mov %c[rdi](%[svm]), %%rdi \n\t"
1511 "mov %c[rbp](%[svm]), %%rbp \n\t"
1512 "mov %c[r8](%[svm]), %%r8 \n\t"
1513 "mov %c[r9](%[svm]), %%r9 \n\t"
1514 "mov %c[r10](%[svm]), %%r10 \n\t"
1515 "mov %c[r11](%[svm]), %%r11 \n\t"
1516 "mov %c[r12](%[svm]), %%r12 \n\t"
1517 "mov %c[r13](%[svm]), %%r13 \n\t"
1518 "mov %c[r14](%[svm]), %%r14 \n\t"
1519 "mov %c[r15](%[svm]), %%r15 \n\t"
1521 "mov %c[rbx](%[svm]), %%ebx \n\t"
1522 "mov %c[rcx](%[svm]), %%ecx \n\t"
1523 "mov %c[rdx](%[svm]), %%edx \n\t"
1524 "mov %c[rsi](%[svm]), %%esi \n\t"
1525 "mov %c[rdi](%[svm]), %%edi \n\t"
1526 "mov %c[rbp](%[svm]), %%ebp \n\t"
1529 #ifdef CONFIG_X86_64
1530 /* Enter guest mode */
1532 "mov %c[vmcb](%[svm]), %%rax \n\t"
1538 /* Enter guest mode */
1540 "mov %c[vmcb](%[svm]), %%eax \n\t"
1547 /* Save guest registers, load host registers */
1548 #ifdef CONFIG_X86_64
1549 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1550 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1551 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1552 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1553 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1554 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1555 "mov %%r8, %c[r8](%[svm]) \n\t"
1556 "mov %%r9, %c[r9](%[svm]) \n\t"
1557 "mov %%r10, %c[r10](%[svm]) \n\t"
1558 "mov %%r11, %c[r11](%[svm]) \n\t"
1559 "mov %%r12, %c[r12](%[svm]) \n\t"
1560 "mov %%r13, %c[r13](%[svm]) \n\t"
1561 "mov %%r14, %c[r14](%[svm]) \n\t"
1562 "mov %%r15, %c[r15](%[svm]) \n\t"
1564 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1565 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1566 "pop %%rbp; pop %%rdi; pop %%rsi;"
1567 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1569 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1570 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1571 "mov %%edx, %c[rdx](%[svm]) \n\t"
1572 "mov %%esi, %c[rsi](%[svm]) \n\t"
1573 "mov %%edi, %c[rdi](%[svm]) \n\t"
1574 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1576 "pop %%ebp; pop %%edi; pop %%esi;"
1577 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1581 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1582 [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])),
1583 [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])),
1584 [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])),
1585 [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])),
1586 [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])),
1587 [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP]))
1588 #ifdef CONFIG_X86_64
1589 ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])),
1590 [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])),
1591 [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])),
1592 [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])),
1593 [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])),
1594 [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])),
1595 [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])),
1596 [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15]))
1600 vcpu->guest_mode = 0;
1602 if (vcpu->fpu_active) {
1603 fx_save(&vcpu->guest_fx_image);
1604 fx_restore(&vcpu->host_fx_image);
1607 if ((svm->vmcb->save.dr7 & 0xff))
1608 load_db_regs(svm->host_db_regs);
1610 vcpu->cr2 = svm->vmcb->save.cr2;
1612 write_dr6(svm->host_dr6);
1613 write_dr7(svm->host_dr7);
1614 kvm_write_cr2(svm->host_cr2);
1616 load_fs(fs_selector);
1617 load_gs(gs_selector);
1618 load_ldt(ldt_selector);
1619 load_host_msrs(vcpu);
1624 * Profile KVM exit RIPs:
1626 if (unlikely(prof_on == KVM_PROFILING))
1627 profile_hit(KVM_PROFILING,
1628 (void *)(unsigned long)svm->vmcb->save.rip);
1636 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1637 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1638 kvm_run->fail_entry.hardware_entry_failure_reason
1639 = svm->vmcb->control.exit_code;
1640 post_kvm_run_save(svm, kvm_run);
1644 r = handle_exit(svm, kvm_run);
1646 if (dm_request_for_irq_injection(svm, kvm_run)) {
1647 ++vcpu->stat.request_irq_exits;
1648 post_kvm_run_save(svm, kvm_run);
1649 kvm_run->exit_reason = KVM_EXIT_INTR;
1655 post_kvm_run_save(svm, kvm_run);
1659 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1661 struct vcpu_svm *svm = to_svm(vcpu);
1663 svm->vmcb->save.cr3 = root;
1664 force_new_asid(vcpu);
1666 if (vcpu->fpu_active) {
1667 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1668 svm->vmcb->save.cr0 |= X86_CR0_TS;
1669 vcpu->fpu_active = 0;
1673 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1677 struct vcpu_svm *svm = to_svm(vcpu);
1678 uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
1680 ++vcpu->stat.pf_guest;
1682 if (is_page_fault(exit_int_info)) {
1684 svm->vmcb->control.event_inj_err = 0;
1685 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1686 SVM_EVTINJ_VALID_ERR |
1687 SVM_EVTINJ_TYPE_EXEPT |
1692 svm->vmcb->save.cr2 = addr;
1693 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1694 SVM_EVTINJ_VALID_ERR |
1695 SVM_EVTINJ_TYPE_EXEPT |
1697 svm->vmcb->control.event_inj_err = err_code;
1701 static int is_disabled(void)
1705 rdmsrl(MSR_VM_CR, vm_cr);
1706 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1713 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1716 * Patch in the VMMCALL instruction:
1718 hypercall[0] = 0x0f;
1719 hypercall[1] = 0x01;
1720 hypercall[2] = 0xd9;
1721 hypercall[3] = 0xc3;
1724 static void svm_check_processor_compat(void *rtn)
1729 static struct kvm_arch_ops svm_arch_ops = {
1730 .cpu_has_kvm_support = has_svm,
1731 .disabled_by_bios = is_disabled,
1732 .hardware_setup = svm_hardware_setup,
1733 .hardware_unsetup = svm_hardware_unsetup,
1734 .check_processor_compatibility = svm_check_processor_compat,
1735 .hardware_enable = svm_hardware_enable,
1736 .hardware_disable = svm_hardware_disable,
1738 .vcpu_create = svm_create_vcpu,
1739 .vcpu_free = svm_free_vcpu,
1741 .vcpu_load = svm_vcpu_load,
1742 .vcpu_put = svm_vcpu_put,
1743 .vcpu_decache = svm_vcpu_decache,
1745 .set_guest_debug = svm_guest_debug,
1746 .get_msr = svm_get_msr,
1747 .set_msr = svm_set_msr,
1748 .get_segment_base = svm_get_segment_base,
1749 .get_segment = svm_get_segment,
1750 .set_segment = svm_set_segment,
1751 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
1752 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1753 .set_cr0 = svm_set_cr0,
1754 .set_cr3 = svm_set_cr3,
1755 .set_cr4 = svm_set_cr4,
1756 .set_efer = svm_set_efer,
1757 .get_idt = svm_get_idt,
1758 .set_idt = svm_set_idt,
1759 .get_gdt = svm_get_gdt,
1760 .set_gdt = svm_set_gdt,
1761 .get_dr = svm_get_dr,
1762 .set_dr = svm_set_dr,
1763 .cache_regs = svm_cache_regs,
1764 .decache_regs = svm_decache_regs,
1765 .get_rflags = svm_get_rflags,
1766 .set_rflags = svm_set_rflags,
1768 .invlpg = svm_invlpg,
1769 .tlb_flush = svm_flush_tlb,
1770 .inject_page_fault = svm_inject_page_fault,
1772 .inject_gp = svm_inject_gp,
1774 .run = svm_vcpu_run,
1775 .skip_emulated_instruction = skip_emulated_instruction,
1776 .patch_hypercall = svm_patch_hypercall,
1779 static int __init svm_init(void)
1781 return kvm_init_arch(&svm_arch_ops, sizeof(struct vcpu_svm),
1785 static void __exit svm_exit(void)
1790 module_init(svm_init)
1791 module_exit(svm_exit)