drivers/kvm/x86_emulate.c

   1 /******************************************************************************
   2  * x86_emulate.c
   3  *
   4  * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
   5  *
   6  * Copyright (c) 2005 Keir Fraser
   7  *
   8  * Linux coding style, mod r/m decoder, segment base fixes, real-mode
   9  * privileged instructions:
  10  *
  11  * Copyright (C) 2006 Qumranet
  12  *
  13  *   Avi Kivity <avi@qumranet.com>
  14  *   Yaniv Kamay <yaniv@qumranet.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  *
  19  * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
  20  */
  21
  22 #ifndef __KERNEL__
  23 #include <stdio.h>
  24 #include <stdint.h>
  25 #include <public/xen.h>
  26 #define DPRINTF(_f, _a ...) printf( _f , ## _a )
  27 #else
  28 #include "kvm.h"
  29 #define DPRINTF(x...) do {} while (0)
  30 #endif
  31 #include "x86_emulate.h"
  32 #include <linux/module.h>
  33
  34 /*
  35  * Opcode effective-address decode tables.
  36  * Note that we only emulate instructions that have at least one memory
  37  * operand (excluding implicit stack references). We assume that stack
  38  * references and instruction fetches will never occur in special memory
  39  * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
  40  * not be handled.
  41  */
  42
  43 /* Operand sizes: 8-bit operands or specified/overridden size. */
  44 #define ByteOp      (1<<0)      /* 8-bit operands. */
  45 /* Destination operand type. */
  46 #define ImplicitOps (1<<1)      /* Implicit in opcode. No generic decode. */
  47 #define DstReg      (2<<1)      /* Register operand. */
  48 #define DstMem      (3<<1)      /* Memory operand. */
  49 #define DstMask     (3<<1)
  50 /* Source operand type. */
  51 #define SrcNone     (0<<3)      /* No source operand. */
  52 #define SrcImplicit (0<<3)      /* Source operand is implicit in the opcode. */
  53 #define SrcReg      (1<<3)      /* Register operand. */
  54 #define SrcMem      (2<<3)      /* Memory operand. */
  55 #define SrcMem16    (3<<3)      /* Memory operand (16-bit). */
  56 #define SrcMem32    (4<<3)      /* Memory operand (32-bit). */
  57 #define SrcImm      (5<<3)      /* Immediate operand. */
  58 #define SrcImmByte  (6<<3)      /* 8-bit sign-extended immediate operand. */
  59 #define SrcMask     (7<<3)
  60 /* Generic ModRM decode. */
  61 #define ModRM       (1<<6)
  62 /* Destination is only written; never read. */
  63 #define Mov         (1<<7)
  64 #define BitOp       (1<<8)
  65
  66 static u8 opcode_table[256] = {
  67         /* 0x00 - 0x07 */
  68         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  69         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  70         0, 0, 0, 0,
  71         /* 0x08 - 0x0F */
  72         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  73         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  74         0, 0, 0, 0,
  75         /* 0x10 - 0x17 */
  76         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  77         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  78         0, 0, 0, 0,
  79         /* 0x18 - 0x1F */
  80         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  81         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  82         0, 0, 0, 0,
  83         /* 0x20 - 0x27 */
  84         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  85         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  86         SrcImmByte, SrcImm, 0, 0,
  87         /* 0x28 - 0x2F */
  88         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  89         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  90         0, 0, 0, 0,
  91         /* 0x30 - 0x37 */
  92         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  93         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  94         0, 0, 0, 0,
  95         /* 0x38 - 0x3F */
  96         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  97         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  98         0, 0, 0, 0,
  99         /* 0x40 - 0x4F */
 100         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 101         /* 0x50 - 0x57 */
 102         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 103         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 104         /* 0x58 - 0x5F */
 105         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 106         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 107         /* 0x60 - 0x67 */
 108         0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
 109         0, 0, 0, 0,
 110         /* 0x68 - 0x6F */
 111         0, 0, ImplicitOps|Mov, 0,
 112         SrcNone  | ByteOp  | ImplicitOps, SrcNone  | ImplicitOps, /* insb, insw/insd */
 113         SrcNone  | ByteOp  | ImplicitOps, SrcNone  | ImplicitOps, /* outsb, outsw/outsd */
 114         /* 0x70 - 0x77 */
 115         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 116         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 117         /* 0x78 - 0x7F */
 118         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 119         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 120         /* 0x80 - 0x87 */
 121         ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
 122         ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
 123         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
 124         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
 125         /* 0x88 - 0x8F */
 126         ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
 127         ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 128         0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
 129         /* 0x90 - 0x9F */
 130         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
 131         /* 0xA0 - 0xA7 */
 132         ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
 133         ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
 134         ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
 135         ByteOp | ImplicitOps, ImplicitOps,
 136         /* 0xA8 - 0xAF */
 137         0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
 138         ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
 139         ByteOp | ImplicitOps, ImplicitOps,
 140         /* 0xB0 - 0xBF */
 141         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 142         /* 0xC0 - 0xC7 */
 143         ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
 144         0, ImplicitOps, 0, 0,
 145         ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
 146         /* 0xC8 - 0xCF */
 147         0, 0, 0, 0, 0, 0, 0, 0,
 148         /* 0xD0 - 0xD7 */
 149         ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
 150         ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
 151         0, 0, 0, 0,
 152         /* 0xD8 - 0xDF */
 153         0, 0, 0, 0, 0, 0, 0, 0,
 154         /* 0xE0 - 0xE7 */
 155         0, 0, 0, 0, 0, 0, 0, 0,
 156         /* 0xE8 - 0xEF */
 157         ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
 158         /* 0xF0 - 0xF7 */
 159         0, 0, 0, 0,
 160         ImplicitOps, 0,
 161         ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
 162         /* 0xF8 - 0xFF */
 163         0, 0, 0, 0,
 164         0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
 165 };
 166
 167 static u16 twobyte_table[256] = {
 168         /* 0x00 - 0x0F */
 169         0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
 170         ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
 171         /* 0x10 - 0x1F */
 172         0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
 173         /* 0x20 - 0x2F */
 174         ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
 175         0, 0, 0, 0, 0, 0, 0, 0,
 176         /* 0x30 - 0x3F */
 177         ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 178         /* 0x40 - 0x47 */
 179         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 180         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 181         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 182         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 183         /* 0x48 - 0x4F */
 184         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 185         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 186         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 187         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 188         /* 0x50 - 0x5F */
 189         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 190         /* 0x60 - 0x6F */
 191         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 192         /* 0x70 - 0x7F */
 193         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 194         /* 0x80 - 0x8F */
 195         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 196         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 197         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 198         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 199         /* 0x90 - 0x9F */
 200         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 201         /* 0xA0 - 0xA7 */
 202         0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
 203         /* 0xA8 - 0xAF */
 204         0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
 205         /* 0xB0 - 0xB7 */
 206         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
 207             DstMem | SrcReg | ModRM | BitOp,
 208         0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
 209             DstReg | SrcMem16 | ModRM | Mov,
 210         /* 0xB8 - 0xBF */
 211         0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
 212         0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
 213             DstReg | SrcMem16 | ModRM | Mov,
 214         /* 0xC0 - 0xCF */
 215         0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
 216         0, 0, 0, 0, 0, 0, 0, 0,
 217         /* 0xD0 - 0xDF */
 218         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 219         /* 0xE0 - 0xEF */
 220         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 221         /* 0xF0 - 0xFF */
 222         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 223 };
 224
 225 /* EFLAGS bit definitions. */
 226 #define EFLG_OF (1<<11)
 227 #define EFLG_DF (1<<10)
 228 #define EFLG_SF (1<<7)
 229 #define EFLG_ZF (1<<6)
 230 #define EFLG_AF (1<<4)
 231 #define EFLG_PF (1<<2)
 232 #define EFLG_CF (1<<0)
 233
 234 /*
 235  * Instruction emulation:
 236  * Most instructions are emulated directly via a fragment of inline assembly
 237  * code. This allows us to save/restore EFLAGS and thus very easily pick up
 238  * any modified flags.
 239  */
 240
 241 #if defined(CONFIG_X86_64)
 242 #define _LO32 "k"               /* force 32-bit operand */
 243 #define _STK  "%%rsp"           /* stack pointer */
 244 #elif defined(__i386__)
 245 #define _LO32 ""                /* force 32-bit operand */
 246 #define _STK  "%%esp"           /* stack pointer */
 247 #endif
 248
 249 /*
 250  * These EFLAGS bits are restored from saved value during emulation, and
 251  * any changes are written back to the saved value after emulation.
 252  */
 253 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
 254
 255 /* Before executing instruction: restore necessary bits in EFLAGS. */
 256 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
 257         /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */        \
 258         "push %"_sav"; "                                        \
 259         "movl %"_msk",%"_LO32 _tmp"; "                          \
 260         "andl %"_LO32 _tmp",("_STK"); "                         \
 261         "pushf; "                                               \
 262         "notl %"_LO32 _tmp"; "                                  \
 263         "andl %"_LO32 _tmp",("_STK"); "                         \
 264         "pop  %"_tmp"; "                                        \
 265         "orl  %"_LO32 _tmp",("_STK"); "                         \
 266         "popf; "                                                \
 267         /* _sav &= ~msk; */                                     \
 268         "movl %"_msk",%"_LO32 _tmp"; "                          \
 269         "notl %"_LO32 _tmp"; "                                  \
 270         "andl %"_LO32 _tmp",%"_sav"; "
 271
 272 /* After executing instruction: write-back necessary bits in EFLAGS. */
 273 #define _POST_EFLAGS(_sav, _msk, _tmp) \
 274         /* _sav |= EFLAGS & _msk; */            \
 275         "pushf; "                               \
 276         "pop  %"_tmp"; "                        \
 277         "andl %"_msk",%"_LO32 _tmp"; "          \
 278         "orl  %"_LO32 _tmp",%"_sav"; "
 279
 280 /* Raw emulation: instruction has two explicit operands. */
 281 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
 282         do {                                                                \
 283                 unsigned long _tmp;                                         \
 284                                                                             \
 285                 switch ((_dst).bytes) {                                     \
 286                 case 2:                                                     \
 287                         __asm__ __volatile__ (                              \
 288                                 _PRE_EFLAGS("0","4","2")                    \
 289                                 _op"w %"_wx"3,%1; "                         \
 290                                 _POST_EFLAGS("0","4","2")                   \
 291                                 : "=m" (_eflags), "=m" ((_dst).val),        \
 292                                   "=&r" (_tmp)                              \
 293                                 : _wy ((_src).val), "i" (EFLAGS_MASK) );    \
 294                         break;                                              \
 295                 case 4:                                                     \
 296                         __asm__ __volatile__ (                              \
 297                                 _PRE_EFLAGS("0","4","2")                    \
 298                                 _op"l %"_lx"3,%1; "                         \
 299                                 _POST_EFLAGS("0","4","2")                   \
 300                                 : "=m" (_eflags), "=m" ((_dst).val),        \
 301                                   "=&r" (_tmp)                              \
 302                                 : _ly ((_src).val), "i" (EFLAGS_MASK) );    \
 303                         break;                                              \
 304                 case 8:                                                     \
 305                         __emulate_2op_8byte(_op, _src, _dst,                \
 306                                             _eflags, _qx, _qy);             \
 307                         break;                                              \
 308                 }                                                           \
 309         } while (0)
 310
 311 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
 312         do {                                                                 \
 313                 unsigned long _tmp;                                          \
 314                 switch ( (_dst).bytes )                                      \
 315                 {                                                            \
 316                 case 1:                                                      \
 317                         __asm__ __volatile__ (                               \
 318                                 _PRE_EFLAGS("0","4","2")                     \
 319                                 _op"b %"_bx"3,%1; "                          \
 320                                 _POST_EFLAGS("0","4","2")                    \
 321                                 : "=m" (_eflags), "=m" ((_dst).val),         \
 322                                   "=&r" (_tmp)                               \
 323                                 : _by ((_src).val), "i" (EFLAGS_MASK) );     \
 324                         break;                                               \
 325                 default:                                                     \
 326                         __emulate_2op_nobyte(_op, _src, _dst, _eflags,       \
 327                                              _wx, _wy, _lx, _ly, _qx, _qy);  \
 328                         break;                                               \
 329                 }                                                            \
 330         } while (0)
 331
 332 /* Source operand is byte-sized and may be restricted to just %cl. */
 333 #define emulate_2op_SrcB(_op, _src, _dst, _eflags)                      \
 334         __emulate_2op(_op, _src, _dst, _eflags,                         \
 335                       "b", "c", "b", "c", "b", "c", "b", "c")
 336
 337 /* Source operand is byte, word, long or quad sized. */
 338 #define emulate_2op_SrcV(_op, _src, _dst, _eflags)                      \
 339         __emulate_2op(_op, _src, _dst, _eflags,                         \
 340                       "b", "q", "w", "r", _LO32, "r", "", "r")
 341
 342 /* Source operand is word, long or quad sized. */
 343 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags)               \
 344         __emulate_2op_nobyte(_op, _src, _dst, _eflags,                  \
 345                              "w", "r", _LO32, "r", "", "r")
 346
 347 /* Instruction has only one explicit operand (no source operand). */
 348 #define emulate_1op(_op, _dst, _eflags)                                    \
 349         do {                                                            \
 350                 unsigned long _tmp;                                     \
 351                                                                         \
 352                 switch ( (_dst).bytes )                                 \
 353                 {                                                       \
 354                 case 1:                                                 \
 355                         __asm__ __volatile__ (                          \
 356                                 _PRE_EFLAGS("0","3","2")                \
 357                                 _op"b %1; "                             \
 358                                 _POST_EFLAGS("0","3","2")               \
 359                                 : "=m" (_eflags), "=m" ((_dst).val),    \
 360                                   "=&r" (_tmp)                          \
 361                                 : "i" (EFLAGS_MASK) );                  \
 362                         break;                                          \
 363                 case 2:                                                 \
 364                         __asm__ __volatile__ (                          \
 365                                 _PRE_EFLAGS("0","3","2")                \
 366                                 _op"w %1; "                             \
 367                                 _POST_EFLAGS("0","3","2")               \
 368                                 : "=m" (_eflags), "=m" ((_dst).val),    \
 369                                   "=&r" (_tmp)                          \
 370                                 : "i" (EFLAGS_MASK) );                  \
 371                         break;                                          \
 372                 case 4:                                                 \
 373                         __asm__ __volatile__ (                          \
 374                                 _PRE_EFLAGS("0","3","2")                \
 375                                 _op"l %1; "                             \
 376                                 _POST_EFLAGS("0","3","2")               \
 377                                 : "=m" (_eflags), "=m" ((_dst).val),    \
 378                                   "=&r" (_tmp)                          \
 379                                 : "i" (EFLAGS_MASK) );                  \
 380                         break;                                          \
 381                 case 8:                                                 \
 382                         __emulate_1op_8byte(_op, _dst, _eflags);        \
 383                         break;                                          \
 384                 }                                                       \
 385         } while (0)
 386
 387 /* Emulate an instruction with quadword operands (x86/64 only). */
 388 #if defined(CONFIG_X86_64)
 389 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)           \
 390         do {                                                              \
 391                 __asm__ __volatile__ (                                    \
 392                         _PRE_EFLAGS("0","4","2")                          \
 393                         _op"q %"_qx"3,%1; "                               \
 394                         _POST_EFLAGS("0","4","2")                         \
 395                         : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
 396                         : _qy ((_src).val), "i" (EFLAGS_MASK) );          \
 397         } while (0)
 398
 399 #define __emulate_1op_8byte(_op, _dst, _eflags)                           \
 400         do {                                                              \
 401                 __asm__ __volatile__ (                                    \
 402                         _PRE_EFLAGS("0","3","2")                          \
 403                         _op"q %1; "                                       \
 404                         _POST_EFLAGS("0","3","2")                         \
 405                         : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
 406                         : "i" (EFLAGS_MASK) );                            \
 407         } while (0)
 408
 409 #elif defined(__i386__)
 410 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
 411 #define __emulate_1op_8byte(_op, _dst, _eflags)
 412 #endif                          /* __i386__ */
 413
 414 /* Fetch next part of the instruction being emulated. */
 415 #define insn_fetch(_type, _size, _eip)                                  \
 416 ({      unsigned long _x;                                               \
 417         rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x,  \
 418                                                   (_size), ctxt->vcpu); \
 419         if ( rc != 0 )                                                  \
 420                 goto done;                                              \
 421         (_eip) += (_size);                                              \
 422         (_type)_x;                                                      \
 423 })
 424
 425 /* Access/update address held in a register, based on addressing mode. */
 426 #define address_mask(reg)                                               \
 427         ((c->ad_bytes == sizeof(unsigned long)) ?                       \
 428                 (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1)))
 429 #define register_address(base, reg)                                     \
 430         ((base) + address_mask(reg))
 431 #define register_address_increment(reg, inc)                            \
 432         do {                                                            \
 433                 /* signed type ensures sign extension to long */        \
 434                 int _inc = (inc);                                       \
 435                 if (c->ad_bytes == sizeof(unsigned long))               \
 436                         (reg) += _inc;                                  \
 437                 else                                                    \
 438                         (reg) = ((reg) &                                \
 439                                  ~((1UL << (c->ad_bytes << 3)) - 1)) |  \
 440                                 (((reg) + _inc) &                       \
 441                                  ((1UL << (c->ad_bytes << 3)) - 1));    \
 442         } while (0)
 443
 444 #define JMP_REL(rel)                                                    \
 445         do {                                                            \
 446                 register_address_increment(c->eip, rel);                \
 447         } while (0)
 448
 449 /*
 450  * Given the 'reg' portion of a ModRM byte, and a register block, return a
 451  * pointer into the block that addresses the relevant register.
 452  * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 453  */
 454 static void *decode_register(u8 modrm_reg, unsigned long *regs,
 455                              int highbyte_regs)
 456 {
 457         void *p;
 458
 459         p = &regs[modrm_reg];
 460         if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
 461                 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
 462         return p;
 463 }
 464
 465 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
 466                            struct x86_emulate_ops *ops,
 467                            void *ptr,
 468                            u16 *size, unsigned long *address, int op_bytes)
 469 {
 470         int rc;
 471
 472         if (op_bytes == 2)
 473                 op_bytes = 3;
 474         *address = 0;
 475         rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
 476                            ctxt->vcpu);
 477         if (rc)
 478                 return rc;
 479         rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
 480                            ctxt->vcpu);
 481         return rc;
 482 }
 483
 484 static int test_cc(unsigned int condition, unsigned int flags)
 485 {
 486         int rc = 0;
 487
 488         switch ((condition & 15) >> 1) {
 489         case 0: /* o */
 490                 rc |= (flags & EFLG_OF);
 491                 break;
 492         case 1: /* b/c/nae */
 493                 rc |= (flags & EFLG_CF);
 494                 break;
 495         case 2: /* z/e */
 496                 rc |= (flags & EFLG_ZF);
 497                 break;
 498         case 3: /* be/na */
 499                 rc |= (flags & (EFLG_CF|EFLG_ZF));
 500                 break;
 501         case 4: /* s */
 502                 rc |= (flags & EFLG_SF);
 503                 break;
 504         case 5: /* p/pe */
 505                 rc |= (flags & EFLG_PF);
 506                 break;
 507         case 7: /* le/ng */
 508                 rc |= (flags & EFLG_ZF);
 509                 /* fall through */
 510         case 6: /* l/nge */
 511                 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
 512                 break;
 513         }
 514
 515         /* Odd condition identifiers (lsb == 1) have inverted sense. */
 516         return (!!rc ^ (condition & 1));
 517 }
 518
 519 int
 520 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
 521 {
 522         struct decode_cache *c = &ctxt->decode;
 523         u8 sib, rex_prefix = 0;
 524         unsigned int i;
 525         int rc = 0;
 526         int mode = ctxt->mode;
 527         int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
 528
 529         /* Shadow copy of register state. Committed on successful emulation. */
 530
 531         memset(c, 0, sizeof(struct decode_cache));
 532         c->eip = ctxt->vcpu->rip;
 533         memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
 534
 535         switch (mode) {
 536         case X86EMUL_MODE_REAL:
 537         case X86EMUL_MODE_PROT16:
 538                 c->op_bytes = c->ad_bytes = 2;
 539                 break;
 540         case X86EMUL_MODE_PROT32:
 541                 c->op_bytes = c->ad_bytes = 4;
 542                 break;
 543 #ifdef CONFIG_X86_64
 544         case X86EMUL_MODE_PROT64:
 545                 c->op_bytes = 4;
 546                 c->ad_bytes = 8;
 547                 break;
 548 #endif
 549         default:
 550                 return -1;
 551         }
 552
 553         /* Legacy prefixes. */
 554         for (i = 0; i < 8; i++) {
 555                 switch (c->b = insn_fetch(u8, 1, c->eip)) {
 556                 case 0x66:      /* operand-size override */
 557                         c->op_bytes ^= 6;       /* switch between 2/4 bytes */
 558                         break;
 559                 case 0x67:      /* address-size override */
 560                         if (mode == X86EMUL_MODE_PROT64)
 561                                 /* switch between 4/8 bytes */
 562                                 c->ad_bytes ^= 12;
 563                         else
 564                                 /* switch between 2/4 bytes */
 565                                 c->ad_bytes ^= 6;
 566                         break;
 567                 case 0x2e:      /* CS override */
 568                         c->override_base = &ctxt->cs_base;
 569                         break;
 570                 case 0x3e:      /* DS override */
 571                         c->override_base = &ctxt->ds_base;
 572                         break;
 573                 case 0x26:      /* ES override */
 574                         c->override_base = &ctxt->es_base;
 575                         break;
 576                 case 0x64:      /* FS override */
 577                         c->override_base = &ctxt->fs_base;
 578                         break;
 579                 case 0x65:      /* GS override */
 580                         c->override_base = &ctxt->gs_base;
 581                         break;
 582                 case 0x36:      /* SS override */
 583                         c->override_base = &ctxt->ss_base;
 584                         break;
 585                 case 0xf0:      /* LOCK */
 586                         c->lock_prefix = 1;
 587                         break;
 588                 case 0xf2:      /* REPNE/REPNZ */
 589                 case 0xf3:      /* REP/REPE/REPZ */
 590                         c->rep_prefix = 1;
 591                         break;
 592                 default:
 593                         goto done_prefixes;
 594                 }
 595         }
 596
 597 done_prefixes:
 598
 599         /* REX prefix. */
 600         if ((mode == X86EMUL_MODE_PROT64) && ((c->b & 0xf0) == 0x40)) {
 601                 rex_prefix = c->b;
 602                 if (c->b & 8)
 603                         c->op_bytes = 8;        /* REX.W */
 604                 c->modrm_reg = (c->b & 4) << 1; /* REX.R */
 605                 index_reg = (c->b & 2) << 2; /* REX.X */
 606                 c->modrm_rm = base_reg = (c->b & 1) << 3; /* REG.B */
 607                 c->b = insn_fetch(u8, 1, c->eip);
 608         }
 609
 610         /* Opcode byte(s). */
 611         c->d = opcode_table[c->b];
 612         if (c->d == 0) {
 613                 /* Two-byte opcode? */
 614                 if (c->b == 0x0f) {
 615                         c->twobyte = 1;
 616                         c->b = insn_fetch(u8, 1, c->eip);
 617                         c->d = twobyte_table[c->b];
 618                 }
 619
 620                 /* Unrecognised? */
 621                 if (c->d == 0) {
 622                         DPRINTF("Cannot emulate %02x\n", c->b);
 623                         return -1;
 624                 }
 625         }
 626
 627         /* ModRM and SIB bytes. */
 628         if (c->d & ModRM) {
 629                 c->modrm = insn_fetch(u8, 1, c->eip);
 630                 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
 631                 c->modrm_reg |= (c->modrm & 0x38) >> 3;
 632                 c->modrm_rm |= (c->modrm & 0x07);
 633                 c->modrm_ea = 0;
 634                 c->use_modrm_ea = 1;
 635
 636                 if (c->modrm_mod == 3) {
 637                         c->modrm_val = *(unsigned long *)
 638                           decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
 639                         goto modrm_done;
 640                 }
 641
 642                 if (c->ad_bytes == 2) {
 643                         unsigned bx = c->regs[VCPU_REGS_RBX];
 644                         unsigned bp = c->regs[VCPU_REGS_RBP];
 645                         unsigned si = c->regs[VCPU_REGS_RSI];
 646                         unsigned di = c->regs[VCPU_REGS_RDI];
 647
 648                         /* 16-bit ModR/M decode. */
 649                         switch (c->modrm_mod) {
 650                         case 0:
 651                                 if (c->modrm_rm == 6)
 652                                         c->modrm_ea +=
 653                                                 insn_fetch(u16, 2, c->eip);
 654                                 break;
 655                         case 1:
 656                                 c->modrm_ea += insn_fetch(s8, 1, c->eip);
 657                                 break;
 658                         case 2:
 659                                 c->modrm_ea += insn_fetch(u16, 2, c->eip);
 660                                 break;
 661                         }
 662                         switch (c->modrm_rm) {
 663                         case 0:
 664                                 c->modrm_ea += bx + si;
 665                                 break;
 666                         case 1:
 667                                 c->modrm_ea += bx + di;
 668                                 break;
 669                         case 2:
 670                                 c->modrm_ea += bp + si;
 671                                 break;
 672                         case 3:
 673                                 c->modrm_ea += bp + di;
 674                                 break;
 675                         case 4:
 676                                 c->modrm_ea += si;
 677                                 break;
 678                         case 5:
 679                                 c->modrm_ea += di;
 680                                 break;
 681                         case 6:
 682                                 if (c->modrm_mod != 0)
 683                                         c->modrm_ea += bp;
 684                                 break;
 685                         case 7:
 686                                 c->modrm_ea += bx;
 687                                 break;
 688                         }
 689                         if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
 690                             (c->modrm_rm == 6 && c->modrm_mod != 0))
 691                                 if (!c->override_base)
 692                                         c->override_base = &ctxt->ss_base;
 693                         c->modrm_ea = (u16)c->modrm_ea;
 694                 } else {
 695                         /* 32/64-bit ModR/M decode. */
 696                         switch (c->modrm_rm) {
 697                         case 4:
 698                         case 12:
 699                                 sib = insn_fetch(u8, 1, c->eip);
 700                                 index_reg |= (sib >> 3) & 7;
 701                                 base_reg |= sib & 7;
 702                                 scale = sib >> 6;
 703
 704                                 switch (base_reg) {
 705                                 case 5:
 706                                         if (c->modrm_mod != 0)
 707                                                 c->modrm_ea +=
 708                                                         c->regs[base_reg];
 709                                         else
 710                                                 c->modrm_ea +=
 711                                                     insn_fetch(s32, 4, c->eip);
 712                                         break;
 713                                 default:
 714                                         c->modrm_ea += c->regs[base_reg];
 715                                 }
 716                                 switch (index_reg) {
 717                                 case 4:
 718                                         break;
 719                                 default:
 720                                         c->modrm_ea +=
 721                                                 c->regs[index_reg] << scale;
 722
 723                                 }
 724                                 break;
 725                         case 5:
 726                                 if (c->modrm_mod != 0)
 727                                         c->modrm_ea += c->regs[c->modrm_rm];
 728                                 else if (mode == X86EMUL_MODE_PROT64)
 729                                         rip_relative = 1;
 730                                 break;
 731                         default:
 732                                 c->modrm_ea += c->regs[c->modrm_rm];
 733                                 break;
 734                         }
 735                         switch (c->modrm_mod) {
 736                         case 0:
 737                                 if (c->modrm_rm == 5)
 738                                         c->modrm_ea +=
 739                                                 insn_fetch(s32, 4, c->eip);
 740                                 break;
 741                         case 1:
 742                                 c->modrm_ea += insn_fetch(s8, 1, c->eip);
 743                                 break;
 744                         case 2:
 745                                 c->modrm_ea += insn_fetch(s32, 4, c->eip);
 746                                 break;
 747                         }
 748                 }
 749                 if (!c->override_base)
 750                         c->override_base = &ctxt->ds_base;
 751                 if (mode == X86EMUL_MODE_PROT64 &&
 752                     c->override_base != &ctxt->fs_base &&
 753                     c->override_base != &ctxt->gs_base)
 754                         c->override_base = NULL;
 755
 756                 if (c->override_base)
 757                         c->modrm_ea += *c->override_base;
 758
 759                 if (rip_relative) {
 760                         c->modrm_ea += c->eip;
 761                         switch (c->d & SrcMask) {
 762                         case SrcImmByte:
 763                                 c->modrm_ea += 1;
 764                                 break;
 765                         case SrcImm:
 766                                 if (c->d & ByteOp)
 767                                         c->modrm_ea += 1;
 768                                 else
 769                                         if (c->op_bytes == 8)
 770                                                 c->modrm_ea += 4;
 771                                         else
 772                                                 c->modrm_ea += c->op_bytes;
 773                         }
 774                 }
 775                 if (c->ad_bytes != 8)
 776                         c->modrm_ea = (u32)c->modrm_ea;
 777         modrm_done:
 778                 ;
 779         }
 780
 781         /*
 782          * Decode and fetch the source operand: register, memory
 783          * or immediate.
 784          */
 785         switch (c->d & SrcMask) {
 786         case SrcNone:
 787                 break;
 788         case SrcReg:
 789                 c->src.type = OP_REG;
 790                 if (c->d & ByteOp) {
 791                         c->src.ptr =
 792                                 decode_register(c->modrm_reg, c->regs,
 793                                                   (rex_prefix == 0));
 794                         c->src.val = c->src.orig_val = *(u8 *)c->src.ptr;
 795                         c->src.bytes = 1;
 796                 } else {
 797                         c->src.ptr =
 798                             decode_register(c->modrm_reg, c->regs, 0);
 799                         switch ((c->src.bytes = c->op_bytes)) {
 800                         case 2:
 801                                 c->src.val = c->src.orig_val =
 802                                                        *(u16 *) c->src.ptr;
 803                                 break;
 804                         case 4:
 805                                 c->src.val = c->src.orig_val =
 806                                                        *(u32 *) c->src.ptr;
 807                                 break;
 808                         case 8:
 809                                 c->src.val = c->src.orig_val =
 810                                                        *(u64 *) c->src.ptr;
 811                                 break;
 812                         }
 813                 }
 814                 break;
 815         case SrcMem16:
 816                 c->src.bytes = 2;
 817                 goto srcmem_common;
 818         case SrcMem32:
 819                 c->src.bytes = 4;
 820                 goto srcmem_common;
 821         case SrcMem:
 822                 c->src.bytes = (c->d & ByteOp) ? 1 :
 823                                                            c->op_bytes;
 824                 /* Don't fetch the address for invlpg: it could be unmapped. */
 825                 if (c->twobyte && c->b == 0x01
 826                                     && c->modrm_reg == 7)
 827                         break;
 828               srcmem_common:
 829                 /*
 830                  * For instructions with a ModR/M byte, switch to register
 831                  * access if Mod = 3.
 832                  */
 833                 if ((c->d & ModRM) && c->modrm_mod == 3) {
 834                         c->src.type = OP_REG;
 835                         break;
 836                 }
 837                 c->src.type = OP_MEM;
 838                 break;
 839         case SrcImm:
 840                 c->src.type = OP_IMM;
 841                 c->src.ptr = (unsigned long *)c->eip;
 842                 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
 843                 if (c->src.bytes == 8)
 844                         c->src.bytes = 4;
 845                 /* NB. Immediates are sign-extended as necessary. */
 846                 switch (c->src.bytes) {
 847                 case 1:
 848                         c->src.val = insn_fetch(s8, 1, c->eip);
 849                         break;
 850                 case 2:
 851                         c->src.val = insn_fetch(s16, 2, c->eip);
 852                         break;
 853                 case 4:
 854                         c->src.val = insn_fetch(s32, 4, c->eip);
 855                         break;
 856                 }
 857                 break;
 858         case SrcImmByte:
 859                 c->src.type = OP_IMM;
 860                 c->src.ptr = (unsigned long *)c->eip;
 861                 c->src.bytes = 1;
 862                 c->src.val = insn_fetch(s8, 1, c->eip);
 863                 break;
 864         }
 865
 866         /* Decode and fetch the destination operand: register or memory. */
 867         switch (c->d & DstMask) {
 868         case ImplicitOps:
 869                 /* Special instructions do their own operand decoding. */
 870                 return 0;
 871         case DstReg:
 872                 c->dst.type = OP_REG;
 873                 if ((c->d & ByteOp)
 874                     && !(c->twobyte &&
 875                         (c->b == 0xb6 || c->b == 0xb7))) {
 876                         c->dst.ptr =
 877                                 decode_register(c->modrm_reg, c->regs,
 878                                                   (rex_prefix == 0));
 879                         c->dst.val = *(u8 *) c->dst.ptr;
 880                         c->dst.bytes = 1;
 881                 } else {
 882                         c->dst.ptr =
 883                             decode_register(c->modrm_reg, c->regs, 0);
 884                         switch ((c->dst.bytes = c->op_bytes)) {
 885                         case 2:
 886                                 c->dst.val = *(u16 *)c->dst.ptr;
 887                                 break;
 888                         case 4:
 889                                 c->dst.val = *(u32 *)c->dst.ptr;
 890                                 break;
 891                         case 8:
 892                                 c->dst.val = *(u64 *)c->dst.ptr;
 893                                 break;
 894                         }
 895                 }
 896                 break;
 897         case DstMem:
 898                 if ((c->d & ModRM) && c->modrm_mod == 3) {
 899                         c->dst.type = OP_REG;
 900                         break;
 901                 }
 902                 c->dst.type = OP_MEM;
 903                 break;
 904         }
 905
 906 done:
 907         return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
 908 }
 909
 910 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
 911 {
 912         struct decode_cache *c = &ctxt->decode;
 913
 914         c->dst.type  = OP_MEM;
 915         c->dst.bytes = c->op_bytes;
 916         c->dst.val = c->src.val;
 917         register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
 918         c->dst.ptr = (void *) register_address(ctxt->ss_base,
 919                                                c->regs[VCPU_REGS_RSP]);
 920 }
 921
 922 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
 923                                 struct x86_emulate_ops *ops)
 924 {
 925         struct decode_cache *c = &ctxt->decode;
 926         int rc;
 927
 928         /* 64-bit mode: POP always pops a 64-bit operand. */
 929
 930         if (ctxt->mode == X86EMUL_MODE_PROT64)
 931                 c->dst.bytes = 8;
 932
 933         rc = ops->read_std(register_address(ctxt->ss_base,
 934                                             c->regs[VCPU_REGS_RSP]),
 935                            &c->dst.val, c->dst.bytes, ctxt->vcpu);
 936         if (rc != 0)
 937                 return rc;
 938
 939         register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
 940
 941         return 0;
 942 }
 943
 944 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
 945 {
 946         struct decode_cache *c = &ctxt->decode;
 947         switch (c->modrm_reg) {
 948         case 0: /* rol */
 949                 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
 950                 break;
 951         case 1: /* ror */
 952                 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
 953                 break;
 954         case 2: /* rcl */
 955                 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
 956                 break;
 957         case 3: /* rcr */
 958                 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
 959                 break;
 960         case 4: /* sal/shl */
 961         case 6: /* sal/shl */
 962                 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
 963                 break;
 964         case 5: /* shr */
 965                 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
 966                 break;
 967         case 7: /* sar */
 968                 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
 969                 break;
 970         }
 971 }
 972
 973 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
 974                                struct x86_emulate_ops *ops)
 975 {
 976         struct decode_cache *c = &ctxt->decode;
 977         int rc = 0;
 978
 979         switch (c->modrm_reg) {
 980         case 0 ... 1:   /* test */
 981                 /*
 982                  * Special case in Grp3: test has an immediate
 983                  * source operand.
 984                  */
 985                 c->src.type = OP_IMM;
 986                 c->src.ptr = (unsigned long *)c->eip;
 987                 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
 988                 if (c->src.bytes == 8)
 989                         c->src.bytes = 4;
 990                 switch (c->src.bytes) {
 991                 case 1:
 992                         c->src.val = insn_fetch(s8, 1, c->eip);
 993                         break;
 994                 case 2:
 995                         c->src.val = insn_fetch(s16, 2, c->eip);
 996                         break;
 997                 case 4:
 998                         c->src.val = insn_fetch(s32, 4, c->eip);
 999                         break;
1000                 }
1001                 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1002                 break;
1003         case 2: /* not */
1004                 c->dst.val = ~c->dst.val;
1005                 break;
1006         case 3: /* neg */
1007                 emulate_1op("neg", c->dst, ctxt->eflags);
1008                 break;
1009         default:
1010                 DPRINTF("Cannot emulate %02x\n", c->b);
1011                 rc = X86EMUL_UNHANDLEABLE;
1012                 break;
1013         }
1014 done:
1015         return rc;
1016 }
1017
1018 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1019                                struct x86_emulate_ops *ops,
1020                                int *no_wb)
1021 {
1022         struct decode_cache *c = &ctxt->decode;
1023         int rc;
1024
1025         switch (c->modrm_reg) {
1026         case 0: /* inc */
1027                 emulate_1op("inc", c->dst, ctxt->eflags);
1028                 break;
1029         case 1: /* dec */
1030                 emulate_1op("dec", c->dst, ctxt->eflags);
1031                 break;
1032         case 4: /* jmp abs */
1033                 if (c->b == 0xff)
1034                         c->eip = c->dst.val;
1035                 else {
1036                         DPRINTF("Cannot emulate %02x\n", c->b);
1037                         return X86EMUL_UNHANDLEABLE;
1038                 }
1039                 break;
1040         case 6: /* push */
1041
1042                 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1043
1044                 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1045                         c->dst.bytes = 8;
1046                         rc = ops->read_std((unsigned long)c->dst.ptr,
1047                                            &c->dst.val, 8, ctxt->vcpu);
1048                         if (rc != 0)
1049                                 return rc;
1050                 }
1051                 register_address_increment(c->regs[VCPU_REGS_RSP],
1052                                            -c->dst.bytes);
1053                 rc = ops->write_emulated(register_address(ctxt->ss_base,
1054                                     c->regs[VCPU_REGS_RSP]), &c->dst.val,
1055                                     c->dst.bytes, ctxt->vcpu);
1056                 if (rc != 0)
1057                         return rc;
1058                 *no_wb = 1;
1059                 break;
1060         default:
1061                 DPRINTF("Cannot emulate %02x\n", c->b);
1062                 return X86EMUL_UNHANDLEABLE;
1063         }
1064         return 0;
1065 }
1066
1067 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1068                                struct x86_emulate_ops *ops,
1069                                unsigned long cr2)
1070 {
1071         struct decode_cache *c = &ctxt->decode;
1072         u64 old, new;
1073         int rc;
1074
1075         rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu);
1076         if (rc != 0)
1077                 return rc;
1078
1079         if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1080             ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1081
1082                 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1083                 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1084                 ctxt->eflags &= ~EFLG_ZF;
1085
1086         } else {
1087                 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1088                        (u32) c->regs[VCPU_REGS_RBX];
1089
1090                 rc = ops->cmpxchg_emulated(cr2, &old, &new, 8, ctxt->vcpu);
1091                 if (rc != 0)
1092                         return rc;
1093                 ctxt->eflags |= EFLG_ZF;
1094         }
1095         return 0;
1096 }
1097
1098 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1099                             struct x86_emulate_ops *ops)
1100 {
1101         int rc;
1102         struct decode_cache *c = &ctxt->decode;
1103
1104         switch (c->dst.type) {
1105         case OP_REG:
1106                 /* The 4-byte case *is* correct:
1107                  * in 64-bit mode we zero-extend.
1108                  */
1109                 switch (c->dst.bytes) {
1110                 case 1:
1111                         *(u8 *)c->dst.ptr = (u8)c->dst.val;
1112                         break;
1113                 case 2:
1114                         *(u16 *)c->dst.ptr = (u16)c->dst.val;
1115                         break;
1116                 case 4:
1117                         *c->dst.ptr = (u32)c->dst.val;
1118                         break;  /* 64b: zero-ext */
1119                 case 8:
1120                         *c->dst.ptr = c->dst.val;
1121                         break;
1122                 }
1123                 break;
1124         case OP_MEM:
1125                 if (c->lock_prefix)
1126                         rc = ops->cmpxchg_emulated(
1127                                         (unsigned long)c->dst.ptr,
1128                                         &c->dst.orig_val,
1129                                         &c->dst.val,
1130                                         c->dst.bytes,
1131                                         ctxt->vcpu);
1132                 else
1133                         rc = ops->write_emulated(
1134                                         (unsigned long)c->dst.ptr,
1135                                         &c->dst.val,
1136                                         c->dst.bytes,
1137                                         ctxt->vcpu);
1138                 if (rc != 0)
1139                         return rc;
1140         default:
1141                 break;
1142         }
1143         return 0;
1144 }
1145
1146 int
1147 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1148 {
1149         unsigned long cr2 = ctxt->cr2;
1150         int no_wb = 0;
1151         u64 msr_data;
1152         unsigned long saved_eip = 0;
1153         struct decode_cache *c = &ctxt->decode;
1154         int rc = 0;
1155
1156         /* Shadow copy of register state. Committed on successful emulation.
1157          * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1158          * modify them.
1159          */
1160
1161         memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
1162         saved_eip = c->eip;
1163
1164         if ((c->d & ModRM) && (c->modrm_mod != 3))
1165                 cr2 = c->modrm_ea;
1166
1167         if (c->src.type == OP_MEM) {
1168                 c->src.ptr = (unsigned long *)cr2;
1169                 c->src.val = 0;
1170                 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1171                                              &c->src.val,
1172                                              c->src.bytes,
1173                                              ctxt->vcpu)) != 0)
1174                         goto done;
1175                 c->src.orig_val = c->src.val;
1176         }
1177
1178         if ((c->d & DstMask) == ImplicitOps)
1179                 goto special_insn;
1180
1181
1182         if (c->dst.type == OP_MEM) {
1183                 c->dst.ptr = (unsigned long *)cr2;
1184                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1185                 c->dst.val = 0;
1186                 if (c->d & BitOp) {
1187                         unsigned long mask = ~(c->dst.bytes * 8 - 1);
1188
1189                         c->dst.ptr = (void *)c->dst.ptr +
1190                                                    (c->src.val & mask) / 8;
1191                 }
1192                 if (!(c->d & Mov) &&
1193                                    /* optimisation - avoid slow emulated read */
1194                     ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1195                                            &c->dst.val,
1196                                           c->dst.bytes, ctxt->vcpu)) != 0))
1197                         goto done;
1198         }
1199         c->dst.orig_val = c->dst.val;
1200
1201         if (c->twobyte)
1202                 goto twobyte_insn;
1203
1204         switch (c->b) {
1205         case 0x00 ... 0x05:
1206               add:              /* add */
1207                 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1208                 break;
1209         case 0x08 ... 0x0d:
1210               or:               /* or */
1211                 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1212                 break;
1213         case 0x10 ... 0x15:
1214               adc:              /* adc */
1215                 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1216                 break;
1217         case 0x18 ... 0x1d:
1218               sbb:              /* sbb */
1219                 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1220                 break;
1221         case 0x20 ... 0x23:
1222               and:              /* and */
1223                 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1224                 break;
1225         case 0x24:              /* and al imm8 */
1226                 c->dst.type = OP_REG;
1227                 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1228                 c->dst.val = *(u8 *)c->dst.ptr;
1229                 c->dst.bytes = 1;
1230                 c->dst.orig_val = c->dst.val;
1231                 goto and;
1232         case 0x25:              /* and ax imm16, or eax imm32 */
1233                 c->dst.type = OP_REG;
1234                 c->dst.bytes = c->op_bytes;
1235                 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1236                 if (c->op_bytes == 2)
1237                         c->dst.val = *(u16 *)c->dst.ptr;
1238                 else
1239                         c->dst.val = *(u32 *)c->dst.ptr;
1240                 c->dst.orig_val = c->dst.val;
1241                 goto and;
1242         case 0x28 ... 0x2d:
1243               sub:              /* sub */
1244                 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1245                 break;
1246         case 0x30 ... 0x35:
1247               xor:              /* xor */
1248                 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1249                 break;
1250         case 0x38 ... 0x3d:
1251               cmp:              /* cmp */
1252                 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1253                 break;
1254         case 0x63:              /* movsxd */
1255                 if (ctxt->mode != X86EMUL_MODE_PROT64)
1256                         goto cannot_emulate;
1257                 c->dst.val = (s32) c->src.val;
1258                 break;
1259         case 0x80 ... 0x83:     /* Grp1 */
1260                 switch (c->modrm_reg) {
1261                 case 0:
1262                         goto add;
1263                 case 1:
1264                         goto or;
1265                 case 2:
1266                         goto adc;
1267                 case 3:
1268                         goto sbb;
1269                 case 4:
1270                         goto and;
1271                 case 5:
1272                         goto sub;
1273                 case 6:
1274                         goto xor;
1275                 case 7:
1276                         goto cmp;
1277                 }
1278                 break;
1279         case 0x84 ... 0x85:
1280                 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1281                 break;
1282         case 0x86 ... 0x87:     /* xchg */
1283                 /* Write back the register source. */
1284                 switch (c->dst.bytes) {
1285                 case 1:
1286                         *(u8 *) c->src.ptr = (u8) c->dst.val;
1287                         break;
1288                 case 2:
1289                         *(u16 *) c->src.ptr = (u16) c->dst.val;
1290                         break;
1291                 case 4:
1292                         *c->src.ptr = (u32) c->dst.val;
1293                         break;  /* 64b reg: zero-extend */
1294                 case 8:
1295                         *c->src.ptr = c->dst.val;
1296                         break;
1297                 }
1298                 /*
1299                  * Write back the memory destination with implicit LOCK
1300                  * prefix.
1301                  */
1302                 c->dst.val = c->src.val;
1303                 c->lock_prefix = 1;
1304                 break;
1305         case 0x88 ... 0x8b:     /* mov */
1306                 goto mov;
1307         case 0x8d: /* lea r16/r32, m */
1308                 c->dst.val = c->modrm_val;
1309                 break;
1310         case 0x8f:              /* pop (sole member of Grp1a) */
1311                 rc = emulate_grp1a(ctxt, ops);
1312                 if (rc != 0)
1313                         goto done;
1314                 break;
1315         case 0xa0 ... 0xa1:     /* mov */
1316                 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1317                 c->dst.val = c->src.val;
1318                 /* skip src displacement */
1319                 c->eip += c->ad_bytes;
1320                 break;
1321         case 0xa2 ... 0xa3:     /* mov */
1322                 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1323                 /* skip c->dst displacement */
1324                 c->eip += c->ad_bytes;
1325                 break;
1326         case 0xc0 ... 0xc1:
1327                 emulate_grp2(ctxt);
1328                 break;
1329         case 0xc6 ... 0xc7:     /* mov (sole member of Grp11) */
1330         mov:
1331                 c->dst.val = c->src.val;
1332                 break;
1333         case 0xd0 ... 0xd1:     /* Grp2 */
1334                 c->src.val = 1;
1335                 emulate_grp2(ctxt);
1336                 break;
1337         case 0xd2 ... 0xd3:     /* Grp2 */
1338                 c->src.val = c->regs[VCPU_REGS_RCX];
1339                 emulate_grp2(ctxt);
1340                 break;
1341         case 0xf6 ... 0xf7:     /* Grp3 */
1342                 rc = emulate_grp3(ctxt, ops);
1343                 if (rc != 0)
1344                         goto done;
1345                 break;
1346         case 0xfe ... 0xff:     /* Grp4/Grp5 */
1347                 rc = emulate_grp45(ctxt, ops, &no_wb);
1348                 if (rc != 0)
1349                         goto done;
1350                 break;
1351         }
1352
1353 writeback:
1354         if (!no_wb) {
1355                 rc = writeback(ctxt, ops);
1356                 if (rc != 0)
1357                         goto done;
1358         }
1359
1360         /* Commit shadow register state. */
1361         memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs);
1362         ctxt->vcpu->rip = c->eip;
1363
1364 done:
1365         if (rc == X86EMUL_UNHANDLEABLE) {
1366                 c->eip = saved_eip;
1367                 return -1;
1368         }
1369         return 0;
1370
1371 special_insn:
1372         if (c->twobyte)
1373                 goto twobyte_special_insn;
1374         switch (c->b) {
1375         case 0x50 ... 0x57:  /* push reg */
1376                 if (c->op_bytes == 2)
1377                         c->src.val = (u16) c->regs[c->b & 0x7];
1378                 else
1379                         c->src.val = (u32) c->regs[c->b & 0x7];
1380                 c->dst.type  = OP_MEM;
1381                 c->dst.bytes = c->op_bytes;
1382                 c->dst.val = c->src.val;
1383                 register_address_increment(c->regs[VCPU_REGS_RSP],
1384                                            -c->op_bytes);
1385                 c->dst.ptr = (void *) register_address(
1386                         ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
1387                 break;
1388         case 0x58 ... 0x5f: /* pop reg */
1389                 c->dst.ptr = (unsigned long *)&c->regs[c->b & 0x7];
1390         pop_instruction:
1391                 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1392                         c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1393                         c->op_bytes, ctxt->vcpu)) != 0)
1394                         goto done;
1395
1396                 register_address_increment(c->regs[VCPU_REGS_RSP],
1397                                            c->op_bytes);
1398                 no_wb = 1; /* Disable writeback. */
1399                 break;
1400         case 0x6a: /* push imm8 */
1401                 c->src.val = 0L;
1402                 c->src.val = insn_fetch(s8, 1, c->eip);
1403                 emulate_push(ctxt);
1404                 break;
1405         case 0x6c:              /* insb */
1406         case 0x6d:              /* insw/insd */
1407                  if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1408                                 1,
1409                                 (c->d & ByteOp) ? 1 : c->op_bytes,
1410                                 c->rep_prefix ?
1411                                 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1412                                 (ctxt->eflags & EFLG_DF),
1413                                 register_address(ctxt->es_base,
1414                                                  c->regs[VCPU_REGS_RDI]),
1415                                 c->rep_prefix,
1416                                 c->regs[VCPU_REGS_RDX]) == 0) {
1417                         c->eip = saved_eip;
1418                         return -1;
1419                 }
1420                 return 0;
1421         case 0x6e:              /* outsb */
1422         case 0x6f:              /* outsw/outsd */
1423                 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1424                                 0,
1425                                 (c->d & ByteOp) ? 1 : c->op_bytes,
1426                                 c->rep_prefix ?
1427                                 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1428                                 (ctxt->eflags & EFLG_DF),
1429                                 register_address(c->override_base ?
1430                                                         *c->override_base :
1431                                                         ctxt->ds_base,
1432                                                  c->regs[VCPU_REGS_RSI]),
1433                                 c->rep_prefix,
1434                                 c->regs[VCPU_REGS_RDX]) == 0) {
1435                         c->eip = saved_eip;
1436                         return -1;
1437                 }
1438                 return 0;
1439         case 0x70 ... 0x7f: /* jcc (short) */ {
1440                 int rel = insn_fetch(s8, 1, c->eip);
1441
1442                 if (test_cc(c->b, ctxt->eflags))
1443                 JMP_REL(rel);
1444                 break;
1445         }
1446         case 0x9c: /* pushf */
1447                 c->src.val =  (unsigned long) ctxt->eflags;
1448                 emulate_push(ctxt);
1449                 break;
1450         case 0x9d: /* popf */
1451                 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1452                 goto pop_instruction;
1453         case 0xc3: /* ret */
1454                 c->dst.ptr = &c->eip;
1455                 goto pop_instruction;
1456         case 0xf4:              /* hlt */
1457                 ctxt->vcpu->halt_request = 1;
1458                 goto done;
1459         }
1460         if (c->rep_prefix) {
1461                 if (c->regs[VCPU_REGS_RCX] == 0) {
1462                         ctxt->vcpu->rip = c->eip;
1463                         goto done;
1464                 }
1465                 c->regs[VCPU_REGS_RCX]--;
1466                 c->eip = ctxt->vcpu->rip;
1467         }
1468         switch (c->b) {
1469         case 0xa4 ... 0xa5:     /* movs */
1470                 c->dst.type = OP_MEM;
1471                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1472                 c->dst.ptr = (unsigned long *)register_address(
1473                                                    ctxt->es_base,
1474                                                    c->regs[VCPU_REGS_RDI]);
1475                 if ((rc = ops->read_emulated(register_address(
1476                       c->override_base ? *c->override_base :
1477                                         ctxt->ds_base,
1478                                         c->regs[VCPU_REGS_RSI]),
1479                                         &c->dst.val,
1480                                         c->dst.bytes, ctxt->vcpu)) != 0)
1481                         goto done;
1482                 register_address_increment(c->regs[VCPU_REGS_RSI],
1483                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1484                                                            : c->dst.bytes);
1485                 register_address_increment(c->regs[VCPU_REGS_RDI],
1486                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1487                                                            : c->dst.bytes);
1488                 break;
1489         case 0xa6 ... 0xa7:     /* cmps */
1490                 DPRINTF("Urk! I don't handle CMPS.\n");
1491                 goto cannot_emulate;
1492         case 0xaa ... 0xab:     /* stos */
1493                 c->dst.type = OP_MEM;
1494                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1495                 c->dst.ptr = (unsigned long *)cr2;
1496                 c->dst.val = c->regs[VCPU_REGS_RAX];
1497                 register_address_increment(c->regs[VCPU_REGS_RDI],
1498                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1499                                                            : c->dst.bytes);
1500                 break;
1501         case 0xac ... 0xad:     /* lods */
1502                 c->dst.type = OP_REG;
1503                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1504                 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1505                 if ((rc = ops->read_emulated(cr2, &c->dst.val,
1506                                              c->dst.bytes,
1507                                              ctxt->vcpu)) != 0)
1508                         goto done;
1509                 register_address_increment(c->regs[VCPU_REGS_RSI],
1510                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1511                                                            : c->dst.bytes);
1512                 break;
1513         case 0xae ... 0xaf:     /* scas */
1514                 DPRINTF("Urk! I don't handle SCAS.\n");
1515                 goto cannot_emulate;
1516         case 0xe8: /* call (near) */ {
1517                 long int rel;
1518                 switch (c->op_bytes) {
1519                 case 2:
1520                         rel = insn_fetch(s16, 2, c->eip);
1521                         break;
1522                 case 4:
1523                         rel = insn_fetch(s32, 4, c->eip);
1524                         break;
1525                 case 8:
1526                         rel = insn_fetch(s64, 8, c->eip);
1527                         break;
1528                 default:
1529                         DPRINTF("Call: Invalid op_bytes\n");
1530                         goto cannot_emulate;
1531                 }
1532                 c->src.val = (unsigned long) c->eip;
1533                 JMP_REL(rel);
1534                 c->op_bytes = c->ad_bytes;
1535                 emulate_push(ctxt);
1536                 break;
1537         }
1538         case 0xe9: /* jmp rel */
1539         case 0xeb: /* jmp rel short */
1540                 JMP_REL(c->src.val);
1541                 no_wb = 1; /* Disable writeback. */
1542                 break;
1543
1544
1545         }
1546         goto writeback;
1547
1548 twobyte_insn:
1549         switch (c->b) {
1550         case 0x01: /* lgdt, lidt, lmsw */
1551                 /* Disable writeback. */
1552                 no_wb = 1;
1553                 switch (c->modrm_reg) {
1554                         u16 size;
1555                         unsigned long address;
1556
1557                 case 0: /* vmcall */
1558                         if (c->modrm_mod != 3 || c->modrm_rm != 1)
1559                                 goto cannot_emulate;
1560
1561                         rc = kvm_fix_hypercall(ctxt->vcpu);
1562                         if (rc)
1563                                 goto done;
1564
1565                         kvm_emulate_hypercall(ctxt->vcpu);
1566                         break;
1567                 case 2: /* lgdt */
1568                         rc = read_descriptor(ctxt, ops, c->src.ptr,
1569                                              &size, &address, c->op_bytes);
1570                         if (rc)
1571                                 goto done;
1572                         realmode_lgdt(ctxt->vcpu, size, address);
1573                         break;
1574                 case 3: /* lidt/vmmcall */
1575                         if (c->modrm_mod == 3 && c->modrm_rm == 1) {
1576                                 rc = kvm_fix_hypercall(ctxt->vcpu);
1577                                 if (rc)
1578                                         goto done;
1579                                 kvm_emulate_hypercall(ctxt->vcpu);
1580                         } else {
1581                                 rc = read_descriptor(ctxt, ops, c->src.ptr,
1582                                                      &size, &address,
1583                                                      c->op_bytes);
1584                                 if (rc)
1585                                         goto done;
1586                                 realmode_lidt(ctxt->vcpu, size, address);
1587                         }
1588                         break;
1589                 case 4: /* smsw */
1590                         if (c->modrm_mod != 3)
1591                                 goto cannot_emulate;
1592                         *(u16 *)&c->regs[c->modrm_rm]
1593                                 = realmode_get_cr(ctxt->vcpu, 0);
1594                         break;
1595                 case 6: /* lmsw */
1596                         if (c->modrm_mod != 3)
1597                                 goto cannot_emulate;
1598                         realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1599                                                   &ctxt->eflags);
1600                         break;
1601                 case 7: /* invlpg*/
1602                         emulate_invlpg(ctxt->vcpu, cr2);
1603                         break;
1604                 default:
1605                         goto cannot_emulate;
1606                 }
1607                 break;
1608         case 0x21: /* mov from dr to reg */
1609                 no_wb = 1;
1610                 if (c->modrm_mod != 3)
1611                         goto cannot_emulate;
1612                 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
1613                 break;
1614         case 0x23: /* mov from reg to dr */
1615                 no_wb = 1;
1616                 if (c->modrm_mod != 3)
1617                         goto cannot_emulate;
1618                 rc = emulator_set_dr(ctxt, c->modrm_reg,
1619                                      c->regs[c->modrm_rm]);
1620                 break;
1621         case 0x40 ... 0x4f:     /* cmov */
1622                 c->dst.val = c->dst.orig_val = c->src.val;
1623                 no_wb = 1;
1624                 /*
1625                  * First, assume we're decoding an even cmov opcode
1626                  * (lsb == 0).
1627                  */
1628                 switch ((c->b & 15) >> 1) {
1629                 case 0: /* cmovo */
1630                         no_wb = (ctxt->eflags & EFLG_OF) ? 0 : 1;
1631                         break;
1632                 case 1: /* cmovb/cmovc/cmovnae */
1633                         no_wb = (ctxt->eflags & EFLG_CF) ? 0 : 1;
1634                         break;
1635                 case 2: /* cmovz/cmove */
1636                         no_wb = (ctxt->eflags & EFLG_ZF) ? 0 : 1;
1637                         break;
1638                 case 3: /* cmovbe/cmovna */
1639                         no_wb = (ctxt->eflags & (EFLG_CF | EFLG_ZF)) ? 0 : 1;
1640                         break;
1641                 case 4: /* cmovs */
1642                         no_wb = (ctxt->eflags & EFLG_SF) ? 0 : 1;
1643                         break;
1644                 case 5: /* cmovp/cmovpe */
1645                         no_wb = (ctxt->eflags & EFLG_PF) ? 0 : 1;
1646                         break;
1647                 case 7: /* cmovle/cmovng */
1648                         no_wb = (ctxt->eflags & EFLG_ZF) ? 0 : 1;
1649                         /* fall through */
1650                 case 6: /* cmovl/cmovnge */
1651                         no_wb &= (!(ctxt->eflags & EFLG_SF) !=
1652                               !(ctxt->eflags & EFLG_OF)) ? 0 : 1;
1653                         break;
1654                 }
1655                 /* Odd cmov opcodes (lsb == 1) have inverted sense. */
1656                 no_wb ^= c->b & 1;
1657                 break;
1658         case 0xa3:
1659               bt:               /* bt */
1660                 /* only subword offset */
1661                 c->src.val &= (c->dst.bytes << 3) - 1;
1662                 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
1663                 break;
1664         case 0xab:
1665               bts:              /* bts */
1666                 /* only subword offset */
1667                 c->src.val &= (c->dst.bytes << 3) - 1;
1668                 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
1669                 break;
1670         case 0xb0 ... 0xb1:     /* cmpxchg */
1671                 /*
1672                  * Save real source value, then compare EAX against
1673                  * destination.
1674                  */
1675                 c->src.orig_val = c->src.val;
1676                 c->src.val = c->regs[VCPU_REGS_RAX];
1677                 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1678                 if (ctxt->eflags & EFLG_ZF) {
1679                         /* Success: write back to memory. */
1680                         c->dst.val = c->src.orig_val;
1681                 } else {
1682                         /* Failure: write the value we saw to EAX. */
1683                         c->dst.type = OP_REG;
1684                         c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1685                 }
1686                 break;
1687         case 0xb3:
1688               btr:              /* btr */
1689                 /* only subword offset */
1690                 c->src.val &= (c->dst.bytes << 3) - 1;
1691                 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
1692                 break;
1693         case 0xb6 ... 0xb7:     /* movzx */
1694                 c->dst.bytes = c->op_bytes;
1695                 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1696                                                        : (u16) c->src.val;
1697                 break;
1698         case 0xba:              /* Grp8 */
1699                 switch (c->modrm_reg & 3) {
1700                 case 0:
1701                         goto bt;
1702                 case 1:
1703                         goto bts;
1704                 case 2:
1705                         goto btr;
1706                 case 3:
1707                         goto btc;
1708                 }
1709                 break;
1710         case 0xbb:
1711               btc:              /* btc */
1712                 /* only subword offset */
1713                 c->src.val &= (c->dst.bytes << 3) - 1;
1714                 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
1715                 break;
1716         case 0xbe ... 0xbf:     /* movsx */
1717                 c->dst.bytes = c->op_bytes;
1718                 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1719                                                         (s16) c->src.val;
1720                 break;
1721         case 0xc3:              /* movnti */
1722                 c->dst.bytes = c->op_bytes;
1723                 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1724                                                         (u64) c->src.val;
1725                 break;
1726         }
1727         goto writeback;
1728
1729 twobyte_special_insn:
1730         /* Disable writeback. */
1731         no_wb = 1;
1732         switch (c->b) {
1733         case 0x06:
1734                 emulate_clts(ctxt->vcpu);
1735                 break;
1736         case 0x08:              /* invd */
1737                 break;
1738         case 0x09:              /* wbinvd */
1739                 break;
1740         case 0x0d:              /* GrpP (prefetch) */
1741         case 0x18:              /* Grp16 (prefetch/nop) */
1742                 break;
1743         case 0x20: /* mov cr, reg */
1744                 if (c->modrm_mod != 3)
1745                         goto cannot_emulate;
1746                 c->regs[c->modrm_rm] =
1747                                 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1748                 break;
1749         case 0x22: /* mov reg, cr */
1750                 if (c->modrm_mod != 3)
1751                         goto cannot_emulate;
1752                 realmode_set_cr(ctxt->vcpu,
1753                                 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1754                 break;
1755         case 0x30:
1756                 /* wrmsr */
1757                 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1758                         | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1759                 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1760                 if (rc) {
1761                         kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
1762                         c->eip = ctxt->vcpu->rip;
1763                 }
1764                 rc = X86EMUL_CONTINUE;
1765                 break;
1766         case 0x32:
1767                 /* rdmsr */
1768                 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1769                 if (rc) {
1770                         kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
1771                         c->eip = ctxt->vcpu->rip;
1772                 } else {
1773                         c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1774                         c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1775                 }
1776                 rc = X86EMUL_CONTINUE;
1777                 break;
1778         case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1779                 long int rel;
1780
1781                 switch (c->op_bytes) {
1782                 case 2:
1783                         rel = insn_fetch(s16, 2, c->eip);
1784                         break;
1785                 case 4:
1786                         rel = insn_fetch(s32, 4, c->eip);
1787                         break;
1788                 case 8:
1789                         rel = insn_fetch(s64, 8, c->eip);
1790                         break;
1791                 default:
1792                         DPRINTF("jnz: Invalid op_bytes\n");
1793                         goto cannot_emulate;
1794                 }
1795                 if (test_cc(c->b, ctxt->eflags))
1796                         JMP_REL(rel);
1797                 break;
1798         }
1799         case 0xc7:              /* Grp9 (cmpxchg8b) */
1800                 rc = emulate_grp9(ctxt, ops, cr2);
1801                 if (rc != 0)
1802                         goto done;
1803                 break;
1804         }
1805         goto writeback;
1806
1807 cannot_emulate:
1808         DPRINTF("Cannot emulate %02x\n", c->b);
1809         c->eip = saved_eip;
1810         return -1;
1811 }