2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pnp.h>
32 #include <linux/interrupt.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/input.h>
36 #include <media/ir-core.h>
37 #include <linux/pci_ids.h>
39 #include "nuvoton-cir.h"
41 static char *chip_id = "w836x7hg";
43 /* write val to config reg */
44 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
46 outb(reg, nvt->cr_efir);
47 outb(val, nvt->cr_efdr);
50 /* read val from config reg */
51 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
53 outb(reg, nvt->cr_efir);
54 return inb(nvt->cr_efdr);
57 /* update config register bit without changing other bits */
58 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
60 u8 tmp = nvt_cr_read(nvt, reg) | val;
61 nvt_cr_write(nvt, tmp, reg);
64 /* clear config register bit without changing other bits */
65 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
67 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
68 nvt_cr_write(nvt, tmp, reg);
71 /* enter extended function mode */
72 static inline void nvt_efm_enable(struct nvt_dev *nvt)
74 /* Enabling Extended Function Mode explicitly requires writing 2x */
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
76 outb(EFER_EFM_ENABLE, nvt->cr_efir);
79 /* exit extended function mode */
80 static inline void nvt_efm_disable(struct nvt_dev *nvt)
82 outb(EFER_EFM_DISABLE, nvt->cr_efir);
86 * When you want to address a specific logical device, write its logical
87 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
88 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
90 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
92 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
93 outb(ldev, nvt->cr_efdr);
96 /* write val to cir config register */
97 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
99 outb(val, nvt->cir_addr + offset);
102 /* read val from cir config register */
103 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
107 val = inb(nvt->cir_addr + offset);
112 /* write val to cir wake register */
113 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
116 outb(val, nvt->cir_wake_addr + offset);
119 /* read val from cir wake config register */
120 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
124 val = inb(nvt->cir_wake_addr + offset);
129 #define pr_reg(text, ...) \
130 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
132 /* dump current cir register contents */
133 static void cir_dump_regs(struct nvt_dev *nvt)
136 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
138 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
139 pr_reg(" * CR CIR ACTIVE : 0x%x\n",
140 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
141 pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
142 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
143 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
144 pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
145 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
147 nvt_efm_disable(nvt);
149 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
150 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
151 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
152 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
153 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
154 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
155 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
156 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
157 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
158 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
159 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
160 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
161 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
162 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
163 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
164 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
165 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
168 /* dump current cir wake register contents */
169 static void cir_wake_dump_regs(struct nvt_dev *nvt)
174 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
176 pr_reg("%s: Dump CIR WAKE logical device registers:\n",
178 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
179 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
180 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
181 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
182 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
183 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
184 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
186 nvt_efm_disable(nvt);
188 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
189 pr_reg(" * IRCON: 0x%x\n",
190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
191 pr_reg(" * IRSTS: 0x%x\n",
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
193 pr_reg(" * IREN: 0x%x\n",
194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
195 pr_reg(" * FIFO CMP DEEP: 0x%x\n",
196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
197 pr_reg(" * FIFO CMP TOL: 0x%x\n",
198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
199 pr_reg(" * FIFO COUNT: 0x%x\n",
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
201 pr_reg(" * SLCH: 0x%x\n",
202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
203 pr_reg(" * SLCL: 0x%x\n",
204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
205 pr_reg(" * FIFOCON: 0x%x\n",
206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
207 pr_reg(" * SRXFSTS: 0x%x\n",
208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
209 pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
211 pr_reg(" * WR FIFO DATA: 0x%x\n",
212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
213 pr_reg(" * RD FIFO ONLY: 0x%x\n",
214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
215 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
217 pr_reg(" * FIFO IGNORE: 0x%x\n",
218 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
219 pr_reg(" * IRFSM: 0x%x\n",
220 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
222 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
223 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
224 pr_reg("* Contents = ");
225 for (i = 0; i < fifo_len; i++)
226 printk(KERN_CONT "%02x ",
227 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
228 printk(KERN_CONT "\n");
231 /* detect hardware features */
232 static int nvt_hw_detect(struct nvt_dev *nvt)
235 u8 chip_major, chip_minor;
240 /* Check if we're wired for the alternate EFER setup */
241 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
242 if (chip_major == 0xff) {
243 nvt->cr_efir = CR_EFIR2;
244 nvt->cr_efdr = CR_EFDR2;
246 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
249 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
250 nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
252 if (chip_major != CHIP_ID_HIGH &&
253 (chip_minor != CHIP_ID_LOW || chip_minor != CHIP_ID_LOW2))
256 nvt_efm_disable(nvt);
258 spin_lock_irqsave(&nvt->nvt_lock, flags);
259 nvt->chip_major = chip_major;
260 nvt->chip_minor = chip_minor;
261 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
266 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
270 /* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
271 val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
272 val &= OUTPUT_PIN_SEL_MASK;
273 val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
274 nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
276 /* Select CIR logical device and enable */
277 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
278 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
280 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
281 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
283 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
285 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
286 nvt->cir_addr, nvt->cir_irq);
289 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
291 /* Select ACPI logical device, enable it and CIR Wake */
292 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
293 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
295 /* Enable CIR Wake via PSOUT# (Pin60) */
296 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
298 /* enable cir interrupt of mouse/keyboard IRQ event */
299 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
301 /* enable pme interrupt of cir wakeup event */
302 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
304 /* Select CIR Wake logical device and enable */
305 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
306 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
308 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
309 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
311 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
313 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
314 nvt->cir_wake_addr, nvt->cir_wake_irq);
317 /* clear out the hardware's cir rx fifo */
318 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
322 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
323 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
326 /* clear out the hardware's cir wake rx fifo */
327 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
331 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
332 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
336 /* clear out the hardware's cir tx fifo */
337 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
341 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
342 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
345 /* enable RX Trigger Level Reach and Packet End interrupts */
346 static void nvt_set_cir_iren(struct nvt_dev *nvt)
350 iren = CIR_IREN_RTR | CIR_IREN_PE;
351 nvt_cir_reg_write(nvt, iren, CIR_IREN);
354 static void nvt_cir_regs_init(struct nvt_dev *nvt)
356 /* set sample limit count (PE interrupt raised when reached) */
357 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
358 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
360 /* set fifo irq trigger levels */
361 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
362 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
365 * Enable TX and RX, specify carrier on = low, off = high, and set
366 * sample period (currently 50us)
368 nvt_cir_reg_write(nvt,
369 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
370 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
373 /* clear hardware rx and tx fifos */
374 nvt_clear_cir_fifo(nvt);
375 nvt_clear_tx_fifo(nvt);
377 /* clear any and all stray interrupts */
378 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
380 /* and finally, enable interrupts */
381 nvt_set_cir_iren(nvt);
384 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
386 /* set number of bytes needed for wake key comparison (default 67) */
387 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_LEN, CIR_WAKE_FIFO_CMP_DEEP);
389 /* set tolerance/variance allowed per byte during wake compare */
390 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
391 CIR_WAKE_FIFO_CMP_TOL);
393 /* set sample limit count (PE interrupt raised when reached) */
394 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
395 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
397 /* set cir wake fifo rx trigger level (currently 67) */
398 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
402 * Enable TX and RX, specific carrier on = low, off = high, and set
403 * sample period (currently 50us)
405 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
406 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
407 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
410 /* clear cir wake rx fifo */
411 nvt_clear_cir_wake_fifo(nvt);
413 /* clear any and all stray interrupts */
414 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
417 static void nvt_enable_wake(struct nvt_dev *nvt)
421 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
422 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
423 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
424 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
426 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
427 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
429 nvt_efm_disable(nvt);
431 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
432 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
433 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
435 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
436 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
439 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
440 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
442 u32 count, carrier, duration = 0;
445 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
446 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
448 for (i = 0; i < nvt->pkts; i++) {
449 if (nvt->buf[i] & BUF_PULSE_BIT)
450 duration += nvt->buf[i] & BUF_LEN_MASK;
453 duration *= SAMPLE_PERIOD;
455 if (!count || !duration) {
456 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
461 carrier = (count * 1000000) / duration;
463 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
464 nvt_dbg("WTF? Carrier frequency out of range!");
466 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
467 carrier, count, duration);
473 * set carrier frequency
475 * set carrier on 2 registers: CP & CC
476 * always set CP as 0x81
477 * set CC by SPEC, CC = 3MHz/carrier - 1
479 static int nvt_set_tx_carrier(void *data, u32 carrier)
481 struct nvt_dev *nvt = data;
484 nvt_cir_reg_write(nvt, 1, CIR_CP);
485 val = 3000000 / (carrier) - 1;
486 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
488 nvt_dbg("cp: 0x%x cc: 0x%x\n",
489 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
497 * 1) clean TX fifo first (handled by AP)
498 * 2) copy data from user space
499 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
500 * 4) send 9 packets to TX FIFO to open TTR
501 * in interrupt_handler:
502 * 5) send all data out
503 * go back to write():
504 * 6) disable TX interrupts, re-enable RX interupts
506 * The key problem of this function is user space data may larger than
507 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
508 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
509 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
510 * set TXFCONT as 0xff, until buf_count less than 0xff.
512 static int nvt_tx_ir(void *priv, int *txbuf, u32 n)
514 struct nvt_dev *nvt = priv;
521 spin_lock_irqsave(&nvt->tx.lock, flags);
523 if (n >= TX_BUF_LEN) {
524 nvt->tx.buf_count = cur_count = TX_BUF_LEN;
527 nvt->tx.buf_count = cur_count = n;
531 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
533 nvt->tx.cur_buf_num = 0;
535 /* save currently enabled interrupts */
536 iren = nvt_cir_reg_read(nvt, CIR_IREN);
538 /* now disable all interrupts, save TFU & TTR */
539 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
541 nvt->tx.tx_state = ST_TX_REPLY;
543 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
544 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
546 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
547 for (i = 0; i < 9; i++)
548 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
550 spin_unlock_irqrestore(&nvt->tx.lock, flags);
552 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
554 spin_lock_irqsave(&nvt->tx.lock, flags);
555 nvt->tx.tx_state = ST_TX_NONE;
556 spin_unlock_irqrestore(&nvt->tx.lock, flags);
558 /* restore enabled interrupts to prior state */
559 nvt_cir_reg_write(nvt, iren, CIR_IREN);
564 /* dump contents of the last rx buffer we got from the hw rx fifo */
565 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
569 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
570 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
571 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
572 printk(KERN_CONT "\n");
576 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
577 * trigger decode when appropriate.
579 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
580 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
581 * (default 50us) intervals for that pulse/space. A discrete signal is
582 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
583 * to signal more IR coming (repeats) or end of IR, respectively. We store
584 * sample data in the raw event kfifo until we see 0x7<something> (except f)
585 * or 0x80, at which time, we trigger a decode operation.
587 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
589 DEFINE_IR_RAW_EVENT(rawir);
595 nvt_dbg_verbose("%s firing", __func__);
598 nvt_dump_rx_buf(nvt);
600 if (nvt->carrier_detect_enabled)
601 carrier = nvt_rx_carrier_detect(nvt);
604 nvt_dbg_verbose("Processing buffer of len %d", count);
606 for (i = 0; i < count; i++) {
608 sample = nvt->buf[i];
610 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
611 rawir.duration = (sample & BUF_LEN_MASK)
612 * SAMPLE_PERIOD * 1000;
614 if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) {
615 if (nvt->rawir.pulse == rawir.pulse)
616 nvt->rawir.duration += rawir.duration;
618 nvt->rawir.duration = rawir.duration;
619 nvt->rawir.pulse = rawir.pulse;
624 rawir.duration += nvt->rawir.duration;
626 init_ir_raw_event(&nvt->rawir);
627 nvt->rawir.duration = 0;
628 nvt->rawir.pulse = rawir.pulse;
630 if (sample == BUF_PULSE_BIT)
633 if (rawir.duration) {
634 nvt_dbg("Storing %s with duration %d",
635 rawir.pulse ? "pulse" : "space",
638 ir_raw_event_store(nvt->rdev, &rawir);
642 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
643 * indicates end of IR signal, but new data incoming. In both
644 * cases, it means we're ready to call ir_raw_event_handle
646 if (sample == BUF_PULSE_BIT || ((sample != BUF_LEN_MASK) &&
647 (sample & BUF_REPEAT_MASK) == BUF_REPEAT_BYTE))
648 ir_raw_event_handle(nvt->rdev);
652 nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts);
656 nvt_dbg_verbose("%s done", __func__);
659 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
661 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
664 nvt_clear_cir_fifo(nvt);
665 ir_raw_event_reset(nvt->rdev);
668 /* copy data from hardware rx fifo into driver buffer */
669 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
674 bool overrun = false;
677 /* Get count of how many bytes to read from RX FIFO */
678 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
679 /* if we get 0xff, probably means the logical dev is disabled */
680 if (fifocount == 0xff)
682 /* watch out for a fifo overrun condition */
683 else if (fifocount > RX_BUF_LEN) {
685 fifocount = RX_BUF_LEN;
688 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
690 spin_lock_irqsave(&nvt->nvt_lock, flags);
694 /* This should never happen, but lets check anyway... */
695 if (b_idx + fifocount > RX_BUF_LEN) {
696 nvt_process_rx_ir_data(nvt);
700 /* Read fifocount bytes from CIR Sample RX FIFO register */
701 for (i = 0; i < fifocount; i++) {
702 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
703 nvt->buf[b_idx + i] = val;
706 nvt->pkts += fifocount;
707 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
709 nvt_process_rx_ir_data(nvt);
712 nvt_handle_rx_fifo_overrun(nvt);
714 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
717 static void nvt_cir_log_irqs(u8 status, u8 iren)
719 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
721 status & CIR_IRSTS_RDR ? " RDR" : "",
722 status & CIR_IRSTS_RTR ? " RTR" : "",
723 status & CIR_IRSTS_PE ? " PE" : "",
724 status & CIR_IRSTS_RFO ? " RFO" : "",
725 status & CIR_IRSTS_TE ? " TE" : "",
726 status & CIR_IRSTS_TTR ? " TTR" : "",
727 status & CIR_IRSTS_TFU ? " TFU" : "",
728 status & CIR_IRSTS_GH ? " GH" : "",
729 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
730 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
731 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
734 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
740 spin_lock_irqsave(&nvt->tx.lock, flags);
741 tx_state = nvt->tx.tx_state;
742 spin_unlock_irqrestore(&nvt->tx.lock, flags);
744 tx_inactive = (tx_state == ST_TX_NONE);
749 /* interrupt service routine for incoming and outgoing CIR data */
750 static irqreturn_t nvt_cir_isr(int irq, void *data)
752 struct nvt_dev *nvt = data;
753 u8 status, iren, cur_state;
756 nvt_dbg_verbose("%s firing", __func__);
759 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
760 nvt_efm_disable(nvt);
763 * Get IR Status register contents. Write 1 to ack/clear
765 * bit: reg name - description
766 * 7: CIR_IRSTS_RDR - RX Data Ready
767 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
768 * 5: CIR_IRSTS_PE - Packet End
769 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
770 * 3: CIR_IRSTS_TE - TX FIFO Empty
771 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
772 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
773 * 0: CIR_IRSTS_GH - Min Length Detected
775 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
777 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
778 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
779 return IRQ_RETVAL(IRQ_NONE);
782 /* ack/clear all irq flags we've got */
783 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
784 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
786 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
787 iren = nvt_cir_reg_read(nvt, CIR_IREN);
789 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
790 return IRQ_RETVAL(IRQ_NONE);
794 nvt_cir_log_irqs(status, iren);
796 if (status & CIR_IRSTS_RTR) {
797 /* FIXME: add code for study/learn mode */
798 /* We only do rx if not tx'ing */
799 if (nvt_cir_tx_inactive(nvt))
800 nvt_get_rx_ir_data(nvt);
803 if (status & CIR_IRSTS_PE) {
804 if (nvt_cir_tx_inactive(nvt))
805 nvt_get_rx_ir_data(nvt);
807 spin_lock_irqsave(&nvt->nvt_lock, flags);
809 cur_state = nvt->study_state;
811 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
813 if (cur_state == ST_STUDY_NONE)
814 nvt_clear_cir_fifo(nvt);
817 if (status & CIR_IRSTS_TE)
818 nvt_clear_tx_fifo(nvt);
820 if (status & CIR_IRSTS_TTR) {
821 unsigned int pos, count;
824 spin_lock_irqsave(&nvt->tx.lock, flags);
826 pos = nvt->tx.cur_buf_num;
827 count = nvt->tx.buf_count;
829 /* Write data into the hardware tx fifo while pos < count */
831 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
832 nvt->tx.cur_buf_num++;
833 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
835 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
836 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
839 spin_unlock_irqrestore(&nvt->tx.lock, flags);
843 if (status & CIR_IRSTS_TFU) {
844 spin_lock_irqsave(&nvt->tx.lock, flags);
845 if (nvt->tx.tx_state == ST_TX_REPLY) {
846 nvt->tx.tx_state = ST_TX_REQUEST;
847 wake_up(&nvt->tx.queue);
849 spin_unlock_irqrestore(&nvt->tx.lock, flags);
852 nvt_dbg_verbose("%s done", __func__);
853 return IRQ_RETVAL(IRQ_HANDLED);
856 /* Interrupt service routine for CIR Wake */
857 static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
859 u8 status, iren, val;
860 struct nvt_dev *nvt = data;
863 nvt_dbg_wake("%s firing", __func__);
865 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
867 return IRQ_RETVAL(IRQ_NONE);
869 if (status & CIR_WAKE_IRSTS_IR_PENDING)
870 nvt_clear_cir_wake_fifo(nvt);
872 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
873 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
875 /* Interrupt may be shared with CIR, bail if Wake not enabled */
876 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
878 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
879 return IRQ_RETVAL(IRQ_HANDLED);
882 if ((status & CIR_WAKE_IRSTS_PE) &&
883 (nvt->wake_state == ST_WAKE_START)) {
884 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
885 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
886 nvt_dbg("setting wake up key: 0x%x", val);
889 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
890 spin_lock_irqsave(&nvt->nvt_lock, flags);
891 nvt->wake_state = ST_WAKE_FINISH;
892 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
895 nvt_dbg_wake("%s done", __func__);
896 return IRQ_RETVAL(IRQ_HANDLED);
899 static void nvt_enable_cir(struct nvt_dev *nvt)
901 /* set function enable flags */
902 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
903 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
908 /* enable the CIR logical device */
909 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
910 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
912 nvt_efm_disable(nvt);
914 /* clear all pending interrupts */
915 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
917 /* enable interrupts */
918 nvt_set_cir_iren(nvt);
921 static void nvt_disable_cir(struct nvt_dev *nvt)
923 /* disable CIR interrupts */
924 nvt_cir_reg_write(nvt, 0, CIR_IREN);
926 /* clear any and all pending interrupts */
927 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
929 /* clear all function enable flags */
930 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
932 /* clear hardware rx and tx fifos */
933 nvt_clear_cir_fifo(nvt);
934 nvt_clear_tx_fifo(nvt);
938 /* disable the CIR logical device */
939 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
940 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
942 nvt_efm_disable(nvt);
945 static int nvt_open(void *data)
947 struct nvt_dev *nvt = (struct nvt_dev *)data;
950 spin_lock_irqsave(&nvt->nvt_lock, flags);
953 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
958 static void nvt_close(void *data)
960 struct nvt_dev *nvt = (struct nvt_dev *)data;
963 spin_lock_irqsave(&nvt->nvt_lock, flags);
965 nvt_disable_cir(nvt);
966 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
969 /* Allocate memory, probe hardware, and initialize everything */
970 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
972 struct nvt_dev *nvt = NULL;
973 struct input_dev *rdev = NULL;
974 struct ir_dev_props *props = NULL;
977 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
981 props = kzalloc(sizeof(struct ir_dev_props), GFP_KERNEL);
985 /* input device for IR remote (and tx) */
986 rdev = input_allocate_device();
991 /* validate pnp resources */
992 if (!pnp_port_valid(pdev, 0) ||
993 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
994 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
998 if (!pnp_irq_valid(pdev, 0)) {
999 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1003 if (!pnp_port_valid(pdev, 1) ||
1004 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1005 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1009 nvt->cir_addr = pnp_port_start(pdev, 0);
1010 nvt->cir_irq = pnp_irq(pdev, 0);
1012 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1013 /* irq is always shared between cir and cir wake */
1014 nvt->cir_wake_irq = nvt->cir_irq;
1016 nvt->cr_efir = CR_EFIR;
1017 nvt->cr_efdr = CR_EFDR;
1019 spin_lock_init(&nvt->nvt_lock);
1020 spin_lock_init(&nvt->tx.lock);
1021 init_ir_raw_event(&nvt->rawir);
1024 /* now claim resources */
1025 if (!request_region(nvt->cir_addr,
1026 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1029 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1030 NVT_DRIVER_NAME, (void *)nvt))
1033 if (!request_region(nvt->cir_wake_addr,
1034 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1037 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1038 NVT_DRIVER_NAME, (void *)nvt))
1041 pnp_set_drvdata(pdev, nvt);
1044 init_waitqueue_head(&nvt->tx.queue);
1046 ret = nvt_hw_detect(nvt);
1050 /* Initialize CIR & CIR Wake Logical Devices */
1051 nvt_efm_enable(nvt);
1052 nvt_cir_ldev_init(nvt);
1053 nvt_cir_wake_ldev_init(nvt);
1054 nvt_efm_disable(nvt);
1056 /* Initialize CIR & CIR Wake Config Registers */
1057 nvt_cir_regs_init(nvt);
1058 nvt_cir_wake_regs_init(nvt);
1060 /* Set up ir-core props */
1062 props->driver_type = RC_DRIVER_IR_RAW;
1063 props->allowed_protos = IR_TYPE_ALL;
1064 props->open = nvt_open;
1065 props->close = nvt_close;
1067 props->min_timeout = XYZ;
1068 props->max_timeout = XYZ;
1069 props->timeout = XYZ;
1070 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1071 props->rx_resolution = XYZ;
1074 props->tx_resolution = XYZ;
1076 props->tx_ir = nvt_tx_ir;
1077 props->s_tx_carrier = nvt_set_tx_carrier;
1079 rdev->name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1080 rdev->id.bustype = BUS_HOST;
1081 rdev->id.vendor = PCI_VENDOR_ID_WINBOND2;
1082 rdev->id.product = nvt->chip_major;
1083 rdev->id.version = nvt->chip_minor;
1088 device_set_wakeup_capable(&pdev->dev, 1);
1089 device_set_wakeup_enable(&pdev->dev, 1);
1091 ret = ir_input_register(rdev, RC_MAP_RC6_MCE, props, NVT_DRIVER_NAME);
1095 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1098 cir_wake_dump_regs(nvt);
1105 free_irq(nvt->cir_irq, nvt);
1107 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1109 if (nvt->cir_wake_irq)
1110 free_irq(nvt->cir_wake_irq, nvt);
1111 if (nvt->cir_wake_addr)
1112 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1114 input_free_device(rdev);
1121 static void __devexit nvt_remove(struct pnp_dev *pdev)
1123 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1124 unsigned long flags;
1126 spin_lock_irqsave(&nvt->nvt_lock, flags);
1128 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1129 nvt_disable_cir(nvt);
1130 /* enable CIR Wake (for IR power-on) */
1131 nvt_enable_wake(nvt);
1132 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1134 /* free resources */
1135 free_irq(nvt->cir_irq, nvt);
1136 free_irq(nvt->cir_wake_irq, nvt);
1137 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1138 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1140 ir_input_unregister(nvt->rdev);
1146 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1148 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1149 unsigned long flags;
1151 nvt_dbg("%s called", __func__);
1153 /* zero out misc state tracking */
1154 spin_lock_irqsave(&nvt->nvt_lock, flags);
1155 nvt->study_state = ST_STUDY_NONE;
1156 nvt->wake_state = ST_WAKE_NONE;
1157 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1159 spin_lock_irqsave(&nvt->tx.lock, flags);
1160 nvt->tx.tx_state = ST_TX_NONE;
1161 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1163 /* disable all CIR interrupts */
1164 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1166 nvt_efm_enable(nvt);
1168 /* disable cir logical dev */
1169 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1170 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1172 nvt_efm_disable(nvt);
1174 /* make sure wake is enabled */
1175 nvt_enable_wake(nvt);
1180 static int nvt_resume(struct pnp_dev *pdev)
1183 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1185 nvt_dbg("%s called", __func__);
1187 /* open interrupt */
1188 nvt_set_cir_iren(nvt);
1190 /* Enable CIR logical device */
1191 nvt_efm_enable(nvt);
1192 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1193 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1195 nvt_efm_disable(nvt);
1197 nvt_cir_regs_init(nvt);
1198 nvt_cir_wake_regs_init(nvt);
1203 static void nvt_shutdown(struct pnp_dev *pdev)
1205 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1206 nvt_enable_wake(nvt);
1209 static const struct pnp_device_id nvt_ids[] = {
1210 { "WEC0530", 0 }, /* CIR */
1211 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1215 static struct pnp_driver nvt_driver = {
1216 .name = NVT_DRIVER_NAME,
1217 .id_table = nvt_ids,
1218 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1220 .remove = __devexit_p(nvt_remove),
1221 .suspend = nvt_suspend,
1222 .resume = nvt_resume,
1223 .shutdown = nvt_shutdown,
1228 return pnp_register_driver(&nvt_driver);
1233 pnp_unregister_driver(&nvt_driver);
1236 module_param(debug, int, S_IRUGO | S_IWUSR);
1237 MODULE_PARM_DESC(debug, "Enable debugging output");
1239 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1240 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1242 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1243 MODULE_LICENSE("GPL");
1245 module_init(nvt_init);
1246 module_exit(nvt_exit);