2 Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
4 Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/slab.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/init.h>
27 #include "dvb_frontend.h"
31 #define dprintk(args...) \
33 if (debug) printk (KERN_DEBUG "cx24123: " args); \
38 struct i2c_adapter* i2c;
39 struct dvb_frontend_ops ops;
40 const struct cx24123_config* config;
42 struct dvb_frontend frontend;
48 /* Some PLL specifics for tuning */
54 /* The Demod/Tuner can't easily provide these, we cache them */
56 u32 currentsymbolrate;
59 /* Various tuner defaults need to be established for a given symbol rate Sps */
70 } cx24123_AGC_vals[] =
73 .symbolrate_low = 1000000,
74 .symbolrate_high = 4999999,
79 .VGAprogdata = (2 << 18) | (0x1f8 << 9) | 0x1f8,
80 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x07,
83 .symbolrate_low = 5000000,
84 .symbolrate_high = 14999999,
89 .VGAprogdata = (2 << 18) | (0x180 << 9) | 0x1e0,
90 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x1f,
93 .symbolrate_low = 15000000,
94 .symbolrate_high = 45000000,
99 .VGAprogdata = (2 << 18) | (0x100 << 9) | 0x180,
100 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x3f,
105 * Various tuner defaults need to be established for a given frequency kHz.
106 * fixme: The bounds on the bands do not match the doc in real life.
107 * fixme: Some of them have been moved, other might need adjustment.
117 } cx24123_bandselect_vals[] =
121 .freq_high = 1018999,
125 .progdata = (0 << 18) | (0 << 9) | 0x40,
129 .freq_high = 1074999,
133 .progdata = (0 << 18) | (0 << 9) | 0x80,
137 .freq_high = 1227999,
141 .progdata = (0 << 18) | (1 << 9) | 0x01,
145 .freq_high = 1349999,
149 .progdata = (0 << 18) | (1 << 9) | 0x02,
153 .freq_high = 1481999,
157 .progdata = (0 << 18) | (1 << 9) | 0x04,
161 .freq_high = 1595999,
165 .progdata = (0 << 18) | (1 << 9) | 0x08,
169 .freq_high = 1717999,
173 .progdata = (0 << 18) | (1 << 9) | 0x10,
177 .freq_high = 1855999,
181 .progdata = (0 << 18) | (1 << 9) | 0x20,
185 .freq_high = 2035999,
189 .progdata = (0 << 18) | (1 << 9) | 0x40,
193 .freq_high = 2149999,
197 .progdata = (0 << 18) | (1 << 9) | 0x80,
204 } cx24123_regdata[] =
206 {0x00, 0x03}, /* Reset system */
207 {0x00, 0x00}, /* Clear reset */
208 {0x01, 0x3b}, /* Apply sensible defaults, from an i2c sniffer */
244 {0x3a, 0x00}, /* Enable AGC accumulator */
253 static int cx24123_writereg(struct cx24123_state* state, int reg, int data)
255 u8 buf[] = { reg, data };
256 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
259 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
260 printk("%s: writereg error(err == %i, reg == 0x%02x,"
261 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
268 static int cx24123_writelnbreg(struct cx24123_state* state, int reg, int data)
270 u8 buf[] = { reg, data };
271 /* fixme: put the intersil addr int the config */
272 struct i2c_msg msg = { .addr = 0x08, .flags = 0, .buf = buf, .len = 2 };
275 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
276 printk("%s: writelnbreg error (err == %i, reg == 0x%02x,"
277 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
281 /* cache the write, no way to read back */
282 state->lnbreg = data;
287 static int cx24123_readreg(struct cx24123_state* state, u8 reg)
292 struct i2c_msg msg[] = {
293 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
294 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }
297 ret = i2c_transfer(state->i2c, msg, 2);
300 printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);
307 static int cx24123_readlnbreg(struct cx24123_state* state, u8 reg)
309 return state->lnbreg;
312 static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion)
316 cx24123_writereg(state, 0x0e, cx24123_readreg(state, 0x0e) & 0x7f);
317 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) | 0x80);
320 cx24123_writereg(state, 0x0e, cx24123_readreg(state, 0x0e) | 0x80);
321 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) | 0x80);
324 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) & 0x7f);
333 static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion)
337 val = cx24123_readreg(state, 0x1b) >> 7;
340 *inversion = INVERSION_OFF;
342 *inversion = INVERSION_ON;
347 static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
349 if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
352 /* Hardware has 5/11 and 3/5 but are never unused */
355 return cx24123_writereg(state, 0x0f, 0x01);
357 return cx24123_writereg(state, 0x0f, 0x02);
359 return cx24123_writereg(state, 0x0f, 0x04);
361 return cx24123_writereg(state, 0x0f, 0x08);
363 return cx24123_writereg(state, 0x0f, 0x20);
365 return cx24123_writereg(state, 0x0f, 0x80);
367 return cx24123_writereg(state, 0x0f, 0xae);
373 static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
378 ret = cx24123_readreg (state, 0x1b);
401 case 2: /* *fec = FEC_3_5; break; */
402 case 0: /* *fec = FEC_5_11; break; */
406 *fec = FEC_NONE; // can't happen
412 /* fixme: Symbol rates < 3MSps may not work because of precision loss */
413 static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
417 val = (srate / 1185) * 100;
419 /* Compensate for scaling up, by removing 17 symbols per 1Msps */
420 val = val - (17 * (srate / 1000000));
422 cx24123_writereg(state, 0x08, (val >> 16) & 0xff );
423 cx24123_writereg(state, 0x09, (val >> 8) & 0xff );
424 cx24123_writereg(state, 0x0a, (val ) & 0xff );
430 * Based on the required frequency and symbolrate, the tuner AGC has to be configured
431 * and the correct band selected. Calculate those values
433 static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
435 struct cx24123_state *state = fe->demodulator_priv;
436 u32 ndiv = 0, adiv = 0, vco_div = 0;
439 /* Defaults for low freq, low rate */
440 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
441 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
442 state->bandselectarg = cx24123_bandselect_vals[0].progdata;
443 vco_div = cx24123_bandselect_vals[0].VCOdivider;
445 /* For the given symbolerate, determine the VCA and VGA programming bits */
446 for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
448 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
449 (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
450 state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
451 state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
455 /* For the given frequency, determine the bandselect programming bits */
456 for (i = 0; i < sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); i++)
458 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
459 (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) {
460 state->bandselectarg = cx24123_bandselect_vals[i].progdata;
461 vco_div = cx24123_bandselect_vals[i].VCOdivider;
465 /* Determine the N/A dividers for the requested lband freq (in kHz). */
466 /* Note: 10111 (kHz) is the Crystal Freq and divider of 10. */
467 ndiv = ( ((p->frequency * vco_div) / (10111 / 10) / 2) / 32) & 0x1ff;
468 adiv = ( ((p->frequency * vco_div) / (10111 / 10) / 2) % 32) & 0x1f;
473 /* determine the correct pll frequency values. */
474 /* Command 11, refdiv 11, cpump polarity 1, cpump current 3mA 10. */
475 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (2 << 14);
476 state->pllarg |= (ndiv << 5) | adiv;
482 * Tuner data is 21 bits long, must be left-aligned in data.
483 * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip.
485 static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data)
487 struct cx24123_state *state = fe->demodulator_priv;
491 /* align the 21 bytes into to bit23 boundary */
494 /* Reset the demod pll word length to 0x15 bits */
495 cx24123_writereg(state, 0x21, 0x15);
498 /* write the msb 8 bits, wait for the send to be completed */
499 cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
500 while ( ( cx24123_readreg(state, 0x20) & 0x40 ) == 0 )
502 /* Safety - No reason why the write should not complete, and we never get here, avoid hang */
503 if (timeout++ >= 4) {
504 printk("%s: demodulator is no longer responding, aborting.\n",__FUNCTION__);
511 /* send another 8 bytes, wait for the send to be completed */
512 cx24123_writereg(state, 0x22, (data>>8) & 0xff );
513 while ( (cx24123_readreg(state, 0x20) & 0x40 ) == 0 )
515 /* Safety - No reason why the write should not complete, and we never get here, avoid hang */
516 if (timeout++ >= 4) {
517 printk("%s: demodulator is not responding, possibly hung, aborting.\n",__FUNCTION__);
524 /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
525 cx24123_writereg(state, 0x22, (data) & 0xff );
526 while ((cx24123_readreg(state, 0x20) & 0x80))
528 /* Safety - No reason why the write should not complete, and we never get here, avoid hang */
529 if (timeout++ >= 4) {
530 printk("%s: demodulator is not responding, possibly hung, aborting.\n",__FUNCTION__);
536 /* Trigger the demod to configure the tuner */
537 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
538 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
543 static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
545 struct cx24123_state *state = fe->demodulator_priv;
547 if (cx24123_pll_calculate(fe, p) != 0) {
548 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
552 /* Write the new VCO/VGA */
553 cx24123_pll_writereg(fe, p, state->VCAarg);
554 cx24123_pll_writereg(fe, p, state->VGAarg);
556 /* Write the new bandselect and pll args */
557 cx24123_pll_writereg(fe, p, state->bandselectarg);
558 cx24123_pll_writereg(fe, p, state->pllarg);
563 static int cx24123_initfe(struct dvb_frontend* fe)
565 struct cx24123_state *state = fe->demodulator_priv;
568 /* Configure the demod to a good set of defaults */
569 for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
570 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
572 if (state->config->pll_init)
573 state->config->pll_init(fe);
575 /* Configure the LNB for 14V */
576 cx24123_writelnbreg(state, 0x0, 0x2a);
581 static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
583 struct cx24123_state *state = fe->demodulator_priv;
586 val = cx24123_readlnbreg(state, 0x0);
590 return cx24123_writelnbreg(state, 0x0, val & 0x32); /* V 13v */
592 return cx24123_writelnbreg(state, 0x0, val | 0x04); /* H 18v */
593 case SEC_VOLTAGE_OFF:
594 return cx24123_writelnbreg(state, 0x0, val & 0x30);
600 static int cx24123_send_diseqc_msg(struct dvb_frontend* fe,
601 struct dvb_diseqc_master_cmd *cmd)
603 /* fixme: Implement diseqc */
604 printk("%s: No support yet\n",__FUNCTION__);
609 static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
611 struct cx24123_state *state = fe->demodulator_priv;
613 int sync = cx24123_readreg(state, 0x14);
614 int lock = cx24123_readreg(state, 0x20);
618 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
620 *status |= FE_HAS_VITERBI;
622 *status |= FE_HAS_CARRIER;
624 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
630 * Configured to return the measurement of errors in blocks, because no UCBLOCKS value
631 * is available, so this value doubles up to satisfy both measurements
633 static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber)
635 struct cx24123_state *state = fe->demodulator_priv;
638 ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
639 (cx24123_readreg(state, 0x1d) << 8 |
640 cx24123_readreg(state, 0x1e));
642 /* Do the signal quality processing here, it's derived from the BER. */
643 /* Scale the BER from a 24bit to a SNR 16 bit where higher = better */
644 if (state->lastber < 5000)
645 state->snr = 655*100;
646 else if ( (state->lastber >= 5000) && (state->lastber < 55000) )
648 else if ( (state->lastber >= 55000) && (state->lastber < 150000) )
650 else if ( (state->lastber >= 150000) && (state->lastber < 250000) )
652 else if ( (state->lastber >= 250000) && (state->lastber < 450000) )
657 *ber = state->lastber;
662 static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
664 struct cx24123_state *state = fe->demodulator_priv;
665 *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */
670 static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr)
672 struct cx24123_state *state = fe->demodulator_priv;
678 static int cx24123_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
680 struct cx24123_state *state = fe->demodulator_priv;
681 *ucblocks = state->lastber;
686 static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
688 struct cx24123_state *state = fe->demodulator_priv;
690 if (state->config->set_ts_params)
691 state->config->set_ts_params(fe, 0);
693 state->currentfreq=p->frequency;
694 state->currentsymbolrate = p->u.qpsk.symbol_rate;
696 cx24123_set_inversion(state, p->inversion);
697 cx24123_set_fec(state, p->u.qpsk.fec_inner);
698 cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate);
699 cx24123_pll_tune(fe, p);
701 /* Enable automatic aquisition and reset cycle */
702 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
703 cx24123_writereg(state, 0x00, 0x10);
704 cx24123_writereg(state, 0x00, 0);
709 static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
711 struct cx24123_state *state = fe->demodulator_priv;
713 if (cx24123_get_inversion(state, &p->inversion) != 0) {
714 printk("%s: Failed to get inversion status\n",__FUNCTION__);
717 if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) {
718 printk("%s: Failed to get fec status\n",__FUNCTION__);
721 p->frequency = state->currentfreq;
722 p->u.qpsk.symbol_rate = state->currentsymbolrate;
727 static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
729 struct cx24123_state *state = fe->demodulator_priv;
732 val = cx24123_readlnbreg(state, 0x0);
736 return cx24123_writelnbreg(state, 0x0, val | 0x10);
738 return cx24123_writelnbreg(state, 0x0, val & 0x2f);
740 printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
745 static void cx24123_release(struct dvb_frontend* fe)
747 struct cx24123_state* state = fe->demodulator_priv;
748 dprintk("%s\n",__FUNCTION__);
752 static struct dvb_frontend_ops cx24123_ops;
754 struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
755 struct i2c_adapter* i2c)
757 struct cx24123_state* state = NULL;
760 dprintk("%s\n",__FUNCTION__);
762 /* allocate memory for the internal state */
763 state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL);
765 printk("Unable to kmalloc\n");
769 /* setup the state */
770 state->config = config;
772 memcpy(&state->ops, &cx24123_ops, sizeof(struct dvb_frontend_ops));
778 state->bandselectarg = 0;
780 state->currentfreq = 0;
781 state->currentsymbolrate = 0;
783 /* check if the demod is there */
784 ret = cx24123_readreg(state, 0x00);
785 if ((ret != 0xd1) && (ret != 0xe1)) {
786 printk("Version != d1 or e1\n");
790 /* create dvb_frontend */
791 state->frontend.ops = &state->ops;
792 state->frontend.demodulator_priv = state;
793 return &state->frontend;
801 static struct dvb_frontend_ops cx24123_ops = {
804 .name = "Conexant CX24123/CX24109",
806 .frequency_min = 950000,
807 .frequency_max = 2150000,
808 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
809 .frequency_tolerance = 29500,
810 .symbol_rate_min = 1000000,
811 .symbol_rate_max = 45000000,
812 .caps = FE_CAN_INVERSION_AUTO |
813 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
814 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
815 FE_CAN_QPSK | FE_CAN_RECOVER
818 .release = cx24123_release,
820 .init = cx24123_initfe,
821 .set_frontend = cx24123_set_frontend,
822 .get_frontend = cx24123_get_frontend,
823 .read_status = cx24123_read_status,
824 .read_ber = cx24123_read_ber,
825 .read_signal_strength = cx24123_read_signal_strength,
826 .read_snr = cx24123_read_snr,
827 .read_ucblocks = cx24123_read_ucblocks,
828 .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
829 .set_tone = cx24123_set_tone,
830 .set_voltage = cx24123_set_voltage,
833 module_param(debug, int, 0644);
834 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
836 MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware");
837 MODULE_AUTHOR("Steven Toth");
838 MODULE_LICENSE("GPL");
840 EXPORT_SYMBOL(cx24123_attach);