2 * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
4 * Copyright (C) 2009 DiBcom (http://www.dibcom.fr/)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
10 #include <linux/kernel.h>
11 #include <linux/i2c.h>
14 #include "dvb_frontend.h"
23 #define FE_CALLBACK_TIME_NEVER 0xffffffff
26 module_param(debug, int, 0644);
27 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
29 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB8000: "); printk(args); printk("\n"); } } while (0)
31 #define FE_STATUS_TUNE_FAILED 0
34 struct i2c_adapter *adap;
38 struct dib8000_state {
39 struct dvb_frontend fe;
40 struct dib8000_config cfg;
42 struct i2c_device i2c;
44 struct dibx000_i2c_master i2c_master;
49 u32 current_bandwidth;
50 struct dibx000_agc_config *current_agc;
59 u8 differential_constellation;
62 s16 ber_monitored_layer;
68 enum frontend_tune_state tune_state;
72 enum dib8000_power_mode {
73 DIB8000M_POWER_ALL = 0,
74 DIB8000M_POWER_INTERFACE_ONLY,
77 static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
79 u8 wb[2] = { reg >> 8, reg & 0xff };
81 struct i2c_msg msg[2] = {
82 {.addr = i2c->addr >> 1,.flags = 0,.buf = wb,.len = 2},
83 {.addr = i2c->addr >> 1,.flags = I2C_M_RD,.buf = rb,.len = 2},
86 if (i2c_transfer(i2c->adap, msg, 2) != 2)
87 dprintk("i2c read error on %d", reg);
89 return (rb[0] << 8) | rb[1];
92 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
94 return dib8000_i2c_read16(&state->i2c, reg);
97 static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
101 rw[0] = dib8000_read_word(state, reg + 0);
102 rw[1] = dib8000_read_word(state, reg + 1);
104 return ((rw[0] << 16) | (rw[1]));
107 static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
110 (reg >> 8) & 0xff, reg & 0xff,
111 (val >> 8) & 0xff, val & 0xff,
113 struct i2c_msg msg = {
114 .addr = i2c->addr >> 1,.flags = 0,.buf = b,.len = 4
116 return i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
119 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
121 return dib8000_i2c_write16(&state->i2c, reg, val);
124 static const int16_t coeff_2k_sb_1seg_dqpsk[8] = {
125 (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
129 static const int16_t coeff_2k_sb_1seg[8] = {
130 (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
133 static const int16_t coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
134 (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
138 static const int16_t coeff_2k_sb_3seg_0dqpsk[8] = {
139 (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
143 static const int16_t coeff_2k_sb_3seg_1dqpsk[8] = {
144 (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
148 static const int16_t coeff_2k_sb_3seg[8] = {
149 (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
153 static const int16_t coeff_4k_sb_1seg_dqpsk[8] = {
154 (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
158 static const int16_t coeff_4k_sb_1seg[8] = {
159 (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
163 static const int16_t coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
164 (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
168 static const int16_t coeff_4k_sb_3seg_0dqpsk[8] = {
169 (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
173 static const int16_t coeff_4k_sb_3seg_1dqpsk[8] = {
174 (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
178 static const int16_t coeff_4k_sb_3seg[8] = {
179 (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
183 static const int16_t coeff_8k_sb_1seg_dqpsk[8] = {
184 (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
188 static const int16_t coeff_8k_sb_1seg[8] = {
189 (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
193 static const int16_t coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
194 (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
198 static const int16_t coeff_8k_sb_3seg_0dqpsk[8] = {
199 (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
203 static const int16_t coeff_8k_sb_3seg_1dqpsk[8] = {
204 (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
208 static const int16_t coeff_8k_sb_3seg[8] = {
209 (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
213 static const int16_t ana_fe_coeff_3seg[24] = {
214 81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
217 static const int16_t ana_fe_coeff_1seg[24] = {
218 249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
221 static const int16_t ana_fe_coeff_13seg[24] = {
222 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
225 static u16 fft_to_mode(struct dib8000_state *state)
228 switch (state->fe.dtv_property_cache.transmission_mode) {
229 case TRANSMISSION_MODE_2K:
232 case TRANSMISSION_MODE_4K:
236 case TRANSMISSION_MODE_AUTO:
237 case TRANSMISSION_MODE_8K:
244 static void dib8000_set_acquisition_mode(struct dib8000_state *state)
246 u16 nud = dib8000_read_word(state, 298);
247 nud |= (1 << 3) | (1 << 0);
248 dprintk("acquisition mode activated");
249 dib8000_write_word(state, 298, nud);
252 static int dib8000_set_output_mode(struct dib8000_state *state, int mode)
254 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */
257 fifo_threshold = 1792;
258 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
260 dprintk("-I- Setting output mode for demod %p to %d", &state->fe, mode);
263 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
264 outreg = (1 << 10); /* 0x0400 */
266 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
267 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
269 case OUTMODE_MPEG2_SERIAL: // STBs with serial input
270 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
272 case OUTMODE_DIVERSITY:
273 if (state->cfg.hostbus_diversity) {
274 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
279 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
280 smo_mode |= (3 << 1);
281 fifo_threshold = 512;
282 outreg = (1 << 10) | (5 << 6);
284 case OUTMODE_HIGH_Z: // disable
288 case OUTMODE_ANALOG_ADC:
289 outreg = (1 << 10) | (3 << 6);
290 dib8000_set_acquisition_mode(state);
294 dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe);
298 if (state->cfg.output_mpeg2_in_188_bytes)
299 smo_mode |= (1 << 5);
301 dib8000_write_word(state, 299, smo_mode);
302 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */
303 dib8000_write_word(state, 1286, outreg);
304 dib8000_write_word(state, 1291, sram);
309 static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff)
311 struct dib8000_state *state = fe->demodulator_priv;
312 u16 sync_wait = dib8000_read_word(state, 273) & 0xfff0;
314 if (!state->differential_constellation) {
315 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1
316 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2
318 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0
319 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0
321 state->diversity_onoff = onoff;
324 case 0: /* only use the internal way - not the diversity input */
325 dib8000_write_word(state, 270, 1);
326 dib8000_write_word(state, 271, 0);
328 case 1: /* both ways */
329 dib8000_write_word(state, 270, 6);
330 dib8000_write_word(state, 271, 6);
332 case 2: /* only the diversity input */
333 dib8000_write_word(state, 270, 0);
334 dib8000_write_word(state, 271, 1);
340 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
342 /* by default everything is going to be powered off */
343 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
344 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
346 /* now, depending on the requested mode, we power on */
348 /* power up everything in the demod */
349 case DIB8000M_POWER_ALL:
356 case DIB8000M_POWER_INTERFACE_ONLY:
361 dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x", reg_774, reg_775, reg_776, reg_900, reg_1280);
362 dib8000_write_word(state, 774, reg_774);
363 dib8000_write_word(state, 775, reg_775);
364 dib8000_write_word(state, 776, reg_776);
365 dib8000_write_word(state, 900, reg_900);
366 dib8000_write_word(state, 1280, reg_1280);
369 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
372 u16 reg_907 = dib8000_read_word(state, 907), reg_908 = dib8000_read_word(state, 908);
375 case DIBX000_SLOW_ADC_ON:
376 reg_908 |= (1 << 1) | (1 << 0);
377 ret |= dib8000_write_word(state, 908, reg_908);
378 reg_908 &= ~(1 << 1);
381 case DIBX000_SLOW_ADC_OFF:
382 reg_908 |= (1 << 1) | (1 << 0);
390 case DIBX000_ADC_OFF: // leave the VBG voltage on
391 reg_907 |= (1 << 14) | (1 << 13) | (1 << 12);
392 reg_908 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
395 case DIBX000_VBG_ENABLE:
396 reg_907 &= ~(1 << 15);
399 case DIBX000_VBG_DISABLE:
400 reg_907 |= (1 << 15);
407 ret |= dib8000_write_word(state, 907, reg_907);
408 ret |= dib8000_write_word(state, 908, reg_908);
413 static int dib8000_set_bandwidth(struct dib8000_state *state, u32 bw)
420 if (state->timf == 0) {
421 dprintk("using default timf");
422 timf = state->timf_default;
424 dprintk("using updated timf");
428 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
429 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
434 static int dib8000_sad_calib(struct dib8000_state *state)
437 dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
438 dib8000_write_word(state, 924, 776); // 0.625*3.3 / 4096
440 /* do the calibration */
441 dib8000_write_word(state, 923, (1 << 0));
442 dib8000_write_word(state, 923, (0 << 0));
448 int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
450 struct dib8000_state *state = fe->demodulator_priv;
453 state->wbd_ref = value;
454 return dib8000_write_word(state, 106, value);
457 EXPORT_SYMBOL(dib8000_set_wbd_ref);
458 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
460 dprintk("ifreq: %d %x, inversion: %d", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
461 dib8000_write_word(state, 23, (u16) (((bw->internal * 1000) >> 16) & 0xffff)); /* P_sec_len */
462 dib8000_write_word(state, 24, (u16) ((bw->internal * 1000) & 0xffff));
463 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
464 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
465 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
467 dib8000_write_word(state, 922, bw->sad_cfg);
470 static void dib8000_reset_pll(struct dib8000_state *state)
472 const struct dibx000_bandwidth_config *pll = state->cfg.pll;
476 dib8000_write_word(state, 901, (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
479 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
480 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | (pll->pll_range << 1) | (pll->pll_reset << 0);
482 dib8000_write_word(state, 902, clk_cfg1);
483 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
484 dib8000_write_word(state, 902, clk_cfg1);
486 dprintk("clk_cfg1: 0x%04x", clk_cfg1); /* 0x507 1 0 1 000 0 0 11 1 */
488 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
489 if (state->cfg.pll->ADClkSrc == 0)
490 dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
491 else if (state->cfg.refclksel != 0)
492 dib8000_write_word(state, 904,
493 (0 << 15) | (1 << 12) | ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) | (pll->
494 ADClkSrc << 7) | (0 << 1));
496 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
498 dib8000_reset_pll_common(state, pll);
501 static int dib8000_reset_gpio(struct dib8000_state *st)
503 /* reset the GPIOs */
504 dib8000_write_word(st, 1029, st->cfg.gpio_dir);
505 dib8000_write_word(st, 1030, st->cfg.gpio_val);
507 /* TODO 782 is P_gpio_od */
509 dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
511 dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
515 static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val)
517 st->cfg.gpio_dir = dib8000_read_word(st, 1029);
518 st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */
519 st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */
520 dib8000_write_word(st, 1029, st->cfg.gpio_dir);
522 st->cfg.gpio_val = dib8000_read_word(st, 1030);
523 st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */
524 st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */
525 dib8000_write_word(st, 1030, st->cfg.gpio_val);
527 dprintk("gpio dir: %x: gpio val: %x", st->cfg.gpio_dir, st->cfg.gpio_val);
532 int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
534 struct dib8000_state *state = fe->demodulator_priv;
535 return dib8000_cfg_gpio(state, num, dir, val);
538 EXPORT_SYMBOL(dib8000_set_gpio);
539 static const u16 dib8000_defaults[] = {
540 /* auto search configuration - lock0 by default waiting
541 * for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */
562 0x6680 // P_corm_thres Lock algorithms configuration */
564 11, 80, /* set ADC level to -16 */
565 (1 << 13) - 825 - 117,
566 (1 << 13) - 837 - 117,
567 (1 << 13) - 811 - 117,
568 (1 << 13) - 766 - 117,
569 (1 << 13) - 737 - 117,
570 (1 << 13) - 693 - 117,
571 (1 << 13) - 648 - 117,
572 (1 << 13) - 619 - 117,
573 (1 << 13) - 575 - 117,
574 (1 << 13) - 531 - 117,
575 (1 << 13) - 501 - 117,
586 8192, // P_fft_nb_to_cut
589 0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800
592 0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
597 0x0666, // P_pha3_thres
598 0x0000, // P_cti_use_cpe, P_cti_use_prog
601 0x200f, // P_cspu_regul, P_cspu_win_cut
602 0x000f, // P_des_shift_work
605 0x023d, // P_adp_regul_cnt
606 0x00a4, // P_adp_noise_cnt
607 0x00a4, // P_adp_regul_ext
608 0x7ff0, // P_adp_noise_ext
612 0x0000, // P_2d_byp_ti_num
615 0x800, //P_equal_thres_wgn
618 (2 << 9) | 39, // P_equal_ctrl_synchro, P_equal_speedmode
621 0x0001, // P_div_lock0_wait
625 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
628 (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1
629 (1 << 10) | // P_ctrl_pre_freq_mode_sat=1
630 (0 << 9) | // P_ctrl_pre_freq_inh=0
631 (3 << 5) | // P_ctrl_pre_freq_step=3
632 (1 << 0), // P_pre_freq_win_len=1
635 (0 << 4) | 2, // P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW)
640 static u16 dib8000_identify(struct i2c_device *client)
644 //because of glitches sometimes
645 value = dib8000_i2c_read16(client, 896);
647 if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) {
648 dprintk("wrong Vendor ID (read=0x%x)", value);
652 value = dib8000_i2c_read16(client, 897);
653 if (value != 0x8000 && value != 0x8001 && value != 0x8002) {
654 dprintk("wrong Device ID (%x)", value);
660 dprintk("found DiB8000A");
663 dprintk("found DiB8000B");
666 dprintk("found DiB8000C");
672 static int dib8000_reset(struct dvb_frontend *fe)
674 struct dib8000_state *state = fe->demodulator_priv;
676 dib8000_write_word(state, 1287, 0x0003); /* sram lead in, rdy */
678 if ((state->revision = dib8000_identify(&state->i2c)) == 0)
681 if (state->revision == 0x8000)
682 dprintk("error : dib8000 MA not supported");
684 dibx000_reset_i2c_master(&state->i2c_master);
686 dib8000_set_power_mode(state, DIB8000M_POWER_ALL);
688 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
689 dib8000_set_adc_state(state, DIBX000_VBG_ENABLE);
691 /* restart all parts */
692 dib8000_write_word(state, 770, 0xffff);
693 dib8000_write_word(state, 771, 0xffff);
694 dib8000_write_word(state, 772, 0xfffc);
695 dib8000_write_word(state, 898, 0x000c); // sad
696 dib8000_write_word(state, 1280, 0x004d);
697 dib8000_write_word(state, 1281, 0x000c);
699 dib8000_write_word(state, 770, 0x0000);
700 dib8000_write_word(state, 771, 0x0000);
701 dib8000_write_word(state, 772, 0x0000);
702 dib8000_write_word(state, 898, 0x0004); // sad
703 dib8000_write_word(state, 1280, 0x0000);
704 dib8000_write_word(state, 1281, 0x0000);
707 if (state->cfg.drives)
708 dib8000_write_word(state, 906, state->cfg.drives);
710 dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.");
711 dib8000_write_word(state, 906, 0x2d98); // min drive SDRAM - not optimal - adjust
714 dib8000_reset_pll(state);
716 if (dib8000_reset_gpio(state) != 0)
717 dprintk("GPIO reset was not successful.");
719 if (dib8000_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
720 dprintk("OUTPUT_MODE could not be resetted.");
722 state->current_agc = NULL;
724 // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
725 /* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */
726 if (state->cfg.pll->ifreq == 0)
727 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */
729 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */
734 n = dib8000_defaults;
739 dib8000_write_word(state, r, *n++);
745 state->isdbt_cfg_loaded = 0;
747 //div_cfg override for special configs
748 if (state->cfg.div_cfg != 0)
749 dib8000_write_word(state, 903, state->cfg.div_cfg);
751 /* unforce divstr regardless whether i2c enumeration was done or not */
752 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
754 dib8000_set_bandwidth(state, 6000);
756 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
757 dib8000_sad_calib(state);
758 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
760 dib8000_set_power_mode(state, DIB8000M_POWER_INTERFACE_ONLY);
765 static void dib8000_restart_agc(struct dib8000_state *state)
767 // P_restart_iqc & P_restart_agc
768 dib8000_write_word(state, 770, 0x0a00);
769 dib8000_write_word(state, 770, 0x0000);
772 static int dib8000_update_lna(struct dib8000_state *state)
776 if (state->cfg.update_lna) {
777 // read dyn_gain here (because it is demod-dependent and not tuner)
778 dyn_gain = dib8000_read_word(state, 390);
780 if (state->cfg.update_lna(&state->fe, dyn_gain)) { // LNA has changed
781 dib8000_restart_agc(state);
788 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
790 struct dibx000_agc_config *agc = NULL;
792 if (state->current_band == band && state->current_agc != NULL)
794 state->current_band = band;
796 for (i = 0; i < state->cfg.agc_config_count; i++)
797 if (state->cfg.agc[i].band_caps & band) {
798 agc = &state->cfg.agc[i];
803 dprintk("no valid AGC configuration found for band 0x%02x", band);
807 state->current_agc = agc;
810 dib8000_write_word(state, 76, agc->setup);
811 dib8000_write_word(state, 77, agc->inv_gain);
812 dib8000_write_word(state, 78, agc->time_stabiliz);
813 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
815 // Demod AGC loop configuration
816 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
817 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
819 dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
820 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
823 if (state->wbd_ref != 0)
824 dib8000_write_word(state, 106, state->wbd_ref);
826 dib8000_write_word(state, 106, agc->wbd_ref);
827 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
828 dib8000_write_word(state, 108, agc->agc1_max);
829 dib8000_write_word(state, 109, agc->agc1_min);
830 dib8000_write_word(state, 110, agc->agc2_max);
831 dib8000_write_word(state, 111, agc->agc2_min);
832 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
833 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
834 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
835 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
837 dib8000_write_word(state, 75, agc->agc1_pt3);
838 dib8000_write_word(state, 923, (dib8000_read_word(state, 923) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2)); /*LB : 929 -> 923 */
843 void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
845 struct dib8000_state *state = fe->demodulator_priv;
846 dib8000_set_adc_state(state, DIBX000_ADC_ON);
847 dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
849 EXPORT_SYMBOL(dib8000_pwm_agc_reset);
851 static int dib8000_agc_soft_split(struct dib8000_state *state)
853 u16 agc, split_offset;
855 if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
856 return FE_CALLBACK_TIME_NEVER;
859 agc = dib8000_read_word(state, 390);
861 if (agc > state->current_agc->split.min_thres)
862 split_offset = state->current_agc->split.min;
863 else if (agc < state->current_agc->split.max_thres)
864 split_offset = state->current_agc->split.max;
866 split_offset = state->current_agc->split.max *
867 (agc - state->current_agc->split.min_thres) / (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
869 dprintk("AGC split_offset: %d", split_offset);
871 // P_agc_force_split and P_agc_split_offset
872 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
876 static int dib8000_agc_startup(struct dvb_frontend *fe)
878 struct dib8000_state *state = fe->demodulator_priv;
879 enum frontend_tune_state *tune_state = &state->tune_state;
883 switch (*tune_state) {
885 // set power-up level: interf+analog+AGC
887 dib8000_set_adc_state(state, DIBX000_ADC_ON);
889 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
890 *tune_state = CT_AGC_STOP;
891 state->status = FE_STATUS_TUNE_FAILED;
896 *tune_state = CT_AGC_STEP_0;
901 if (state->cfg.agc_control)
902 state->cfg.agc_control(&state->fe, 1);
904 dib8000_restart_agc(state);
906 // wait AGC rough lock time
908 *tune_state = CT_AGC_STEP_1;
912 // wait AGC accurate lock time
915 if (dib8000_update_lna(state))
916 // wait only AGC rough lock time
919 *tune_state = CT_AGC_STEP_2;
923 dib8000_agc_soft_split(state);
925 if (state->cfg.agc_control)
926 state->cfg.agc_control(&state->fe, 0);
928 *tune_state = CT_AGC_STOP;
931 ret = dib8000_agc_soft_split(state);
938 static const int32_t lut_1000ln_mant[] =
940 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
943 int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode)
945 struct dib8000_state *state = fe->demodulator_priv;
946 uint32_t ix = 0, tmp_val = 0, exp = 0, mant = 0;
949 val = dib8000_read32(state, 384);
950 /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */
953 while (tmp_val >>= 1)
955 mant = (val * 1000 / (1<<exp));
956 ix = (uint8_t)((mant-1000)/100); /* index of the LUT */
957 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */
958 val = (val*256)/1000;
962 EXPORT_SYMBOL(dib8000_get_adc_power);
964 static void dib8000_update_timf(struct dib8000_state *state)
966 u32 timf = state->timf = dib8000_read32(state, 435);
968 dib8000_write_word(state, 29, (u16) (timf >> 16));
969 dib8000_write_word(state, 30, (u16) (timf & 0xffff));
970 dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default);
973 static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
975 u16 mode, max_constellation, seg_diff_mask = 0, nbseg_diff = 0;
976 u8 guard, crate, constellation, timeI;
977 u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
978 u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled
979 const s16 *ncoeff = NULL, *ana_fe;
981 u16 coff_pow = 0x2800;
982 u16 init_prbs = 0xfff;
984 u16 adc_target_16dB[11] = {
985 (1 << 13) - 825 - 117,
986 (1 << 13) - 837 - 117,
987 (1 << 13) - 811 - 117,
988 (1 << 13) - 766 - 117,
989 (1 << 13) - 737 - 117,
990 (1 << 13) - 693 - 117,
991 (1 << 13) - 648 - 117,
992 (1 << 13) - 619 - 117,
993 (1 << 13) - 575 - 117,
994 (1 << 13) - 531 - 117,
995 (1 << 13) - 501 - 117
998 if (state->ber_monitored_layer != LAYER_ALL)
999 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer);
1001 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
1003 i = dib8000_read_word(state, 26) & 1; // P_dds_invspec
1004 dib8000_write_word(state, 26, state->fe.dtv_property_cache.inversion ^ i);
1006 if (state->fe.dtv_property_cache.isdbt_sb_mode) {
1007 //compute new dds_freq for the seg and adjust prbs
1009 state->fe.dtv_property_cache.isdbt_sb_segment_idx - (state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) -
1010 (state->fe.dtv_property_cache.isdbt_sb_segment_count % 2);
1011 int clk = state->cfg.pll->internal;
1012 u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26)
1013 int dds_offset = seg_offset * segtodds;
1014 int new_dds, sub_channel;
1015 if ((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0) // if even
1016 dds_offset -= (int)(segtodds / 2);
1018 if (state->cfg.pll->ifreq == 0) {
1019 if ((state->fe.dtv_property_cache.inversion ^ i) == 0) {
1020 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
1021 new_dds = dds_offset;
1023 new_dds = dds_offset;
1025 // We shift tuning frequency if the wanted segment is :
1026 // - the segment of center frequency with an odd total number of segments
1027 // - the segment to the left of center frequency with an even total number of segments
1028 // - the segment to the right of center frequency with an even total number of segments
1029 if ((state->fe.dtv_property_cache.delivery_system == SYS_ISDBT) && (state->fe.dtv_property_cache.isdbt_sb_mode == 1)
1031 (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2)
1032 && (state->fe.dtv_property_cache.isdbt_sb_segment_idx ==
1033 ((state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
1034 || (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
1035 && (state->fe.dtv_property_cache.isdbt_sb_segment_idx == (state->fe.dtv_property_cache.isdbt_sb_segment_count / 2)))
1036 || (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
1037 && (state->fe.dtv_property_cache.isdbt_sb_segment_idx ==
1038 ((state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
1040 new_dds -= ((u32) (850 << 22) / clk) << 4; // new_dds = 850 (freq shift in KHz) / Fclk * pow(2,26)
1043 if ((state->fe.dtv_property_cache.inversion ^ i) == 0)
1044 new_dds = state->cfg.pll->ifreq - dds_offset;
1046 new_dds = state->cfg.pll->ifreq + dds_offset;
1048 dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff));
1049 dib8000_write_word(state, 28, (u16) (new_dds & 0xffff));
1050 if (state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) // if odd
1051 sub_channel = ((state->fe.dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3;
1053 sub_channel = ((state->fe.dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3;
1056 if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K
1057 || state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) {
1058 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1
1059 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shift = 1
1061 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); //adp_pass =0
1062 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0
1065 switch (state->fe.dtv_property_cache.transmission_mode) {
1066 case TRANSMISSION_MODE_2K:
1067 switch (sub_channel) {
1114 case TRANSMISSION_MODE_4K:
1115 switch (sub_channel) {
1163 case TRANSMISSION_MODE_8K:
1164 switch (sub_channel) {
1211 } else { // if not state->fe.dtv_property_cache.isdbt_sb_mode
1212 dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff));
1213 dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff));
1214 dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003));
1217 dib8000_write_word(state, 10, (seq << 4));
1218 // dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000);
1220 switch (state->fe.dtv_property_cache.guard_interval) {
1221 case GUARD_INTERVAL_1_32:
1224 case GUARD_INTERVAL_1_16:
1227 case GUARD_INTERVAL_1_8:
1230 case GUARD_INTERVAL_1_4:
1236 dib8000_write_word(state, 1, (init_prbs << 2) | (guard & 0x3)); // ADDR 1
1238 max_constellation = DQPSK;
1239 for (i = 0; i < 3; i++) {
1240 switch (state->fe.dtv_property_cache.layer[i].modulation) {
1256 switch (state->fe.dtv_property_cache.layer[i].fec) {
1275 if ((state->fe.dtv_property_cache.layer[i].interleaving > 0) &&
1276 ((state->fe.dtv_property_cache.layer[i].interleaving <= 3) ||
1277 (state->fe.dtv_property_cache.layer[i].interleaving == 4 && state->fe.dtv_property_cache.isdbt_sb_mode == 1))
1279 timeI = state->fe.dtv_property_cache.layer[i].interleaving;
1282 dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe.dtv_property_cache.layer[i].segment_count & 0xf) << 6) |
1283 (crate << 3) | timeI);
1284 if (state->fe.dtv_property_cache.layer[i].segment_count > 0) {
1285 switch (max_constellation) {
1288 if (state->fe.dtv_property_cache.layer[i].modulation == QAM_16 ||
1289 state->fe.dtv_property_cache.layer[i].modulation == QAM_64)
1290 max_constellation = state->fe.dtv_property_cache.layer[i].modulation;
1293 if (state->fe.dtv_property_cache.layer[i].modulation == QAM_64)
1294 max_constellation = state->fe.dtv_property_cache.layer[i].modulation;
1300 mode = fft_to_mode(state);
1302 //dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/
1304 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) |
1305 ((state->fe.dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe.dtv_property_cache.
1306 isdbt_sb_mode & 1) << 4));
1308 dprintk("mode = %d ; guard = %d", mode, state->fe.dtv_property_cache.guard_interval);
1310 /* signal optimization parameter */
1312 if (state->fe.dtv_property_cache.isdbt_partial_reception) {
1313 seg_diff_mask = (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0];
1314 for (i = 1; i < 3; i++)
1316 (state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * state->fe.dtv_property_cache.layer[i].segment_count;
1317 for (i = 0; i < nbseg_diff; i++)
1318 seg_diff_mask |= 1 << permu_seg[i + 1];
1320 for (i = 0; i < 3; i++)
1322 (state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * state->fe.dtv_property_cache.layer[i].segment_count;
1323 for (i = 0; i < nbseg_diff; i++)
1324 seg_diff_mask |= 1 << permu_seg[i];
1326 dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask);
1328 state->differential_constellation = (seg_diff_mask != 0);
1329 dib8000_set_diversity_in(&state->fe, state->diversity_onoff);
1331 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb
1332 if (state->fe.dtv_property_cache.isdbt_partial_reception == 1) // 3-segments
1333 seg_mask13 = 0x00E0;
1335 seg_mask13 = 0x0040;
1337 seg_mask13 = 0x1fff;
1339 // WRITE: Mode & Diff mask
1340 dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask);
1342 if ((seg_diff_mask) || (state->fe.dtv_property_cache.isdbt_sb_mode))
1343 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
1345 dib8000_write_word(state, 268, (2 << 9) | 39); //init value
1349 dib8000_write_word(state, 352, seg_diff_mask); // ADDR 352
1351 dib8000_write_word(state, 353, seg_mask13); // ADDR 353
1353 /* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */
1354 // dib8000_write_word(state, 351, (state->fe.dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5 );
1357 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
1358 switch (state->fe.dtv_property_cache.transmission_mode) {
1359 case TRANSMISSION_MODE_2K:
1360 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg
1361 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK
1362 ncoeff = coeff_2k_sb_1seg_dqpsk;
1364 ncoeff = coeff_2k_sb_1seg;
1365 } else { // 3-segments
1366 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment
1367 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments
1368 ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
1369 else // QPSK or QAM on external segments
1370 ncoeff = coeff_2k_sb_3seg_0dqpsk;
1371 } else { // QPSK or QAM on central segment
1372 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments
1373 ncoeff = coeff_2k_sb_3seg_1dqpsk;
1374 else // QPSK or QAM on external segments
1375 ncoeff = coeff_2k_sb_3seg;
1380 case TRANSMISSION_MODE_4K:
1381 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg
1382 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK
1383 ncoeff = coeff_4k_sb_1seg_dqpsk;
1385 ncoeff = coeff_4k_sb_1seg;
1386 } else { // 3-segments
1387 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment
1388 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments
1389 ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
1390 } else { // QPSK or QAM on external segments
1391 ncoeff = coeff_4k_sb_3seg_0dqpsk;
1393 } else { // QPSK or QAM on central segment
1394 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments
1395 ncoeff = coeff_4k_sb_3seg_1dqpsk;
1396 } else // QPSK or QAM on external segments
1397 ncoeff = coeff_4k_sb_3seg;
1402 case TRANSMISSION_MODE_AUTO:
1403 case TRANSMISSION_MODE_8K:
1405 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg
1406 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK
1407 ncoeff = coeff_8k_sb_1seg_dqpsk;
1409 ncoeff = coeff_8k_sb_1seg;
1410 } else { // 3-segments
1411 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment
1412 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments
1413 ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
1414 } else { // QPSK or QAM on external segments
1415 ncoeff = coeff_8k_sb_3seg_0dqpsk;
1417 } else { // QPSK or QAM on central segment
1418 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments
1419 ncoeff = coeff_8k_sb_3seg_1dqpsk;
1420 } else // QPSK or QAM on external segments
1421 ncoeff = coeff_8k_sb_3seg;
1426 for (i = 0; i < 8; i++)
1427 dib8000_write_word(state, 343 + i, ncoeff[i]);
1430 // P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5
1431 dib8000_write_word(state, 351,
1432 (state->fe.dtv_property_cache.isdbt_sb_mode << 9) | (state->fe.dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5);
1435 // Carloff, the most robust
1436 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // Sound Broadcasting mode - use both TMCC and AC pilots
1438 // P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64
1439 // P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1
1440 dib8000_write_word(state, 187,
1441 (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe.dtv_property_cache.isdbt_partial_reception & 1) << 2)
1444 /* // P_small_coef_ext_enable = 1 */
1445 /* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */
1447 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg
1449 // P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1)
1451 dib8000_write_word(state, 180, 0x1fcf | ((mode - 1) << 14));
1453 dib8000_write_word(state, 180, 0x0fcf | ((mode - 1) << 14));
1454 // P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1,
1455 // P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4
1456 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
1457 // P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8
1458 dib8000_write_word(state, 340, (16 << 6) | (8 << 0));
1459 // P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1
1460 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
1462 // P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k
1463 dib8000_write_word(state, 181, 300);
1464 dib8000_write_word(state, 182, 150);
1465 dib8000_write_word(state, 183, 80);
1466 dib8000_write_word(state, 184, 300);
1467 dib8000_write_word(state, 185, 150);
1468 dib8000_write_word(state, 186, 80);
1469 } else { // Sound Broadcasting mode 3 seg
1470 // P_coff_one_seg_sym= 1, P_coff_one_seg_width= 1, P_coff_winlen=63, P_coff_thres_lock=15
1471 /* if (mode == 3) */
1472 /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */
1474 /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */
1475 dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
1477 // P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1,
1478 // P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4
1479 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
1480 // P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8
1481 dib8000_write_word(state, 340, (16 << 6) | (8 << 0));
1482 //P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1
1483 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
1485 // P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k
1486 dib8000_write_word(state, 181, 350);
1487 dib8000_write_word(state, 182, 300);
1488 dib8000_write_word(state, 183, 250);
1489 dib8000_write_word(state, 184, 350);
1490 dib8000_write_word(state, 185, 300);
1491 dib8000_write_word(state, 186, 250);
1494 } else if (state->isdbt_cfg_loaded == 0) { // if not Sound Broadcasting mode : put default values for 13 segments
1495 dib8000_write_word(state, 180, (16 << 6) | 9);
1496 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
1498 for (i = 0; i < 6; i++)
1499 dib8000_write_word(state, 181 + i, coff_pow);
1501 // P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1,
1502 // P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1
1503 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
1505 // P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6
1506 dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
1507 // P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1
1508 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
1511 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1 && state->fe.dtv_property_cache.isdbt_partial_reception == 0) // 1-seg
1512 dib8000_write_word(state, 178, 64); // P_fft_powrange=64
1514 dib8000_write_word(state, 178, 32); // P_fft_powrange=32
1516 /* make the cpil_coff_lock more robust but slower p_coff_winlen
1517 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
1519 /* if ( ( nbseg_diff>0)&&(nbseg_diff<13))
1520 dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */
1522 dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */
1523 dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */
1524 dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */
1525 if ((!state->fe.dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0))
1526 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
1528 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */
1529 dib8000_write_word(state, 287, ~seg_mask13 | 0x1000); /* P_tmcc_seg_inh */
1530 //dib8000_write_word(state, 288, ~seg_mask13 | seg_diff_mask); /* P_tmcc_seg_eq_inh */
1532 dib8000_write_word(state, 288, (~seg_mask13 | seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
1534 dib8000_write_word(state, 288, 0x1fff); //disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels.
1535 dprintk("287 = %X (%d)", ~seg_mask13 | 0x1000, ~seg_mask13 | 0x1000);
1537 dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */
1539 /* offset loop parameters */
1540 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
1541 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg
1542 /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
1543 dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40);
1545 else // Sound Broadcasting mode 3 seg
1546 /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
1547 dib8000_write_word(state, 32, ((10 - mode) << 12) | (6 << 8) | 0x60);
1549 // TODO in 13 seg, timf_alpha can always be the same or not ?
1550 /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
1551 dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80);
1553 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
1554 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg
1555 /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */
1556 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode));
1558 else // Sound Broadcasting mode 3 seg
1559 /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */
1560 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (9 - mode));
1562 /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */
1563 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode));
1565 /* P_dvsy_sync_wait - reuse mode */
1566 switch (state->fe.dtv_property_cache.transmission_mode) {
1567 case TRANSMISSION_MODE_8K:
1570 case TRANSMISSION_MODE_4K:
1574 case TRANSMISSION_MODE_2K:
1578 if (state->cfg.diversity_delay == 0)
1579 mode = (mode * (1 << (guard)) * 3) / 2 + 48; // add 50% SFN margin + compensate for one DVSY-fifo
1581 mode = (mode * (1 << (guard)) * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compensate for DVSY-fifo
1583 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | mode);
1585 /* channel estimation fine configuration */
1586 switch (max_constellation) {
1588 ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB
1589 coeff[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
1590 coeff[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
1591 coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
1592 coeff[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
1593 //if (!state->cfg.hostbus_diversity) //if diversity, we should prehaps use the configuration of the max_constallation -1
1596 ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB
1597 coeff[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
1598 coeff[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
1599 coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
1600 coeff[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
1601 //if (!((state->cfg.hostbus_diversity) && (max_constellation == QAM_16)))
1604 ana_gain = 0; // 0 : goes along with ADC target at -22dB to keep good mobile performance and lock at sensitivity level
1605 coeff[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
1606 coeff[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
1607 coeff[2] = 0x0333; /* P_adp_regul_ext 0.1 */
1608 coeff[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
1611 for (mode = 0; mode < 4; mode++)
1612 dib8000_write_word(state, 215 + mode, coeff[mode]);
1614 // update ana_gain depending on max constellation
1615 dib8000_write_word(state, 116, ana_gain);
1616 // update ADC target depending on ana_gain
1617 if (ana_gain) { // set -16dB ADC target for ana_gain=-1
1618 for (i = 0; i < 10; i++)
1619 dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
1620 } else { // set -22dB ADC target for ana_gain=0
1621 for (i = 0; i < 10; i++)
1622 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
1626 if (state->fe.dtv_property_cache.isdbt_sb_mode) {
1627 if (state->fe.dtv_property_cache.isdbt_partial_reception == 1) // 3-segments
1628 ana_fe = ana_fe_coeff_3seg;
1630 ana_fe = ana_fe_coeff_1seg;
1632 ana_fe = ana_fe_coeff_13seg;
1634 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0)
1635 for (mode = 0; mode < 24; mode++)
1636 dib8000_write_word(state, 117 + mode, ana_fe[mode]);
1638 // ---- CHAN_BLK ----
1639 for (i = 0; i < 13; i++) {
1640 if ((((~seg_diff_mask) >> i) & 1) == 1) {
1641 P_cfr_left_edge += (1 << i) * ((i == 0) || ((((seg_mask13 & (~seg_diff_mask)) >> (i - 1)) & 1) == 0));
1642 P_cfr_right_edge += (1 << i) * ((i == 12) || ((((seg_mask13 & (~seg_diff_mask)) >> (i + 1)) & 1) == 0));
1645 dib8000_write_word(state, 222, P_cfr_left_edge); // P_cfr_left_edge
1646 dib8000_write_word(state, 223, P_cfr_right_edge); // P_cfr_right_edge
1647 // "P_cspu_left_edge" not used => do not care
1648 // "P_cspu_right_edge" not used => do not care
1650 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb
1651 dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1
1652 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0
1653 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0 // 1-segment
1654 && state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) {
1655 //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0
1656 dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15
1658 } else if (state->isdbt_cfg_loaded == 0) {
1659 dib8000_write_word(state, 228, 0); // default value
1660 dib8000_write_word(state, 265, 31); // default value
1661 dib8000_write_word(state, 205, 0x200f); // init value
1664 for (i = 0; i < 3; i++)
1666 (((state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe.dtv_property_cache.layer[i].segment_count);
1667 // Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9);
1668 // Threshold is set at 1/4 of max power.
1669 tmcc_pow *= (1 << (9 - 2));
1671 dib8000_write_word(state, 290, tmcc_pow); // P_tmcc_dec_thres_2k
1672 dib8000_write_word(state, 291, tmcc_pow); // P_tmcc_dec_thres_4k
1673 dib8000_write_word(state, 292, tmcc_pow); // P_tmcc_dec_thres_8k
1674 //dib8000_write_word(state, 287, (1 << 13) | 0x1000 );
1677 if (state->isdbt_cfg_loaded == 0)
1678 dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */
1680 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1)
1681 state->isdbt_cfg_loaded = 0;
1683 state->isdbt_cfg_loaded = 1;
1687 static int dib8000_autosearch_start(struct dvb_frontend *fe)
1691 struct dib8000_state *state = fe->demodulator_priv;
1695 state->fe.dtv_property_cache.inversion = 0;
1696 if (!state->fe.dtv_property_cache.isdbt_sb_mode)
1697 state->fe.dtv_property_cache.layer[0].segment_count = 13;
1698 state->fe.dtv_property_cache.layer[0].modulation = QAM_64;
1699 state->fe.dtv_property_cache.layer[0].fec = FEC_2_3;
1700 state->fe.dtv_property_cache.layer[0].interleaving = 0;
1702 //choose the right list, in sb, always do everything
1703 if (state->fe.dtv_property_cache.isdbt_sb_mode) {
1704 state->fe.dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1705 state->fe.dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1707 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
1709 if (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) {
1710 if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
1712 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to have autosearch start ok with mode2
1716 if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
1718 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
1723 if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO)
1724 state->fe.dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1725 if (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO)
1726 state->fe.dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1728 dprintk("using list for autosearch : %d", slist);
1729 dib8000_set_channel(state, (unsigned char)slist, 1);
1730 //dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
1734 //set lock_mask values
1735 dib8000_write_word(state, 6, 0x4);
1736 dib8000_write_word(state, 7, 0x8);
1737 dib8000_write_word(state, 8, 0x1000);
1739 //set lock_mask wait time values
1740 value = 50 * state->cfg.pll->internal * factor;
1741 dib8000_write_word(state, 11, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
1742 dib8000_write_word(state, 12, (u16) (value & 0xffff)); // lock0 wait time
1743 value = 100 * state->cfg.pll->internal * factor;
1744 dib8000_write_word(state, 13, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
1745 dib8000_write_word(state, 14, (u16) (value & 0xffff)); // lock1 wait time
1746 value = 1000 * state->cfg.pll->internal * factor;
1747 dib8000_write_word(state, 15, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
1748 dib8000_write_word(state, 16, (u16) (value & 0xffff)); // lock2 wait time
1750 value = dib8000_read_word(state, 0);
1751 dib8000_write_word(state, 0, (u16) ((1 << 15) | value));
1752 dib8000_read_word(state, 1284); // reset the INT. n_irq_pending
1753 dib8000_write_word(state, 0, (u16) value);
1760 static int dib8000_autosearch_irq(struct dvb_frontend *fe)
1762 struct dib8000_state *state = fe->demodulator_priv;
1763 u16 irq_pending = dib8000_read_word(state, 1284);
1765 if (irq_pending & 0x1) { // failed
1766 dprintk("dib8000_autosearch_irq failed");
1770 if (irq_pending & 0x2) { // succeeded
1771 dprintk("dib8000_autosearch_irq succeeded");
1775 return 0; // still pending
1778 static int dib8000_tune(struct dvb_frontend *fe)
1780 struct dib8000_state *state = fe->demodulator_priv;
1782 u16 value, mode = fft_to_mode(state);
1784 // we are already tuned - just resuming from suspend
1788 dib8000_set_bandwidth(state, state->fe.dtv_property_cache.bandwidth_hz / 1000);
1789 dib8000_set_channel(state, 0, 0);
1792 ret |= dib8000_write_word(state, 770, 0x4000);
1793 ret |= dib8000_write_word(state, 770, 0x0000);
1796 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3 */
1797 /* ret |= dib8000_write_word(state, 29, (0 << 9) | (4 << 5) | (0 << 4) | (3 << 0) ); workaround inh_isi stays at 1 */
1799 // never achieved a lock before - wait for timfreq to update
1800 if (state->timf == 0) {
1801 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
1802 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg
1804 else // Sound Broadcasting mode 3 seg
1810 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
1811 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg
1813 /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */
1814 dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40);
1815 //dib8000_write_word(state, 32, (8 << 12) | (6 << 8) | 0x80);
1817 /* P_ctrl_sfreq_step= (12-P_mode) P_ctrl_sfreq_inh =0 P_ctrl_pha_off_max */
1818 ret |= dib8000_write_word(state, 37, (12 - mode) | ((5 + mode) << 5));
1820 } else { // Sound Broadcasting mode 3 seg
1822 /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 alpha to check on board */
1823 dib8000_write_word(state, 32, ((12 - mode) << 12) | (6 << 8) | 0x60);
1825 ret |= dib8000_write_word(state, 37, (11 - mode) | ((5 + mode) << 5));
1829 /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 alpha to check on board */
1830 dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x80);
1832 ret |= dib8000_write_word(state, 37, (10 - mode) | ((5 + mode) << 5));
1836 // we achieved a coff_cpil_lock - it's time to update the timf
1837 if ((dib8000_read_word(state, 568) >> 11) & 0x1)
1838 dib8000_update_timf(state);
1840 //now that tune is finished, lock0 should lock on fec_mpeg to output this lock on MP_LOCK. It's changed in autosearch start
1841 dib8000_write_word(state, 6, 0x200);
1843 if (state->revision == 0x8002) {
1844 value = dib8000_read_word(state, 903);
1845 dib8000_write_word(state, 903, value & ~(1 << 3));
1847 dib8000_write_word(state, 903, value | (1 << 3));
1853 static int dib8000_wakeup(struct dvb_frontend *fe)
1855 struct dib8000_state *state = fe->demodulator_priv;
1857 dib8000_set_power_mode(state, DIB8000M_POWER_ALL);
1858 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1859 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
1860 dprintk("could not start Slow ADC");
1865 static int dib8000_sleep(struct dvb_frontend *fe)
1867 struct dib8000_state *st = fe->demodulator_priv;
1869 dib8000_set_output_mode(st, OUTMODE_HIGH_Z);
1870 dib8000_set_power_mode(st, DIB8000M_POWER_INTERFACE_ONLY);
1871 return dib8000_set_adc_state(st, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(st, DIBX000_ADC_OFF);
1878 enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
1880 struct dib8000_state *state = fe->demodulator_priv;
1881 return state->tune_state;
1883 EXPORT_SYMBOL(dib8000_get_tune_state);
1885 int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
1887 struct dib8000_state *state = fe->demodulator_priv;
1888 state->tune_state = tune_state;
1891 EXPORT_SYMBOL(dib8000_set_tune_state);
1896 static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1898 struct dib8000_state *state = fe->demodulator_priv;
1901 fe->dtv_property_cache.bandwidth_hz = 6000000;
1903 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
1905 val = dib8000_read_word(state, 570);
1906 fe->dtv_property_cache.inversion = (val & 0x40) >> 6;
1907 switch ((val & 0x30) >> 4) {
1909 fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
1913 fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1917 switch (val & 0x3) {
1919 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
1920 dprintk("dib8000_get_frontend GI = 1/32 ");
1923 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
1924 dprintk("dib8000_get_frontend GI = 1/16 ");
1927 dprintk("dib8000_get_frontend GI = 1/8 ");
1928 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1931 dprintk("dib8000_get_frontend GI = 1/4 ");
1932 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
1936 val = dib8000_read_word(state, 505);
1937 fe->dtv_property_cache.isdbt_partial_reception = val & 1;
1938 dprintk("dib8000_get_frontend : partial_reception = %d ", fe->dtv_property_cache.isdbt_partial_reception);
1940 for (i = 0; i < 3; i++) {
1941 val = dib8000_read_word(state, 493 + i);
1942 fe->dtv_property_cache.layer[i].segment_count = val & 0x0F;
1943 dprintk("dib8000_get_frontend : Layer %d segments = %d ", i, fe->dtv_property_cache.layer[i].segment_count);
1945 val = dib8000_read_word(state, 499 + i);
1946 fe->dtv_property_cache.layer[i].interleaving = val & 0x3;
1947 dprintk("dib8000_get_frontend : Layer %d time_intlv = %d ", i, fe->dtv_property_cache.layer[i].interleaving);
1949 val = dib8000_read_word(state, 481 + i);
1950 switch (val & 0x7) {
1952 fe->dtv_property_cache.layer[i].fec = FEC_1_2;
1953 dprintk("dib8000_get_frontend : Layer %d Code Rate = 1/2 ", i);
1956 fe->dtv_property_cache.layer[i].fec = FEC_2_3;
1957 dprintk("dib8000_get_frontend : Layer %d Code Rate = 2/3 ", i);
1960 fe->dtv_property_cache.layer[i].fec = FEC_3_4;
1961 dprintk("dib8000_get_frontend : Layer %d Code Rate = 3/4 ", i);
1964 fe->dtv_property_cache.layer[i].fec = FEC_5_6;
1965 dprintk("dib8000_get_frontend : Layer %d Code Rate = 5/6 ", i);
1968 fe->dtv_property_cache.layer[i].fec = FEC_7_8;
1969 dprintk("dib8000_get_frontend : Layer %d Code Rate = 7/8 ", i);
1973 val = dib8000_read_word(state, 487 + i);
1974 switch (val & 0x3) {
1976 dprintk("dib8000_get_frontend : Layer %d DQPSK ", i);
1977 fe->dtv_property_cache.layer[i].modulation = DQPSK;
1980 fe->dtv_property_cache.layer[i].modulation = QPSK;
1981 dprintk("dib8000_get_frontend : Layer %d QPSK ", i);
1984 fe->dtv_property_cache.layer[i].modulation = QAM_16;
1985 dprintk("dib8000_get_frontend : Layer %d QAM16 ", i);
1989 dprintk("dib8000_get_frontend : Layer %d QAM64 ", i);
1990 fe->dtv_property_cache.layer[i].modulation = QAM_64;
1997 static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1999 struct dib8000_state *state = fe->demodulator_priv;
2002 dib8000_set_output_mode(state, OUTMODE_HIGH_Z);
2004 if (fe->ops.tuner_ops.set_params)
2005 fe->ops.tuner_ops.set_params(fe, fep);
2007 /* start up the AGC */
2008 state->tune_state = CT_AGC_START;
2010 time = dib8000_agc_startup(fe);
2011 if (time != FE_CALLBACK_TIME_NEVER)
2015 } while (state->tune_state != CT_AGC_STOP);
2017 if (state->fe.dtv_property_cache.frequency == 0) {
2018 dprintk("dib8000: must at least specify frequency ");
2022 if (state->fe.dtv_property_cache.bandwidth_hz == 0) {
2023 dprintk("dib8000: no bandwidth specified, set to default ");
2024 state->fe.dtv_property_cache.bandwidth_hz = 6000000;
2027 state->tune_state = CT_DEMOD_START;
2029 if ((state->fe.dtv_property_cache.delivery_system != SYS_ISDBT) ||
2030 (state->fe.dtv_property_cache.inversion == INVERSION_AUTO) ||
2031 (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) ||
2032 (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) ||
2033 (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) &&
2034 (state->fe.dtv_property_cache.layer[0].segment_count != 0xff) &&
2035 (state->fe.dtv_property_cache.layer[0].segment_count != 0) &&
2036 ((state->fe.dtv_property_cache.layer[0].modulation == QAM_AUTO) ||
2037 (state->fe.dtv_property_cache.layer[0].fec == FEC_AUTO))) ||
2038 (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) &&
2039 (state->fe.dtv_property_cache.layer[1].segment_count != 0xff) &&
2040 (state->fe.dtv_property_cache.layer[1].segment_count != 0) &&
2041 ((state->fe.dtv_property_cache.layer[1].modulation == QAM_AUTO) ||
2042 (state->fe.dtv_property_cache.layer[1].fec == FEC_AUTO))) ||
2043 (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) &&
2044 (state->fe.dtv_property_cache.layer[2].segment_count != 0xff) &&
2045 (state->fe.dtv_property_cache.layer[2].segment_count != 0) &&
2046 ((state->fe.dtv_property_cache.layer[2].modulation == QAM_AUTO) ||
2047 (state->fe.dtv_property_cache.layer[2].fec == FEC_AUTO))) ||
2048 (((state->fe.dtv_property_cache.layer[0].segment_count == 0) ||
2049 ((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) &&
2050 ((state->fe.dtv_property_cache.layer[1].segment_count == 0) ||
2051 ((state->fe.dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
2052 ((state->fe.dtv_property_cache.layer[2].segment_count == 0) || ((state->fe.dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
2055 dib8000_set_bandwidth(state, fe->dtv_property_cache.bandwidth_hz / 1000);
2056 dib8000_autosearch_start(fe);
2059 found = dib8000_autosearch_irq(fe);
2060 } while (found == 0 && i--);
2062 dprintk("Frequency %d Hz, autosearch returns: %d", fep->frequency, found);
2064 if (found == 0 || found == 1)
2065 return 0; // no channel found
2067 dib8000_get_frontend(fe, fep);
2070 ret = dib8000_tune(fe);
2072 /* make this a config parameter */
2073 dib8000_set_output_mode(state, state->cfg.output_mode);
2078 static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2080 struct dib8000_state *state = fe->demodulator_priv;
2081 u16 lock = dib8000_read_word(state, 568);
2085 if ((lock >> 13) & 1)
2086 *stat |= FE_HAS_SIGNAL;
2088 if ((lock >> 8) & 1) /* Equal */
2089 *stat |= FE_HAS_CARRIER;
2091 if (((lock >> 1) & 0xf) == 0xf) /* TMCC_SYNC */
2092 *stat |= FE_HAS_SYNC;
2094 if (((lock >> 12) & 1) && ((lock >> 5) & 7)) /* FEC MPEG */
2095 *stat |= FE_HAS_LOCK;
2097 if ((lock >> 12) & 1) {
2098 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
2100 *stat |= FE_HAS_VITERBI;
2102 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
2104 *stat |= FE_HAS_VITERBI;
2106 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
2108 *stat |= FE_HAS_VITERBI;
2114 static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
2116 struct dib8000_state *state = fe->demodulator_priv;
2117 *ber = (dib8000_read_word(state, 560) << 16) | dib8000_read_word(state, 561); // 13 segments
2121 static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
2123 struct dib8000_state *state = fe->demodulator_priv;
2124 *unc = dib8000_read_word(state, 565); // packet error on 13 seg
2128 static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2130 struct dib8000_state *state = fe->demodulator_priv;
2131 u16 val = dib8000_read_word(state, 390);
2132 *strength = 65535 - val;
2136 static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
2138 struct dib8000_state *state = fe->demodulator_priv;
2140 s32 signal_mant, signal_exp, noise_mant, noise_exp;
2143 val = dib8000_read_word(state, 542);
2144 noise_mant = (val >> 6) & 0xff;
2145 noise_exp = (val & 0x3f);
2147 val = dib8000_read_word(state, 543);
2148 signal_mant = (val >> 6) & 0xff;
2149 signal_exp = (val & 0x3f);
2151 if ((noise_exp & 0x20) != 0)
2153 if ((signal_exp & 0x20) != 0)
2156 if (signal_mant != 0)
2157 result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
2159 result = intlog10(2) * 10 * signal_exp - 100;
2160 if (noise_mant != 0)
2161 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
2163 result -= intlog10(2) * 10 * noise_exp - 100;
2165 *snr = result / ((1 << 24) / 10);
2169 int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
2173 struct i2c_device client = {.adap = host };
2175 for (k = no_of_demods - 1; k >= 0; k--) {
2176 /* designated i2c address */
2177 new_addr = first_addr + (k << 1);
2179 client.addr = new_addr;
2180 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */
2181 if (dib8000_identify(&client) == 0) {
2182 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */
2183 client.addr = default_addr;
2184 if (dib8000_identify(&client) == 0) {
2185 dprintk("#%d: not identified", k);
2190 /* start diversity to pull_down div_str - just for i2c-enumeration */
2191 dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6));
2193 /* set new i2c address and force divstart */
2194 dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2);
2195 client.addr = new_addr;
2196 dib8000_identify(&client);
2198 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
2201 for (k = 0; k < no_of_demods; k++) {
2202 new_addr = first_addr | (k << 1);
2203 client.addr = new_addr;
2206 dib8000_i2c_write16(&client, 1285, new_addr << 2);
2208 /* deactivate div - it was just for i2c-enumeration */
2209 dib8000_i2c_write16(&client, 1286, 0);
2215 EXPORT_SYMBOL(dib8000_i2c_enumeration);
2216 static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
2218 tune->min_delay_ms = 1000;
2219 tune->step_size = 0;
2220 tune->max_drift = 0;
2224 static void dib8000_release(struct dvb_frontend *fe)
2226 struct dib8000_state *st = fe->demodulator_priv;
2227 dibx000_exit_i2c_master(&st->i2c_master);
2231 struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
2233 struct dib8000_state *st = fe->demodulator_priv;
2234 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
2237 EXPORT_SYMBOL(dib8000_get_i2c_master);
2239 int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
2241 struct dib8000_state *st = fe->demodulator_priv;
2242 u16 val = dib8000_read_word(st, 299) & 0xffef;
2243 val |= (onoff & 0x1) << 4;
2245 dprintk("pid filter enabled %d", onoff);
2246 return dib8000_write_word(st, 299, val);
2248 EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
2250 int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
2252 struct dib8000_state *st = fe->demodulator_priv;
2253 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
2254 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
2256 EXPORT_SYMBOL(dib8000_pid_filter);
2258 static const struct dvb_frontend_ops dib8000_ops = {
2260 .name = "DiBcom 8000 ISDB-T",
2262 .frequency_min = 44250000,
2263 .frequency_max = 867250000,
2264 .frequency_stepsize = 62500,
2265 .caps = FE_CAN_INVERSION_AUTO |
2266 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2267 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2268 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2269 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2272 .release = dib8000_release,
2274 .init = dib8000_wakeup,
2275 .sleep = dib8000_sleep,
2277 .set_frontend = dib8000_set_frontend,
2278 .get_tune_settings = dib8000_fe_get_tune_settings,
2279 .get_frontend = dib8000_get_frontend,
2281 .read_status = dib8000_read_status,
2282 .read_ber = dib8000_read_ber,
2283 .read_signal_strength = dib8000_read_signal_strength,
2284 .read_snr = dib8000_read_snr,
2285 .read_ucblocks = dib8000_read_unc_blocks,
2288 struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
2290 struct dvb_frontend *fe;
2291 struct dib8000_state *state;
2293 dprintk("dib8000_attach");
2295 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
2299 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
2300 state->i2c.adap = i2c_adap;
2301 state->i2c.addr = i2c_addr;
2302 state->gpio_val = cfg->gpio_val;
2303 state->gpio_dir = cfg->gpio_dir;
2305 /* Ensure the output mode remains at the previous default if it's
2306 * not specifically set by the caller.
2308 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2309 state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
2312 fe->demodulator_priv = state;
2313 memcpy(&state->fe.ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
2315 state->timf_default = cfg->pll->timf;
2317 if (dib8000_identify(&state->i2c) == 0)
2320 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
2324 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
2333 EXPORT_SYMBOL(dib8000_attach);
2335 MODULE_AUTHOR("Olivier Grenie <Olivier.Grenie@dibcom.fr, " "Patrick Boettcher <pboettcher@dibcom.fr>");
2336 MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");
2337 MODULE_LICENSE("GPL");