drivers/media/dvb/frontends/stv0900_core.c

   1 /*
   2  * stv0900_core.c
   3  *
   4  * Driver for ST STV0900 satellite demodulator IC.
   5  *
   6  * Copyright (C) ST Microelectronics.
   7  * Copyright (C) 2009 NetUP Inc.
   8  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/string.h>
  29 #include <linux/slab.h>
  30 #include <linux/i2c.h>
  31
  32 #include "stv0900.h"
  33 #include "stv0900_reg.h"
  34 #include "stv0900_priv.h"
  35 #include "stv0900_init.h"
  36
  37 int stvdebug = 1;
  38 module_param_named(debug, stvdebug, int, 0644);
  39
  40 /* internal params node */
  41 struct stv0900_inode {
  42         /* pointer for internal params, one for each pair of demods */
  43         struct stv0900_internal         *internal;
  44         struct stv0900_inode            *next_inode;
  45 };
  46
  47 /* first internal params */
  48 static struct stv0900_inode *stv0900_first_inode;
  49
  50 /* find chip by i2c adapter and i2c address */
  51 static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
  52                                                         u8 i2c_addr)
  53 {
  54         struct stv0900_inode *temp_chip = stv0900_first_inode;
  55
  56         if (temp_chip != NULL) {
  57                 /*
  58                  Search of the last stv0900 chip or
  59                  find it by i2c adapter and i2c address */
  60                 while ((temp_chip != NULL) &&
  61                         ((temp_chip->internal->i2c_adap != i2c_adap) ||
  62                         (temp_chip->internal->i2c_addr != i2c_addr)))
  63
  64                         temp_chip = temp_chip->next_inode;
  65
  66         }
  67
  68         return temp_chip;
  69 }
  70
  71 /* deallocating chip */
  72 static void remove_inode(struct stv0900_internal *internal)
  73 {
  74         struct stv0900_inode *prev_node = stv0900_first_inode;
  75         struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
  76                                                 internal->i2c_addr);
  77
  78         if (del_node != NULL) {
  79                 if (del_node == stv0900_first_inode) {
  80                         stv0900_first_inode = del_node->next_inode;
  81                 } else {
  82                         while (prev_node->next_inode != del_node)
  83                                 prev_node = prev_node->next_inode;
  84
  85                         if (del_node->next_inode == NULL)
  86                                 prev_node->next_inode = NULL;
  87                         else
  88                                 prev_node->next_inode =
  89                                         prev_node->next_inode->next_inode;
  90                 }
  91
  92                 kfree(del_node);
  93         }
  94 }
  95
  96 /* allocating new chip */
  97 static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
  98 {
  99         struct stv0900_inode *new_node = stv0900_first_inode;
 100
 101         if (new_node == NULL) {
 102                 new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
 103                 stv0900_first_inode = new_node;
 104         } else {
 105                 while (new_node->next_inode != NULL)
 106                         new_node = new_node->next_inode;
 107
 108                 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
 109                 if (new_node->next_inode != NULL)
 110                         new_node = new_node->next_inode;
 111                 else
 112                         new_node = NULL;
 113         }
 114
 115         if (new_node != NULL) {
 116                 new_node->internal = internal;
 117                 new_node->next_inode = NULL;
 118         }
 119
 120         return new_node;
 121 }
 122
 123 s32 ge2comp(s32 a, s32 width)
 124 {
 125         if (width == 32)
 126                 return a;
 127         else
 128                 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
 129 }
 130
 131 void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
 132                                                                 u8 reg_data)
 133 {
 134         u8 data[3];
 135         int ret;
 136         struct i2c_msg i2cmsg = {
 137                 .addr  = i_params->i2c_addr,
 138                 .flags = 0,
 139                 .len   = 3,
 140                 .buf   = data,
 141         };
 142
 143         data[0] = MSB(reg_addr);
 144         data[1] = LSB(reg_addr);
 145         data[2] = reg_data;
 146
 147         ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
 148         if (ret != 1)
 149                 dprintk("%s: i2c error %d\n", __func__, ret);
 150 }
 151
 152 u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg)
 153 {
 154         int ret;
 155         u8 b0[] = { MSB(reg), LSB(reg) };
 156         u8 buf = 0;
 157         struct i2c_msg msg[] = {
 158                 {
 159                         .addr   = i_params->i2c_addr,
 160                         .flags  = 0,
 161                         .buf = b0,
 162                         .len = 2,
 163                 }, {
 164                         .addr   = i_params->i2c_addr,
 165                         .flags  = I2C_M_RD,
 166                         .buf = &buf,
 167                         .len = 1,
 168                 },
 169         };
 170
 171         ret = i2c_transfer(i_params->i2c_adap, msg, 2);
 172         if (ret != 2)
 173                 dprintk("%s: i2c error %d, reg[0x%02x]\n",
 174                                 __func__, ret, reg);
 175
 176         return buf;
 177 }
 178
 179 void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
 180 {
 181         u8 position = 0, i = 0;
 182
 183         (*mask) = label & 0xff;
 184
 185         while ((position == 0) && (i < 8)) {
 186                 position = ((*mask) >> i) & 0x01;
 187                 i++;
 188         }
 189
 190         (*pos) = (i - 1);
 191 }
 192
 193 void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val)
 194 {
 195         u8 reg, mask, pos;
 196
 197         reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff);
 198         extract_mask_pos(label, &mask, &pos);
 199
 200         val = mask & (val << pos);
 201
 202         reg = (reg & (~mask)) | val;
 203         stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg);
 204
 205 }
 206
 207 u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label)
 208 {
 209         u8 val = 0xff;
 210         u8 mask, pos;
 211
 212         extract_mask_pos(label, &mask, &pos);
 213
 214         val = stv0900_read_reg(i_params, label >> 16);
 215         val = (val & mask) >> pos;
 216
 217         return val;
 218 }
 219
 220 enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params)
 221 {
 222         s32 i;
 223         enum fe_stv0900_error error;
 224
 225         if (i_params != NULL) {
 226                 i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
 227                 if (i_params->errs == STV0900_NO_ERROR) {
 228                         /*Startup sequence*/
 229                         stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
 230                         stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
 231                         stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
 232                         stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
 233                         stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x20);
 234                         stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x20);
 235                         stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
 236                         msleep(3);
 237                         stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
 238
 239                         switch (i_params->clkmode) {
 240                         case 0:
 241                         case 2:
 242                                 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
 243                                                 | i_params->clkmode);
 244                                 break;
 245                         default:
 246                                 /* preserve SELOSCI bit */
 247                                 i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
 248                                 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
 249                                 break;
 250                         }
 251
 252                         msleep(3);
 253                         for (i = 0; i < 182; i++)
 254                                 stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
 255
 256                         if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) {
 257                                 stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
 258                                 for (i = 0; i < 32; i++)
 259                                         stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
 260                         }
 261
 262                         stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c);
 263                         stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c);
 264                         stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
 265                         stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
 266                 }
 267                 error = i_params->errs;
 268         } else
 269                 error = STV0900_INVALID_HANDLE;
 270
 271         return error;
 272
 273 }
 274
 275 u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
 276 {
 277         u32 mclk = 90000000, div = 0, ad_div = 0;
 278
 279         div = stv0900_get_bits(i_params, F0900_M_DIV);
 280         ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
 281
 282         mclk = (div + 1) * ext_clk / ad_div;
 283
 284         dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
 285
 286         return mclk;
 287 }
 288
 289 enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk)
 290 {
 291         enum fe_stv0900_error error = STV0900_NO_ERROR;
 292         u32 m_div, clk_sel;
 293
 294         dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
 295                         i_params->quartz);
 296
 297         if (i_params == NULL)
 298                 error = STV0900_INVALID_HANDLE;
 299         else {
 300                 if (i_params->errs)
 301                         error = STV0900_I2C_ERROR;
 302                 else {
 303                         clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
 304                         m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
 305                         stv0900_write_bits(i_params, F0900_M_DIV, m_div);
 306                         i_params->mclk = stv0900_get_mclk_freq(i_params,
 307                                                         i_params->quartz);
 308
 309                         /*Set the DiseqC frequency to 22KHz */
 310                         /*
 311                                 Formula:
 312                                 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
 313                                 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
 314                         */
 315                         m_div = i_params->mclk / 704000;
 316                         stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
 317                         stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
 318
 319                         stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
 320                         stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
 321
 322                         if ((i_params->errs))
 323                                 error = STV0900_I2C_ERROR;
 324                 }
 325         }
 326
 327         return error;
 328 }
 329
 330 u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
 331                                         enum fe_stv0900_demod_num demod)
 332 {
 333         u32 lsb, msb, hsb, err_val;
 334         s32 err1field_hsb, err1field_msb, err1field_lsb;
 335         s32 err2field_hsb, err2field_msb, err2field_lsb;
 336
 337         dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
 338         dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
 339         dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
 340
 341         dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
 342         dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
 343         dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
 344
 345         switch (cntr) {
 346         case 0:
 347         default:
 348                 hsb = stv0900_get_bits(i_params, err1field_hsb);
 349                 msb = stv0900_get_bits(i_params, err1field_msb);
 350                 lsb = stv0900_get_bits(i_params, err1field_lsb);
 351                 break;
 352         case 1:
 353                 hsb = stv0900_get_bits(i_params, err2field_hsb);
 354                 msb = stv0900_get_bits(i_params, err2field_msb);
 355                 lsb = stv0900_get_bits(i_params, err2field_lsb);
 356                 break;
 357         }
 358
 359         err_val = (hsb << 16) + (msb << 8) + (lsb);
 360
 361         return err_val;
 362 }
 363
 364 static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 365 {
 366         struct stv0900_state *state = fe->demodulator_priv;
 367         struct stv0900_internal *i_params = state->internal;
 368         enum fe_stv0900_demod_num demod = state->demod;
 369
 370         u32 fi2c;
 371
 372         dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
 373
 374         stv0900_write_bits(i_params, fi2c, enable);
 375
 376         return 0;
 377 }
 378
 379 static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
 380                                         enum fe_stv0900_clock_type path1_ts,
 381                                         enum fe_stv0900_clock_type path2_ts)
 382 {
 383
 384         dprintk("%s\n", __func__);
 385
 386         if (i_params->chip_id >= 0x20) {
 387                 switch (path1_ts) {
 388                 case STV0900_PARALLEL_PUNCT_CLOCK:
 389                 case STV0900_DVBCI_CLOCK:
 390                         switch (path2_ts) {
 391                         case STV0900_SERIAL_PUNCT_CLOCK:
 392                         case STV0900_SERIAL_CONT_CLOCK:
 393                         default:
 394                                 stv0900_write_reg(i_params, R0900_TSGENERAL,
 395                                                         0x00);
 396                                 break;
 397                         case STV0900_PARALLEL_PUNCT_CLOCK:
 398                         case STV0900_DVBCI_CLOCK:
 399                                 stv0900_write_reg(i_params, R0900_TSGENERAL,
 400                                                         0x06);
 401                                 stv0900_write_bits(i_params,
 402                                                 F0900_P1_TSFIFO_MANSPEED, 3);
 403                                 stv0900_write_bits(i_params,
 404                                                 F0900_P2_TSFIFO_MANSPEED, 0);
 405                                 stv0900_write_reg(i_params,
 406                                                 R0900_P1_TSSPEED, 0x14);
 407                                 stv0900_write_reg(i_params,
 408                                                 R0900_P2_TSSPEED, 0x28);
 409                                 break;
 410                         }
 411                         break;
 412                 case STV0900_SERIAL_PUNCT_CLOCK:
 413                 case STV0900_SERIAL_CONT_CLOCK:
 414                 default:
 415                         switch (path2_ts) {
 416                         case STV0900_SERIAL_PUNCT_CLOCK:
 417                         case STV0900_SERIAL_CONT_CLOCK:
 418                         default:
 419                                 stv0900_write_reg(i_params,
 420                                                 R0900_TSGENERAL, 0x0C);
 421                                 break;
 422                         case STV0900_PARALLEL_PUNCT_CLOCK:
 423                         case STV0900_DVBCI_CLOCK:
 424                                 stv0900_write_reg(i_params,
 425                                                 R0900_TSGENERAL, 0x0A);
 426                                 dprintk("%s: 0x0a\n", __func__);
 427                                 break;
 428                         }
 429                         break;
 430                 }
 431         } else {
 432                 switch (path1_ts) {
 433                 case STV0900_PARALLEL_PUNCT_CLOCK:
 434                 case STV0900_DVBCI_CLOCK:
 435                         switch (path2_ts) {
 436                         case STV0900_SERIAL_PUNCT_CLOCK:
 437                         case STV0900_SERIAL_CONT_CLOCK:
 438                         default:
 439                                 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
 440                                                         0x10);
 441                                 break;
 442                         case STV0900_PARALLEL_PUNCT_CLOCK:
 443                         case STV0900_DVBCI_CLOCK:
 444                                 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
 445                                                         0x16);
 446                                 stv0900_write_bits(i_params,
 447                                                 F0900_P1_TSFIFO_MANSPEED, 3);
 448                                 stv0900_write_bits(i_params,
 449                                                 F0900_P2_TSFIFO_MANSPEED, 0);
 450                                 stv0900_write_reg(i_params, R0900_P1_TSSPEED,
 451                                                         0x14);
 452                                 stv0900_write_reg(i_params, R0900_P2_TSSPEED,
 453                                                         0x28);
 454                                 break;
 455                         }
 456
 457                         break;
 458                 case STV0900_SERIAL_PUNCT_CLOCK:
 459                 case STV0900_SERIAL_CONT_CLOCK:
 460                 default:
 461                         switch (path2_ts) {
 462                         case STV0900_SERIAL_PUNCT_CLOCK:
 463                         case STV0900_SERIAL_CONT_CLOCK:
 464                         default:
 465                                 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
 466                                                         0x14);
 467                                 break;
 468                         case STV0900_PARALLEL_PUNCT_CLOCK:
 469                         case STV0900_DVBCI_CLOCK:
 470                                 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
 471                                                         0x12);
 472                                 dprintk("%s: 0x12\n", __func__);
 473                                 break;
 474                         }
 475
 476                         break;
 477                 }
 478         }
 479
 480         switch (path1_ts) {
 481         case STV0900_PARALLEL_PUNCT_CLOCK:
 482                 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
 483                 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
 484                 break;
 485         case STV0900_DVBCI_CLOCK:
 486                 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
 487                 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
 488                 break;
 489         case STV0900_SERIAL_PUNCT_CLOCK:
 490                 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
 491                 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
 492                 break;
 493         case STV0900_SERIAL_CONT_CLOCK:
 494                 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
 495                 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
 496                 break;
 497         default:
 498                 break;
 499         }
 500
 501         switch (path2_ts) {
 502         case STV0900_PARALLEL_PUNCT_CLOCK:
 503                 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
 504                 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
 505                 break;
 506         case STV0900_DVBCI_CLOCK:
 507                 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
 508                 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
 509                 break;
 510         case STV0900_SERIAL_PUNCT_CLOCK:
 511                 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
 512                 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
 513                 break;
 514         case STV0900_SERIAL_CONT_CLOCK:
 515                 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
 516                 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
 517                 break;
 518         default:
 519                 break;
 520         }
 521
 522         stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
 523         stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0);
 524         stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
 525         stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0);
 526 }
 527
 528 void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
 529                                                         u32 bandwidth)
 530 {
 531         struct dvb_frontend_ops *frontend_ops = NULL;
 532         struct dvb_tuner_ops *tuner_ops = NULL;
 533
 534         if (&fe->ops)
 535                 frontend_ops = &fe->ops;
 536
 537         if (&frontend_ops->tuner_ops)
 538                 tuner_ops = &frontend_ops->tuner_ops;
 539
 540         if (tuner_ops->set_frequency) {
 541                 if ((tuner_ops->set_frequency(fe, frequency)) < 0)
 542                         dprintk("%s: Invalid parameter\n", __func__);
 543                 else
 544                         dprintk("%s: Frequency=%d\n", __func__, frequency);
 545
 546         }
 547
 548         if (tuner_ops->set_bandwidth) {
 549                 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
 550                         dprintk("%s: Invalid parameter\n", __func__);
 551                 else
 552                         dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
 553
 554         }
 555 }
 556
 557 void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
 558 {
 559         struct dvb_frontend_ops *frontend_ops = NULL;
 560         struct dvb_tuner_ops *tuner_ops = NULL;
 561
 562         if (&fe->ops)
 563                 frontend_ops = &fe->ops;
 564
 565         if (&frontend_ops->tuner_ops)
 566                 tuner_ops = &frontend_ops->tuner_ops;
 567
 568         if (tuner_ops->set_bandwidth) {
 569                 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
 570                         dprintk("%s: Invalid parameter\n", __func__);
 571                 else
 572                         dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
 573
 574         }
 575 }
 576
 577 static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
 578                                 const struct stv0900_table *lookup,
 579                                 enum fe_stv0900_demod_num demod)
 580 {
 581         s32 agc_gain = 0,
 582                 imin,
 583                 imax,
 584                 i,
 585                 rf_lvl = 0;
 586
 587         dprintk("%s\n", __func__);
 588
 589         if ((lookup != NULL) && lookup->size) {
 590                 switch (demod) {
 591                 case STV0900_DEMOD_1:
 592                 default:
 593                         agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
 594                                                 stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
 595                         break;
 596                 case STV0900_DEMOD_2:
 597                         agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
 598                                                 stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
 599                         break;
 600                 }
 601
 602         dprintk("%s: AGC Gain = 0x%x\n", __func__, agc_gain);
 603
 604                 imin = 0;
 605                 imax = lookup->size - 1;
 606                 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
 607                         while ((imax - imin) > 1) {
 608                                 i = (imax + imin) >> 1;
 609
 610                                 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval))
 611                                         imax = i;
 612                                 else
 613                                         imin = i;
 614                         }
 615
 616                         rf_lvl = (((s32)agc_gain - lookup->table[imin].regval)
 617                                         * (lookup->table[imax].realval - lookup->table[imin].realval)
 618                                         / (lookup->table[imax].regval - lookup->table[imin].regval))
 619                                         + lookup->table[imin].realval;
 620                 } else if (agc_gain > lookup->table[0].regval)
 621                         rf_lvl = 5;
 622                 else if (agc_gain < lookup->table[lookup->size-1].regval)
 623                         rf_lvl = -100;
 624
 625         }
 626
 627         dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
 628
 629         return rf_lvl;
 630 }
 631
 632 static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
 633 {
 634         struct stv0900_state *state = fe->demodulator_priv;
 635         struct stv0900_internal *internal = state->internal;
 636         s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
 637                                                                 state->demod);
 638
 639         rflevel = (rflevel + 100) * (65535 / 70);
 640         if (rflevel < 0)
 641                 rflevel = 0;
 642
 643         if (rflevel > 65535)
 644                 rflevel = 65535;
 645
 646         *strength = rflevel;
 647
 648         return 0;
 649 }
 650
 651
 652 static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
 653                                         const struct stv0900_table *lookup)
 654 {
 655         struct stv0900_state *state = fe->demodulator_priv;
 656         struct stv0900_internal *i_params = state->internal;
 657         enum fe_stv0900_demod_num demod = state->demod;
 658
 659         s32 c_n = -100,
 660                 regval, imin, imax,
 661                 i,
 662                 lock_flag_field,
 663                 noise_field1,
 664                 noise_field0;
 665
 666         dprintk("%s\n", __func__);
 667
 668         dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF,
 669                                         F0900_P2_LOCK_DEFINITIF);
 670         if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
 671                 dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1,
 672                                         F0900_P2_NOSPLHT_NORMED1);
 673                 dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0,
 674                                         F0900_P2_NOSPLHT_NORMED0);
 675         } else {
 676                 dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1,
 677                                         F0900_P2_NOSDATAT_NORMED1);
 678                 dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0,
 679                                         F0900_P2_NOSDATAT_NORMED0);
 680         }
 681
 682         if (stv0900_get_bits(i_params, lock_flag_field)) {
 683                 if ((lookup != NULL) && lookup->size) {
 684                         regval = 0;
 685                         msleep(5);
 686                         for (i = 0; i < 16; i++) {
 687                                 regval += MAKEWORD(stv0900_get_bits(i_params,
 688                                                                 noise_field1),
 689                                                 stv0900_get_bits(i_params,
 690                                                                 noise_field0));
 691                                 msleep(1);
 692                         }
 693
 694                         regval /= 16;
 695                         imin = 0;
 696                         imax = lookup->size - 1;
 697                         if (INRANGE(lookup->table[imin].regval,
 698                                         regval,
 699                                         lookup->table[imax].regval)) {
 700                                 while ((imax - imin) > 1) {
 701                                         i = (imax + imin) >> 1;
 702                                         if (INRANGE(lookup->table[imin].regval,
 703                                                     regval,
 704                                                     lookup->table[i].regval))
 705                                                 imax = i;
 706                                         else
 707                                                 imin = i;
 708                                 }
 709
 710                                 c_n = ((regval - lookup->table[imin].regval)
 711                                                 * (lookup->table[imax].realval
 712                                                 - lookup->table[imin].realval)
 713                                                 / (lookup->table[imax].regval
 714                                                 - lookup->table[imin].regval))
 715                                                 + lookup->table[imin].realval;
 716                         } else if (regval < lookup->table[imin].regval)
 717                                 c_n = 1000;
 718                 }
 719         }
 720
 721         dprintk("%s: Quality = %d\n", __func__, c_n);
 722
 723         return c_n;
 724 }
 725
 726 static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
 727 {
 728         struct stv0900_state *state = fe->demodulator_priv;
 729         struct stv0900_internal *i_params = state->internal;
 730         enum fe_stv0900_demod_num demod = state->demod;
 731         u8 err_val1, err_val0;
 732         s32 err_field1, err_field0;
 733         u32 header_err_val = 0;
 734
 735         *ucblocks = 0x0;
 736         if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
 737                 /* DVB-S2 delineator errors count */
 738
 739                 /* retreiving number for errnous headers */
 740                 dmd_reg(err_field0, R0900_P1_BBFCRCKO0,
 741                                         R0900_P2_BBFCRCKO0);
 742                 dmd_reg(err_field1, R0900_P1_BBFCRCKO1,
 743                                         R0900_P2_BBFCRCKO1);
 744
 745                 err_val1 = stv0900_read_reg(i_params, err_field1);
 746                 err_val0 = stv0900_read_reg(i_params, err_field0);
 747                 header_err_val = (err_val1<<8) | err_val0;
 748
 749                 /* retreiving number for errnous packets */
 750                 dmd_reg(err_field0, R0900_P1_UPCRCKO0,
 751                                         R0900_P2_UPCRCKO0);
 752                 dmd_reg(err_field1, R0900_P1_UPCRCKO1,
 753                                         R0900_P2_UPCRCKO1);
 754
 755                 err_val1 = stv0900_read_reg(i_params, err_field1);
 756                 err_val0 = stv0900_read_reg(i_params, err_field0);
 757                 *ucblocks = (err_val1<<8) | err_val0;
 758                 *ucblocks += header_err_val;
 759         }
 760
 761         return 0;
 762 }
 763
 764 static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
 765 {
 766         s32 snrlcl = stv0900_carr_get_quality(fe,
 767                         (const struct stv0900_table *)&stv0900_s2_cn);
 768         snrlcl = (snrlcl + 30) * 384;
 769         if (snrlcl < 0)
 770                 snrlcl = 0;
 771
 772         if (snrlcl > 65535)
 773                 snrlcl = 65535;
 774
 775         *snr = snrlcl;
 776
 777         return 0;
 778 }
 779
 780 static u32 stv0900_get_ber(struct stv0900_internal *i_params,
 781                                 enum fe_stv0900_demod_num demod)
 782 {
 783         u32 ber = 10000000, i;
 784         s32 dmd_state_reg;
 785         s32 demod_state;
 786         s32 vstatus_reg;
 787         s32 prvit_field;
 788         s32 pdel_status_reg;
 789         s32 pdel_lock_field;
 790
 791         dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
 792         dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
 793         dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
 794         dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
 795         dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
 796                                 F0900_P2_PKTDELIN_LOCK);
 797
 798         demod_state = stv0900_get_bits(i_params, dmd_state_reg);
 799
 800         switch (demod_state) {
 801         case STV0900_SEARCH:
 802         case STV0900_PLH_DETECTED:
 803         default:
 804                 ber = 10000000;
 805                 break;
 806         case STV0900_DVBS_FOUND:
 807                 ber = 0;
 808                 for (i = 0; i < 5; i++) {
 809                         msleep(5);
 810                         ber += stv0900_get_err_count(i_params, 0, demod);
 811                 }
 812
 813                 ber /= 5;
 814                 if (stv0900_get_bits(i_params, prvit_field)) {
 815                         ber *= 9766;
 816                         ber = ber >> 13;
 817                 }
 818
 819                 break;
 820         case STV0900_DVBS2_FOUND:
 821                 ber = 0;
 822                 for (i = 0; i < 5; i++) {
 823                         msleep(5);
 824                         ber += stv0900_get_err_count(i_params, 0, demod);
 825                 }
 826
 827                 ber /= 5;
 828                 if (stv0900_get_bits(i_params, pdel_lock_field)) {
 829                         ber *= 9766;
 830                         ber = ber >> 13;
 831                 }
 832
 833                 break;
 834         }
 835
 836         return ber;
 837 }
 838
 839 static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
 840 {
 841         struct stv0900_state *state = fe->demodulator_priv;
 842         struct stv0900_internal *internal = state->internal;
 843
 844         *ber = stv0900_get_ber(internal, state->demod);
 845
 846         return 0;
 847 }
 848
 849 int stv0900_get_demod_lock(struct stv0900_internal *i_params,
 850                         enum fe_stv0900_demod_num demod, s32 time_out)
 851 {
 852         s32 timer = 0,
 853                 lock = 0,
 854                 header_field,
 855                 lock_field;
 856
 857         enum fe_stv0900_search_state    dmd_state;
 858
 859         dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
 860         dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
 861         while ((timer < time_out) && (lock == 0)) {
 862                 dmd_state = stv0900_get_bits(i_params, header_field);
 863                 dprintk("Demod State = %d\n", dmd_state);
 864                 switch (dmd_state) {
 865                 case STV0900_SEARCH:
 866                 case STV0900_PLH_DETECTED:
 867                 default:
 868                         lock = 0;
 869                         break;
 870                 case STV0900_DVBS2_FOUND:
 871                 case STV0900_DVBS_FOUND:
 872                         lock = stv0900_get_bits(i_params, lock_field);
 873                         break;
 874                 }
 875
 876                 if (lock == 0)
 877                         msleep(10);
 878
 879                 timer += 10;
 880         }
 881
 882         if (lock)
 883                 dprintk("DEMOD LOCK OK\n");
 884         else
 885                 dprintk("DEMOD LOCK FAIL\n");
 886
 887         return lock;
 888 }
 889
 890 void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
 891                                 enum fe_stv0900_demod_num demod)
 892 {
 893         s32 regflist,
 894         i;
 895
 896         dprintk("%s\n", __func__);
 897
 898         dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0);
 899
 900         for (i = 0; i < 16; i++)
 901                 stv0900_write_reg(i_params, regflist + i, 0xff);
 902 }
 903
 904 void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
 905                                 enum fe_stv0900_demod_num demod)
 906 {
 907         u32 matype,
 908         mod_code,
 909         fmod,
 910         reg_index,
 911         field_index;
 912
 913         dprintk("%s\n", __func__);
 914
 915         if (i_params->chip_id <= 0x11) {
 916                 msleep(5);
 917
 918                 switch (demod) {
 919                 case STV0900_DEMOD_1:
 920                 default:
 921                         mod_code = stv0900_read_reg(i_params,
 922                                                         R0900_P1_PLHMODCOD);
 923                         matype = mod_code & 0x3;
 924                         mod_code = (mod_code & 0x7f) >> 2;
 925
 926                         reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
 927                         field_index = mod_code % 2;
 928                         break;
 929                 case STV0900_DEMOD_2:
 930                         mod_code = stv0900_read_reg(i_params,
 931                                                         R0900_P2_PLHMODCOD);
 932                         matype = mod_code & 0x3;
 933                         mod_code = (mod_code & 0x7f) >> 2;
 934
 935                         reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
 936                         field_index = mod_code % 2;
 937                         break;
 938                 }
 939
 940
 941                 switch (matype) {
 942                 case 0:
 943                 default:
 944                         fmod = 14;
 945                         break;
 946                 case 1:
 947                         fmod = 13;
 948                         break;
 949                 case 2:
 950                         fmod = 11;
 951                         break;
 952                 case 3:
 953                         fmod = 7;
 954                         break;
 955                 }
 956
 957                 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
 958                                                         && (matype <= 1)) {
 959                         if (field_index == 0)
 960                                 stv0900_write_reg(i_params, reg_index,
 961                                                         0xf0 | fmod);
 962                         else
 963                                 stv0900_write_reg(i_params, reg_index,
 964                                                         (fmod << 4) | 0xf);
 965                 }
 966         } else if (i_params->chip_id >= 0x12) {
 967                 switch (demod) {
 968                 case STV0900_DEMOD_1:
 969                 default:
 970                         for (reg_index = 0; reg_index < 7; reg_index++)
 971                                 stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
 972
 973                         stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff);
 974                         stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf);
 975                         for (reg_index = 0; reg_index < 8; reg_index++)
 976                                 stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
 977
 978                         break;
 979                 case STV0900_DEMOD_2:
 980                         for (reg_index = 0; reg_index < 7; reg_index++)
 981                                 stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff);
 982
 983                         stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff);
 984                         stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf);
 985                         for (reg_index = 0; reg_index < 8; reg_index++)
 986                                 stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc);
 987
 988                         break;
 989                 }
 990
 991         }
 992 }
 993
 994 void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
 995                                         enum fe_stv0900_demod_num demod)
 996 {
 997         u32 reg_index;
 998
 999         dprintk("%s\n", __func__);
1000
1001         switch (demod) {
1002         case STV0900_DEMOD_1:
1003         default:
1004                 stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff);
1005                 stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0);
1006                 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
1007                 for (reg_index = 0; reg_index < 13; reg_index++)
1008                         stv0900_write_reg(i_params,
1009                                         R0900_P1_MODCODLST2 + reg_index, 0);
1010
1011                 break;
1012         case STV0900_DEMOD_2:
1013                 stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff);
1014                 stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0);
1015                 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f);
1016                 for (reg_index = 0; reg_index < 13; reg_index++)
1017                         stv0900_write_reg(i_params,
1018                                         R0900_P2_MODCODLST2 + reg_index, 0);
1019
1020                 break;
1021         }
1022 }
1023
1024 static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
1025 {
1026         return DVBFE_ALGO_CUSTOM;
1027 }
1028
1029 static int stb0900_set_property(struct dvb_frontend *fe,
1030                                 struct dtv_property *tvp)
1031 {
1032         dprintk("%s(..)\n", __func__);
1033
1034         return 0;
1035 }
1036
1037 static int stb0900_get_property(struct dvb_frontend *fe,
1038                                 struct dtv_property *tvp)
1039 {
1040         dprintk("%s(..)\n", __func__);
1041
1042         return 0;
1043 }
1044
1045 void stv0900_start_search(struct stv0900_internal *i_params,
1046                                 enum fe_stv0900_demod_num demod)
1047 {
1048
1049         switch (demod) {
1050         case STV0900_DEMOD_1:
1051         default:
1052                 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f);
1053
1054                 if (i_params->chip_id == 0x10)
1055                         stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa);
1056
1057                 if (i_params->chip_id < 0x20)
1058                         stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
1059
1060                 if (i_params->dmd1_symbol_rate <= 5000000) {
1061                         stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44);
1062                         stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f);
1063                         stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff);
1064                         stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0);
1065                         stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00);
1066                         stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
1067                 } else {
1068                         stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4);
1069                         stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
1070                 }
1071
1072                 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
1073                 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
1074
1075                 if (i_params->chip_id >= 0x20) {
1076                         stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
1077                         stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
1078
1079                         if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
1080                                 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
1081                                 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
1082                         }
1083                 }
1084
1085                 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
1086                 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0);
1087                 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0);
1088                 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
1089                 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1090                 stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
1091                 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
1092                 if (i_params->chip_id >= 0x20) {
1093                         if (i_params->dmd1_symbol_rate < 2000000) {
1094                                 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
1095                                 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
1096                         }
1097
1098                         if (i_params->dmd1_symbol_rate < 10000000) {
1099                                 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
1100                                 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1101                         } else {
1102                                 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
1103                                 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1104                         }
1105
1106                 } else {
1107                         if (i_params->dmd1_symbol_rate < 10000000)
1108                                 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef);
1109                         else
1110                                 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
1111                 }
1112
1113                 switch (i_params->dmd1_srch_algo) {
1114                 case STV0900_WARM_START:
1115                         stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1116                         stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1117                         break;
1118                 case STV0900_COLD_START:
1119                         stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1120                         stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
1121                         break;
1122                 default:
1123                         break;
1124                 }
1125
1126                 break;
1127         case STV0900_DEMOD_2:
1128                 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f);
1129                 if (i_params->chip_id == 0x10)
1130                         stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
1131
1132                 if (i_params->chip_id < 0x20)
1133                         stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
1134
1135                 if (i_params->dmd2_symbol_rate <= 5000000) {
1136                         stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
1137                         stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
1138                         stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
1139                         stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
1140                         stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
1141                         stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
1142                 } else {
1143                         stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
1144                         stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
1145                 }
1146
1147                 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
1148                 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
1149
1150                 if (i_params->chip_id >= 0x20) {
1151                         stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
1152                         stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
1153                         if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
1154                                 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
1155                                 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
1156                         }
1157                 }
1158
1159                 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
1160                 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0);
1161                 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0);
1162                 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
1163                 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1164                 stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
1165                 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
1166                 if (i_params->chip_id >= 0x20) {
1167                         if (i_params->dmd2_symbol_rate < 2000000) {
1168                                 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
1169                                 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
1170                         }
1171
1172                         if (i_params->dmd2_symbol_rate < 10000000) {
1173                                 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c);
1174                                 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
1175                         } else {
1176                                 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b);
1177                                 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
1178                         }
1179
1180                 } else {
1181                         if (i_params->dmd2_symbol_rate < 10000000)
1182                                 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef);
1183                         else
1184                                 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
1185                 }
1186
1187                 switch (i_params->dmd2_srch_algo) {
1188                 case STV0900_WARM_START:
1189                         stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1190                         stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1191                         break;
1192                 case STV0900_COLD_START:
1193                         stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1194                         stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
1195                         break;
1196                 default:
1197                         break;
1198                 }
1199
1200                 break;
1201         }
1202 }
1203
1204 u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1205                                                         s32 pilot, u8 chip_id)
1206 {
1207         u8 aclc_value = 0x29;
1208         s32     i;
1209         const struct stv0900_car_loop_optim *car_loop_s2;
1210
1211         dprintk("%s\n", __func__);
1212
1213         if (chip_id <= 0x12)
1214                 car_loop_s2 = FE_STV0900_S2CarLoop;
1215         else if (chip_id == 0x20)
1216                 car_loop_s2 = FE_STV0900_S2CarLoopCut20;
1217         else
1218                 car_loop_s2 = FE_STV0900_S2CarLoop;
1219
1220         if (modcode < STV0900_QPSK_12) {
1221                 i = 0;
1222                 while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode))
1223                         i++;
1224
1225                 if (i >= 3)
1226                         i = 2;
1227         } else {
1228                 i = 0;
1229                 while ((i < 14) && (modcode != car_loop_s2[i].modcode))
1230                         i++;
1231
1232                 if (i >= 14) {
1233                         i = 0;
1234                         while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode))
1235                                 i++;
1236
1237                         if (i >= 11)
1238                                 i = 10;
1239                 }
1240         }
1241
1242         if (modcode <= STV0900_QPSK_25) {
1243                 if (pilot) {
1244                         if (srate <= 3000000)
1245                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2;
1246                         else if (srate <= 7000000)
1247                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5;
1248                         else if (srate <= 15000000)
1249                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10;
1250                         else if (srate <= 25000000)
1251                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20;
1252                         else
1253                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30;
1254                 } else {
1255                         if (srate <= 3000000)
1256                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2;
1257                         else if (srate <= 7000000)
1258                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5;
1259                         else if (srate <= 15000000)
1260                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10;
1261                         else if (srate <= 25000000)
1262                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20;
1263                         else
1264                                 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30;
1265                 }
1266
1267         } else if (modcode <= STV0900_8PSK_910) {
1268                 if (pilot) {
1269                         if (srate <= 3000000)
1270                                 aclc_value = car_loop_s2[i].car_loop_pilots_on_2;
1271                         else if (srate <= 7000000)
1272                                 aclc_value = car_loop_s2[i].car_loop_pilots_on_5;
1273                         else if (srate <= 15000000)
1274                                 aclc_value = car_loop_s2[i].car_loop_pilots_on_10;
1275                         else if (srate <= 25000000)
1276                                 aclc_value = car_loop_s2[i].car_loop_pilots_on_20;
1277                         else
1278                                 aclc_value = car_loop_s2[i].car_loop_pilots_on_30;
1279                 } else {
1280                         if (srate <= 3000000)
1281                                 aclc_value = car_loop_s2[i].car_loop_pilots_off_2;
1282                         else if (srate <= 7000000)
1283                                 aclc_value = car_loop_s2[i].car_loop_pilots_off_5;
1284                         else if (srate <= 15000000)
1285                                 aclc_value = car_loop_s2[i].car_loop_pilots_off_10;
1286                         else if (srate <= 25000000)
1287                                 aclc_value = car_loop_s2[i].car_loop_pilots_off_20;
1288                         else
1289                                 aclc_value = car_loop_s2[i].car_loop_pilots_off_30;
1290                 }
1291
1292         } else {
1293                 if (srate <= 3000000)
1294                         aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2;
1295                 else if (srate <= 7000000)
1296                         aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5;
1297                 else if (srate <= 15000000)
1298                         aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10;
1299                 else if (srate <= 25000000)
1300                         aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20;
1301                 else
1302                         aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30;
1303         }
1304
1305         return aclc_value;
1306 }
1307
1308 u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id)
1309 {
1310         s32 mod_index = 0;
1311
1312         u8 aclc_value = 0x0b;
1313
1314         dprintk("%s\n", __func__);
1315
1316         switch (modulation) {
1317         case STV0900_QPSK:
1318         default:
1319                 mod_index = 0;
1320                 break;
1321         case STV0900_8PSK:
1322                 mod_index = 1;
1323                 break;
1324         case STV0900_16APSK:
1325                 mod_index = 2;
1326                 break;
1327         case STV0900_32APSK:
1328                 mod_index = 3;
1329                 break;
1330         }
1331
1332         switch (chip_id) {
1333         case 0x20:
1334                 if (srate <= 3000000)
1335                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2;
1336                 else if (srate <= 7000000)
1337                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5;
1338                 else if (srate <= 15000000)
1339                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10;
1340                 else if (srate <= 25000000)
1341                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20;
1342                 else
1343                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30;
1344
1345                 break;
1346         case 0x12:
1347         default:
1348                 if (srate <= 3000000)
1349                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2;
1350                 else if (srate <= 7000000)
1351                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5;
1352                 else if (srate <= 15000000)
1353                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10;
1354                 else if (srate <= 25000000)
1355                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20;
1356                 else
1357                         aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30;
1358
1359                 break;
1360         }
1361
1362         return aclc_value;
1363 }
1364
1365 static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params,
1366                                         enum fe_stv0900_demod_mode LDPC_Mode,
1367                                         enum fe_stv0900_demod_num demod)
1368 {
1369         enum fe_stv0900_error error = STV0900_NO_ERROR;
1370
1371         dprintk("%s\n", __func__);
1372
1373         switch (LDPC_Mode) {
1374         case STV0900_DUAL:
1375         default:
1376                 if ((i_params->demod_mode != STV0900_DUAL)
1377                         || (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) {
1378                         stv0900_write_reg(i_params, R0900_GENCFG, 0x1d);
1379
1380                         i_params->demod_mode = STV0900_DUAL;
1381
1382                         stv0900_write_bits(i_params, F0900_FRESFEC, 1);
1383                         stv0900_write_bits(i_params, F0900_FRESFEC, 0);
1384                 }
1385
1386                 break;
1387         case STV0900_SINGLE:
1388                 if (demod == STV0900_DEMOD_2)
1389                         stv0900_write_reg(i_params, R0900_GENCFG, 0x06);
1390                 else
1391                         stv0900_write_reg(i_params, R0900_GENCFG, 0x04);
1392
1393                 i_params->demod_mode = STV0900_SINGLE;
1394
1395                 stv0900_write_bits(i_params, F0900_FRESFEC, 1);
1396                 stv0900_write_bits(i_params, F0900_FRESFEC, 0);
1397                 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
1398                 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
1399                 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
1400                 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
1401                 break;
1402         }
1403
1404         return error;
1405 }
1406
1407 static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1408                                         struct stv0900_init_params *p_init)
1409 {
1410         struct stv0900_state *state = fe->demodulator_priv;
1411         enum fe_stv0900_error error = STV0900_NO_ERROR;
1412         enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1413         int selosci, i;
1414
1415         struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1416                                                 state->config->demod_address);
1417
1418         dprintk("%s\n", __func__);
1419
1420         if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
1421                 state->internal = temp_int->internal;
1422                 (state->internal->dmds_used)++;
1423                 dprintk("%s: Find Internal Structure!\n", __func__);
1424                 return STV0900_NO_ERROR;
1425         } else {
1426                 state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL);
1427                 temp_int = append_internal(state->internal);
1428                 state->internal->dmds_used = 1;
1429                 state->internal->i2c_adap = state->i2c_adap;
1430                 state->internal->i2c_addr = state->config->demod_address;
1431                 state->internal->clkmode = state->config->clkmode;
1432                 state->internal->errs = STV0900_NO_ERROR;
1433                 dprintk("%s: Create New Internal Structure!\n", __func__);
1434         }
1435
1436         if (state->internal != NULL) {
1437                 demodError = stv0900_initialize(state->internal);
1438                 if (demodError == STV0900_NO_ERROR) {
1439                                 error = STV0900_NO_ERROR;
1440                 } else {
1441                         if (demodError == STV0900_INVALID_HANDLE)
1442                                 error = STV0900_INVALID_HANDLE;
1443                         else
1444                                 error = STV0900_I2C_ERROR;
1445                 }
1446
1447                 if (state->internal != NULL) {
1448                         if (error == STV0900_NO_ERROR) {
1449                                 state->internal->demod_mode = p_init->demod_mode;
1450
1451                                 stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1);
1452
1453                                 state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID);
1454                                 state->internal->rolloff = p_init->rolloff;
1455                                 state->internal->quartz = p_init->dmd_ref_clk;
1456
1457                                 stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1458                                 stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1459
1460                                 state->internal->ts_config = p_init->ts_config;
1461                                 if (state->internal->ts_config == NULL)
1462                                         stv0900_set_ts_parallel_serial(state->internal,
1463                                                         p_init->path1_ts_clock,
1464                                                         p_init->path2_ts_clock);
1465                                 else {
1466                                         for (i = 0; state->internal->ts_config[i].addr != 0xffff; i++)
1467                                                 stv0900_write_reg(state->internal,
1468                                                                 state->internal->ts_config[i].addr,
1469                                                                 state->internal->ts_config[i].val);
1470
1471                                         stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 1);
1472                                         stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 0);
1473                                         stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 1);
1474                                         stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 0);
1475                                 }
1476
1477                                 stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1478                                 switch (p_init->tuner1_adc) {
1479                                 case 1:
1480                                         stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
1481                                         break;
1482                                 default:
1483                                         break;
1484                                 }
1485
1486                                 stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1487                                 switch (p_init->tuner2_adc) {
1488                                 case 1:
1489                                         stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26);
1490                                         break;
1491                                 default:
1492                                         break;
1493                                 }
1494
1495                                 stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion);
1496                                 stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
1497                                 stv0900_set_mclk(state->internal, 135000000);
1498                                 msleep(3);
1499
1500                                 switch (state->internal->clkmode) {
1501                                 case 0:
1502                                 case 2:
1503                                         stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
1504                                         break;
1505                                 default:
1506                                         selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
1507                                         stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
1508                                         break;
1509                                 }
1510                                 msleep(3);
1511
1512                                 state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz);
1513                                 if (state->internal->errs)
1514                                         error = STV0900_I2C_ERROR;
1515                         }
1516                 } else {
1517                         error = STV0900_INVALID_HANDLE;
1518                 }
1519         }
1520
1521         return error;
1522 }
1523
1524 static int stv0900_status(struct stv0900_internal *i_params,
1525                                         enum fe_stv0900_demod_num demod)
1526 {
1527         enum fe_stv0900_search_state demod_state;
1528         s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
1529         int locked = FALSE;
1530
1531         dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
1532         dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
1533         dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1534         dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1535         dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1536
1537         demod_state = stv0900_get_bits(i_params, mode_field);
1538         switch (demod_state) {
1539         case STV0900_SEARCH:
1540         case STV0900_PLH_DETECTED:
1541         default:
1542                 locked = FALSE;
1543                 break;
1544         case STV0900_DVBS2_FOUND:
1545                 locked = stv0900_get_bits(i_params, lock_field) &&
1546                                 stv0900_get_bits(i_params, delin_field) &&
1547                                 stv0900_get_bits(i_params, fifo_field);
1548                 break;
1549         case STV0900_DVBS_FOUND:
1550                 locked = stv0900_get_bits(i_params, lock_field) &&
1551                                 stv0900_get_bits(i_params, lockedvit_field) &&
1552                                 stv0900_get_bits(i_params, fifo_field);
1553                 break;
1554         }
1555
1556         return locked;
1557 }
1558
1559 static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1560                                         struct dvb_frontend_parameters *params)
1561 {
1562         struct stv0900_state *state = fe->demodulator_priv;
1563         struct stv0900_internal *i_params = state->internal;
1564         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1565
1566         struct stv0900_search_params p_search;
1567         struct stv0900_signal_info p_result;
1568
1569         enum fe_stv0900_error error = STV0900_NO_ERROR;
1570
1571         dprintk("%s: ", __func__);
1572
1573         p_result.locked = FALSE;
1574         p_search.path = state->demod;
1575         p_search.frequency = c->frequency;
1576         p_search.symbol_rate = c->symbol_rate;
1577         p_search.search_range = 10000000;
1578         p_search.fec = STV0900_FEC_UNKNOWN;
1579         p_search.standard = STV0900_AUTO_SEARCH;
1580         p_search.iq_inversion = STV0900_IQ_AUTO;
1581         p_search.search_algo = STV0900_BLIND_SEARCH;
1582
1583         if ((INRANGE(100000, p_search.symbol_rate, 70000000)) &&
1584                         (INRANGE(100000, p_search.search_range, 50000000))) {
1585                 switch (p_search.path) {
1586                 case STV0900_DEMOD_1:
1587                 default:
1588                         i_params->dmd1_srch_standard = p_search.standard;
1589                         i_params->dmd1_symbol_rate = p_search.symbol_rate;
1590                         i_params->dmd1_srch_range = p_search.search_range;
1591                         i_params->tuner1_freq = p_search.frequency;
1592                         i_params->dmd1_srch_algo = p_search.search_algo;
1593                         i_params->dmd1_srch_iq_inv = p_search.iq_inversion;
1594                         i_params->dmd1_fec = p_search.fec;
1595                         break;
1596
1597                 case STV0900_DEMOD_2:
1598                         i_params->dmd2_srch_stndrd = p_search.standard;
1599                         i_params->dmd2_symbol_rate = p_search.symbol_rate;
1600                         i_params->dmd2_srch_range = p_search.search_range;
1601                         i_params->tuner2_freq = p_search.frequency;
1602                         i_params->dmd2_srch_algo = p_search.search_algo;
1603                         i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
1604                         i_params->dmd2_fec = p_search.fec;
1605                         break;
1606                 }
1607
1608                 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1609                                         (i_params->errs == STV0900_NO_ERROR)) {
1610                         switch (p_search.path) {
1611                         case STV0900_DEMOD_1:
1612                         default:
1613                                 p_result.locked = i_params->dmd1_rslts.locked;
1614                                 p_result.standard = i_params->dmd1_rslts.standard;
1615                                 p_result.frequency = i_params->dmd1_rslts.frequency;
1616                                 p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
1617                                 p_result.fec = i_params->dmd1_rslts.fec;
1618                                 p_result.modcode = i_params->dmd1_rslts.modcode;
1619                                 p_result.pilot = i_params->dmd1_rslts.pilot;
1620                                 p_result.frame_length = i_params->dmd1_rslts.frame_length;
1621                                 p_result.spectrum = i_params->dmd1_rslts.spectrum;
1622                                 p_result.rolloff = i_params->dmd1_rslts.rolloff;
1623                                 p_result.modulation = i_params->dmd1_rslts.modulation;
1624                                 break;
1625                         case STV0900_DEMOD_2:
1626                                 p_result.locked = i_params->dmd2_rslts.locked;
1627                                 p_result.standard = i_params->dmd2_rslts.standard;
1628                                 p_result.frequency = i_params->dmd2_rslts.frequency;
1629                                 p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
1630                                 p_result.fec = i_params->dmd2_rslts.fec;
1631                                 p_result.modcode = i_params->dmd2_rslts.modcode;
1632                                 p_result.pilot = i_params->dmd2_rslts.pilot;
1633                                 p_result.frame_length = i_params->dmd2_rslts.frame_length;
1634                                 p_result.spectrum = i_params->dmd2_rslts.spectrum;
1635                                 p_result.rolloff = i_params->dmd2_rslts.rolloff;
1636                                 p_result.modulation = i_params->dmd2_rslts.modulation;
1637                                 break;
1638                         }
1639
1640                 } else {
1641                         p_result.locked = FALSE;
1642                         switch (p_search.path) {
1643                         case STV0900_DEMOD_1:
1644                                 switch (i_params->dmd1_err) {
1645                                 case STV0900_I2C_ERROR:
1646                                         error = STV0900_I2C_ERROR;
1647                                         break;
1648                                 case STV0900_NO_ERROR:
1649                                 default:
1650                                         error = STV0900_SEARCH_FAILED;
1651                                         break;
1652                                 }
1653                                 break;
1654                         case STV0900_DEMOD_2:
1655                                 switch (i_params->dmd2_err) {
1656                                 case STV0900_I2C_ERROR:
1657                                         error = STV0900_I2C_ERROR;
1658                                         break;
1659                                 case STV0900_NO_ERROR:
1660                                 default:
1661                                         error = STV0900_SEARCH_FAILED;
1662                                         break;
1663                                 }
1664                                 break;
1665                         }
1666                 }
1667
1668         } else
1669                 error = STV0900_BAD_PARAMETER;
1670
1671         if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1672                 dprintk("Search Success\n");
1673                 return DVBFE_ALGO_SEARCH_SUCCESS;
1674         } else {
1675                 dprintk("Search Fail\n");
1676                 return DVBFE_ALGO_SEARCH_FAILED;
1677         }
1678
1679         return DVBFE_ALGO_SEARCH_ERROR;
1680 }
1681
1682 static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1683 {
1684         struct stv0900_state *state = fe->demodulator_priv;
1685
1686         dprintk("%s: ", __func__);
1687
1688         if ((stv0900_status(state->internal, state->demod)) == TRUE) {
1689                 dprintk("DEMOD LOCK OK\n");
1690                 *status = FE_HAS_CARRIER
1691                         | FE_HAS_VITERBI
1692                         | FE_HAS_SYNC
1693                         | FE_HAS_LOCK;
1694         } else
1695                 dprintk("DEMOD LOCK FAIL\n");
1696
1697         return 0;
1698 }
1699
1700 static int stv0900_track(struct dvb_frontend *fe,
1701                         struct dvb_frontend_parameters *p)
1702 {
1703         return 0;
1704 }
1705
1706 static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1707 {
1708
1709         struct stv0900_state *state = fe->demodulator_priv;
1710         struct stv0900_internal *i_params = state->internal;
1711         enum fe_stv0900_demod_num demod = state->demod;
1712         s32 rst_field;
1713
1714         dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
1715
1716         if (stop_ts == TRUE)
1717                 stv0900_write_bits(i_params, rst_field, 1);
1718         else
1719                 stv0900_write_bits(i_params, rst_field, 0);
1720
1721         return 0;
1722 }
1723
1724 static int stv0900_diseqc_init(struct dvb_frontend *fe)
1725 {
1726         struct stv0900_state *state = fe->demodulator_priv;
1727         struct stv0900_internal *i_params = state->internal;
1728         enum fe_stv0900_demod_num demod = state->demod;
1729         s32 mode_field, reset_field;
1730
1731         dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1732         dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1733
1734         stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
1735         stv0900_write_bits(i_params, reset_field, 1);
1736         stv0900_write_bits(i_params, reset_field, 0);
1737
1738         return 0;
1739 }
1740
1741 static int stv0900_init(struct dvb_frontend *fe)
1742 {
1743         dprintk("%s\n", __func__);
1744
1745         stv0900_stop_ts(fe, 1);
1746         stv0900_diseqc_init(fe);
1747
1748         return 0;
1749 }
1750
1751 static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data,
1752                                 u32 NbData, enum fe_stv0900_demod_num demod)
1753 {
1754         s32 i = 0;
1755
1756         switch (demod) {
1757         case STV0900_DEMOD_1:
1758         default:
1759                 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1);
1760                 while (i < NbData) {
1761                         while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL))
1762                                 ;/* checkpatch complains */
1763                         stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
1764                         i++;
1765                 }
1766
1767                 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
1768                 i = 0;
1769                 while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
1770                         msleep(10);
1771                         i++;
1772                 }
1773
1774                 break;
1775         case STV0900_DEMOD_2:
1776                 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
1777
1778                 while (i < NbData) {
1779                         while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
1780                                 ;/* checkpatch complains */
1781                         stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
1782                         i++;
1783                 }
1784
1785                 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0);
1786                 i = 0;
1787                 while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) {
1788                         msleep(10);
1789                         i++;
1790                 }
1791                 break;
1792         }
1793
1794         return 0;
1795 }
1796
1797 static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1798                                         struct dvb_diseqc_master_cmd *cmd)
1799 {
1800         struct stv0900_state *state = fe->demodulator_priv;
1801
1802         return stv0900_diseqc_send(state->internal,
1803                                 cmd->msg,
1804                                 cmd->msg_len,
1805                                 state->demod);
1806 }
1807
1808 static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1809 {
1810         struct stv0900_state *state = fe->demodulator_priv;
1811         struct stv0900_internal *i_params = state->internal;
1812         enum fe_stv0900_demod_num demod = state->demod;
1813         s32 mode_field;
1814         u8 data;
1815
1816         dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1817
1818         switch (burst) {
1819         case SEC_MINI_A:
1820                 stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */
1821                 data = 0x00;
1822                 stv0900_diseqc_send(state->internal, &data, 1, state->demod);
1823                 break;
1824         case SEC_MINI_B:
1825                 stv0900_write_bits(i_params, mode_field, 2);/* Modulated */
1826                 data = 0xff;
1827                 stv0900_diseqc_send(state->internal, &data, 1, state->demod);
1828                 break;
1829         }
1830
1831         return 0;
1832 }
1833
1834 static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1835                                 struct dvb_diseqc_slave_reply *reply)
1836 {
1837         struct stv0900_state *state = fe->demodulator_priv;
1838         struct stv0900_internal *i_params = state->internal;
1839         s32 i = 0;
1840
1841         switch (state->demod) {
1842         case STV0900_DEMOD_1:
1843         default:
1844                 reply->msg_len = 0;
1845
1846                 while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
1847                         msleep(10);
1848                         i++;
1849                 }
1850
1851                 if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
1852                         reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
1853
1854                         for (i = 0; i < reply->msg_len; i++)
1855                                 reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA);
1856                 }
1857                 break;
1858         case STV0900_DEMOD_2:
1859                 reply->msg_len = 0;
1860
1861                 while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) {
1862                         msleep(10);
1863                         i++;
1864                 }
1865
1866                 if (stv0900_get_bits(i_params, F0900_P2_RX_END)) {
1867                         reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR);
1868
1869                         for (i = 0; i < reply->msg_len; i++)
1870                                 reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA);
1871                 }
1872                 break;
1873         }
1874
1875         return 0;
1876 }
1877
1878 static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
1879 {
1880         struct stv0900_state *state = fe->demodulator_priv;
1881         struct stv0900_internal *i_params = state->internal;
1882         enum fe_stv0900_demod_num demod = state->demod;
1883         s32 mode_field, reset_field;
1884
1885         dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
1886
1887         dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1888         dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1889
1890         switch (toneoff) {
1891         case SEC_TONE_ON:
1892                 /*Set the DiseqC mode to 22Khz _continues_ tone*/
1893                 stv0900_write_bits(i_params, mode_field, 0);
1894                 stv0900_write_bits(i_params, reset_field, 1);
1895                 /*release DiseqC reset to enable the 22KHz tone*/
1896                 stv0900_write_bits(i_params, reset_field, 0);
1897                 break;
1898         case SEC_TONE_OFF:
1899                 /*return diseqc mode to config->diseqc_mode.
1900                 Usually it's without _continues_ tone */
1901                 stv0900_write_bits(i_params, mode_field,
1902                                 state->config->diseqc_mode);
1903                 /*maintain the DiseqC reset to disable the 22KHz tone*/
1904                 stv0900_write_bits(i_params, reset_field, 1);
1905                 stv0900_write_bits(i_params, reset_field, 0);
1906                 break;
1907         default:
1908                 return -EINVAL;
1909         }
1910
1911         return 0;
1912 }
1913
1914 static void stv0900_release(struct dvb_frontend *fe)
1915 {
1916         struct stv0900_state *state = fe->demodulator_priv;
1917
1918         dprintk("%s\n", __func__);
1919
1920         if ((--(state->internal->dmds_used)) <= 0) {
1921
1922                 dprintk("%s: Actually removing\n", __func__);
1923
1924                 remove_inode(state->internal);
1925                 kfree(state->internal);
1926         }
1927
1928         kfree(state);
1929 }
1930
1931 static struct dvb_frontend_ops stv0900_ops = {
1932
1933         .info = {
1934                 .name                   = "STV0900 frontend",
1935                 .type                   = FE_QPSK,
1936                 .frequency_min          = 950000,
1937                 .frequency_max          = 2150000,
1938                 .frequency_stepsize     = 125,
1939                 .frequency_tolerance    = 0,
1940                 .symbol_rate_min        = 1000000,
1941                 .symbol_rate_max        = 45000000,
1942                 .symbol_rate_tolerance  = 500,
1943                 .caps                   = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1944                                           FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1945                                           FE_CAN_FEC_7_8 | FE_CAN_QPSK    |
1946                                           FE_CAN_2G_MODULATION |
1947                                           FE_CAN_FEC_AUTO
1948         },
1949         .release                        = stv0900_release,
1950         .init                           = stv0900_init,
1951         .get_frontend_algo              = stv0900_frontend_algo,
1952         .i2c_gate_ctrl                  = stv0900_i2c_gate_ctrl,
1953         .diseqc_send_master_cmd         = stv0900_send_master_cmd,
1954         .diseqc_send_burst              = stv0900_send_burst,
1955         .diseqc_recv_slave_reply        = stv0900_recv_slave_reply,
1956         .set_tone                       = stv0900_set_tone,
1957         .set_property                   = stb0900_set_property,
1958         .get_property                   = stb0900_get_property,
1959         .search                         = stv0900_search,
1960         .track                          = stv0900_track,
1961         .read_status                    = stv0900_read_status,
1962         .read_ber                       = stv0900_read_ber,
1963         .read_signal_strength           = stv0900_read_signal_strength,
1964         .read_snr                       = stv0900_read_snr,
1965         .read_ucblocks                  = stv0900_read_ucblocks,
1966 };
1967
1968 struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1969                                         struct i2c_adapter *i2c,
1970                                         int demod)
1971 {
1972         struct stv0900_state *state = NULL;
1973         struct stv0900_init_params init_params;
1974         enum fe_stv0900_error err_stv0900;
1975
1976         state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
1977         if (state == NULL)
1978                 goto error;
1979
1980         state->demod            = demod;
1981         state->config           = config;
1982         state->i2c_adap         = i2c;
1983
1984         memcpy(&state->frontend.ops, &stv0900_ops,
1985                         sizeof(struct dvb_frontend_ops));
1986         state->frontend.demodulator_priv = state;
1987
1988         switch (demod) {
1989         case 0:
1990         case 1:
1991                 init_params.dmd_ref_clk         = config->xtal;
1992                 init_params.demod_mode          = config->demod_mode;
1993                 init_params.rolloff             = STV0900_35;
1994                 init_params.path1_ts_clock      = config->path1_mode;
1995                 init_params.tun1_maddress       = config->tun1_maddress;
1996                 init_params.tun1_iq_inversion   = STV0900_IQ_NORMAL;
1997                 init_params.tuner1_adc          = config->tun1_adc;
1998                 init_params.path2_ts_clock      = config->path2_mode;
1999                 init_params.ts_config           = config->ts_config_regs;
2000                 init_params.tun2_maddress       = config->tun2_maddress;
2001                 init_params.tuner2_adc          = config->tun2_adc;
2002                 init_params.tun2_iq_inversion   = STV0900_IQ_SWAPPED;
2003
2004                 err_stv0900 = stv0900_init_internal(&state->frontend,
2005                                                         &init_params);
2006
2007                 if (err_stv0900)
2008                         goto error;
2009
2010                 break;
2011         default:
2012                 goto error;
2013                 break;
2014         }
2015
2016         dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
2017         return &state->frontend;
2018
2019 error:
2020         dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
2021                 __func__, demod);
2022         kfree(state);
2023         return NULL;
2024 }
2025 EXPORT_SYMBOL(stv0900_attach);
2026
2027 MODULE_PARM_DESC(debug, "Set debug");
2028
2029 MODULE_AUTHOR("Igor M. Liplianin");
2030 MODULE_DESCRIPTION("ST STV0900 frontend");
2031 MODULE_LICENSE("GPL");