4 * Driver for ST STV0900 satellite demodulator IC.
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include <linux/i2c.h>
33 #include "stv0900_reg.h"
34 #include "stv0900_priv.h"
35 #include "stv0900_init.h"
38 module_param_named(debug, stvdebug, int, 0644);
40 /* internal params node */
41 struct stv0900_inode {
42 /* pointer for internal params, one for each pair of demods */
43 struct stv0900_internal *internal;
44 struct stv0900_inode *next_inode;
47 /* first internal params */
48 static struct stv0900_inode *stv0900_first_inode;
50 /* find chip by i2c adapter and i2c address */
51 static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
54 struct stv0900_inode *temp_chip = stv0900_first_inode;
56 if (temp_chip != NULL) {
58 Search of the last stv0900 chip or
59 find it by i2c adapter and i2c address */
60 while ((temp_chip != NULL) &&
61 ((temp_chip->internal->i2c_adap != i2c_adap) ||
62 (temp_chip->internal->i2c_addr != i2c_addr)))
64 temp_chip = temp_chip->next_inode;
71 /* deallocating chip */
72 static void remove_inode(struct stv0900_internal *internal)
74 struct stv0900_inode *prev_node = stv0900_first_inode;
75 struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
78 if (del_node != NULL) {
79 if (del_node == stv0900_first_inode) {
80 stv0900_first_inode = del_node->next_inode;
82 while (prev_node->next_inode != del_node)
83 prev_node = prev_node->next_inode;
85 if (del_node->next_inode == NULL)
86 prev_node->next_inode = NULL;
88 prev_node->next_inode =
89 prev_node->next_inode->next_inode;
96 /* allocating new chip */
97 static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
99 struct stv0900_inode *new_node = stv0900_first_inode;
101 if (new_node == NULL) {
102 new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
103 stv0900_first_inode = new_node;
105 while (new_node->next_inode != NULL)
106 new_node = new_node->next_inode;
108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
110 if (new_node->next_inode != NULL)
111 new_node = new_node->next_inode;
116 if (new_node != NULL) {
117 new_node->internal = internal;
118 new_node->next_inode = NULL;
124 s32 ge2comp(s32 a, s32 width)
129 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
132 void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
137 struct i2c_msg i2cmsg = {
138 .addr = intp->i2c_addr,
144 data[0] = MSB(reg_addr);
145 data[1] = LSB(reg_addr);
148 ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
150 dprintk("%s: i2c error %d\n", __func__, ret);
153 u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
156 u8 b0[] = { MSB(reg), LSB(reg) };
158 struct i2c_msg msg[] = {
160 .addr = intp->i2c_addr,
165 .addr = intp->i2c_addr,
172 ret = i2c_transfer(intp->i2c_adap, msg, 2);
174 dprintk("%s: i2c error %d, reg[0x%02x]\n",
180 void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
182 u8 position = 0, i = 0;
184 (*mask) = label & 0xff;
186 while ((position == 0) && (i < 8)) {
187 position = ((*mask) >> i) & 0x01;
194 void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
198 reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
199 extract_mask_pos(label, &mask, &pos);
201 val = mask & (val << pos);
203 reg = (reg & (~mask)) | val;
204 stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
208 u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
213 extract_mask_pos(label, &mask, &pos);
215 val = stv0900_read_reg(intp, label >> 16);
216 val = (val & mask) >> pos;
221 enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
226 return STV0900_INVALID_HANDLE;
228 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
230 if (intp->errs != STV0900_NO_ERROR)
234 stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
235 stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
237 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
238 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
239 stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
240 stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
241 stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
243 stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
245 switch (intp->clkmode) {
248 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
252 /* preserve SELOSCI bit */
253 i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
254 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
259 for (i = 0; i < 181; i++)
260 stv0900_write_reg(intp, STV0900_InitVal[i][0],
261 STV0900_InitVal[i][1]);
263 if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
264 stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
265 for (i = 0; i < 32; i++)
266 stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
267 STV0900_Cut20_AddOnVal[i][1]);
270 stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
271 stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
273 stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
274 stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
276 stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
277 stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
279 stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
280 stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
282 return STV0900_NO_ERROR;
285 u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
287 u32 mclk = 90000000, div = 0, ad_div = 0;
289 div = stv0900_get_bits(intp, F0900_M_DIV);
290 ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
292 mclk = (div + 1) * ext_clk / ad_div;
294 dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
299 enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
303 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
307 return STV0900_INVALID_HANDLE;
310 return STV0900_I2C_ERROR;
312 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
313 m_div = ((clk_sel * mclk) / intp->quartz) - 1;
314 stv0900_write_bits(intp, F0900_M_DIV, m_div);
315 intp->mclk = stv0900_get_mclk_freq(intp,
318 /*Set the DiseqC frequency to 22KHz */
321 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
322 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
324 m_div = intp->mclk / 704000;
325 stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
326 stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
328 stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
329 stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
332 return STV0900_I2C_ERROR;
334 return STV0900_NO_ERROR;
337 u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
338 enum fe_stv0900_demod_num demod)
340 u32 lsb, msb, hsb, err_val;
345 hsb = stv0900_get_bits(intp, ERR_CNT12);
346 msb = stv0900_get_bits(intp, ERR_CNT11);
347 lsb = stv0900_get_bits(intp, ERR_CNT10);
350 hsb = stv0900_get_bits(intp, ERR_CNT22);
351 msb = stv0900_get_bits(intp, ERR_CNT21);
352 lsb = stv0900_get_bits(intp, ERR_CNT20);
356 err_val = (hsb << 16) + (msb << 8) + (lsb);
361 static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
363 struct stv0900_state *state = fe->demodulator_priv;
364 struct stv0900_internal *intp = state->internal;
365 enum fe_stv0900_demod_num demod = state->demod;
367 stv0900_write_bits(intp, I2CT_ON, enable);
372 static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
373 enum fe_stv0900_clock_type path1_ts,
374 enum fe_stv0900_clock_type path2_ts)
377 dprintk("%s\n", __func__);
379 if (intp->chip_id >= 0x20) {
381 case STV0900_PARALLEL_PUNCT_CLOCK:
382 case STV0900_DVBCI_CLOCK:
384 case STV0900_SERIAL_PUNCT_CLOCK:
385 case STV0900_SERIAL_CONT_CLOCK:
387 stv0900_write_reg(intp, R0900_TSGENERAL,
390 case STV0900_PARALLEL_PUNCT_CLOCK:
391 case STV0900_DVBCI_CLOCK:
392 stv0900_write_reg(intp, R0900_TSGENERAL,
394 stv0900_write_bits(intp,
395 F0900_P1_TSFIFO_MANSPEED, 3);
396 stv0900_write_bits(intp,
397 F0900_P2_TSFIFO_MANSPEED, 0);
398 stv0900_write_reg(intp,
399 R0900_P1_TSSPEED, 0x14);
400 stv0900_write_reg(intp,
401 R0900_P2_TSSPEED, 0x28);
405 case STV0900_SERIAL_PUNCT_CLOCK:
406 case STV0900_SERIAL_CONT_CLOCK:
409 case STV0900_SERIAL_PUNCT_CLOCK:
410 case STV0900_SERIAL_CONT_CLOCK:
412 stv0900_write_reg(intp,
413 R0900_TSGENERAL, 0x0C);
415 case STV0900_PARALLEL_PUNCT_CLOCK:
416 case STV0900_DVBCI_CLOCK:
417 stv0900_write_reg(intp,
418 R0900_TSGENERAL, 0x0A);
419 dprintk("%s: 0x0a\n", __func__);
426 case STV0900_PARALLEL_PUNCT_CLOCK:
427 case STV0900_DVBCI_CLOCK:
429 case STV0900_SERIAL_PUNCT_CLOCK:
430 case STV0900_SERIAL_CONT_CLOCK:
432 stv0900_write_reg(intp, R0900_TSGENERAL1X,
435 case STV0900_PARALLEL_PUNCT_CLOCK:
436 case STV0900_DVBCI_CLOCK:
437 stv0900_write_reg(intp, R0900_TSGENERAL1X,
439 stv0900_write_bits(intp,
440 F0900_P1_TSFIFO_MANSPEED, 3);
441 stv0900_write_bits(intp,
442 F0900_P2_TSFIFO_MANSPEED, 0);
443 stv0900_write_reg(intp, R0900_P1_TSSPEED,
445 stv0900_write_reg(intp, R0900_P2_TSSPEED,
451 case STV0900_SERIAL_PUNCT_CLOCK:
452 case STV0900_SERIAL_CONT_CLOCK:
455 case STV0900_SERIAL_PUNCT_CLOCK:
456 case STV0900_SERIAL_CONT_CLOCK:
458 stv0900_write_reg(intp, R0900_TSGENERAL1X,
461 case STV0900_PARALLEL_PUNCT_CLOCK:
462 case STV0900_DVBCI_CLOCK:
463 stv0900_write_reg(intp, R0900_TSGENERAL1X,
465 dprintk("%s: 0x12\n", __func__);
474 case STV0900_PARALLEL_PUNCT_CLOCK:
475 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
476 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
478 case STV0900_DVBCI_CLOCK:
479 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
480 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
482 case STV0900_SERIAL_PUNCT_CLOCK:
483 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
484 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
486 case STV0900_SERIAL_CONT_CLOCK:
487 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
488 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
495 case STV0900_PARALLEL_PUNCT_CLOCK:
496 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
497 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
499 case STV0900_DVBCI_CLOCK:
500 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
501 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
503 case STV0900_SERIAL_PUNCT_CLOCK:
504 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
505 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
507 case STV0900_SERIAL_CONT_CLOCK:
508 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
509 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
515 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
516 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
517 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
518 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
521 void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
524 struct dvb_frontend_ops *frontend_ops = NULL;
525 struct dvb_tuner_ops *tuner_ops = NULL;
528 frontend_ops = &fe->ops;
530 if (&frontend_ops->tuner_ops)
531 tuner_ops = &frontend_ops->tuner_ops;
533 if (tuner_ops->set_frequency) {
534 if ((tuner_ops->set_frequency(fe, frequency)) < 0)
535 dprintk("%s: Invalid parameter\n", __func__);
537 dprintk("%s: Frequency=%d\n", __func__, frequency);
541 if (tuner_ops->set_bandwidth) {
542 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
543 dprintk("%s: Invalid parameter\n", __func__);
545 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
550 void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
552 struct dvb_frontend_ops *frontend_ops = NULL;
553 struct dvb_tuner_ops *tuner_ops = NULL;
556 frontend_ops = &fe->ops;
558 if (&frontend_ops->tuner_ops)
559 tuner_ops = &frontend_ops->tuner_ops;
561 if (tuner_ops->set_bandwidth) {
562 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
563 dprintk("%s: Invalid parameter\n", __func__);
565 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
570 u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod)
574 Tuner_Frequency(MHz) = Regs / 64
575 Tuner_granularity(MHz) = Regs / 2048
576 real_Tuner_Frequency = Tuner_Frequency(MHz) - Tuner_granularity(MHz)
578 freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) +
579 (stv0900_get_bits(intp, TUN_RFFREQ1) << 2) +
580 stv0900_get_bits(intp, TUN_RFFREQ0);
582 freq = (freq * 1000) / 64;
584 round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) +
585 stv0900_get_bits(intp, TUN_RFRESTE0);
587 round = (round * 1000) / 2048;
592 void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency,
593 u32 Bandwidth, int demod)
597 Tuner_frequency_reg= Frequency(MHz)*64
599 tunerFrequency = (Frequency * 64) / 1000;
601 stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10));
602 stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff);
603 stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03));
604 /* Low Pass Filter = BW /2 (MHz)*/
605 stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000);
606 /* Tuner Write trig */
607 stv0900_write_reg(intp, TNRLD, 1);
610 static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
611 const struct stv0900_table *lookup,
612 enum fe_stv0900_demod_num demod)
620 dprintk("%s\n", __func__);
622 if ((lookup == NULL) || (lookup->size <= 0))
625 agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
626 stv0900_get_bits(intp, AGCIQ_VALUE0));
629 imax = lookup->size - 1;
630 if (INRANGE(lookup->table[imin].regval, agc_gain,
631 lookup->table[imax].regval)) {
632 while ((imax - imin) > 1) {
633 i = (imax + imin) >> 1;
635 if (INRANGE(lookup->table[imin].regval,
637 lookup->table[i].regval))
643 rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
644 rf_lvl *= (lookup->table[imax].realval -
645 lookup->table[imin].realval);
646 rf_lvl /= (lookup->table[imax].regval -
647 lookup->table[imin].regval);
648 rf_lvl += lookup->table[imin].realval;
649 } else if (agc_gain > lookup->table[0].regval)
651 else if (agc_gain < lookup->table[lookup->size-1].regval)
654 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
659 static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
661 struct stv0900_state *state = fe->demodulator_priv;
662 struct stv0900_internal *internal = state->internal;
663 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
666 rflevel = (rflevel + 100) * (65535 / 70);
678 static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
679 const struct stv0900_table *lookup)
681 struct stv0900_state *state = fe->demodulator_priv;
682 struct stv0900_internal *intp = state->internal;
683 enum fe_stv0900_demod_num demod = state->demod;
693 dprintk("%s\n", __func__);
695 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
696 noise_field1 = NOSPLHT_NORMED1;
697 noise_field0 = NOSPLHT_NORMED0;
699 noise_field1 = NOSDATAT_NORMED1;
700 noise_field0 = NOSDATAT_NORMED0;
703 if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
704 if ((lookup != NULL) && lookup->size) {
707 for (i = 0; i < 16; i++) {
708 regval += MAKEWORD(stv0900_get_bits(intp,
710 stv0900_get_bits(intp,
717 imax = lookup->size - 1;
718 if (INRANGE(lookup->table[imin].regval,
720 lookup->table[imax].regval)) {
721 while ((imax - imin) > 1) {
722 i = (imax + imin) >> 1;
723 if (INRANGE(lookup->table[imin].regval,
725 lookup->table[i].regval))
731 c_n = ((regval - lookup->table[imin].regval)
732 * (lookup->table[imax].realval
733 - lookup->table[imin].realval)
734 / (lookup->table[imax].regval
735 - lookup->table[imin].regval))
736 + lookup->table[imin].realval;
737 } else if (regval < lookup->table[imin].regval)
745 static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
747 struct stv0900_state *state = fe->demodulator_priv;
748 struct stv0900_internal *intp = state->internal;
749 enum fe_stv0900_demod_num demod = state->demod;
750 u8 err_val1, err_val0;
751 u32 header_err_val = 0;
754 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
755 /* DVB-S2 delineator errors count */
757 /* retreiving number for errnous headers */
758 err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
759 err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
760 header_err_val = (err_val1 << 8) | err_val0;
762 /* retreiving number for errnous packets */
763 err_val1 = stv0900_read_reg(intp, UPCRCKO1);
764 err_val0 = stv0900_read_reg(intp, UPCRCKO0);
765 *ucblocks = (err_val1 << 8) | err_val0;
766 *ucblocks += header_err_val;
772 static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
774 s32 snrlcl = stv0900_carr_get_quality(fe,
775 (const struct stv0900_table *)&stv0900_s2_cn);
776 snrlcl = (snrlcl + 30) * 384;
788 static u32 stv0900_get_ber(struct stv0900_internal *intp,
789 enum fe_stv0900_demod_num demod)
791 u32 ber = 10000000, i;
794 demod_state = stv0900_get_bits(intp, HEADER_MODE);
796 switch (demod_state) {
798 case STV0900_PLH_DETECTED:
802 case STV0900_DVBS_FOUND:
804 for (i = 0; i < 5; i++) {
806 ber += stv0900_get_err_count(intp, 0, demod);
810 if (stv0900_get_bits(intp, PRFVIT)) {
816 case STV0900_DVBS2_FOUND:
818 for (i = 0; i < 5; i++) {
820 ber += stv0900_get_err_count(intp, 0, demod);
824 if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
835 static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
837 struct stv0900_state *state = fe->demodulator_priv;
838 struct stv0900_internal *internal = state->internal;
840 *ber = stv0900_get_ber(internal, state->demod);
845 int stv0900_get_demod_lock(struct stv0900_internal *intp,
846 enum fe_stv0900_demod_num demod, s32 time_out)
851 enum fe_stv0900_search_state dmd_state;
853 while ((timer < time_out) && (lock == 0)) {
854 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
855 dprintk("Demod State = %d\n", dmd_state);
858 case STV0900_PLH_DETECTED:
862 case STV0900_DVBS2_FOUND:
863 case STV0900_DVBS_FOUND:
864 lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
875 dprintk("DEMOD LOCK OK\n");
877 dprintk("DEMOD LOCK FAIL\n");
882 void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
883 enum fe_stv0900_demod_num demod)
888 dprintk("%s\n", __func__);
890 regflist = MODCODLST0;
892 for (i = 0; i < 16; i++)
893 stv0900_write_reg(intp, regflist + i, 0xff);
896 void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
897 enum fe_stv0900_demod_num demod)
905 dprintk("%s\n", __func__);
907 if (intp->chip_id <= 0x11) {
910 mod_code = stv0900_read_reg(intp, PLHMODCOD);
911 matype = mod_code & 0x3;
912 mod_code = (mod_code & 0x7f) >> 2;
914 reg_index = MODCODLSTF - mod_code / 2;
915 field_index = mod_code % 2;
933 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
935 if (field_index == 0)
936 stv0900_write_reg(intp, reg_index,
939 stv0900_write_reg(intp, reg_index,
943 } else if (intp->chip_id >= 0x12) {
944 for (reg_index = 0; reg_index < 7; reg_index++)
945 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
947 stv0900_write_reg(intp, MODCODLSTE, 0xff);
948 stv0900_write_reg(intp, MODCODLSTF, 0xcf);
949 for (reg_index = 0; reg_index < 8; reg_index++)
950 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
956 void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
957 enum fe_stv0900_demod_num demod)
961 dprintk("%s\n", __func__);
963 stv0900_write_reg(intp, MODCODLST0, 0xff);
964 stv0900_write_reg(intp, MODCODLST1, 0xf0);
965 stv0900_write_reg(intp, MODCODLSTF, 0x0f);
966 for (reg_index = 0; reg_index < 13; reg_index++)
967 stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
971 static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
973 return DVBFE_ALGO_CUSTOM;
976 static int stb0900_set_property(struct dvb_frontend *fe,
977 struct dtv_property *tvp)
979 dprintk("%s(..)\n", __func__);
984 static int stb0900_get_property(struct dvb_frontend *fe,
985 struct dtv_property *tvp)
987 dprintk("%s(..)\n", __func__);
992 void stv0900_start_search(struct stv0900_internal *intp,
993 enum fe_stv0900_demod_num demod)
998 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
999 if (intp->chip_id == 0x10)
1000 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1002 if (intp->chip_id < 0x20)
1003 stv0900_write_reg(intp, CARHDR, 0x55);
1005 if (intp->chip_id <= 0x20) {
1006 if (intp->symbol_rate[0] <= 5000000) {
1007 stv0900_write_reg(intp, CARCFG, 0x44);
1008 stv0900_write_reg(intp, CFRUP1, 0x0f);
1009 stv0900_write_reg(intp, CFRUP0, 0xff);
1010 stv0900_write_reg(intp, CFRLOW1, 0xf0);
1011 stv0900_write_reg(intp, CFRLOW0, 0x00);
1012 stv0900_write_reg(intp, RTCS2, 0x68);
1014 stv0900_write_reg(intp, CARCFG, 0xc4);
1015 stv0900_write_reg(intp, RTCS2, 0x44);
1018 } else { /*cut 3.0 above*/
1019 if (intp->symbol_rate[demod] <= 5000000)
1020 stv0900_write_reg(intp, RTCS2, 0x68);
1022 stv0900_write_reg(intp, RTCS2, 0x44);
1024 stv0900_write_reg(intp, CARCFG, 0x46);
1025 if (intp->srch_algo[demod] == STV0900_WARM_START) {
1027 freq /= (intp->mclk / 1000);
1028 freq_s16 = (s16)freq;
1030 freq = (intp->srch_range[demod] / 2000);
1031 if (intp->symbol_rate[demod] <= 5000000)
1037 freq /= (intp->mclk / 1000);
1038 freq_s16 = (s16)freq;
1041 stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
1042 stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
1044 stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
1045 stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
1048 stv0900_write_reg(intp, CFRINIT1, 0);
1049 stv0900_write_reg(intp, CFRINIT0, 0);
1051 if (intp->chip_id >= 0x20) {
1052 stv0900_write_reg(intp, EQUALCFG, 0x41);
1053 stv0900_write_reg(intp, FFECFG, 0x41);
1055 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
1056 (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
1057 (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
1058 stv0900_write_reg(intp, VITSCALE,
1060 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1064 stv0900_write_reg(intp, SFRSTEP, 0x00);
1065 stv0900_write_reg(intp, TMGTHRISE, 0xe0);
1066 stv0900_write_reg(intp, TMGTHFALL, 0xc0);
1067 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1068 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1069 stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
1070 stv0900_write_reg(intp, RTC, 0x88);
1071 if (intp->chip_id >= 0x20) {
1072 if (intp->symbol_rate[demod] < 2000000) {
1073 if (intp->chip_id <= 0x20)
1074 stv0900_write_reg(intp, CARFREQ, 0x39);
1076 stv0900_write_reg(intp, CARFREQ, 0x89);
1078 stv0900_write_reg(intp, CARHDR, 0x40);
1079 } else if (intp->symbol_rate[demod] < 10000000) {
1080 stv0900_write_reg(intp, CARFREQ, 0x4c);
1081 stv0900_write_reg(intp, CARHDR, 0x20);
1083 stv0900_write_reg(intp, CARFREQ, 0x4b);
1084 stv0900_write_reg(intp, CARHDR, 0x20);
1088 if (intp->symbol_rate[demod] < 10000000)
1089 stv0900_write_reg(intp, CARFREQ, 0xef);
1091 stv0900_write_reg(intp, CARFREQ, 0xed);
1094 switch (intp->srch_algo[demod]) {
1095 case STV0900_WARM_START:
1096 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1097 stv0900_write_reg(intp, DMDISTATE, 0x18);
1099 case STV0900_COLD_START:
1100 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1101 stv0900_write_reg(intp, DMDISTATE, 0x15);
1108 u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1109 s32 pilot, u8 chip_id)
1111 u8 aclc_value = 0x29;
1113 const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
1115 dprintk("%s\n", __func__);
1117 if (chip_id <= 0x12) {
1118 cls2 = FE_STV0900_S2CarLoop;
1119 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1120 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1121 } else if (chip_id == 0x20) {
1122 cls2 = FE_STV0900_S2CarLoopCut20;
1123 cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
1124 cllas2 = FE_STV0900_S2APSKCarLoopCut20;
1126 cls2 = FE_STV0900_S2CarLoopCut30;
1127 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1128 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1131 if (modcode < STV0900_QPSK_12) {
1133 while ((i < 3) && (modcode != cllqs2[i].modcode))
1140 while ((i < 14) && (modcode != cls2[i].modcode))
1145 while ((i < 11) && (modcode != cllas2[i].modcode))
1153 if (modcode <= STV0900_QPSK_25) {
1155 if (srate <= 3000000)
1156 aclc_value = cllqs2[i].car_loop_pilots_on_2;
1157 else if (srate <= 7000000)
1158 aclc_value = cllqs2[i].car_loop_pilots_on_5;
1159 else if (srate <= 15000000)
1160 aclc_value = cllqs2[i].car_loop_pilots_on_10;
1161 else if (srate <= 25000000)
1162 aclc_value = cllqs2[i].car_loop_pilots_on_20;
1164 aclc_value = cllqs2[i].car_loop_pilots_on_30;
1166 if (srate <= 3000000)
1167 aclc_value = cllqs2[i].car_loop_pilots_off_2;
1168 else if (srate <= 7000000)
1169 aclc_value = cllqs2[i].car_loop_pilots_off_5;
1170 else if (srate <= 15000000)
1171 aclc_value = cllqs2[i].car_loop_pilots_off_10;
1172 else if (srate <= 25000000)
1173 aclc_value = cllqs2[i].car_loop_pilots_off_20;
1175 aclc_value = cllqs2[i].car_loop_pilots_off_30;
1178 } else if (modcode <= STV0900_8PSK_910) {
1180 if (srate <= 3000000)
1181 aclc_value = cls2[i].car_loop_pilots_on_2;
1182 else if (srate <= 7000000)
1183 aclc_value = cls2[i].car_loop_pilots_on_5;
1184 else if (srate <= 15000000)
1185 aclc_value = cls2[i].car_loop_pilots_on_10;
1186 else if (srate <= 25000000)
1187 aclc_value = cls2[i].car_loop_pilots_on_20;
1189 aclc_value = cls2[i].car_loop_pilots_on_30;
1191 if (srate <= 3000000)
1192 aclc_value = cls2[i].car_loop_pilots_off_2;
1193 else if (srate <= 7000000)
1194 aclc_value = cls2[i].car_loop_pilots_off_5;
1195 else if (srate <= 15000000)
1196 aclc_value = cls2[i].car_loop_pilots_off_10;
1197 else if (srate <= 25000000)
1198 aclc_value = cls2[i].car_loop_pilots_off_20;
1200 aclc_value = cls2[i].car_loop_pilots_off_30;
1204 if (srate <= 3000000)
1205 aclc_value = cllas2[i].car_loop_pilots_on_2;
1206 else if (srate <= 7000000)
1207 aclc_value = cllas2[i].car_loop_pilots_on_5;
1208 else if (srate <= 15000000)
1209 aclc_value = cllas2[i].car_loop_pilots_on_10;
1210 else if (srate <= 25000000)
1211 aclc_value = cllas2[i].car_loop_pilots_on_20;
1213 aclc_value = cllas2[i].car_loop_pilots_on_30;
1219 u8 stv0900_get_optim_short_carr_loop(s32 srate,
1220 enum fe_stv0900_modulation modulation,
1223 const struct stv0900_short_frames_car_loop_optim *s2scl;
1224 const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
1226 u8 aclc_value = 0x0b;
1228 dprintk("%s\n", __func__);
1230 s2scl = FE_STV0900_S2ShortCarLoop;
1231 s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
1233 switch (modulation) {
1241 case STV0900_16APSK:
1244 case STV0900_32APSK:
1249 if (chip_id >= 0x30) {
1250 if (srate <= 3000000)
1251 aclc_value = s2sclc30[mod_index].car_loop_2;
1252 else if (srate <= 7000000)
1253 aclc_value = s2sclc30[mod_index].car_loop_5;
1254 else if (srate <= 15000000)
1255 aclc_value = s2sclc30[mod_index].car_loop_10;
1256 else if (srate <= 25000000)
1257 aclc_value = s2sclc30[mod_index].car_loop_20;
1259 aclc_value = s2sclc30[mod_index].car_loop_30;
1261 } else if (chip_id >= 0x20) {
1262 if (srate <= 3000000)
1263 aclc_value = s2scl[mod_index].car_loop_cut20_2;
1264 else if (srate <= 7000000)
1265 aclc_value = s2scl[mod_index].car_loop_cut20_5;
1266 else if (srate <= 15000000)
1267 aclc_value = s2scl[mod_index].car_loop_cut20_10;
1268 else if (srate <= 25000000)
1269 aclc_value = s2scl[mod_index].car_loop_cut20_20;
1271 aclc_value = s2scl[mod_index].car_loop_cut20_30;
1274 if (srate <= 3000000)
1275 aclc_value = s2scl[mod_index].car_loop_cut12_2;
1276 else if (srate <= 7000000)
1277 aclc_value = s2scl[mod_index].car_loop_cut12_5;
1278 else if (srate <= 15000000)
1279 aclc_value = s2scl[mod_index].car_loop_cut12_10;
1280 else if (srate <= 25000000)
1281 aclc_value = s2scl[mod_index].car_loop_cut12_20;
1283 aclc_value = s2scl[mod_index].car_loop_cut12_30;
1291 enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
1292 enum fe_stv0900_demod_mode LDPC_Mode,
1293 enum fe_stv0900_demod_num demod)
1295 enum fe_stv0900_error error = STV0900_NO_ERROR;
1298 dprintk("%s\n", __func__);
1300 switch (LDPC_Mode) {
1303 if ((intp->demod_mode != STV0900_DUAL)
1304 || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
1305 stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
1307 intp->demod_mode = STV0900_DUAL;
1309 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1310 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1312 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1313 stv0900_write_reg(intp,
1314 R0900_P1_MODCODLST0 + reg_ind,
1316 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1317 stv0900_write_reg(intp,
1318 R0900_P1_MODCODLST7 + reg_ind,
1321 stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
1322 stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
1324 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1325 stv0900_write_reg(intp,
1326 R0900_P2_MODCODLST0 + reg_ind,
1328 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1329 stv0900_write_reg(intp,
1330 R0900_P2_MODCODLST7 + reg_ind,
1333 stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
1334 stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
1338 case STV0900_SINGLE:
1339 if (demod == STV0900_DEMOD_2) {
1340 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
1341 stv0900_activate_s2_modcod_single(intp,
1343 stv0900_write_reg(intp, R0900_GENCFG, 0x06);
1345 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
1346 stv0900_activate_s2_modcod_single(intp,
1348 stv0900_write_reg(intp, R0900_GENCFG, 0x04);
1351 intp->demod_mode = STV0900_SINGLE;
1353 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1354 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1355 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
1356 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
1357 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
1358 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
1365 static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1366 struct stv0900_init_params *p_init)
1368 struct stv0900_state *state = fe->demodulator_priv;
1369 enum fe_stv0900_error error = STV0900_NO_ERROR;
1370 enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1371 struct stv0900_internal *intp = NULL;
1374 struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1375 state->config->demod_address);
1377 dprintk("%s\n", __func__);
1379 if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
1380 state->internal = temp_int->internal;
1381 (state->internal->dmds_used)++;
1382 dprintk("%s: Find Internal Structure!\n", __func__);
1383 return STV0900_NO_ERROR;
1385 state->internal = kmalloc(sizeof(struct stv0900_internal),
1387 temp_int = append_internal(state->internal);
1388 state->internal->dmds_used = 1;
1389 state->internal->i2c_adap = state->i2c_adap;
1390 state->internal->i2c_addr = state->config->demod_address;
1391 state->internal->clkmode = state->config->clkmode;
1392 state->internal->errs = STV0900_NO_ERROR;
1393 dprintk("%s: Create New Internal Structure!\n", __func__);
1396 if (state->internal == NULL) {
1397 error = STV0900_INVALID_HANDLE;
1401 demodError = stv0900_initialize(state->internal);
1402 if (demodError == STV0900_NO_ERROR) {
1403 error = STV0900_NO_ERROR;
1405 if (demodError == STV0900_INVALID_HANDLE)
1406 error = STV0900_INVALID_HANDLE;
1408 error = STV0900_I2C_ERROR;
1413 if (state->internal == NULL) {
1414 error = STV0900_INVALID_HANDLE;
1418 intp = state->internal;
1420 intp->demod_mode = p_init->demod_mode;
1421 stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
1422 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
1423 intp->rolloff = p_init->rolloff;
1424 intp->quartz = p_init->dmd_ref_clk;
1426 stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1427 stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1429 intp->ts_config = p_init->ts_config;
1430 if (intp->ts_config == NULL)
1431 stv0900_set_ts_parallel_serial(intp,
1432 p_init->path1_ts_clock,
1433 p_init->path2_ts_clock);
1435 for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
1436 stv0900_write_reg(intp,
1437 intp->ts_config[i].addr,
1438 intp->ts_config[i].val);
1440 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
1441 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
1442 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
1443 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
1446 intp->tuner_type[0] = p_init->tuner1_type;
1447 intp->tuner_type[1] = p_init->tuner2_type;
1449 switch (p_init->tuner1_type) {
1450 case 3: /*FE_AUTO_STB6100:*/
1451 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c);
1452 stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86);
1453 stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18);
1454 stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */
1455 stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05);
1456 stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17);
1457 stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f);
1458 stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0);
1459 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3);
1461 /* case FE_SW_TUNER: */
1463 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6);
1467 stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1468 switch (p_init->tuner1_adc) {
1470 stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
1476 stv0900_write_reg(intp, R0900_P1_TNRLD, 1); /* hw tuner */
1479 switch (p_init->tuner2_type) {
1480 case 3: /*FE_AUTO_STB6100:*/
1481 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c);
1482 stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86);
1483 stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18);
1484 stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */
1485 stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05);
1486 stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17);
1487 stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f);
1488 stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0);
1489 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3);
1491 /* case FE_SW_TUNER: */
1493 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6);
1497 stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1498 switch (p_init->tuner2_adc) {
1500 stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
1506 stv0900_write_reg(intp, R0900_P2_TNRLD, 1); /* hw tuner */
1508 stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
1509 stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
1510 stv0900_set_mclk(intp, 135000000);
1513 switch (intp->clkmode) {
1516 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
1519 selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
1520 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
1525 intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
1527 error = STV0900_I2C_ERROR;
1532 static int stv0900_status(struct stv0900_internal *intp,
1533 enum fe_stv0900_demod_num demod)
1535 enum fe_stv0900_search_state demod_state;
1537 u8 tsbitrate0_val, tsbitrate1_val;
1540 demod_state = stv0900_get_bits(intp, HEADER_MODE);
1541 switch (demod_state) {
1542 case STV0900_SEARCH:
1543 case STV0900_PLH_DETECTED:
1547 case STV0900_DVBS2_FOUND:
1548 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1549 stv0900_get_bits(intp, PKTDELIN_LOCK) &&
1550 stv0900_get_bits(intp, TSFIFO_LINEOK);
1552 case STV0900_DVBS_FOUND:
1553 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1554 stv0900_get_bits(intp, LOCKEDVIT) &&
1555 stv0900_get_bits(intp, TSFIFO_LINEOK);
1559 dprintk("%s: locked = %d\n", __func__, locked);
1562 /* Print TS bitrate */
1563 tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0);
1564 tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1);
1565 /* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */
1566 bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
1567 * (tsbitrate1_val << 8 | tsbitrate0_val);
1569 dprintk("TS bitrate = %d Mbit/sec \n", bitrate);
1575 static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1576 struct dvb_frontend_parameters *params)
1578 struct stv0900_state *state = fe->demodulator_priv;
1579 struct stv0900_internal *intp = state->internal;
1580 enum fe_stv0900_demod_num demod = state->demod;
1581 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1583 struct stv0900_search_params p_search;
1584 struct stv0900_signal_info p_result;
1586 enum fe_stv0900_error error = STV0900_NO_ERROR;
1588 dprintk("%s: ", __func__);
1590 if (!(INRANGE(100000, c->symbol_rate, 70000000)))
1591 return DVBFE_ALGO_SEARCH_FAILED;
1593 if (state->config->set_ts_params)
1594 state->config->set_ts_params(fe, 0);
1596 p_result.locked = FALSE;
1597 p_search.path = demod;
1598 p_search.frequency = c->frequency;
1599 p_search.symbol_rate = c->symbol_rate;
1600 p_search.search_range = 10000000;
1601 p_search.fec = STV0900_FEC_UNKNOWN;
1602 p_search.standard = STV0900_AUTO_SEARCH;
1603 p_search.iq_inversion = STV0900_IQ_AUTO;
1604 p_search.search_algo = STV0900_BLIND_SEARCH;
1606 intp->srch_standard[demod] = p_search.standard;
1607 intp->symbol_rate[demod] = p_search.symbol_rate;
1608 intp->srch_range[demod] = p_search.search_range;
1609 intp->freq[demod] = p_search.frequency;
1610 intp->srch_algo[demod] = p_search.search_algo;
1611 intp->srch_iq_inv[demod] = p_search.iq_inversion;
1612 intp->fec[demod] = p_search.fec;
1613 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1614 (intp->errs == STV0900_NO_ERROR)) {
1615 p_result.locked = intp->result[demod].locked;
1616 p_result.standard = intp->result[demod].standard;
1617 p_result.frequency = intp->result[demod].frequency;
1618 p_result.symbol_rate = intp->result[demod].symbol_rate;
1619 p_result.fec = intp->result[demod].fec;
1620 p_result.modcode = intp->result[demod].modcode;
1621 p_result.pilot = intp->result[demod].pilot;
1622 p_result.frame_len = intp->result[demod].frame_len;
1623 p_result.spectrum = intp->result[demod].spectrum;
1624 p_result.rolloff = intp->result[demod].rolloff;
1625 p_result.modulation = intp->result[demod].modulation;
1627 p_result.locked = FALSE;
1628 switch (intp->err[demod]) {
1629 case STV0900_I2C_ERROR:
1630 error = STV0900_I2C_ERROR;
1632 case STV0900_NO_ERROR:
1634 error = STV0900_SEARCH_FAILED;
1639 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1640 dprintk("Search Success\n");
1641 return DVBFE_ALGO_SEARCH_SUCCESS;
1643 dprintk("Search Fail\n");
1644 return DVBFE_ALGO_SEARCH_FAILED;
1649 static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1651 struct stv0900_state *state = fe->demodulator_priv;
1653 dprintk("%s: ", __func__);
1655 if ((stv0900_status(state->internal, state->demod)) == TRUE) {
1656 dprintk("DEMOD LOCK OK\n");
1657 *status = FE_HAS_CARRIER
1662 dprintk("DEMOD LOCK FAIL\n");
1667 static int stv0900_track(struct dvb_frontend *fe,
1668 struct dvb_frontend_parameters *p)
1673 static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1676 struct stv0900_state *state = fe->demodulator_priv;
1677 struct stv0900_internal *intp = state->internal;
1678 enum fe_stv0900_demod_num demod = state->demod;
1680 if (stop_ts == TRUE)
1681 stv0900_write_bits(intp, RST_HWARE, 1);
1683 stv0900_write_bits(intp, RST_HWARE, 0);
1688 static int stv0900_diseqc_init(struct dvb_frontend *fe)
1690 struct stv0900_state *state = fe->demodulator_priv;
1691 struct stv0900_internal *intp = state->internal;
1692 enum fe_stv0900_demod_num demod = state->demod;
1694 stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
1695 stv0900_write_bits(intp, DISEQC_RESET, 1);
1696 stv0900_write_bits(intp, DISEQC_RESET, 0);
1701 static int stv0900_init(struct dvb_frontend *fe)
1703 dprintk("%s\n", __func__);
1705 stv0900_stop_ts(fe, 1);
1706 stv0900_diseqc_init(fe);
1711 static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
1712 u32 NbData, enum fe_stv0900_demod_num demod)
1716 stv0900_write_bits(intp, DIS_PRECHARGE, 1);
1717 while (i < NbData) {
1718 while (stv0900_get_bits(intp, FIFO_FULL))
1719 ;/* checkpatch complains */
1720 stv0900_write_reg(intp, DISTXDATA, data[i]);
1724 stv0900_write_bits(intp, DIS_PRECHARGE, 0);
1726 while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
1734 static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1735 struct dvb_diseqc_master_cmd *cmd)
1737 struct stv0900_state *state = fe->demodulator_priv;
1739 return stv0900_diseqc_send(state->internal,
1745 static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1747 struct stv0900_state *state = fe->demodulator_priv;
1748 struct stv0900_internal *intp = state->internal;
1749 enum fe_stv0900_demod_num demod = state->demod;
1755 stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
1757 stv0900_diseqc_send(intp, &data, 1, state->demod);
1760 stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
1762 stv0900_diseqc_send(intp, &data, 1, state->demod);
1769 static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1770 struct dvb_diseqc_slave_reply *reply)
1772 struct stv0900_state *state = fe->demodulator_priv;
1773 struct stv0900_internal *intp = state->internal;
1774 enum fe_stv0900_demod_num demod = state->demod;
1779 while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
1784 if (stv0900_get_bits(intp, RX_END)) {
1785 reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
1787 for (i = 0; i < reply->msg_len; i++)
1788 reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
1794 static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
1796 struct stv0900_state *state = fe->demodulator_priv;
1797 struct stv0900_internal *intp = state->internal;
1798 enum fe_stv0900_demod_num demod = state->demod;
1800 dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
1804 /*Set the DiseqC mode to 22Khz _continues_ tone*/
1805 stv0900_write_bits(intp, DISTX_MODE, 0);
1806 stv0900_write_bits(intp, DISEQC_RESET, 1);
1807 /*release DiseqC reset to enable the 22KHz tone*/
1808 stv0900_write_bits(intp, DISEQC_RESET, 0);
1811 /*return diseqc mode to config->diseqc_mode.
1812 Usually it's without _continues_ tone */
1813 stv0900_write_bits(intp, DISTX_MODE,
1814 state->config->diseqc_mode);
1815 /*maintain the DiseqC reset to disable the 22KHz tone*/
1816 stv0900_write_bits(intp, DISEQC_RESET, 1);
1817 stv0900_write_bits(intp, DISEQC_RESET, 0);
1826 static void stv0900_release(struct dvb_frontend *fe)
1828 struct stv0900_state *state = fe->demodulator_priv;
1830 dprintk("%s\n", __func__);
1832 if ((--(state->internal->dmds_used)) <= 0) {
1834 dprintk("%s: Actually removing\n", __func__);
1836 remove_inode(state->internal);
1837 kfree(state->internal);
1843 static struct dvb_frontend_ops stv0900_ops = {
1846 .name = "STV0900 frontend",
1848 .frequency_min = 950000,
1849 .frequency_max = 2150000,
1850 .frequency_stepsize = 125,
1851 .frequency_tolerance = 0,
1852 .symbol_rate_min = 1000000,
1853 .symbol_rate_max = 45000000,
1854 .symbol_rate_tolerance = 500,
1855 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1856 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1857 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1858 FE_CAN_2G_MODULATION |
1861 .release = stv0900_release,
1862 .init = stv0900_init,
1863 .get_frontend_algo = stv0900_frontend_algo,
1864 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
1865 .diseqc_send_master_cmd = stv0900_send_master_cmd,
1866 .diseqc_send_burst = stv0900_send_burst,
1867 .diseqc_recv_slave_reply = stv0900_recv_slave_reply,
1868 .set_tone = stv0900_set_tone,
1869 .set_property = stb0900_set_property,
1870 .get_property = stb0900_get_property,
1871 .search = stv0900_search,
1872 .track = stv0900_track,
1873 .read_status = stv0900_read_status,
1874 .read_ber = stv0900_read_ber,
1875 .read_signal_strength = stv0900_read_signal_strength,
1876 .read_snr = stv0900_read_snr,
1877 .read_ucblocks = stv0900_read_ucblocks,
1880 struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1881 struct i2c_adapter *i2c,
1884 struct stv0900_state *state = NULL;
1885 struct stv0900_init_params init_params;
1886 enum fe_stv0900_error err_stv0900;
1888 state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
1892 state->demod = demod;
1893 state->config = config;
1894 state->i2c_adap = i2c;
1896 memcpy(&state->frontend.ops, &stv0900_ops,
1897 sizeof(struct dvb_frontend_ops));
1898 state->frontend.demodulator_priv = state;
1903 init_params.dmd_ref_clk = config->xtal;
1904 init_params.demod_mode = config->demod_mode;
1905 init_params.rolloff = STV0900_35;
1906 init_params.path1_ts_clock = config->path1_mode;
1907 init_params.tun1_maddress = config->tun1_maddress;
1908 init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
1909 init_params.tuner1_adc = config->tun1_adc;
1910 init_params.tuner1_type = config->tun1_type;
1911 init_params.path2_ts_clock = config->path2_mode;
1912 init_params.ts_config = config->ts_config_regs;
1913 init_params.tun2_maddress = config->tun2_maddress;
1914 init_params.tuner2_adc = config->tun2_adc;
1915 init_params.tuner2_type = config->tun2_type;
1916 init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
1918 err_stv0900 = stv0900_init_internal(&state->frontend,
1930 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
1931 return &state->frontend;
1934 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
1939 EXPORT_SYMBOL(stv0900_attach);
1941 MODULE_PARM_DESC(debug, "Set debug");
1943 MODULE_AUTHOR("Igor M. Liplianin");
1944 MODULE_DESCRIPTION("ST STV0900 frontend");
1945 MODULE_LICENSE("GPL");