4 * Driver for ST STV0900 satellite demodulator IC.
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include "stv0900_reg.h"
28 #include "stv0900_priv.h"
30 s32 shiftx(s32 x, int demod, s32 shift)
38 int stv0900_check_signal_presence(struct stv0900_internal *intp,
39 enum fe_stv0900_demod_num demod)
45 int no_signal = FALSE;
47 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
48 | stv0900_read_reg(intp, CFR1);
49 carr_offset = ge2comp(carr_offset, 16);
50 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
51 | stv0900_read_reg(intp, AGC2I0);
52 max_carrier = intp->srch_range[demod] / 1000;
54 max_carrier += (max_carrier / 10);
55 max_carrier = 65536 * (max_carrier / 2);
56 max_carrier /= intp->mclk / 1000;
57 if (max_carrier > 0x4000)
60 if ((agc2_integr > 0x2000)
61 || (carr_offset > (2 * max_carrier))
62 || (carr_offset < (-2 * max_carrier)))
68 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
69 s32 *frequency_inc, s32 *sw_timeout,
71 enum fe_stv0900_demod_num demod)
73 s32 timeout, freq_inc, max_steps, srate, max_carrier;
75 enum fe_stv0900_search_standard standard;
77 srate = intp->symbol_rate[demod];
78 max_carrier = intp->srch_range[demod] / 1000;
79 max_carrier += max_carrier / 10;
80 standard = intp->srch_standard[demod];
82 max_carrier = 65536 * (max_carrier / 2);
83 max_carrier /= intp->mclk / 1000;
85 if (max_carrier > 0x4000)
89 freq_inc /= intp->mclk >> 10;
90 freq_inc = freq_inc << 6;
93 case STV0900_SEARCH_DVBS1:
94 case STV0900_SEARCH_DSS:
98 case STV0900_SEARCH_DVBS2:
102 case STV0900_AUTO_SEARCH:
111 if ((freq_inc > max_carrier) || (freq_inc < 0))
112 freq_inc = max_carrier / 2;
117 timeout /= srate / 1000;
119 if ((timeout > 100) || (timeout < 0))
122 max_steps = (max_carrier / freq_inc) + 1;
124 if ((max_steps > 100) || (max_steps < 0)) {
126 freq_inc = max_carrier / max_steps;
129 *frequency_inc = freq_inc;
130 *sw_timeout = timeout;
135 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
136 s32 FreqIncr, s32 Timeout, int zigzag,
137 s32 MaxStep, enum fe_stv0900_demod_num demod)
145 max_carrier = intp->srch_range[demod] / 1000;
146 max_carrier += (max_carrier / 10);
148 max_carrier = 65536 * (max_carrier / 2);
149 max_carrier /= intp->mclk / 1000;
151 if (max_carrier > 0x4000)
152 max_carrier = 0x4000;
157 freqOffset = -max_carrier + FreqIncr;
162 stv0900_write_reg(intp, DMDISTATE, 0x1c);
163 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
164 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
165 stv0900_write_reg(intp, DMDISTATE, 0x18);
166 stv0900_write_bits(intp, ALGOSWRST, 1);
168 if (intp->chip_id == 0x12) {
169 stv0900_write_bits(intp, RST_HWARE, 1);
170 stv0900_write_bits(intp, RST_HWARE, 0);
173 if (zigzag == TRUE) {
175 freqOffset = -freqOffset - 2 * FreqIncr;
177 freqOffset = -freqOffset;
179 freqOffset += + 2 * FreqIncr;
182 lock = stv0900_get_demod_lock(intp, demod, Timeout);
183 no_signal = stv0900_check_signal_presence(intp, demod);
185 } while ((lock == FALSE)
186 && (no_signal == FALSE)
187 && ((freqOffset - FreqIncr) < max_carrier)
188 && ((freqOffset + FreqIncr) > -max_carrier)
189 && (stepCpt < MaxStep));
191 stv0900_write_bits(intp, ALGOSWRST, 0);
196 static int stv0900_sw_algo(struct stv0900_internal *intp,
197 enum fe_stv0900_demod_num demod)
208 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
210 switch (intp->srch_standard[demod]) {
211 case STV0900_SEARCH_DVBS1:
212 case STV0900_SEARCH_DSS:
213 if (intp->chip_id >= 0x20)
214 stv0900_write_reg(intp, CARFREQ, 0x3b);
216 stv0900_write_reg(intp, CARFREQ, 0xef);
218 stv0900_write_reg(intp, DMDCFGMD, 0x49);
221 case STV0900_SEARCH_DVBS2:
222 if (intp->chip_id >= 0x20)
223 stv0900_write_reg(intp, CORRELABS, 0x79);
225 stv0900_write_reg(intp, CORRELABS, 0x68);
227 stv0900_write_reg(intp, DMDCFGMD, 0x89);
231 case STV0900_AUTO_SEARCH:
233 if (intp->chip_id >= 0x20) {
234 stv0900_write_reg(intp, CARFREQ, 0x3b);
235 stv0900_write_reg(intp, CORRELABS, 0x79);
237 stv0900_write_reg(intp, CARFREQ, 0xef);
238 stv0900_write_reg(intp, CORRELABS, 0x68);
241 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
248 lock = stv0900_search_carr_sw_loop(intp,
254 no_signal = stv0900_check_signal_presence(intp, demod);
257 || (no_signal == TRUE)
258 || (trial_cntr == 2)) {
260 if (intp->chip_id >= 0x20) {
261 stv0900_write_reg(intp, CARFREQ, 0x49);
262 stv0900_write_reg(intp, CORRELABS, 0x9e);
264 stv0900_write_reg(intp, CARFREQ, 0xed);
265 stv0900_write_reg(intp, CORRELABS, 0x88);
268 if ((stv0900_get_bits(intp, HEADER_MODE) ==
269 STV0900_DVBS2_FOUND) &&
271 msleep(sft_stp_tout);
272 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
275 msleep(sft_stp_tout);
276 s2fw = stv0900_get_bits(intp,
283 if (trial_cntr < 2) {
284 if (intp->chip_id >= 0x20)
285 stv0900_write_reg(intp,
289 stv0900_write_reg(intp,
293 stv0900_write_reg(intp,
301 } while ((lock == FALSE)
303 && (no_signal == FALSE));
308 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
310 enum fe_stv0900_demod_num demod)
312 s32 rem1, rem2, intval1, intval2, srate;
314 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
315 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
316 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
317 (stv0900_get_bits(intp, SYMB_FREQ0));
318 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
319 srate, stv0900_get_bits(intp, SYMB_FREQ0),
320 stv0900_get_bits(intp, SYMB_FREQ1),
321 stv0900_get_bits(intp, SYMB_FREQ2),
322 stv0900_get_bits(intp, SYMB_FREQ3));
324 intval1 = (mclk) >> 16;
325 intval2 = (srate) >> 16;
327 rem1 = (mclk) % 0x10000;
328 rem2 = (srate) % 0x10000;
329 srate = (intval1 * intval2) +
330 ((intval1 * rem2) >> 16) +
331 ((intval2 * rem1) >> 16);
336 static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
338 enum fe_stv0900_demod_num demod)
342 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
345 if (srate > 60000000) {
347 symb /= (mclk >> 12);
348 } else if (srate > 6000000) {
350 symb /= (mclk >> 10);
356 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
357 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
360 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
362 enum fe_stv0900_demod_num demod)
366 srate = 105 * (srate / 100);
368 if (srate > 60000000) {
370 symb /= (mclk >> 12);
371 } else if (srate > 6000000) {
373 symb /= (mclk >> 10);
380 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
381 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
383 stv0900_write_reg(intp, SFRUP1, 0x7f);
384 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
388 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
390 enum fe_stv0900_demod_num demod)
394 srate = 95 * (srate / 100);
395 if (srate > 60000000) {
397 symb /= (mclk >> 12);
399 } else if (srate > 6000000) {
401 symb /= (mclk >> 10);
408 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
409 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
412 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
414 enum fe_stv0900_demod_num demod)
419 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
420 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
421 (stv0900_read_reg(intp, TMGREG2 + 2));
423 timingoffset = ge2comp(timingoffset, 24);
426 if (timingoffset == 0)
429 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
435 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
436 enum fe_stv0900_demod_num demod)
440 if (intp->chip_id == 0x10) {
441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
442 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
443 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
444 } else if (intp->chip_id <= 0x20)
445 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
447 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
450 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
467 return srate + (srate * rolloff) / 100;
470 static int stv0900_check_timing_lock(struct stv0900_internal *intp,
471 enum fe_stv0900_demod_num demod)
473 int timingLock = FALSE;
480 car_freq = stv0900_read_reg(intp, CARFREQ);
481 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
482 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
483 stv0900_write_reg(intp, TMGTHRISE, 0x20);
484 stv0900_write_reg(intp, TMGTHFALL, 0x0);
485 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
486 stv0900_write_reg(intp, RTC, 0x80);
487 stv0900_write_reg(intp, RTCS2, 0x40);
488 stv0900_write_reg(intp, CARFREQ, 0x0);
489 stv0900_write_reg(intp, CFRINIT1, 0x0);
490 stv0900_write_reg(intp, CFRINIT0, 0x0);
491 stv0900_write_reg(intp, AGC2REF, 0x65);
492 stv0900_write_reg(intp, DMDISTATE, 0x18);
495 for (i = 0; i < 10; i++) {
496 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
505 stv0900_write_reg(intp, AGC2REF, 0x38);
506 stv0900_write_reg(intp, RTC, 0x88);
507 stv0900_write_reg(intp, RTCS2, 0x68);
508 stv0900_write_reg(intp, CARFREQ, car_freq);
509 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
510 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
515 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
518 struct stv0900_state *state = fe->demodulator_priv;
519 struct stv0900_internal *intp = state->internal;
520 enum fe_stv0900_demod_num demod = state->demod;
534 srate = intp->symbol_rate[d];
535 search_range = intp->srch_range[d];
537 if (srate >= 10000000)
538 locktimeout = demod_timeout / 3;
540 locktimeout = demod_timeout / 2;
542 lock = stv0900_get_demod_lock(intp, d, locktimeout);
547 if (srate >= 10000000) {
548 if (stv0900_check_timing_lock(intp, d) == TRUE) {
549 stv0900_write_reg(intp, DMDISTATE, 0x1f);
550 stv0900_write_reg(intp, DMDISTATE, 0x15);
551 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
558 if (intp->chip_id <= 0x20) {
559 if (srate <= 1000000)
561 else if (srate <= 4000000)
563 else if (srate <= 7000000)
565 else if (srate <= 10000000)
570 if (srate >= 2000000) {
571 timeout = (demod_timeout / 3);
575 timeout = (demod_timeout / 2);
578 currier_step = srate / 4000;
579 timeout = (demod_timeout * 3) / 4;
582 nb_steps = ((search_range / 1000) / currier_step);
584 if ((nb_steps % 2) != 0)
589 else if (nb_steps > 12)
595 if (intp->chip_id <= 0x20) {
596 tuner_freq = intp->freq[d];
597 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
598 intp->rolloff) + intp->symbol_rate[d];
602 while ((current_step <= nb_steps) && (lock == FALSE)) {
604 tuner_freq += (current_step * currier_step);
606 tuner_freq -= (current_step * currier_step);
608 if (intp->chip_id <= 0x20) {
609 if (intp->tuner_type[d] == 3)
610 stv0900_set_tuner_auto(intp, tuner_freq,
613 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
615 stv0900_write_reg(intp, DMDISTATE, 0x1c);
616 stv0900_write_reg(intp, CFRINIT1, 0);
617 stv0900_write_reg(intp, CFRINIT0, 0);
618 stv0900_write_reg(intp, DMDISTATE, 0x1f);
619 stv0900_write_reg(intp, DMDISTATE, 0x15);
621 stv0900_write_reg(intp, DMDISTATE, 0x1c);
622 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
623 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
624 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
625 stv0900_write_reg(intp, DMDISTATE, 0x1f);
626 stv0900_write_reg(intp, DMDISTATE, 0x05);
629 lock = stv0900_get_demod_lock(intp, d, timeout);
637 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
639 enum fe_stv0900_search_algo algo)
642 case STV0900_BLIND_SEARCH:
643 if (srate <= 1500000) {
644 (*demod_timeout) = 1500;
645 (*fec_timeout) = 400;
646 } else if (srate <= 5000000) {
647 (*demod_timeout) = 1000;
648 (*fec_timeout) = 300;
650 (*demod_timeout) = 700;
651 (*fec_timeout) = 100;
655 case STV0900_COLD_START:
656 case STV0900_WARM_START:
658 if (srate <= 1000000) {
659 (*demod_timeout) = 3000;
660 (*fec_timeout) = 1700;
661 } else if (srate <= 2000000) {
662 (*demod_timeout) = 2500;
663 (*fec_timeout) = 1100;
664 } else if (srate <= 5000000) {
665 (*demod_timeout) = 1000;
666 (*fec_timeout) = 550;
667 } else if (srate <= 10000000) {
668 (*demod_timeout) = 700;
669 (*fec_timeout) = 250;
670 } else if (srate <= 20000000) {
671 (*demod_timeout) = 400;
672 (*fec_timeout) = 130;
674 (*demod_timeout) = 300;
675 (*fec_timeout) = 100;
682 if (algo == STV0900_WARM_START)
683 (*demod_timeout) /= 2;
686 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
687 enum fe_stv0900_demod_num demod)
692 dprintk("%s\n", __func__);
694 stv0900_write_reg(intp, vth_reg++, 0xd0);
695 stv0900_write_reg(intp, vth_reg++, 0x7d);
696 stv0900_write_reg(intp, vth_reg++, 0x53);
697 stv0900_write_reg(intp, vth_reg++, 0x2f);
698 stv0900_write_reg(intp, vth_reg++, 0x24);
699 stv0900_write_reg(intp, vth_reg++, 0x1f);
702 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
703 enum fe_stv0900_search_standard standard,
704 enum fe_stv0900_fec fec,
705 enum fe_stv0900_demod_num demod)
707 dprintk("%s: ViterbiStandard = ", __func__);
710 case STV0900_AUTO_SEARCH:
712 stv0900_write_reg(intp, FECM, 0x10);
713 stv0900_write_reg(intp, PRVIT, 0x3f);
715 case STV0900_SEARCH_DVBS1:
717 stv0900_write_reg(intp, FECM, 0x00);
719 case STV0900_FEC_UNKNOWN:
721 stv0900_write_reg(intp, PRVIT, 0x2f);
723 case STV0900_FEC_1_2:
724 stv0900_write_reg(intp, PRVIT, 0x01);
726 case STV0900_FEC_2_3:
727 stv0900_write_reg(intp, PRVIT, 0x02);
729 case STV0900_FEC_3_4:
730 stv0900_write_reg(intp, PRVIT, 0x04);
732 case STV0900_FEC_5_6:
733 stv0900_write_reg(intp, PRVIT, 0x08);
735 case STV0900_FEC_7_8:
736 stv0900_write_reg(intp, PRVIT, 0x20);
741 case STV0900_SEARCH_DSS:
743 stv0900_write_reg(intp, FECM, 0x80);
745 case STV0900_FEC_UNKNOWN:
747 stv0900_write_reg(intp, PRVIT, 0x13);
749 case STV0900_FEC_1_2:
750 stv0900_write_reg(intp, PRVIT, 0x01);
752 case STV0900_FEC_2_3:
753 stv0900_write_reg(intp, PRVIT, 0x02);
755 case STV0900_FEC_6_7:
756 stv0900_write_reg(intp, PRVIT, 0x10);
765 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
766 enum fe_stv0900_demod_num demod)
768 enum fe_stv0900_fec prate;
769 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
773 prate = STV0900_FEC_1_2;
776 prate = STV0900_FEC_2_3;
779 prate = STV0900_FEC_3_4;
782 prate = STV0900_FEC_5_6;
785 prate = STV0900_FEC_6_7;
788 prate = STV0900_FEC_7_8;
791 prate = STV0900_FEC_UNKNOWN;
798 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
799 enum fe_stv0900_demod_num demod,
802 if (intp->chip_id >= 0x30) {
803 if (srate >= 15000000) {
804 stv0900_write_reg(intp, ACLC, 0x2b);
805 stv0900_write_reg(intp, BCLC, 0x1a);
806 } else if ((srate >= 7000000) && (15000000 > srate)) {
807 stv0900_write_reg(intp, ACLC, 0x0c);
808 stv0900_write_reg(intp, BCLC, 0x1b);
809 } else if (srate < 7000000) {
810 stv0900_write_reg(intp, ACLC, 0x2c);
811 stv0900_write_reg(intp, BCLC, 0x1c);
814 } else { /*cut 2.0 and 1.x*/
815 stv0900_write_reg(intp, ACLC, 0x1a);
816 stv0900_write_reg(intp, BCLC, 0x09);
821 static void stv0900_track_optimization(struct dvb_frontend *fe)
823 struct stv0900_state *state = fe->demodulator_priv;
824 struct stv0900_internal *intp = state->internal;
825 enum fe_stv0900_demod_num demod = state->demod;
838 enum fe_stv0900_rolloff rolloff;
839 enum fe_stv0900_modcode foundModcod;
841 dprintk("%s\n", __func__);
843 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
844 srate += stv0900_get_timing_offst(intp, srate, demod);
846 switch (intp->result[demod].standard) {
847 case STV0900_DVBS1_STANDARD:
848 case STV0900_DSS_STANDARD:
849 dprintk("%s: found DVB-S or DSS\n", __func__);
850 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
851 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
852 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
855 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
856 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
858 if (intp->chip_id < 0x30) {
859 stv0900_write_reg(intp, ERRCTRL1, 0x75);
863 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
864 stv0900_write_reg(intp, GAUSSR0, 0x98);
865 stv0900_write_reg(intp, CCIR0, 0x18);
867 stv0900_write_reg(intp, GAUSSR0, 0x18);
868 stv0900_write_reg(intp, CCIR0, 0x18);
871 stv0900_write_reg(intp, ERRCTRL1, 0x75);
873 case STV0900_DVBS2_STANDARD:
874 dprintk("%s: found DVB-S2\n", __func__);
875 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
876 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
877 stv0900_write_reg(intp, ACLC, 0);
878 stv0900_write_reg(intp, BCLC, 0);
879 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
880 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
881 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
882 aclc = stv0900_get_optim_carr_loop(srate,
886 if (foundModcod <= STV0900_QPSK_910)
887 stv0900_write_reg(intp, ACLC2S2Q, aclc);
888 else if (foundModcod <= STV0900_8PSK_910) {
889 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
890 stv0900_write_reg(intp, ACLC2S28, aclc);
893 if ((intp->demod_mode == STV0900_SINGLE) &&
894 (foundModcod > STV0900_8PSK_910)) {
895 if (foundModcod <= STV0900_16APSK_910) {
896 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
897 stv0900_write_reg(intp, ACLC2S216A,
899 } else if (foundModcod <= STV0900_32APSK_910) {
900 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
901 stv0900_write_reg(intp, ACLC2S232A,
907 modulation = intp->result[demod].modulation;
908 aclc = stv0900_get_optim_short_carr_loop(srate,
909 modulation, intp->chip_id);
910 if (modulation == STV0900_QPSK)
911 stv0900_write_reg(intp, ACLC2S2Q, aclc);
912 else if (modulation == STV0900_8PSK) {
913 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
914 stv0900_write_reg(intp, ACLC2S28, aclc);
915 } else if (modulation == STV0900_16APSK) {
916 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
917 stv0900_write_reg(intp, ACLC2S216A, aclc);
918 } else if (modulation == STV0900_32APSK) {
919 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
920 stv0900_write_reg(intp, ACLC2S232A, aclc);
925 if (intp->chip_id <= 0x11) {
926 if (intp->demod_mode != STV0900_SINGLE)
927 stv0900_activate_s2_modcod(intp, demod);
931 stv0900_write_reg(intp, ERRCTRL1, 0x67);
933 case STV0900_UNKNOWN_STANDARD:
935 dprintk("%s: found unknown standard\n", __func__);
936 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
937 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
941 freq1 = stv0900_read_reg(intp, CFR2);
942 freq0 = stv0900_read_reg(intp, CFR1);
943 rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
944 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
945 stv0900_write_reg(intp, SFRSTEP, 0x00);
946 stv0900_write_bits(intp, SCAN_ENABLE, 0);
947 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
948 stv0900_write_reg(intp, TMGCFG2, 0xc1);
949 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
951 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
952 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
956 if (intp->chip_id >= 0x20) {
957 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
958 (intp->srch_standard[demod] ==
959 STV0900_SEARCH_DSS) ||
960 (intp->srch_standard[demod] ==
961 STV0900_AUTO_SEARCH)) {
962 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
963 stv0900_write_reg(intp, VITSCALE, 0x0);
967 if (intp->chip_id < 0x20)
968 stv0900_write_reg(intp, CARHDR, 0x08);
970 if (intp->chip_id == 0x10)
971 stv0900_write_reg(intp, CORRELEXP, 0x0a);
973 stv0900_write_reg(intp, AGC2REF, 0x38);
975 if ((intp->chip_id >= 0x20) ||
976 (blind_tun_sw == 1) ||
977 (intp->symbol_rate[demod] < 10000000)) {
978 stv0900_write_reg(intp, CFRINIT1, freq1);
979 stv0900_write_reg(intp, CFRINIT0, freq0);
980 intp->bw[demod] = stv0900_carrier_width(srate,
981 intp->rolloff) + 10000000;
983 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
984 if (intp->srch_algo[demod] != STV0900_WARM_START) {
985 if (intp->tuner_type[demod] == 3)
986 stv0900_set_tuner_auto(intp,
991 stv0900_set_bandwidth(fe,
996 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
997 (intp->symbol_rate[demod] < 10000000))
1002 stv0900_get_lock_timeout(&timed, &timef, srate,
1003 STV0900_WARM_START);
1005 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
1006 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1007 stv0900_write_reg(intp, CFRINIT1, freq1);
1008 stv0900_write_reg(intp, CFRINIT0, freq0);
1009 stv0900_write_reg(intp, DMDISTATE, 0x18);
1011 while ((stv0900_get_demod_lock(intp,
1013 timed / 2) == FALSE) &&
1015 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1016 stv0900_write_reg(intp, CFRINIT1, freq1);
1017 stv0900_write_reg(intp, CFRINIT0, freq0);
1018 stv0900_write_reg(intp, DMDISTATE, 0x18);
1025 if (intp->chip_id >= 0x20)
1026 stv0900_write_reg(intp, CARFREQ, 0x49);
1028 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1029 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1030 stv0900_set_viterbi_tracq(intp, demod);
1034 static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1035 enum fe_stv0900_demod_num demod, s32 time_out)
1037 s32 timer = 0, lock = 0;
1039 enum fe_stv0900_search_state dmd_state;
1041 dprintk("%s\n", __func__);
1043 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1045 while ((timer < time_out) && (lock == 0)) {
1046 switch (dmd_state) {
1047 case STV0900_SEARCH:
1048 case STV0900_PLH_DETECTED:
1052 case STV0900_DVBS2_FOUND:
1053 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1055 case STV0900_DVBS_FOUND:
1056 lock = stv0900_get_bits(intp, LOCKEDVIT);
1067 dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1069 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1074 static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1075 enum fe_stv0900_demod_num demod,
1076 s32 dmd_timeout, s32 fec_timeout)
1079 s32 timer = 0, lock = 0;
1081 dprintk("%s\n", __func__);
1083 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1086 lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
1091 dprintk("%s: Timer = %d, time_out = %d\n",
1092 __func__, timer, fec_timeout);
1094 while ((timer < fec_timeout) && (lock == 0)) {
1095 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1102 dprintk("%s: DEMOD LOCK OK\n", __func__);
1104 dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1112 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1113 enum fe_stv0900_demod_num demod)
1115 struct stv0900_state *state = fe->demodulator_priv;
1116 struct stv0900_internal *intp = state->internal;
1117 enum fe_stv0900_tracking_standard fnd_standard;
1119 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1123 fnd_standard = STV0900_DVBS2_STANDARD;
1126 if (stv0900_get_bits(intp, DSS_DVB) == 1)
1127 fnd_standard = STV0900_DSS_STANDARD;
1129 fnd_standard = STV0900_DVBS1_STANDARD;
1133 fnd_standard = STV0900_UNKNOWN_STANDARD;
1136 dprintk("%s: standard %d\n", __func__, fnd_standard);
1138 return fnd_standard;
1141 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1142 enum fe_stv0900_demod_num demod)
1150 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1151 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1152 (stv0900_get_bits(intp, CAR_FREQ0));
1154 derot = ge2comp(derot, 24);
1155 intval1 = mclk >> 12;
1156 intval2 = derot >> 12;
1157 rem1 = mclk % 0x1000;
1158 rem2 = derot % 0x1000;
1159 derot = (intval1 * intval2) +
1160 ((intval1 * rem2) >> 12) +
1161 ((intval2 * rem1) >> 12);
1166 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1168 struct dvb_frontend_ops *frontend_ops = NULL;
1169 struct dvb_tuner_ops *tuner_ops = NULL;
1173 frontend_ops = &fe->ops;
1175 if (&frontend_ops->tuner_ops)
1176 tuner_ops = &frontend_ops->tuner_ops;
1178 if (tuner_ops->get_frequency) {
1179 if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1180 dprintk("%s: Invalid parameter\n", __func__);
1182 dprintk("%s: Frequency=%d\n", __func__, freq);
1190 fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1192 struct stv0900_state *state = fe->demodulator_priv;
1193 struct stv0900_internal *intp = state->internal;
1194 enum fe_stv0900_demod_num demod = state->demod;
1195 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1196 struct stv0900_signal_info *result = &intp->result[demod];
1205 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1206 timing = stv0900_read_reg(intp, TMGREG2);
1208 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1210 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1211 timing = stv0900_read_reg(intp, TMGREG2);
1217 result->standard = stv0900_get_standard(fe, d);
1218 if (intp->tuner_type[demod] == 3)
1219 result->frequency = stv0900_get_freq_auto(intp, d);
1221 result->frequency = stv0900_get_tuner_freq(fe);
1223 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1224 result->frequency += offsetFreq;
1225 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1226 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1227 result->symbol_rate += srate_offset;
1228 result->fec = stv0900_get_vit_fec(intp, d);
1229 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1230 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1231 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1232 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1234 dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
1236 switch (result->standard) {
1237 case STV0900_DVBS2_STANDARD:
1238 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1239 if (result->modcode <= STV0900_QPSK_910)
1240 result->modulation = STV0900_QPSK;
1241 else if (result->modcode <= STV0900_8PSK_910)
1242 result->modulation = STV0900_8PSK;
1243 else if (result->modcode <= STV0900_16APSK_910)
1244 result->modulation = STV0900_16APSK;
1245 else if (result->modcode <= STV0900_32APSK_910)
1246 result->modulation = STV0900_32APSK;
1248 result->modulation = STV0900_UNKNOWN;
1250 case STV0900_DVBS1_STANDARD:
1251 case STV0900_DSS_STANDARD:
1252 result->spectrum = stv0900_get_bits(intp, IQINV);
1253 result->modulation = STV0900_QPSK;
1259 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1260 (intp->symbol_rate[d] < 10000000)) {
1261 offsetFreq = result->frequency - intp->freq[d];
1262 if (intp->tuner_type[demod] == 3)
1263 intp->freq[d] = stv0900_get_freq_auto(intp, d);
1265 intp->freq[d] = stv0900_get_tuner_freq(fe);
1267 if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1268 range = STV0900_RANGEOK;
1269 else if (ABS(offsetFreq) <=
1270 (stv0900_carrier_width(result->symbol_rate,
1271 result->rolloff) / 2000))
1272 range = STV0900_RANGEOK;
1274 } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1275 range = STV0900_RANGEOK;
1277 dprintk("%s: range %d\n", __func__, range);
1283 fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1285 struct stv0900_state *state = fe->demodulator_priv;
1286 struct stv0900_internal *intp = state->internal;
1287 enum fe_stv0900_demod_num demod = state->demod;
1288 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1296 intp->result[demod].locked = FALSE;
1298 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1299 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1300 srate += stv0900_get_timing_offst(intp, srate, demod);
1301 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1302 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1304 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1305 srate, STV0900_WARM_START);
1306 freq1 = stv0900_read_reg(intp, CFR2);
1307 freq0 = stv0900_read_reg(intp, CFR1);
1308 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1309 stv0900_write_bits(intp, SPECINV_CONTROL,
1310 STV0900_IQ_FORCE_SWAPPED);
1311 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1312 stv0900_write_reg(intp, CFRINIT1, freq1);
1313 stv0900_write_reg(intp, CFRINIT0, freq0);
1314 stv0900_write_reg(intp, DMDISTATE, 0x18);
1315 if (stv0900_wait_for_lock(intp, demod,
1316 demod_timeout, fec_timeout) == TRUE) {
1317 intp->result[demod].locked = TRUE;
1318 signal_type = stv0900_get_signal_params(fe);
1319 stv0900_track_optimization(fe);
1321 stv0900_write_bits(intp, SPECINV_CONTROL,
1322 STV0900_IQ_FORCE_NORMAL);
1323 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1324 stv0900_write_reg(intp, CFRINIT1, freq1);
1325 stv0900_write_reg(intp, CFRINIT0, freq0);
1326 stv0900_write_reg(intp, DMDISTATE, 0x18);
1327 if (stv0900_wait_for_lock(intp, demod,
1328 demod_timeout, fec_timeout) == TRUE) {
1329 intp->result[demod].locked = TRUE;
1330 signal_type = stv0900_get_signal_params(fe);
1331 stv0900_track_optimization(fe);
1337 intp->result[demod].locked = FALSE;
1342 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1343 enum fe_stv0900_demod_num demod)
1345 u32 minagc2level = 0xffff,
1347 init_freq, freq_step;
1349 s32 i, j, nb_steps, direction;
1351 dprintk("%s\n", __func__);
1353 stv0900_write_reg(intp, AGC2REF, 0x38);
1354 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1355 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1357 stv0900_write_bits(intp, AUTO_GUP, 1);
1358 stv0900_write_bits(intp, AUTO_GLOW, 1);
1360 stv0900_write_reg(intp, DMDT0M, 0x0);
1362 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1363 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1365 nb_steps = (2 * nb_steps) + 1;
1372 freq_step = (1000000 << 8) / (intp->mclk >> 8);
1376 for (i = 0; i < nb_steps; i++) {
1378 init_freq = init_freq + (freq_step * i);
1380 init_freq = init_freq - (freq_step * i);
1383 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1384 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1385 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1386 stv0900_write_reg(intp, DMDISTATE, 0x58);
1390 for (j = 0; j < 10; j++)
1391 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1392 | stv0900_read_reg(intp, AGC2I0);
1396 if (agc2level < minagc2level)
1397 minagc2level = agc2level;
1401 return (u16)minagc2level;
1404 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1406 struct stv0900_state *state = fe->demodulator_priv;
1407 struct stv0900_internal *intp = state->internal;
1408 enum fe_stv0900_demod_num demod = state->demod;
1409 int timing_lck = FALSE;
1410 s32 i, timingcpt = 0,
1418 currier_step = 1200;
1420 if (intp->chip_id >= 0x30)
1425 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1426 stv0900_write_reg(intp, TMGCFG, 0x12);
1427 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1428 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1429 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1430 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1431 stv0900_write_reg(intp, SFRUP1, 0x83);
1432 stv0900_write_reg(intp, SFRUP0, 0xc0);
1433 stv0900_write_reg(intp, SFRLOW1, 0x82);
1434 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1435 stv0900_write_reg(intp, DMDT0M, 0x0);
1436 stv0900_write_reg(intp, AGC2REF, 0x50);
1438 if (intp->chip_id >= 0x30) {
1439 stv0900_write_reg(intp, CARFREQ, 0x99);
1440 stv0900_write_reg(intp, SFRSTEP, 0x98);
1441 } else if (intp->chip_id >= 0x20) {
1442 stv0900_write_reg(intp, CARFREQ, 0x6a);
1443 stv0900_write_reg(intp, SFRSTEP, 0x95);
1445 stv0900_write_reg(intp, CARFREQ, 0xed);
1446 stv0900_write_reg(intp, SFRSTEP, 0x73);
1449 if (intp->symbol_rate[demod] <= 2000000)
1450 currier_step = 1000;
1451 else if (intp->symbol_rate[demod] <= 5000000)
1452 currier_step = 2000;
1453 else if (intp->symbol_rate[demod] <= 12000000)
1454 currier_step = 3000;
1456 currier_step = 5000;
1458 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1460 nb_steps = (2 * nb_steps) + 1;
1464 else if (nb_steps > 10) {
1466 currier_step = (intp->srch_range[demod] / 1000) / 10;
1472 tuner_freq = intp->freq[demod];
1474 while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1475 stv0900_write_reg(intp, DMDISTATE, 0x5f);
1476 stv0900_write_bits(intp, DEMOD_MODE, 0);
1480 for (i = 0; i < 10; i++) {
1481 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1484 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1485 stv0900_read_reg(intp, AGC2I0);
1489 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1493 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
1494 " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1495 tuner_freq, agc2_integr, coarse_srate, timingcpt);
1497 if ((timingcpt >= 5) &&
1498 (agc2_integr < agc2_th) &&
1499 (coarse_srate < 55000000) &&
1500 (coarse_srate > 850000))
1502 else if (current_step < nb_steps) {
1504 tuner_freq += (current_step * currier_step);
1506 tuner_freq -= (current_step * currier_step);
1508 if (intp->tuner_type[demod] == 3)
1509 stv0900_set_tuner_auto(intp, tuner_freq,
1510 intp->bw[demod], demod);
1512 stv0900_set_tuner(fe, tuner_freq,
1517 if (timing_lck == FALSE)
1520 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1522 return coarse_srate;
1525 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1527 struct stv0900_state *state = fe->demodulator_priv;
1528 struct stv0900_internal *intp = state->internal;
1529 enum fe_stv0900_demod_num demod = state->demod;
1537 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1539 if (coarse_srate > 3000000) {
1540 symbmax = 13 * (coarse_srate / 10);
1541 symbmax = (symbmax / 1000) * 65536;
1542 symbmax /= (intp->mclk / 1000);
1544 symbmin = 10 * (coarse_srate / 13);
1545 symbmin = (symbmin / 1000)*65536;
1546 symbmin /= (intp->mclk / 1000);
1548 symb = (coarse_srate / 1000) * 65536;
1549 symb /= (intp->mclk / 1000);
1551 symbmax = 13 * (coarse_srate / 10);
1552 symbmax = (symbmax / 100) * 65536;
1553 symbmax /= (intp->mclk / 100);
1555 symbmin = 10 * (coarse_srate / 14);
1556 symbmin = (symbmin / 100) * 65536;
1557 symbmin /= (intp->mclk / 100);
1559 symb = (coarse_srate / 100) * 65536;
1560 symb /= (intp->mclk / 100);
1563 symbcomp = 13 * (coarse_srate / 10);
1564 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1565 | stv0900_read_reg(intp, CFR1);
1567 if (symbcomp < intp->symbol_rate[demod])
1570 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1571 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1572 stv0900_write_reg(intp, TMGTHRISE, 0x20);
1573 stv0900_write_reg(intp, TMGTHFALL, 0x00);
1574 stv0900_write_reg(intp, TMGCFG, 0xd2);
1575 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1576 stv0900_write_reg(intp, AGC2REF, 0x38);
1578 if (intp->chip_id >= 0x30)
1579 stv0900_write_reg(intp, CARFREQ, 0x79);
1580 else if (intp->chip_id >= 0x20)
1581 stv0900_write_reg(intp, CARFREQ, 0x49);
1583 stv0900_write_reg(intp, CARFREQ, 0xed);
1585 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1586 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1588 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1589 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1591 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1592 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1594 stv0900_write_reg(intp, DMDT0M, 0x20);
1595 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1596 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1597 stv0900_write_reg(intp, DMDISTATE, 0x15);
1600 return coarse_srate;
1603 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1605 struct stv0900_state *state = fe->demodulator_priv;
1606 struct stv0900_internal *intp = state->internal;
1607 enum fe_stv0900_demod_num demod = state->demod;
1614 coarse_fail = FALSE;
1615 s32 demod_timeout = 500,
1623 dprintk("%s\n", __func__);
1625 if (intp->chip_id < 0x20) {
1626 k_ref_tmg_max = 233;
1627 k_ref_tmg_min = 143;
1629 k_ref_tmg_max = 110;
1633 if (intp->chip_id <= 0x20)
1634 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1636 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
1638 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1640 dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
1641 if (agc2_int > agc2_th)
1644 if (intp->chip_id == 0x10)
1645 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1647 if (intp->chip_id < 0x20)
1648 stv0900_write_reg(intp, CARHDR, 0x55);
1650 stv0900_write_reg(intp, CARHDR, 0x20);
1652 if (intp->chip_id <= 0x20)
1653 stv0900_write_reg(intp, CARCFG, 0xc4);
1655 stv0900_write_reg(intp, CARCFG, 0x6);
1657 stv0900_write_reg(intp, RTCS2, 0x44);
1659 if (intp->chip_id >= 0x20) {
1660 stv0900_write_reg(intp, EQUALCFG, 0x41);
1661 stv0900_write_reg(intp, FFECFG, 0x41);
1662 stv0900_write_reg(intp, VITSCALE, 0x82);
1663 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1666 k_ref_tmg = k_ref_tmg_max;
1669 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1670 if (stv0900_search_srate_coarse(fe) != 0) {
1671 coarse_srate = stv0900_search_srate_fine(fe);
1673 if (coarse_srate != 0) {
1674 stv0900_get_lock_timeout(&demod_timeout,
1677 STV0900_BLIND_SEARCH);
1678 lock = stv0900_get_demod_lock(intp,
1687 for (i = 0; i < 10; i++) {
1688 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1689 | stv0900_read_reg(intp, AGC2I0);
1691 if (agc2_int >= 0xff00)
1694 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1696 if (((dstatus2 & 0x1) == 0x1) &&
1697 ((dstatus2 >> 7) == 1))
1701 if ((fail_cpt > 7) || (agc2_overflow > 7))
1707 } while ((k_ref_tmg >= k_ref_tmg_min) &&
1709 (coarse_fail == FALSE));
1714 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1715 enum fe_stv0900_demod_num demod)
1717 s32 vth_reg = VTH12;
1719 dprintk("%s\n", __func__);
1721 stv0900_write_reg(intp, vth_reg++, 0x96);
1722 stv0900_write_reg(intp, vth_reg++, 0x64);
1723 stv0900_write_reg(intp, vth_reg++, 0x36);
1724 stv0900_write_reg(intp, vth_reg++, 0x23);
1725 stv0900_write_reg(intp, vth_reg++, 0x1e);
1726 stv0900_write_reg(intp, vth_reg++, 0x19);
1729 static void stv0900_set_search_standard(struct stv0900_internal *intp,
1730 enum fe_stv0900_demod_num demod)
1733 dprintk("%s\n", __func__);
1735 switch (intp->srch_standard[demod]) {
1736 case STV0900_SEARCH_DVBS1:
1737 dprintk("Search Standard = DVBS1\n");
1739 case STV0900_SEARCH_DSS:
1740 dprintk("Search Standard = DSS\n");
1741 case STV0900_SEARCH_DVBS2:
1743 dprintk("Search Standard = DVBS2\n");
1744 case STV0900_AUTO_SEARCH:
1746 dprintk("Search Standard = AUTO\n");
1750 switch (intp->srch_standard[demod]) {
1751 case STV0900_SEARCH_DVBS1:
1752 case STV0900_SEARCH_DSS:
1753 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1754 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1755 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1756 stv0900_set_dvbs1_track_car_loop(intp,
1758 intp->symbol_rate[demod]);
1759 stv0900_write_reg(intp, CAR2CFG, 0x22);
1761 stv0900_set_viterbi_acq(intp, demod);
1762 stv0900_set_viterbi_standard(intp,
1763 intp->srch_standard[demod],
1764 intp->fec[demod], demod);
1767 case STV0900_SEARCH_DVBS2:
1768 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1769 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1770 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1771 stv0900_write_reg(intp, ACLC, 0x1a);
1772 stv0900_write_reg(intp, BCLC, 0x09);
1773 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1774 stv0900_write_reg(intp, CAR2CFG, 0x26);
1776 stv0900_write_reg(intp, CAR2CFG, 0x66);
1778 if (intp->demod_mode != STV0900_SINGLE) {
1779 if (intp->chip_id <= 0x11)
1780 stv0900_stop_all_s2_modcod(intp, demod);
1782 stv0900_activate_s2_modcod(intp, demod);
1785 stv0900_activate_s2_modcod_single(intp, demod);
1787 stv0900_set_viterbi_tracq(intp, demod);
1790 case STV0900_AUTO_SEARCH:
1792 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1793 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1794 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1795 stv0900_write_reg(intp, ACLC, 0x1a);
1796 stv0900_write_reg(intp, BCLC, 0x09);
1797 stv0900_set_dvbs1_track_car_loop(intp,
1799 intp->symbol_rate[demod]);
1800 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1801 stv0900_write_reg(intp, CAR2CFG, 0x26);
1803 stv0900_write_reg(intp, CAR2CFG, 0x66);
1805 if (intp->demod_mode != STV0900_SINGLE) {
1806 if (intp->chip_id <= 0x11)
1807 stv0900_stop_all_s2_modcod(intp, demod);
1809 stv0900_activate_s2_modcod(intp, demod);
1812 stv0900_activate_s2_modcod_single(intp, demod);
1814 stv0900_set_viterbi_tracq(intp, demod);
1815 stv0900_set_viterbi_standard(intp,
1816 intp->srch_standard[demod],
1817 intp->fec[demod], demod);
1823 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1825 struct stv0900_state *state = fe->demodulator_priv;
1826 struct stv0900_internal *intp = state->internal;
1827 enum fe_stv0900_demod_num demod = state->demod;
1829 s32 demod_timeout = 500, fec_timeout = 50;
1830 s32 aq_power, agc1_power, i;
1832 int lock = FALSE, low_sr = FALSE;
1834 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1835 enum fe_stv0900_search_algo algo;
1836 int no_signal = FALSE;
1838 dprintk("%s\n", __func__);
1840 algo = intp->srch_algo[demod];
1841 stv0900_write_bits(intp, RST_HWARE, 1);
1842 stv0900_write_reg(intp, DMDISTATE, 0x5c);
1843 if (intp->chip_id >= 0x20) {
1844 if (intp->symbol_rate[demod] > 5000000)
1845 stv0900_write_reg(intp, CORRELABS, 0x9e);
1847 stv0900_write_reg(intp, CORRELABS, 0x82);
1849 stv0900_write_reg(intp, CORRELABS, 0x88);
1851 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1852 intp->symbol_rate[demod],
1853 intp->srch_algo[demod]);
1855 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1856 intp->bw[demod] = 2 * 36000000;
1858 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1859 stv0900_write_reg(intp, CORRELMANT, 0x70);
1861 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1863 stv0900_write_reg(intp, DMDT0M, 0x20);
1864 stv0900_write_reg(intp, TMGCFG, 0xd2);
1866 if (intp->symbol_rate[demod] < 2000000)
1867 stv0900_write_reg(intp, CORRELMANT, 0x63);
1869 stv0900_write_reg(intp, CORRELMANT, 0x70);
1871 stv0900_write_reg(intp, AGC2REF, 0x38);
1874 stv0900_carrier_width(intp->symbol_rate[demod],
1876 if (intp->chip_id >= 0x20) {
1877 stv0900_write_reg(intp, KREFTMG, 0x5a);
1879 if (intp->srch_algo[demod] == STV0900_COLD_START) {
1880 intp->bw[demod] += 10000000;
1881 intp->bw[demod] *= 15;
1882 intp->bw[demod] /= 10;
1883 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1884 intp->bw[demod] += 10000000;
1887 stv0900_write_reg(intp, KREFTMG, 0xc1);
1888 intp->bw[demod] += 10000000;
1889 intp->bw[demod] *= 15;
1890 intp->bw[demod] /= 10;
1893 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1895 stv0900_set_symbol_rate(intp, intp->mclk,
1896 intp->symbol_rate[demod], demod);
1897 stv0900_set_max_symbol_rate(intp, intp->mclk,
1898 intp->symbol_rate[demod], demod);
1899 stv0900_set_min_symbol_rate(intp, intp->mclk,
1900 intp->symbol_rate[demod], demod);
1901 if (intp->symbol_rate[demod] >= 10000000)
1908 if (intp->tuner_type[demod] == 3)
1909 stv0900_set_tuner_auto(intp, intp->freq[demod],
1910 intp->bw[demod], demod);
1912 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1914 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1915 stv0900_get_bits(intp, AGCIQ_VALUE0));
1919 if (agc1_power == 0) {
1920 for (i = 0; i < 5; i++)
1921 aq_power += (stv0900_get_bits(intp, POWER_I) +
1922 stv0900_get_bits(intp, POWER_Q)) / 2;
1927 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1928 intp->result[demod].locked = FALSE;
1929 signal_type = STV0900_NOAGC1;
1930 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1932 stv0900_write_bits(intp, SPECINV_CONTROL,
1933 intp->srch_iq_inv[demod]);
1934 if (intp->chip_id <= 0x20) /*cut 2.0*/
1935 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1937 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1939 stv0900_set_search_standard(intp, demod);
1941 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1942 stv0900_start_search(intp, demod);
1945 if (signal_type == STV0900_NOAGC1)
1948 if (intp->chip_id == 0x12) {
1949 stv0900_write_bits(intp, RST_HWARE, 0);
1951 stv0900_write_bits(intp, RST_HWARE, 1);
1952 stv0900_write_bits(intp, RST_HWARE, 0);
1955 if (algo == STV0900_BLIND_SEARCH)
1956 lock = stv0900_blind_search_algo(fe);
1957 else if (algo == STV0900_COLD_START)
1958 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1959 else if (algo == STV0900_WARM_START)
1960 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1962 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1963 if (low_sr == FALSE) {
1964 if (stv0900_check_timing_lock(intp, demod) == TRUE)
1965 lock = stv0900_sw_algo(intp, demod);
1970 signal_type = stv0900_get_signal_params(fe);
1972 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1973 stv0900_track_optimization(fe);
1974 if (intp->chip_id <= 0x11) {
1975 if ((stv0900_get_standard(fe, 0) ==
1976 STV0900_DVBS1_STANDARD) &&
1977 (stv0900_get_standard(fe, 1) ==
1978 STV0900_DVBS1_STANDARD)) {
1980 stv0900_write_bits(intp, RST_HWARE, 0);
1982 stv0900_write_bits(intp, RST_HWARE, 0);
1984 stv0900_write_bits(intp, RST_HWARE, 1);
1985 stv0900_write_bits(intp, RST_HWARE, 0);
1988 } else if (intp->chip_id >= 0x20) {
1989 stv0900_write_bits(intp, RST_HWARE, 0);
1991 stv0900_write_bits(intp, RST_HWARE, 1);
1992 stv0900_write_bits(intp, RST_HWARE, 0);
1995 if (stv0900_wait_for_lock(intp, demod,
1996 fec_timeout, fec_timeout) == TRUE) {
1998 intp->result[demod].locked = TRUE;
1999 if (intp->result[demod].standard ==
2000 STV0900_DVBS2_STANDARD) {
2001 stv0900_set_dvbs2_rolloff(intp, demod);
2002 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
2003 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
2004 stv0900_write_reg(intp, ERRCTRL1, 0x67);
2006 stv0900_write_reg(intp, ERRCTRL1, 0x75);
2009 stv0900_write_reg(intp, FBERCPT4, 0);
2010 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
2013 signal_type = STV0900_NODATA;
2014 no_signal = stv0900_check_signal_presence(intp, demod);
2016 intp->result[demod].locked = FALSE;
2020 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2023 if (intp->chip_id > 0x11) {
2024 intp->result[demod].locked = FALSE;
2028 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
2029 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
2030 signal_type = stv0900_dvbs1_acq_workaround(fe);