4 * Driver for ST STV0900 satellite demodulator IC.
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include "stv0900_reg.h"
28 #include "stv0900_priv.h"
30 s32 shiftx(s32 x, int demod, s32 shift)
38 int stv0900_check_signal_presence(struct stv0900_internal *intp,
39 enum fe_stv0900_demod_num demod)
45 int no_signal = FALSE;
47 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
48 | stv0900_read_reg(intp, CFR1);
49 carr_offset = ge2comp(carr_offset, 16);
50 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
51 | stv0900_read_reg(intp, AGC2I0);
52 max_carrier = intp->srch_range[demod] / 1000;
54 max_carrier += (max_carrier / 10);
55 max_carrier = 65536 * (max_carrier / 2);
56 max_carrier /= intp->mclk / 1000;
57 if (max_carrier > 0x4000)
60 if ((agc2_integr > 0x2000)
61 || (carr_offset > (2 * max_carrier))
62 || (carr_offset < (-2 * max_carrier)))
68 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
69 s32 *frequency_inc, s32 *sw_timeout,
71 enum fe_stv0900_demod_num demod)
73 s32 timeout, freq_inc, max_steps, srate, max_carrier;
75 enum fe_stv0900_search_standard standard;
77 srate = intp->symbol_rate[demod];
78 max_carrier = intp->srch_range[demod] / 1000;
79 max_carrier += max_carrier / 10;
80 standard = intp->srch_standard[demod];
82 max_carrier = 65536 * (max_carrier / 2);
83 max_carrier /= intp->mclk / 1000;
85 if (max_carrier > 0x4000)
89 freq_inc /= intp->mclk >> 10;
90 freq_inc = freq_inc << 6;
93 case STV0900_SEARCH_DVBS1:
94 case STV0900_SEARCH_DSS:
98 case STV0900_SEARCH_DVBS2:
102 case STV0900_AUTO_SEARCH:
111 if ((freq_inc > max_carrier) || (freq_inc < 0))
112 freq_inc = max_carrier / 2;
117 timeout /= srate / 1000;
119 if ((timeout > 100) || (timeout < 0))
122 max_steps = (max_carrier / freq_inc) + 1;
124 if ((max_steps > 100) || (max_steps < 0)) {
126 freq_inc = max_carrier / max_steps;
129 *frequency_inc = freq_inc;
130 *sw_timeout = timeout;
135 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
136 s32 FreqIncr, s32 Timeout, int zigzag,
137 s32 MaxStep, enum fe_stv0900_demod_num demod)
145 max_carrier = intp->srch_range[demod] / 1000;
146 max_carrier += (max_carrier / 10);
148 max_carrier = 65536 * (max_carrier / 2);
149 max_carrier /= intp->mclk / 1000;
151 if (max_carrier > 0x4000)
152 max_carrier = 0x4000;
157 freqOffset = -max_carrier + FreqIncr;
162 stv0900_write_reg(intp, DMDISTATE, 0x1c);
163 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
164 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
165 stv0900_write_reg(intp, DMDISTATE, 0x18);
166 stv0900_write_bits(intp, ALGOSWRST, 1);
168 if (intp->chip_id == 0x12) {
169 stv0900_write_bits(intp, RST_HWARE, 1);
170 stv0900_write_bits(intp, RST_HWARE, 0);
173 if (zigzag == TRUE) {
175 freqOffset = -freqOffset - 2 * FreqIncr;
177 freqOffset = -freqOffset;
179 freqOffset += + 2 * FreqIncr;
182 lock = stv0900_get_demod_lock(intp, demod, Timeout);
183 no_signal = stv0900_check_signal_presence(intp, demod);
185 } while ((lock == FALSE)
186 && (no_signal == FALSE)
187 && ((freqOffset - FreqIncr) < max_carrier)
188 && ((freqOffset + FreqIncr) > -max_carrier)
189 && (stepCpt < MaxStep));
191 stv0900_write_bits(intp, ALGOSWRST, 0);
196 int stv0900_sw_algo(struct stv0900_internal *intp,
197 enum fe_stv0900_demod_num demod)
208 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
210 switch (intp->srch_standard[demod]) {
211 case STV0900_SEARCH_DVBS1:
212 case STV0900_SEARCH_DSS:
213 if (intp->chip_id >= 0x20)
214 stv0900_write_reg(intp, CARFREQ, 0x3b);
216 stv0900_write_reg(intp, CARFREQ, 0xef);
218 stv0900_write_reg(intp, DMDCFGMD, 0x49);
221 case STV0900_SEARCH_DVBS2:
222 if (intp->chip_id >= 0x20)
223 stv0900_write_reg(intp, CORRELABS, 0x79);
225 stv0900_write_reg(intp, CORRELABS, 0x68);
227 stv0900_write_reg(intp, DMDCFGMD, 0x89);
231 case STV0900_AUTO_SEARCH:
233 if (intp->chip_id >= 0x20) {
234 stv0900_write_reg(intp, CARFREQ, 0x3b);
235 stv0900_write_reg(intp, CORRELABS, 0x79);
237 stv0900_write_reg(intp, CARFREQ, 0xef);
238 stv0900_write_reg(intp, CORRELABS, 0x68);
241 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
248 lock = stv0900_search_carr_sw_loop(intp,
254 no_signal = stv0900_check_signal_presence(intp, demod);
257 || (no_signal == TRUE)
258 || (trial_cntr == 2)) {
260 if (intp->chip_id >= 0x20) {
261 stv0900_write_reg(intp, CARFREQ, 0x49);
262 stv0900_write_reg(intp, CORRELABS, 0x9e);
264 stv0900_write_reg(intp, CARFREQ, 0xed);
265 stv0900_write_reg(intp, CORRELABS, 0x88);
268 if ((stv0900_get_bits(intp, HEADER_MODE) ==
269 STV0900_DVBS2_FOUND) &&
271 msleep(sft_stp_tout);
272 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
275 msleep(sft_stp_tout);
276 s2fw = stv0900_get_bits(intp,
283 if (trial_cntr < 2) {
284 if (intp->chip_id >= 0x20)
285 stv0900_write_reg(intp,
289 stv0900_write_reg(intp,
293 stv0900_write_reg(intp,
301 } while ((lock == FALSE)
303 && (no_signal == FALSE));
308 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
310 enum fe_stv0900_demod_num demod)
312 s32 rem1, rem2, intval1, intval2, srate;
314 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
315 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
316 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
317 (stv0900_get_bits(intp, SYMB_FREQ0));
318 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
319 srate, stv0900_get_bits(intp, SYMB_FREQ0),
320 stv0900_get_bits(intp, SYMB_FREQ1),
321 stv0900_get_bits(intp, SYMB_FREQ2),
322 stv0900_get_bits(intp, SYMB_FREQ3));
324 intval1 = (mclk) >> 16;
325 intval2 = (srate) >> 16;
327 rem1 = (mclk) % 0x10000;
328 rem2 = (srate) % 0x10000;
329 srate = (intval1 * intval2) +
330 ((intval1 * rem2) >> 16) +
331 ((intval2 * rem1) >> 16);
336 static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
338 enum fe_stv0900_demod_num demod)
342 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
345 if (srate > 60000000) {
347 symb /= (mclk >> 12);
348 } else if (srate > 6000000) {
350 symb /= (mclk >> 10);
356 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
357 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
360 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
362 enum fe_stv0900_demod_num demod)
366 srate = 105 * (srate / 100);
368 if (srate > 60000000) {
370 symb /= (mclk >> 12);
371 } else if (srate > 6000000) {
373 symb /= (mclk >> 10);
380 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
381 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
383 stv0900_write_reg(intp, SFRUP1, 0x7f);
384 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
388 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
390 enum fe_stv0900_demod_num demod)
394 srate = 95 * (srate / 100);
395 if (srate > 60000000) {
397 symb /= (mclk >> 12);
399 } else if (srate > 6000000) {
401 symb /= (mclk >> 10);
408 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
409 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
412 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
414 enum fe_stv0900_demod_num demod)
419 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
420 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
421 (stv0900_read_reg(intp, TMGREG2 + 2));
423 timingoffset = ge2comp(timingoffset, 24);
426 if (timingoffset == 0)
429 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
435 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
436 enum fe_stv0900_demod_num demod)
440 if (intp->chip_id == 0x10) {
441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
442 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
443 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
444 } else if (intp->chip_id <= 0x20)
445 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
447 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
450 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
467 return srate + (srate * rolloff) / 100;
470 static int stv0900_check_timing_lock(struct stv0900_internal *intp,
471 enum fe_stv0900_demod_num demod)
473 int timingLock = FALSE;
480 car_freq = stv0900_read_reg(intp, CARFREQ);
481 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
482 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
483 stv0900_write_reg(intp, TMGTHRISE, 0x20);
484 stv0900_write_reg(intp, TMGTHFALL, 0x0);
485 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
486 stv0900_write_reg(intp, RTC, 0x80);
487 stv0900_write_reg(intp, RTCS2, 0x40);
488 stv0900_write_reg(intp, CARFREQ, 0x0);
489 stv0900_write_reg(intp, CFRINIT1, 0x0);
490 stv0900_write_reg(intp, CFRINIT0, 0x0);
491 stv0900_write_reg(intp, AGC2REF, 0x65);
492 stv0900_write_reg(intp, DMDISTATE, 0x18);
495 for (i = 0; i < 10; i++) {
496 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
505 stv0900_write_reg(intp, AGC2REF, 0x38);
506 stv0900_write_reg(intp, RTC, 0x88);
507 stv0900_write_reg(intp, RTCS2, 0x68);
508 stv0900_write_reg(intp, CARFREQ, car_freq);
509 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
510 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
515 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
518 struct stv0900_state *state = fe->demodulator_priv;
519 struct stv0900_internal *intp = state->internal;
520 enum fe_stv0900_demod_num demod = state->demod;
534 srate = intp->symbol_rate[d];
535 search_range = intp->srch_range[d];
537 if (srate >= 10000000)
538 locktimeout = demod_timeout / 3;
540 locktimeout = demod_timeout / 2;
542 lock = stv0900_get_demod_lock(intp, d, locktimeout);
547 if (srate >= 10000000) {
548 if (stv0900_check_timing_lock(intp, d) == TRUE) {
549 stv0900_write_reg(intp, DMDISTATE, 0x1f);
550 stv0900_write_reg(intp, DMDISTATE, 0x15);
551 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
558 if (intp->chip_id <= 0x20) {
559 if (srate <= 1000000)
561 else if (srate <= 4000000)
563 else if (srate <= 7000000)
565 else if (srate <= 10000000)
570 if (srate >= 2000000) {
571 timeout = (demod_timeout / 3);
575 timeout = (demod_timeout / 2);
578 currier_step = srate / 4000;
579 timeout = (demod_timeout * 3) / 4;
582 nb_steps = ((search_range / 1000) / currier_step);
584 if ((nb_steps % 2) != 0)
589 else if (nb_steps > 12)
595 if (intp->chip_id <= 0x20) {
596 tuner_freq = intp->freq[d];
597 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
598 intp->rolloff) + intp->symbol_rate[d];
602 while ((current_step <= nb_steps) && (lock == FALSE)) {
604 tuner_freq += (current_step * currier_step);
606 tuner_freq -= (current_step * currier_step);
608 if (intp->chip_id <= 0x20) {
609 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
610 stv0900_write_reg(intp, DMDISTATE, 0x1c);
611 stv0900_write_reg(intp, CFRINIT1, 0);
612 stv0900_write_reg(intp, CFRINIT0, 0);
613 stv0900_write_reg(intp, DMDISTATE, 0x1f);
614 stv0900_write_reg(intp, DMDISTATE, 0x15);
616 stv0900_write_reg(intp, DMDISTATE, 0x1c);
617 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
618 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
619 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
620 stv0900_write_reg(intp, DMDISTATE, 0x1f);
621 stv0900_write_reg(intp, DMDISTATE, 0x05);
624 lock = stv0900_get_demod_lock(intp, d, timeout);
632 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
634 enum fe_stv0900_search_algo algo)
637 case STV0900_BLIND_SEARCH:
638 if (srate <= 1500000) {
639 (*demod_timeout) = 1500;
640 (*fec_timeout) = 400;
641 } else if (srate <= 5000000) {
642 (*demod_timeout) = 1000;
643 (*fec_timeout) = 300;
645 (*demod_timeout) = 700;
646 (*fec_timeout) = 100;
650 case STV0900_COLD_START:
651 case STV0900_WARM_START:
653 if (srate <= 1000000) {
654 (*demod_timeout) = 3000;
655 (*fec_timeout) = 1700;
656 } else if (srate <= 2000000) {
657 (*demod_timeout) = 2500;
658 (*fec_timeout) = 1100;
659 } else if (srate <= 5000000) {
660 (*demod_timeout) = 1000;
661 (*fec_timeout) = 550;
662 } else if (srate <= 10000000) {
663 (*demod_timeout) = 700;
664 (*fec_timeout) = 250;
665 } else if (srate <= 20000000) {
666 (*demod_timeout) = 400;
667 (*fec_timeout) = 130;
669 (*demod_timeout) = 300;
670 (*fec_timeout) = 100;
677 if (algo == STV0900_WARM_START)
678 (*demod_timeout) /= 2;
681 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
682 enum fe_stv0900_demod_num demod)
687 dprintk("%s\n", __func__);
689 stv0900_write_reg(intp, vth_reg++, 0xd0);
690 stv0900_write_reg(intp, vth_reg++, 0x7d);
691 stv0900_write_reg(intp, vth_reg++, 0x53);
692 stv0900_write_reg(intp, vth_reg++, 0x2f);
693 stv0900_write_reg(intp, vth_reg++, 0x24);
694 stv0900_write_reg(intp, vth_reg++, 0x1f);
697 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
698 enum fe_stv0900_search_standard standard,
699 enum fe_stv0900_fec fec,
700 enum fe_stv0900_demod_num demod)
702 dprintk("%s: ViterbiStandard = ", __func__);
705 case STV0900_AUTO_SEARCH:
707 stv0900_write_reg(intp, FECM, 0x10);
708 stv0900_write_reg(intp, PRVIT, 0x3f);
710 case STV0900_SEARCH_DVBS1:
712 stv0900_write_reg(intp, FECM, 0x00);
714 case STV0900_FEC_UNKNOWN:
716 stv0900_write_reg(intp, PRVIT, 0x2f);
718 case STV0900_FEC_1_2:
719 stv0900_write_reg(intp, PRVIT, 0x01);
721 case STV0900_FEC_2_3:
722 stv0900_write_reg(intp, PRVIT, 0x02);
724 case STV0900_FEC_3_4:
725 stv0900_write_reg(intp, PRVIT, 0x04);
727 case STV0900_FEC_5_6:
728 stv0900_write_reg(intp, PRVIT, 0x08);
730 case STV0900_FEC_7_8:
731 stv0900_write_reg(intp, PRVIT, 0x20);
736 case STV0900_SEARCH_DSS:
738 stv0900_write_reg(intp, FECM, 0x80);
740 case STV0900_FEC_UNKNOWN:
742 stv0900_write_reg(intp, PRVIT, 0x13);
744 case STV0900_FEC_1_2:
745 stv0900_write_reg(intp, PRVIT, 0x01);
747 case STV0900_FEC_2_3:
748 stv0900_write_reg(intp, PRVIT, 0x02);
750 case STV0900_FEC_6_7:
751 stv0900_write_reg(intp, PRVIT, 0x10);
760 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
761 enum fe_stv0900_demod_num demod)
763 enum fe_stv0900_fec prate;
764 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
768 prate = STV0900_FEC_1_2;
771 prate = STV0900_FEC_2_3;
774 prate = STV0900_FEC_3_4;
777 prate = STV0900_FEC_5_6;
780 prate = STV0900_FEC_6_7;
783 prate = STV0900_FEC_7_8;
786 prate = STV0900_FEC_UNKNOWN;
793 void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
794 enum fe_stv0900_demod_num demod,
797 if (intp->chip_id >= 0x30) {
798 if (srate >= 15000000) {
799 stv0900_write_reg(intp, ACLC, 0x2b);
800 stv0900_write_reg(intp, BCLC, 0x1a);
801 } else if ((srate >= 7000000) && (15000000 > srate)) {
802 stv0900_write_reg(intp, ACLC, 0x0c);
803 stv0900_write_reg(intp, BCLC, 0x1b);
804 } else if (srate < 7000000) {
805 stv0900_write_reg(intp, ACLC, 0x2c);
806 stv0900_write_reg(intp, BCLC, 0x1c);
809 } else { /*cut 2.0 and 1.x*/
810 stv0900_write_reg(intp, ACLC, 0x1a);
811 stv0900_write_reg(intp, BCLC, 0x09);
816 static void stv0900_track_optimization(struct dvb_frontend *fe)
818 struct stv0900_state *state = fe->demodulator_priv;
819 struct stv0900_internal *intp = state->internal;
820 enum fe_stv0900_demod_num demod = state->demod;
833 enum fe_stv0900_rolloff rolloff;
834 enum fe_stv0900_modcode foundModcod;
836 dprintk("%s\n", __func__);
838 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
839 srate += stv0900_get_timing_offst(intp, srate, demod);
841 switch (intp->result[demod].standard) {
842 case STV0900_DVBS1_STANDARD:
843 case STV0900_DSS_STANDARD:
844 dprintk("%s: found DVB-S or DSS\n", __func__);
845 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
846 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
847 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
850 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
851 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
853 if (intp->chip_id < 0x30) {
854 stv0900_write_reg(intp, ERRCTRL1, 0x75);
858 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
859 stv0900_write_reg(intp, GAUSSR0, 0x98);
860 stv0900_write_reg(intp, CCIR0, 0x18);
862 stv0900_write_reg(intp, GAUSSR0, 0x18);
863 stv0900_write_reg(intp, CCIR0, 0x18);
866 stv0900_write_reg(intp, ERRCTRL1, 0x75);
868 case STV0900_DVBS2_STANDARD:
869 dprintk("%s: found DVB-S2\n", __func__);
870 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
871 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
872 stv0900_write_reg(intp, ACLC, 0);
873 stv0900_write_reg(intp, BCLC, 0);
874 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
875 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
876 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
877 aclc = stv0900_get_optim_carr_loop(srate,
881 if (foundModcod <= STV0900_QPSK_910)
882 stv0900_write_reg(intp, ACLC2S2Q, aclc);
883 else if (foundModcod <= STV0900_8PSK_910) {
884 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
885 stv0900_write_reg(intp, ACLC2S28, aclc);
888 if ((intp->demod_mode == STV0900_SINGLE) &&
889 (foundModcod > STV0900_8PSK_910)) {
890 if (foundModcod <= STV0900_16APSK_910) {
891 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
892 stv0900_write_reg(intp, ACLC2S216A,
894 } else if (foundModcod <= STV0900_32APSK_910) {
895 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
896 stv0900_write_reg(intp, ACLC2S232A,
902 modulation = intp->result[demod].modulation;
903 aclc = stv0900_get_optim_short_carr_loop(srate,
904 modulation, intp->chip_id);
905 if (modulation == STV0900_QPSK)
906 stv0900_write_reg(intp, ACLC2S2Q, aclc);
907 else if (modulation == STV0900_8PSK) {
908 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
909 stv0900_write_reg(intp, ACLC2S28, aclc);
910 } else if (modulation == STV0900_16APSK) {
911 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
912 stv0900_write_reg(intp, ACLC2S216A, aclc);
913 } else if (modulation == STV0900_32APSK) {
914 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
915 stv0900_write_reg(intp, ACLC2S232A, aclc);
920 if (intp->chip_id <= 0x11) {
921 if (intp->demod_mode != STV0900_SINGLE)
922 stv0900_activate_s2_modcod(intp, demod);
926 stv0900_write_reg(intp, ERRCTRL1, 0x67);
928 case STV0900_UNKNOWN_STANDARD:
930 dprintk("%s: found unknown standard\n", __func__);
931 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
932 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
936 freq1 = stv0900_read_reg(intp, CFR2);
937 freq0 = stv0900_read_reg(intp, CFR1);
938 rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
939 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
940 stv0900_write_reg(intp, SFRSTEP, 0x00);
941 stv0900_write_bits(intp, SCAN_ENABLE, 0);
942 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
943 stv0900_write_reg(intp, TMGCFG2, 0xc1);
944 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
946 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
947 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
951 if (intp->chip_id >= 0x20) {
952 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
953 (intp->srch_standard[demod] ==
954 STV0900_SEARCH_DSS) ||
955 (intp->srch_standard[demod] ==
956 STV0900_AUTO_SEARCH)) {
957 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
958 stv0900_write_reg(intp, VITSCALE, 0x0);
962 if (intp->chip_id < 0x20)
963 stv0900_write_reg(intp, CARHDR, 0x08);
965 if (intp->chip_id == 0x10)
966 stv0900_write_reg(intp, CORRELEXP, 0x0a);
968 stv0900_write_reg(intp, AGC2REF, 0x38);
970 if ((intp->chip_id >= 0x20) ||
971 (blind_tun_sw == 1) ||
972 (intp->symbol_rate[demod] < 10000000)) {
973 stv0900_write_reg(intp, CFRINIT1, freq1);
974 stv0900_write_reg(intp, CFRINIT0, freq0);
975 intp->bw[demod] = stv0900_carrier_width(srate,
976 intp->rolloff) + 10000000;
978 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
979 if (intp->srch_algo[demod] != STV0900_WARM_START)
980 stv0900_set_bandwidth(fe, intp->bw[demod]);
983 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
984 (intp->symbol_rate[demod] < 10000000))
989 stv0900_get_lock_timeout(&timed, &timef, srate,
992 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
993 stv0900_write_reg(intp, DMDISTATE, 0x1f);
994 stv0900_write_reg(intp, CFRINIT1, freq1);
995 stv0900_write_reg(intp, CFRINIT0, freq0);
996 stv0900_write_reg(intp, DMDISTATE, 0x18);
998 while ((stv0900_get_demod_lock(intp,
1000 timed / 2) == FALSE) &&
1002 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1003 stv0900_write_reg(intp, CFRINIT1, freq1);
1004 stv0900_write_reg(intp, CFRINIT0, freq0);
1005 stv0900_write_reg(intp, DMDISTATE, 0x18);
1012 if (intp->chip_id >= 0x20)
1013 stv0900_write_reg(intp, CARFREQ, 0x49);
1015 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1016 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1017 stv0900_set_viterbi_tracq(intp, demod);
1021 static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1022 enum fe_stv0900_demod_num demod, s32 time_out)
1024 s32 timer = 0, lock = 0;
1026 enum fe_stv0900_search_state dmd_state;
1028 dprintk("%s\n", __func__);
1030 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1032 while ((timer < time_out) && (lock == 0)) {
1033 switch (dmd_state) {
1034 case STV0900_SEARCH:
1035 case STV0900_PLH_DETECTED:
1039 case STV0900_DVBS2_FOUND:
1040 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1042 case STV0900_DVBS_FOUND:
1043 lock = stv0900_get_bits(intp, LOCKEDVIT);
1054 dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1056 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1061 static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1062 enum fe_stv0900_demod_num demod,
1063 s32 dmd_timeout, s32 fec_timeout)
1066 s32 timer = 0, lock = 0;
1068 dprintk("%s\n", __func__);
1070 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1073 lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
1078 dprintk("%s: Timer = %d, time_out = %d\n",
1079 __func__, timer, fec_timeout);
1081 while ((timer < fec_timeout) && (lock == 0)) {
1082 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1089 dprintk("%s: DEMOD LOCK OK\n", __func__);
1091 dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1099 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1100 enum fe_stv0900_demod_num demod)
1102 struct stv0900_state *state = fe->demodulator_priv;
1103 struct stv0900_internal *intp = state->internal;
1104 enum fe_stv0900_tracking_standard fnd_standard;
1106 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1110 fnd_standard = STV0900_DVBS2_STANDARD;
1113 if (stv0900_get_bits(intp, DSS_DVB) == 1)
1114 fnd_standard = STV0900_DSS_STANDARD;
1116 fnd_standard = STV0900_DVBS1_STANDARD;
1120 fnd_standard = STV0900_UNKNOWN_STANDARD;
1123 dprintk("%s: standard %d\n", __func__, fnd_standard);
1125 return fnd_standard;
1128 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1129 enum fe_stv0900_demod_num demod)
1137 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1138 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1139 (stv0900_get_bits(intp, CAR_FREQ0));
1141 derot = ge2comp(derot, 24);
1142 intval1 = mclk >> 12;
1143 intval2 = derot >> 12;
1144 rem1 = mclk % 0x1000;
1145 rem2 = derot % 0x1000;
1146 derot = (intval1 * intval2) +
1147 ((intval1 * rem2) >> 12) +
1148 ((intval2 * rem1) >> 12);
1153 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1155 struct dvb_frontend_ops *frontend_ops = NULL;
1156 struct dvb_tuner_ops *tuner_ops = NULL;
1160 frontend_ops = &fe->ops;
1162 if (&frontend_ops->tuner_ops)
1163 tuner_ops = &frontend_ops->tuner_ops;
1165 if (tuner_ops->get_frequency) {
1166 if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1167 dprintk("%s: Invalid parameter\n", __func__);
1169 dprintk("%s: Frequency=%d\n", __func__, freq);
1177 fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1179 struct stv0900_state *state = fe->demodulator_priv;
1180 struct stv0900_internal *intp = state->internal;
1181 enum fe_stv0900_demod_num demod = state->demod;
1182 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1183 struct stv0900_signal_info *result = &intp->result[demod];
1192 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1193 timing = stv0900_read_reg(intp, TMGREG2);
1195 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1197 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1198 timing = stv0900_read_reg(intp, TMGREG2);
1204 result->standard = stv0900_get_standard(fe, d);
1205 result->frequency = stv0900_get_tuner_freq(fe);
1206 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1207 result->frequency += offsetFreq;
1208 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1209 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1210 result->symbol_rate += srate_offset;
1211 result->fec = stv0900_get_vit_fec(intp, d);
1212 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1213 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1214 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1215 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1216 switch (result->standard) {
1217 case STV0900_DVBS2_STANDARD:
1218 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1219 if (result->modcode <= STV0900_QPSK_910)
1220 result->modulation = STV0900_QPSK;
1221 else if (result->modcode <= STV0900_8PSK_910)
1222 result->modulation = STV0900_8PSK;
1223 else if (result->modcode <= STV0900_16APSK_910)
1224 result->modulation = STV0900_16APSK;
1225 else if (result->modcode <= STV0900_32APSK_910)
1226 result->modulation = STV0900_32APSK;
1228 result->modulation = STV0900_UNKNOWN;
1230 case STV0900_DVBS1_STANDARD:
1231 case STV0900_DSS_STANDARD:
1232 result->spectrum = stv0900_get_bits(intp, IQINV);
1233 result->modulation = STV0900_QPSK;
1239 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1240 (intp->symbol_rate[d] < 10000000)) {
1241 offsetFreq = result->frequency - intp->freq[d];
1242 intp->freq[d] = stv0900_get_tuner_freq(fe);
1243 if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1244 range = STV0900_RANGEOK;
1245 else if (ABS(offsetFreq) <=
1246 (stv0900_carrier_width(result->symbol_rate,
1247 result->rolloff) / 2000))
1248 range = STV0900_RANGEOK;
1250 } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1251 range = STV0900_RANGEOK;
1253 dprintk("%s: range %d\n", __func__, range);
1259 fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1261 struct stv0900_state *state = fe->demodulator_priv;
1262 struct stv0900_internal *intp = state->internal;
1263 enum fe_stv0900_demod_num demod = state->demod;
1264 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1272 intp->result[demod].locked = FALSE;
1274 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1275 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1276 srate += stv0900_get_timing_offst(intp, srate, demod);
1277 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1278 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1280 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1281 srate, STV0900_WARM_START);
1282 freq1 = stv0900_read_reg(intp, CFR2);
1283 freq0 = stv0900_read_reg(intp, CFR1);
1284 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1285 stv0900_write_bits(intp, SPECINV_CONTROL,
1286 STV0900_IQ_FORCE_SWAPPED);
1287 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1288 stv0900_write_reg(intp, CFRINIT1, freq1);
1289 stv0900_write_reg(intp, CFRINIT0, freq0);
1290 stv0900_write_reg(intp, DMDISTATE, 0x18);
1291 if (stv0900_wait_for_lock(intp, demod,
1292 demod_timeout, fec_timeout) == TRUE) {
1293 intp->result[demod].locked = TRUE;
1294 signal_type = stv0900_get_signal_params(fe);
1295 stv0900_track_optimization(fe);
1297 stv0900_write_bits(intp, SPECINV_CONTROL,
1298 STV0900_IQ_FORCE_NORMAL);
1299 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1300 stv0900_write_reg(intp, CFRINIT1, freq1);
1301 stv0900_write_reg(intp, CFRINIT0, freq0);
1302 stv0900_write_reg(intp, DMDISTATE, 0x18);
1303 if (stv0900_wait_for_lock(intp, demod,
1304 demod_timeout, fec_timeout) == TRUE) {
1305 intp->result[demod].locked = TRUE;
1306 signal_type = stv0900_get_signal_params(fe);
1307 stv0900_track_optimization(fe);
1313 intp->result[demod].locked = FALSE;
1318 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1319 enum fe_stv0900_demod_num demod)
1321 u32 minagc2level = 0xffff,
1323 init_freq, freq_step;
1325 s32 i, j, nb_steps, direction;
1327 dprintk("%s\n", __func__);
1329 stv0900_write_reg(intp, AGC2REF, 0x38);
1330 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1331 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1333 stv0900_write_bits(intp, AUTO_GUP, 1);
1334 stv0900_write_bits(intp, AUTO_GLOW, 1);
1336 stv0900_write_reg(intp, DMDT0M, 0x0);
1338 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1339 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1341 nb_steps = (2 * nb_steps) + 1;
1348 freq_step = (1000000 << 8) / (intp->mclk >> 8);
1352 for (i = 0; i < nb_steps; i++) {
1354 init_freq = init_freq + (freq_step * i);
1356 init_freq = init_freq - (freq_step * i);
1359 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1360 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1361 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1362 stv0900_write_reg(intp, DMDISTATE, 0x58);
1366 for (j = 0; j < 10; j++)
1367 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1368 | stv0900_read_reg(intp, AGC2I0);
1372 if (agc2level < minagc2level)
1373 minagc2level = agc2level;
1377 return (u16)minagc2level;
1380 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1382 struct stv0900_state *state = fe->demodulator_priv;
1383 struct stv0900_internal *intp = state->internal;
1384 enum fe_stv0900_demod_num demod = state->demod;
1385 int timing_lck = FALSE;
1386 s32 i, timingcpt = 0,
1394 currier_step = 1200;
1396 if (intp->chip_id >= 0x30)
1401 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1402 stv0900_write_reg(intp, TMGCFG, 0x12);
1403 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1404 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1405 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1406 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1407 stv0900_write_reg(intp, SFRUP1, 0x83);
1408 stv0900_write_reg(intp, SFRUP0, 0xc0);
1409 stv0900_write_reg(intp, SFRLOW1, 0x82);
1410 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1411 stv0900_write_reg(intp, DMDT0M, 0x0);
1412 stv0900_write_reg(intp, AGC2REF, 0x50);
1414 if (intp->chip_id >= 0x30) {
1415 stv0900_write_reg(intp, CARFREQ, 0x99);
1416 stv0900_write_reg(intp, SFRSTEP, 0x98);
1417 } else if (intp->chip_id >= 0x20) {
1418 stv0900_write_reg(intp, CARFREQ, 0x6a);
1419 stv0900_write_reg(intp, SFRSTEP, 0x95);
1421 stv0900_write_reg(intp, CARFREQ, 0xed);
1422 stv0900_write_reg(intp, SFRSTEP, 0x73);
1425 if (intp->symbol_rate[demod] <= 2000000)
1426 currier_step = 1000;
1427 else if (intp->symbol_rate[demod] <= 5000000)
1428 currier_step = 2000;
1429 else if (intp->symbol_rate[demod] <= 12000000)
1430 currier_step = 3000;
1432 currier_step = 5000;
1434 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1436 nb_steps = (2 * nb_steps) + 1;
1440 else if (nb_steps > 10) {
1442 currier_step = (intp->srch_range[demod] / 1000) / 10;
1448 tuner_freq = intp->freq[demod];
1450 while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1451 stv0900_write_reg(intp, DMDISTATE, 0x5f);
1452 stv0900_write_bits(intp, DEMOD_MODE, 0);
1456 for (i = 0; i < 10; i++) {
1457 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1460 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1461 stv0900_read_reg(intp, AGC2I0);
1465 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1469 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
1470 " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1471 tuner_freq, agc2_integr, coarse_srate, timingcpt);
1473 if ((timingcpt >= 5) &&
1474 (agc2_integr < agc2_th) &&
1475 (coarse_srate < 55000000) &&
1476 (coarse_srate > 850000))
1478 else if (current_step < nb_steps) {
1480 tuner_freq += (current_step * currier_step);
1482 tuner_freq -= (current_step * currier_step);
1484 stv0900_set_tuner(fe, tuner_freq, intp->bw[demod]);
1488 if (timing_lck == FALSE)
1491 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1493 return coarse_srate;
1496 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1498 struct stv0900_state *state = fe->demodulator_priv;
1499 struct stv0900_internal *intp = state->internal;
1500 enum fe_stv0900_demod_num demod = state->demod;
1508 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1510 if (coarse_srate > 3000000) {
1511 symbmax = 13 * (coarse_srate / 10);
1512 symbmax = (symbmax / 1000) * 65536;
1513 symbmax /= (intp->mclk / 1000);
1515 symbmin = 10 * (coarse_srate / 13);
1516 symbmin = (symbmin / 1000)*65536;
1517 symbmin /= (intp->mclk / 1000);
1519 symb = (coarse_srate / 1000) * 65536;
1520 symb /= (intp->mclk / 1000);
1522 symbmax = 13 * (coarse_srate / 10);
1523 symbmax = (symbmax / 100) * 65536;
1524 symbmax /= (intp->mclk / 100);
1526 symbmin = 10 * (coarse_srate / 14);
1527 symbmin = (symbmin / 100) * 65536;
1528 symbmin /= (intp->mclk / 100);
1530 symb = (coarse_srate / 100) * 65536;
1531 symb /= (intp->mclk / 100);
1534 symbcomp = 13 * (coarse_srate / 10);
1535 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1536 | stv0900_read_reg(intp, CFR1);
1538 if (symbcomp < intp->symbol_rate[demod])
1541 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1542 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1543 stv0900_write_reg(intp, TMGTHRISE, 0x20);
1544 stv0900_write_reg(intp, TMGTHFALL, 0x00);
1545 stv0900_write_reg(intp, TMGCFG, 0xd2);
1546 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1547 stv0900_write_reg(intp, AGC2REF, 0x38);
1549 if (intp->chip_id >= 0x30)
1550 stv0900_write_reg(intp, CARFREQ, 0x79);
1551 else if (intp->chip_id >= 0x20)
1552 stv0900_write_reg(intp, CARFREQ, 0x49);
1554 stv0900_write_reg(intp, CARFREQ, 0xed);
1556 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1557 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1559 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1560 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1562 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1563 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1565 stv0900_write_reg(intp, DMDT0M, 0x20);
1566 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1567 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1568 stv0900_write_reg(intp, DMDISTATE, 0x15);
1571 return coarse_srate;
1574 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1576 struct stv0900_state *state = fe->demodulator_priv;
1577 struct stv0900_internal *intp = state->internal;
1578 enum fe_stv0900_demod_num demod = state->demod;
1585 coarse_fail = FALSE;
1586 s32 demod_timeout = 500,
1594 dprintk("%s\n", __func__);
1596 if (intp->chip_id < 0x20) {
1597 k_ref_tmg_max = 233;
1598 k_ref_tmg_min = 143;
1600 k_ref_tmg_max = 110;
1604 if (intp->chip_id <= 0x20)
1605 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1607 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
1609 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1611 if (agc2_int > STV0900_BLIND_SEARCH_AGC2_TH)
1614 if (intp->chip_id == 0x10)
1615 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1617 if (intp->chip_id < 0x20)
1618 stv0900_write_reg(intp, CARHDR, 0x55);
1620 stv0900_write_reg(intp, CARHDR, 0x20);
1622 if (intp->chip_id <= 0x20)
1623 stv0900_write_reg(intp, CARCFG, 0xc4);
1625 stv0900_write_reg(intp, CARCFG, 0x6);
1627 stv0900_write_reg(intp, RTCS2, 0x44);
1629 if (intp->chip_id >= 0x20) {
1630 stv0900_write_reg(intp, EQUALCFG, 0x41);
1631 stv0900_write_reg(intp, FFECFG, 0x41);
1632 stv0900_write_reg(intp, VITSCALE, 0x82);
1633 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1636 k_ref_tmg = k_ref_tmg_max;
1639 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1640 if (stv0900_search_srate_coarse(fe) != 0) {
1641 coarse_srate = stv0900_search_srate_fine(fe);
1643 if (coarse_srate != 0) {
1644 stv0900_get_lock_timeout(&demod_timeout,
1647 STV0900_BLIND_SEARCH);
1648 lock = stv0900_get_demod_lock(intp,
1657 for (i = 0; i < 10; i++) {
1658 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1659 | stv0900_read_reg(intp, AGC2I0);
1661 if (agc2_int >= 0xff00)
1664 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1666 if (((dstatus2 & 0x1) == 0x1) &&
1667 ((dstatus2 >> 7) == 1))
1671 if ((fail_cpt > 7) || (agc2_overflow > 7))
1677 } while ((k_ref_tmg >= k_ref_tmg_min) &&
1679 (coarse_fail == FALSE));
1684 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1685 enum fe_stv0900_demod_num demod)
1687 s32 vth_reg = VTH12;
1689 dprintk("%s\n", __func__);
1691 stv0900_write_reg(intp, vth_reg++, 0x96);
1692 stv0900_write_reg(intp, vth_reg++, 0x64);
1693 stv0900_write_reg(intp, vth_reg++, 0x36);
1694 stv0900_write_reg(intp, vth_reg++, 0x23);
1695 stv0900_write_reg(intp, vth_reg++, 0x1e);
1696 stv0900_write_reg(intp, vth_reg++, 0x19);
1699 static void stv0900_set_search_standard(struct stv0900_internal *intp,
1700 enum fe_stv0900_demod_num demod)
1703 dprintk("%s\n", __func__);
1705 switch (intp->srch_standard[demod]) {
1706 case STV0900_SEARCH_DVBS1:
1707 dprintk("Search Standard = DVBS1\n");
1709 case STV0900_SEARCH_DSS:
1710 dprintk("Search Standard = DSS\n");
1711 case STV0900_SEARCH_DVBS2:
1713 dprintk("Search Standard = DVBS2\n");
1714 case STV0900_AUTO_SEARCH:
1716 dprintk("Search Standard = AUTO\n");
1720 switch (intp->srch_standard[demod]) {
1721 case STV0900_SEARCH_DVBS1:
1722 case STV0900_SEARCH_DSS:
1723 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1724 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1725 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1726 stv0900_set_dvbs1_track_car_loop(intp,
1728 intp->symbol_rate[demod]);
1729 stv0900_write_reg(intp, CAR2CFG, 0x22);
1731 stv0900_set_viterbi_acq(intp, demod);
1732 stv0900_set_viterbi_standard(intp,
1733 intp->srch_standard[demod],
1734 intp->fec[demod], demod);
1737 case STV0900_SEARCH_DVBS2:
1738 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1739 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1740 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1741 stv0900_write_reg(intp, ACLC, 0x1a);
1742 stv0900_write_reg(intp, BCLC, 0x09);
1743 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1744 stv0900_write_reg(intp, CAR2CFG, 0x26);
1746 stv0900_write_reg(intp, CAR2CFG, 0x66);
1748 if (intp->demod_mode != STV0900_SINGLE) {
1749 if (intp->chip_id <= 0x11)
1750 stv0900_stop_all_s2_modcod(intp, demod);
1752 stv0900_activate_s2_modcod(intp, demod);
1755 stv0900_activate_s2_modcod_single(intp, demod);
1757 stv0900_set_viterbi_tracq(intp, demod);
1760 case STV0900_AUTO_SEARCH:
1762 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1763 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1764 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1765 stv0900_write_reg(intp, ACLC, 0x1a);
1766 stv0900_write_reg(intp, BCLC, 0x09);
1767 stv0900_set_dvbs1_track_car_loop(intp,
1769 intp->symbol_rate[demod]);
1770 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1771 stv0900_write_reg(intp, CAR2CFG, 0x26);
1773 stv0900_write_reg(intp, CAR2CFG, 0x66);
1775 if (intp->demod_mode != STV0900_SINGLE) {
1776 if (intp->chip_id <= 0x11)
1777 stv0900_stop_all_s2_modcod(intp, demod);
1779 stv0900_activate_s2_modcod(intp, demod);
1782 stv0900_activate_s2_modcod_single(intp, demod);
1784 stv0900_set_viterbi_tracq(intp, demod);
1785 stv0900_set_viterbi_standard(intp,
1786 intp->srch_standard[demod],
1787 intp->fec[demod], demod);
1793 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1795 struct stv0900_state *state = fe->demodulator_priv;
1796 struct stv0900_internal *intp = state->internal;
1797 enum fe_stv0900_demod_num demod = state->demod;
1799 s32 demod_timeout = 500, fec_timeout = 50;
1800 s32 aq_power, agc1_power, i;
1802 int lock = FALSE, low_sr = FALSE;
1804 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1805 enum fe_stv0900_search_algo algo;
1806 int no_signal = FALSE;
1808 dprintk("%s\n", __func__);
1810 algo = intp->srch_algo[demod];
1811 stv0900_write_bits(intp, RST_HWARE, 1);
1812 stv0900_write_reg(intp, DMDISTATE, 0x5c);
1813 if (intp->chip_id >= 0x20) {
1814 if (intp->symbol_rate[demod] > 5000000)
1815 stv0900_write_reg(intp, CORRELABS, 0x9e);
1817 stv0900_write_reg(intp, CORRELABS, 0x82);
1819 stv0900_write_reg(intp, CORRELABS, 0x88);
1821 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1822 intp->symbol_rate[demod],
1823 intp->srch_algo[demod]);
1825 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1826 intp->bw[demod] = 2 * 36000000;
1828 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1829 stv0900_write_reg(intp, CORRELMANT, 0x70);
1831 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1833 stv0900_write_reg(intp, DMDT0M, 0x20);
1834 stv0900_write_reg(intp, TMGCFG, 0xd2);
1836 if (intp->symbol_rate[demod] < 2000000)
1837 stv0900_write_reg(intp, CORRELMANT, 0x63);
1839 stv0900_write_reg(intp, CORRELMANT, 0x70);
1841 stv0900_write_reg(intp, AGC2REF, 0x38);
1844 stv0900_carrier_width(intp->symbol_rate[demod],
1846 if (intp->chip_id >= 0x20) {
1847 stv0900_write_reg(intp, KREFTMG, 0x5a);
1849 if (intp->srch_algo[demod] == STV0900_COLD_START) {
1850 intp->bw[demod] += 10000000;
1851 intp->bw[demod] *= 15;
1852 intp->bw[demod] /= 10;
1853 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1854 intp->bw[demod] += 10000000;
1857 stv0900_write_reg(intp, KREFTMG, 0xc1);
1858 intp->bw[demod] += 10000000;
1859 intp->bw[demod] *= 15;
1860 intp->bw[demod] /= 10;
1863 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1865 stv0900_set_symbol_rate(intp, intp->mclk,
1866 intp->symbol_rate[demod], demod);
1867 stv0900_set_max_symbol_rate(intp, intp->mclk,
1868 intp->symbol_rate[demod], demod);
1869 stv0900_set_min_symbol_rate(intp, intp->mclk,
1870 intp->symbol_rate[demod], demod);
1871 if (intp->symbol_rate[demod] >= 10000000)
1878 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1880 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1881 stv0900_get_bits(intp, AGCIQ_VALUE0));
1885 if (agc1_power == 0) {
1886 for (i = 0; i < 5; i++)
1887 aq_power += (stv0900_get_bits(intp, POWER_I) +
1888 stv0900_get_bits(intp, POWER_Q)) / 2;
1893 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1894 intp->result[demod].locked = FALSE;
1895 signal_type = STV0900_NOAGC1;
1896 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1898 stv0900_write_bits(intp, SPECINV_CONTROL,
1899 intp->srch_iq_inv[demod]);
1900 if (intp->chip_id <= 0x20) /*cut 2.0*/
1901 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1903 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1905 stv0900_set_search_standard(intp, demod);
1907 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1908 stv0900_start_search(intp, demod);
1911 if (signal_type == STV0900_NOAGC1)
1914 if (intp->chip_id == 0x12) {
1915 stv0900_write_bits(intp, RST_HWARE, 0);
1917 stv0900_write_bits(intp, RST_HWARE, 1);
1918 stv0900_write_bits(intp, RST_HWARE, 0);
1921 if (algo == STV0900_BLIND_SEARCH)
1922 lock = stv0900_blind_search_algo(fe);
1923 else if (algo == STV0900_COLD_START)
1924 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1925 else if (algo == STV0900_WARM_START)
1926 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1928 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1929 if (low_sr == FALSE) {
1930 if (stv0900_check_timing_lock(intp, demod) == TRUE)
1931 lock = stv0900_sw_algo(intp, demod);
1936 signal_type = stv0900_get_signal_params(fe);
1938 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1939 stv0900_track_optimization(fe);
1940 if (intp->chip_id <= 0x11) {
1941 if ((stv0900_get_standard(fe, 0) ==
1942 STV0900_DVBS1_STANDARD) &&
1943 (stv0900_get_standard(fe, 1) ==
1944 STV0900_DVBS1_STANDARD)) {
1946 stv0900_write_bits(intp, RST_HWARE, 0);
1948 stv0900_write_bits(intp, RST_HWARE, 0);
1950 stv0900_write_bits(intp, RST_HWARE, 1);
1951 stv0900_write_bits(intp, RST_HWARE, 0);
1954 } else if (intp->chip_id >= 0x20) {
1955 stv0900_write_bits(intp, RST_HWARE, 0);
1957 stv0900_write_bits(intp, RST_HWARE, 1);
1958 stv0900_write_bits(intp, RST_HWARE, 0);
1961 if (stv0900_wait_for_lock(intp, demod,
1962 fec_timeout, fec_timeout) == TRUE) {
1964 intp->result[demod].locked = TRUE;
1965 if (intp->result[demod].standard ==
1966 STV0900_DVBS2_STANDARD) {
1967 stv0900_set_dvbs2_rolloff(intp, demod);
1968 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
1969 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
1970 stv0900_write_reg(intp, ERRCTRL1, 0x67);
1972 stv0900_write_reg(intp, ERRCTRL1, 0x75);
1975 stv0900_write_reg(intp, FBERCPT4, 0);
1976 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
1979 signal_type = STV0900_NODATA;
1980 no_signal = stv0900_check_signal_presence(intp, demod);
1982 intp->result[demod].locked = FALSE;
1986 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
1989 if (intp->chip_id > 0x11) {
1990 intp->result[demod].locked = FALSE;
1994 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
1995 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
1996 signal_type = stv0900_dvbs1_acq_workaround(fe);