2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/mutex.h>
28 #include <linux/dvb/frontend.h>
29 #include "dvb_frontend.h"
31 #include "stv6110x.h" /* for demodulator internal modes */
33 #include "stv090x_reg.h"
35 #include "stv090x_priv.h"
37 static unsigned int verbose;
38 module_param(verbose, int, 0644);
40 struct mutex demod_lock;
42 /* DVBS1 and DSS C/N Lookup table */
43 static const struct stv090x_tab stv090x_s1cn_tab[] = {
44 { 0, 8917 }, /* 0.0dB */
45 { 5, 8801 }, /* 0.5dB */
46 { 10, 8667 }, /* 1.0dB */
47 { 15, 8522 }, /* 1.5dB */
48 { 20, 8355 }, /* 2.0dB */
49 { 25, 8175 }, /* 2.5dB */
50 { 30, 7979 }, /* 3.0dB */
51 { 35, 7763 }, /* 3.5dB */
52 { 40, 7530 }, /* 4.0dB */
53 { 45, 7282 }, /* 4.5dB */
54 { 50, 7026 }, /* 5.0dB */
55 { 55, 6781 }, /* 5.5dB */
56 { 60, 6514 }, /* 6.0dB */
57 { 65, 6241 }, /* 6.5dB */
58 { 70, 5965 }, /* 7.0dB */
59 { 75, 5690 }, /* 7.5dB */
60 { 80, 5424 }, /* 8.0dB */
61 { 85, 5161 }, /* 8.5dB */
62 { 90, 4902 }, /* 9.0dB */
63 { 95, 4654 }, /* 9.5dB */
64 { 100, 4417 }, /* 10.0dB */
65 { 105, 4186 }, /* 10.5dB */
66 { 110, 3968 }, /* 11.0dB */
67 { 115, 3757 }, /* 11.5dB */
68 { 120, 3558 }, /* 12.0dB */
69 { 125, 3366 }, /* 12.5dB */
70 { 130, 3185 }, /* 13.0dB */
71 { 135, 3012 }, /* 13.5dB */
72 { 140, 2850 }, /* 14.0dB */
73 { 145, 2698 }, /* 14.5dB */
74 { 150, 2550 }, /* 15.0dB */
75 { 160, 2283 }, /* 16.0dB */
76 { 170, 2042 }, /* 17.0dB */
77 { 180, 1827 }, /* 18.0dB */
78 { 190, 1636 }, /* 19.0dB */
79 { 200, 1466 }, /* 20.0dB */
80 { 210, 1315 }, /* 21.0dB */
81 { 220, 1181 }, /* 22.0dB */
82 { 230, 1064 }, /* 23.0dB */
83 { 240, 960 }, /* 24.0dB */
84 { 250, 869 }, /* 25.0dB */
85 { 260, 792 }, /* 26.0dB */
86 { 270, 724 }, /* 27.0dB */
87 { 280, 665 }, /* 28.0dB */
88 { 290, 616 }, /* 29.0dB */
89 { 300, 573 }, /* 30.0dB */
90 { 310, 537 }, /* 31.0dB */
91 { 320, 507 }, /* 32.0dB */
92 { 330, 483 }, /* 33.0dB */
93 { 400, 398 }, /* 40.0dB */
94 { 450, 381 }, /* 45.0dB */
95 { 500, 377 } /* 50.0dB */
98 /* DVBS2 C/N Lookup table */
99 static const struct stv090x_tab stv090x_s2cn_tab[] = {
100 { -30, 13348 }, /* -3.0dB */
101 { -20, 12640 }, /* -2d.0B */
102 { -10, 11883 }, /* -1.0dB */
103 { 0, 11101 }, /* -0.0dB */
104 { 5, 10718 }, /* 0.5dB */
105 { 10, 10339 }, /* 1.0dB */
106 { 15, 9947 }, /* 1.5dB */
107 { 20, 9552 }, /* 2.0dB */
108 { 25, 9183 }, /* 2.5dB */
109 { 30, 8799 }, /* 3.0dB */
110 { 35, 8422 }, /* 3.5dB */
111 { 40, 8062 }, /* 4.0dB */
112 { 45, 7707 }, /* 4.5dB */
113 { 50, 7353 }, /* 5.0dB */
114 { 55, 7025 }, /* 5.5dB */
115 { 60, 6684 }, /* 6.0dB */
116 { 65, 6331 }, /* 6.5dB */
117 { 70, 6036 }, /* 7.0dB */
118 { 75, 5727 }, /* 7.5dB */
119 { 80, 5437 }, /* 8.0dB */
120 { 85, 5164 }, /* 8.5dB */
121 { 90, 4902 }, /* 9.0dB */
122 { 95, 4653 }, /* 9.5dB */
123 { 100, 4408 }, /* 10.0dB */
124 { 105, 4187 }, /* 10.5dB */
125 { 110, 3961 }, /* 11.0dB */
126 { 115, 3751 }, /* 11.5dB */
127 { 120, 3558 }, /* 12.0dB */
128 { 125, 3368 }, /* 12.5dB */
129 { 130, 3191 }, /* 13.0dB */
130 { 135, 3017 }, /* 13.5dB */
131 { 140, 2862 }, /* 14.0dB */
132 { 145, 2710 }, /* 14.5dB */
133 { 150, 2565 }, /* 15.0dB */
134 { 160, 2300 }, /* 16.0dB */
135 { 170, 2058 }, /* 17.0dB */
136 { 180, 1849 }, /* 18.0dB */
137 { 190, 1663 }, /* 19.0dB */
138 { 200, 1495 }, /* 20.0dB */
139 { 210, 1349 }, /* 21.0dB */
140 { 220, 1222 }, /* 22.0dB */
141 { 230, 1110 }, /* 23.0dB */
142 { 240, 1011 }, /* 24.0dB */
143 { 250, 925 }, /* 25.0dB */
144 { 260, 853 }, /* 26.0dB */
145 { 270, 789 }, /* 27.0dB */
146 { 280, 734 }, /* 28.0dB */
147 { 290, 690 }, /* 29.0dB */
148 { 300, 650 }, /* 30.0dB */
149 { 310, 619 }, /* 31.0dB */
150 { 320, 593 }, /* 32.0dB */
151 { 330, 571 }, /* 33.0dB */
152 { 400, 498 }, /* 40.0dB */
153 { 450, 484 }, /* 45.0dB */
154 { 500, 481 } /* 50.0dB */
157 /* RF level C/N lookup table */
158 static const struct stv090x_tab stv090x_rf_tab[] = {
159 { -5, 0xcaa1 }, /* -5dBm */
160 { -10, 0xc229 }, /* -10dBm */
161 { -15, 0xbb08 }, /* -15dBm */
162 { -20, 0xb4bc }, /* -20dBm */
163 { -25, 0xad5a }, /* -25dBm */
164 { -30, 0xa298 }, /* -30dBm */
165 { -35, 0x98a8 }, /* -35dBm */
166 { -40, 0x8389 }, /* -40dBm */
167 { -45, 0x59be }, /* -45dBm */
168 { -50, 0x3a14 }, /* -50dBm */
169 { -55, 0x2d11 }, /* -55dBm */
170 { -60, 0x210d }, /* -60dBm */
171 { -65, 0xa14f }, /* -65dBm */
172 { -70, 0x07aa } /* -70dBm */
176 static struct stv090x_reg stv0900_initval[] = {
178 { STV090x_OUTCFG, 0x00 },
179 { STV090x_MODECFG, 0xff },
180 { STV090x_AGCRF1CFG, 0x11 },
181 { STV090x_AGCRF2CFG, 0x13 },
182 { STV090x_TSGENERAL1X, 0x14 },
183 { STV090x_TSTTNR2, 0x21 },
184 { STV090x_TSTTNR4, 0x21 },
185 { STV090x_P2_DISTXCTL, 0x22 },
186 { STV090x_P2_F22TX, 0xc0 },
187 { STV090x_P2_F22RX, 0xc0 },
188 { STV090x_P2_DISRXCTL, 0x00 },
189 { STV090x_P2_DMDCFGMD, 0xF9 },
190 { STV090x_P2_DEMOD, 0x08 },
191 { STV090x_P2_DMDCFG3, 0xc4 },
192 { STV090x_P2_CARFREQ, 0xed },
193 { STV090x_P2_LDT, 0xd0 },
194 { STV090x_P2_LDT2, 0xb8 },
195 { STV090x_P2_TMGCFG, 0xd2 },
196 { STV090x_P2_TMGTHRISE, 0x20 },
197 { STV090x_P1_TMGCFG, 0xd2 },
199 { STV090x_P2_TMGTHFALL, 0x00 },
200 { STV090x_P2_FECSPY, 0x88 },
201 { STV090x_P2_FSPYDATA, 0x3a },
202 { STV090x_P2_FBERCPT4, 0x00 },
203 { STV090x_P2_FSPYBER, 0x10 },
204 { STV090x_P2_ERRCTRL1, 0x35 },
205 { STV090x_P2_ERRCTRL2, 0xc1 },
206 { STV090x_P2_CFRICFG, 0xf8 },
207 { STV090x_P2_NOSCFG, 0x1c },
208 { STV090x_P2_DMDTOM, 0x20 },
209 { STV090x_P2_CORRELMANT, 0x70 },
210 { STV090x_P2_CORRELABS, 0x88 },
211 { STV090x_P2_AGC2O, 0x5b },
212 { STV090x_P2_AGC2REF, 0x38 },
213 { STV090x_P2_CARCFG, 0xe4 },
214 { STV090x_P2_ACLC, 0x1A },
215 { STV090x_P2_BCLC, 0x09 },
216 { STV090x_P2_CARHDR, 0x08 },
217 { STV090x_P2_KREFTMG, 0xc1 },
218 { STV090x_P2_SFRUPRATIO, 0xf0 },
219 { STV090x_P2_SFRLOWRATIO, 0x70 },
220 { STV090x_P2_SFRSTEP, 0x58 },
221 { STV090x_P2_TMGCFG2, 0x01 },
222 { STV090x_P2_CAR2CFG, 0x26 },
223 { STV090x_P2_BCLC2S2Q, 0x86 },
224 { STV090x_P2_BCLC2S28, 0x86 },
225 { STV090x_P2_SMAPCOEF7, 0x77 },
226 { STV090x_P2_SMAPCOEF6, 0x85 },
227 { STV090x_P2_SMAPCOEF5, 0x77 },
228 { STV090x_P2_TSCFGL, 0x20 },
229 { STV090x_P2_DMDCFG2, 0x3b },
230 { STV090x_P2_MODCODLST0, 0xff },
231 { STV090x_P2_MODCODLST1, 0xff },
232 { STV090x_P2_MODCODLST2, 0xff },
233 { STV090x_P2_MODCODLST3, 0xff },
234 { STV090x_P2_MODCODLST4, 0xff },
235 { STV090x_P2_MODCODLST5, 0xff },
236 { STV090x_P2_MODCODLST6, 0xff },
237 { STV090x_P2_MODCODLST7, 0xcc },
238 { STV090x_P2_MODCODLST8, 0xcc },
239 { STV090x_P2_MODCODLST9, 0xcc },
240 { STV090x_P2_MODCODLSTA, 0xcc },
241 { STV090x_P2_MODCODLSTB, 0xcc },
242 { STV090x_P2_MODCODLSTC, 0xcc },
243 { STV090x_P2_MODCODLSTD, 0xcc },
244 { STV090x_P2_MODCODLSTE, 0xcc },
245 { STV090x_P2_MODCODLSTF, 0xcf },
246 { STV090x_P1_DISTXCTL, 0x22 },
247 { STV090x_P1_F22TX, 0xc0 },
248 { STV090x_P1_F22RX, 0xc0 },
249 { STV090x_P1_DISRXCTL, 0x00 },
250 { STV090x_P1_DMDCFGMD, 0xf9 },
251 { STV090x_P1_DEMOD, 0x08 },
252 { STV090x_P1_DMDCFG3, 0xc4 },
253 { STV090x_P1_DMDTOM, 0x20 },
254 { STV090x_P1_CARFREQ, 0xed },
255 { STV090x_P1_LDT, 0xd0 },
256 { STV090x_P1_LDT2, 0xb8 },
257 { STV090x_P1_TMGCFG, 0xd2 },
258 { STV090x_P1_TMGTHRISE, 0x20 },
259 { STV090x_P1_TMGTHFALL, 0x00 },
260 { STV090x_P1_SFRUPRATIO, 0xf0 },
261 { STV090x_P1_SFRLOWRATIO, 0x70 },
262 { STV090x_P1_TSCFGL, 0x20 },
263 { STV090x_P1_FECSPY, 0x88 },
264 { STV090x_P1_FSPYDATA, 0x3a },
265 { STV090x_P1_FBERCPT4, 0x00 },
266 { STV090x_P1_FSPYBER, 0x10 },
267 { STV090x_P1_ERRCTRL1, 0x35 },
268 { STV090x_P1_ERRCTRL2, 0xc1 },
269 { STV090x_P1_CFRICFG, 0xf8 },
270 { STV090x_P1_NOSCFG, 0x1c },
271 { STV090x_P1_CORRELMANT, 0x70 },
272 { STV090x_P1_CORRELABS, 0x88 },
273 { STV090x_P1_AGC2O, 0x5b },
274 { STV090x_P1_AGC2REF, 0x38 },
275 { STV090x_P1_CARCFG, 0xe4 },
276 { STV090x_P1_ACLC, 0x1A },
277 { STV090x_P1_BCLC, 0x09 },
278 { STV090x_P1_CARHDR, 0x08 },
279 { STV090x_P1_KREFTMG, 0xc1 },
280 { STV090x_P1_SFRSTEP, 0x58 },
281 { STV090x_P1_TMGCFG2, 0x01 },
282 { STV090x_P1_CAR2CFG, 0x26 },
283 { STV090x_P1_BCLC2S2Q, 0x86 },
284 { STV090x_P1_BCLC2S28, 0x86 },
285 { STV090x_P1_SMAPCOEF7, 0x77 },
286 { STV090x_P1_SMAPCOEF6, 0x85 },
287 { STV090x_P1_SMAPCOEF5, 0x77 },
288 { STV090x_P1_DMDCFG2, 0x3b },
289 { STV090x_P1_MODCODLST0, 0xff },
290 { STV090x_P1_MODCODLST1, 0xff },
291 { STV090x_P1_MODCODLST2, 0xff },
292 { STV090x_P1_MODCODLST3, 0xff },
293 { STV090x_P1_MODCODLST4, 0xff },
294 { STV090x_P1_MODCODLST5, 0xff },
295 { STV090x_P1_MODCODLST6, 0xff },
296 { STV090x_P1_MODCODLST7, 0xcc },
297 { STV090x_P1_MODCODLST8, 0xcc },
298 { STV090x_P1_MODCODLST9, 0xcc },
299 { STV090x_P1_MODCODLSTA, 0xcc },
300 { STV090x_P1_MODCODLSTB, 0xcc },
301 { STV090x_P1_MODCODLSTC, 0xcc },
302 { STV090x_P1_MODCODLSTD, 0xcc },
303 { STV090x_P1_MODCODLSTE, 0xcc },
304 { STV090x_P1_MODCODLSTF, 0xcf },
305 { STV090x_GENCFG, 0x1d },
306 { STV090x_NBITER_NF4, 0x37 },
307 { STV090x_NBITER_NF5, 0x29 },
308 { STV090x_NBITER_NF6, 0x37 },
309 { STV090x_NBITER_NF7, 0x33 },
310 { STV090x_NBITER_NF8, 0x31 },
311 { STV090x_NBITER_NF9, 0x2f },
312 { STV090x_NBITER_NF10, 0x39 },
313 { STV090x_NBITER_NF11, 0x3a },
314 { STV090x_NBITER_NF12, 0x29 },
315 { STV090x_NBITER_NF13, 0x37 },
316 { STV090x_NBITER_NF14, 0x33 },
317 { STV090x_NBITER_NF15, 0x2f },
318 { STV090x_NBITER_NF16, 0x39 },
319 { STV090x_NBITER_NF17, 0x3a },
320 { STV090x_NBITERNOERR, 0x04 },
321 { STV090x_GAINLLR_NF4, 0x0C },
322 { STV090x_GAINLLR_NF5, 0x0F },
323 { STV090x_GAINLLR_NF6, 0x11 },
324 { STV090x_GAINLLR_NF7, 0x14 },
325 { STV090x_GAINLLR_NF8, 0x17 },
326 { STV090x_GAINLLR_NF9, 0x19 },
327 { STV090x_GAINLLR_NF10, 0x20 },
328 { STV090x_GAINLLR_NF11, 0x21 },
329 { STV090x_GAINLLR_NF12, 0x0D },
330 { STV090x_GAINLLR_NF13, 0x0F },
331 { STV090x_GAINLLR_NF14, 0x13 },
332 { STV090x_GAINLLR_NF15, 0x1A },
333 { STV090x_GAINLLR_NF16, 0x1F },
334 { STV090x_GAINLLR_NF17, 0x21 },
335 { STV090x_RCCFGH, 0x20 },
336 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
337 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
338 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
339 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
342 static struct stv090x_reg stv0903_initval[] = {
343 { STV090x_OUTCFG, 0x00 },
344 { STV090x_AGCRF1CFG, 0x11 },
345 { STV090x_STOPCLK1, 0x48 },
346 { STV090x_STOPCLK2, 0x14 },
347 { STV090x_TSTTNR1, 0x27 },
348 { STV090x_TSTTNR2, 0x21 },
349 { STV090x_P1_DISTXCTL, 0x22 },
350 { STV090x_P1_F22TX, 0xc0 },
351 { STV090x_P1_F22RX, 0xc0 },
352 { STV090x_P1_DISRXCTL, 0x00 },
353 { STV090x_P1_DMDCFGMD, 0xF9 },
354 { STV090x_P1_DEMOD, 0x08 },
355 { STV090x_P1_DMDCFG3, 0xc4 },
356 { STV090x_P1_CARFREQ, 0xed },
357 { STV090x_P1_TNRCFG2, 0x82 },
358 { STV090x_P1_LDT, 0xd0 },
359 { STV090x_P1_LDT2, 0xb8 },
360 { STV090x_P1_TMGCFG, 0xd2 },
361 { STV090x_P1_TMGTHRISE, 0x20 },
362 { STV090x_P1_TMGTHFALL, 0x00 },
363 { STV090x_P1_SFRUPRATIO, 0xf0 },
364 { STV090x_P1_SFRLOWRATIO, 0x70 },
365 { STV090x_P1_TSCFGL, 0x20 },
366 { STV090x_P1_FECSPY, 0x88 },
367 { STV090x_P1_FSPYDATA, 0x3a },
368 { STV090x_P1_FBERCPT4, 0x00 },
369 { STV090x_P1_FSPYBER, 0x10 },
370 { STV090x_P1_ERRCTRL1, 0x35 },
371 { STV090x_P1_ERRCTRL2, 0xc1 },
372 { STV090x_P1_CFRICFG, 0xf8 },
373 { STV090x_P1_NOSCFG, 0x1c },
374 { STV090x_P1_DMDTOM, 0x20 },
375 { STV090x_P1_CORRELMANT, 0x70 },
376 { STV090x_P1_CORRELABS, 0x88 },
377 { STV090x_P1_AGC2O, 0x5b },
378 { STV090x_P1_AGC2REF, 0x38 },
379 { STV090x_P1_CARCFG, 0xe4 },
380 { STV090x_P1_ACLC, 0x1A },
381 { STV090x_P1_BCLC, 0x09 },
382 { STV090x_P1_CARHDR, 0x08 },
383 { STV090x_P1_KREFTMG, 0xc1 },
384 { STV090x_P1_SFRSTEP, 0x58 },
385 { STV090x_P1_TMGCFG2, 0x01 },
386 { STV090x_P1_CAR2CFG, 0x26 },
387 { STV090x_P1_BCLC2S2Q, 0x86 },
388 { STV090x_P1_BCLC2S28, 0x86 },
389 { STV090x_P1_SMAPCOEF7, 0x77 },
390 { STV090x_P1_SMAPCOEF6, 0x85 },
391 { STV090x_P1_SMAPCOEF5, 0x77 },
392 { STV090x_P1_DMDCFG2, 0x3b },
393 { STV090x_P1_MODCODLST0, 0xff },
394 { STV090x_P1_MODCODLST1, 0xff },
395 { STV090x_P1_MODCODLST2, 0xff },
396 { STV090x_P1_MODCODLST3, 0xff },
397 { STV090x_P1_MODCODLST4, 0xff },
398 { STV090x_P1_MODCODLST5, 0xff },
399 { STV090x_P1_MODCODLST6, 0xff },
400 { STV090x_P1_MODCODLST7, 0xcc },
401 { STV090x_P1_MODCODLST8, 0xcc },
402 { STV090x_P1_MODCODLST9, 0xcc },
403 { STV090x_P1_MODCODLSTA, 0xcc },
404 { STV090x_P1_MODCODLSTB, 0xcc },
405 { STV090x_P1_MODCODLSTC, 0xcc },
406 { STV090x_P1_MODCODLSTD, 0xcc },
407 { STV090x_P1_MODCODLSTE, 0xcc },
408 { STV090x_P1_MODCODLSTF, 0xcf },
409 { STV090x_GENCFG, 0x1c },
410 { STV090x_NBITER_NF4, 0x37 },
411 { STV090x_NBITER_NF5, 0x29 },
412 { STV090x_NBITER_NF6, 0x37 },
413 { STV090x_NBITER_NF7, 0x33 },
414 { STV090x_NBITER_NF8, 0x31 },
415 { STV090x_NBITER_NF9, 0x2f },
416 { STV090x_NBITER_NF10, 0x39 },
417 { STV090x_NBITER_NF11, 0x3a },
418 { STV090x_NBITER_NF12, 0x29 },
419 { STV090x_NBITER_NF13, 0x37 },
420 { STV090x_NBITER_NF14, 0x33 },
421 { STV090x_NBITER_NF15, 0x2f },
422 { STV090x_NBITER_NF16, 0x39 },
423 { STV090x_NBITER_NF17, 0x3a },
424 { STV090x_NBITERNOERR, 0x04 },
425 { STV090x_GAINLLR_NF4, 0x0C },
426 { STV090x_GAINLLR_NF5, 0x0F },
427 { STV090x_GAINLLR_NF6, 0x11 },
428 { STV090x_GAINLLR_NF7, 0x14 },
429 { STV090x_GAINLLR_NF8, 0x17 },
430 { STV090x_GAINLLR_NF9, 0x19 },
431 { STV090x_GAINLLR_NF10, 0x20 },
432 { STV090x_GAINLLR_NF11, 0x21 },
433 { STV090x_GAINLLR_NF12, 0x0D },
434 { STV090x_GAINLLR_NF13, 0x0F },
435 { STV090x_GAINLLR_NF14, 0x13 },
436 { STV090x_GAINLLR_NF15, 0x1A },
437 { STV090x_GAINLLR_NF16, 0x1F },
438 { STV090x_GAINLLR_NF17, 0x21 },
439 { STV090x_RCCFGH, 0x20 },
440 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
441 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
444 static struct stv090x_reg stv0900_cut20_val[] = {
446 { STV090x_P2_DMDCFG3, 0xe8 },
447 { STV090x_P2_DMDCFG4, 0x10 },
448 { STV090x_P2_CARFREQ, 0x38 },
449 { STV090x_P2_CARHDR, 0x20 },
450 { STV090x_P2_KREFTMG, 0x5a },
451 { STV090x_P2_SMAPCOEF7, 0x06 },
452 { STV090x_P2_SMAPCOEF6, 0x00 },
453 { STV090x_P2_SMAPCOEF5, 0x04 },
454 { STV090x_P2_NOSCFG, 0x0c },
455 { STV090x_P1_DMDCFG3, 0xe8 },
456 { STV090x_P1_DMDCFG4, 0x10 },
457 { STV090x_P1_CARFREQ, 0x38 },
458 { STV090x_P1_CARHDR, 0x20 },
459 { STV090x_P1_KREFTMG, 0x5a },
460 { STV090x_P1_SMAPCOEF7, 0x06 },
461 { STV090x_P1_SMAPCOEF6, 0x00 },
462 { STV090x_P1_SMAPCOEF5, 0x04 },
463 { STV090x_P1_NOSCFG, 0x0c },
464 { STV090x_GAINLLR_NF4, 0x21 },
465 { STV090x_GAINLLR_NF5, 0x21 },
466 { STV090x_GAINLLR_NF6, 0x20 },
467 { STV090x_GAINLLR_NF7, 0x1F },
468 { STV090x_GAINLLR_NF8, 0x1E },
469 { STV090x_GAINLLR_NF9, 0x1E },
470 { STV090x_GAINLLR_NF10, 0x1D },
471 { STV090x_GAINLLR_NF11, 0x1B },
472 { STV090x_GAINLLR_NF12, 0x20 },
473 { STV090x_GAINLLR_NF13, 0x20 },
474 { STV090x_GAINLLR_NF14, 0x20 },
475 { STV090x_GAINLLR_NF15, 0x20 },
476 { STV090x_GAINLLR_NF16, 0x20 },
477 { STV090x_GAINLLR_NF17, 0x21 },
480 static struct stv090x_reg stv0903_cut20_val[] = {
481 { STV090x_P1_DMDCFG3, 0xe8 },
482 { STV090x_P1_DMDCFG4, 0x10 },
483 { STV090x_P1_CARFREQ, 0x38 },
484 { STV090x_P1_CARHDR, 0x20 },
485 { STV090x_P1_KREFTMG, 0x5a },
486 { STV090x_P1_SMAPCOEF7, 0x06 },
487 { STV090x_P1_SMAPCOEF6, 0x00 },
488 { STV090x_P1_SMAPCOEF5, 0x04 },
489 { STV090x_P1_NOSCFG, 0x0c },
490 { STV090x_GAINLLR_NF4, 0x21 },
491 { STV090x_GAINLLR_NF5, 0x21 },
492 { STV090x_GAINLLR_NF6, 0x20 },
493 { STV090x_GAINLLR_NF7, 0x1F },
494 { STV090x_GAINLLR_NF8, 0x1E },
495 { STV090x_GAINLLR_NF9, 0x1E },
496 { STV090x_GAINLLR_NF10, 0x1D },
497 { STV090x_GAINLLR_NF11, 0x1B },
498 { STV090x_GAINLLR_NF12, 0x20 },
499 { STV090x_GAINLLR_NF13, 0x20 },
500 { STV090x_GAINLLR_NF14, 0x20 },
501 { STV090x_GAINLLR_NF15, 0x20 },
502 { STV090x_GAINLLR_NF16, 0x20 },
503 { STV090x_GAINLLR_NF17, 0x21 }
506 /* Cut 1.x Long Frame Tracking CR loop */
507 static struct stv090x_long_frame_crloop stv090x_s2_crl[] = {
508 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
509 { STV090x_QPSK_12, 0x1c, 0x0d, 0x1b, 0x2c, 0x3a, 0x1c, 0x2a, 0x3b, 0x2a, 0x1b },
510 { STV090x_QPSK_35, 0x2c, 0x0d, 0x2b, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b, 0x2a, 0x0b },
511 { STV090x_QPSK_23, 0x2c, 0x0d, 0x2b, 0x2c, 0x0b, 0x0c, 0x3a, 0x1b, 0x2a, 0x3a },
512 { STV090x_QPSK_34, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
513 { STV090x_QPSK_45, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
514 { STV090x_QPSK_56, 0x0d, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
515 { STV090x_QPSK_89, 0x0d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
516 { STV090x_QPSK_910, 0x1d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
517 { STV090x_8PSK_35, 0x29, 0x3b, 0x09, 0x2b, 0x38, 0x0b, 0x18, 0x1a, 0x08, 0x0a },
518 { STV090x_8PSK_23, 0x0a, 0x3b, 0x29, 0x2b, 0x19, 0x0b, 0x38, 0x1a, 0x18, 0x0a },
519 { STV090x_8PSK_34, 0x3a, 0x3b, 0x2a, 0x2b, 0x39, 0x0b, 0x19, 0x1a, 0x38, 0x0a },
520 { STV090x_8PSK_56, 0x1b, 0x3b, 0x0b, 0x2b, 0x1a, 0x0b, 0x39, 0x1a, 0x19, 0x0a },
521 { STV090x_8PSK_89, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 },
522 { STV090x_8PSK_910, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 }
525 /* Cut 2.0 Long Frame Tracking CR loop */
526 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
527 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
528 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
529 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
530 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
531 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
532 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
533 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
534 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
535 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
536 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
537 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
538 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
539 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
540 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
541 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
545 /* Cut 2.0 Long Frame Tracking CR Loop */
546 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
547 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
548 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
549 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
550 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
551 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
552 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
553 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
554 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
555 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
556 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
557 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
558 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
562 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
563 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
564 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
565 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
566 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
570 /* Cut 1.2 & 2.0 Short Frame Tracking CR Loop */
571 static struct stv090x_short_frame_crloop stv090x_s2_short_crl[] = {
572 /* MODCOD 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
573 { STV090x_QPSK, 0x3c, 0x2f, 0x2b, 0x2e, 0x0b, 0x0e, 0x3a, 0x0e, 0x2a, 0x3d },
574 { STV090x_8PSK, 0x0b, 0x3e, 0x2a, 0x0e, 0x0a, 0x2d, 0x19, 0x0d, 0x09, 0x3c },
575 { STV090x_16APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d },
576 { STV090x_32APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d }
580 static inline s32 comp2(s32 __x, s32 __width)
585 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
588 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
590 const struct stv090x_config *config = state->config;
593 u8 b0[] = { reg >> 8, reg & 0xff };
596 struct i2c_msg msg[] = {
597 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
598 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
601 ret = i2c_transfer(state->i2c, msg, 2);
603 if (ret != -ERESTARTSYS)
605 "Read error, Reg=[0x%02x], Status=%d",
608 return ret < 0 ? ret : -EREMOTEIO;
610 if (unlikely(*state->verbose >= FE_DEBUGREG))
611 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
614 return (unsigned int) buf;
617 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
619 const struct stv090x_config *config = state->config;
622 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
626 memcpy(&buf[2], data, count);
628 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
631 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
632 for (i = 0; i < count; i++)
633 printk(" %02x", data[i]);
637 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
639 if (ret != -ERESTARTSYS)
640 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
641 reg, data[0], count, ret);
642 return ret < 0 ? ret : -EREMOTEIO;
648 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
650 return stv090x_write_regs(state, reg, &data, 1);
653 static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
655 struct stv090x_state *state = fe->demodulator_priv;
658 reg = STV090x_READ_DEMOD(state, I2CRPT);
660 dprintk(FE_DEBUG, 1, "Enable Gate");
661 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
662 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
666 dprintk(FE_DEBUG, 1, "Disable Gate");
667 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
668 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
673 dprintk(FE_ERROR, 1, "I/O error");
677 static void stv090x_get_lock_tmg(struct stv090x_state *state)
679 switch (state->algo) {
680 case STV090x_BLIND_SEARCH:
681 dprintk(FE_DEBUG, 1, "Blind Search");
682 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
683 state->DemodTimeout = 1500;
684 state->FecTimeout = 400;
685 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
686 state->DemodTimeout = 1000;
687 state->FecTimeout = 300;
688 } else { /*SR >20Msps*/
689 state->DemodTimeout = 700;
690 state->FecTimeout = 100;
694 case STV090x_COLD_SEARCH:
695 case STV090x_WARM_SEARCH:
697 dprintk(FE_DEBUG, 1, "Normal Search");
698 if (state->srate <= 1000000) { /*SR <=1Msps*/
699 state->DemodTimeout = 4500;
700 state->FecTimeout = 1700;
701 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
702 state->DemodTimeout = 2500;
703 state->FecTimeout = 1100;
704 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
705 state->DemodTimeout = 1000;
706 state->FecTimeout = 550;
707 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
708 state->DemodTimeout = 700;
709 state->FecTimeout = 250;
710 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
711 state->DemodTimeout = 400;
712 state->FecTimeout = 130;
713 } else { /*SR >20Msps*/
714 state->DemodTimeout = 300;
715 state->FecTimeout = 100;
720 if (state->algo == STV090x_WARM_SEARCH)
721 state->DemodTimeout /= 2;
724 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
728 if (srate > 6000000) {
729 sym = (srate / 1000) * 65536;
730 sym /= (state->mclk / 1000);
732 sym = (srate / 100) * 65536;
733 sym /= (state->mclk / 100);
736 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) /* MSB */
738 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
742 dprintk(FE_ERROR, 1, "I/O error");
746 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
750 srate = 105 * (srate / 100);
751 if (srate > 6000000) {
752 sym = (srate / 1000) * 65536;
755 sym = (srate / 100) * 65536;
758 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
760 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
764 dprintk(FE_ERROR, 1, "I/O error");
768 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
772 srate = 95 * (srate / 100);
773 if (srate > 6000000) {
774 sym = (srate / 1000) * 65536;
777 sym = (srate / 100) * 65536;
780 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
782 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
786 dprintk(FE_ERROR, 1, "I/O error");
790 static u32 stv090x_car_width(u32 srate, u32 rolloff)
792 return srate + (srate * rolloff) / 100;
795 static int stv090x_set_vit_thacq(struct stv090x_state *state)
797 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
799 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
801 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
803 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
805 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
807 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
811 dprintk(FE_ERROR, 1, "I/O error");
815 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
817 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
819 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
821 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
823 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
825 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
827 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
831 dprintk(FE_ERROR, 1, "I/O error");
835 static int stv090x_set_viterbi(struct stv090x_state *state)
837 switch (state->search_mode) {
838 case STV090x_SEARCH_AUTO:
839 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
841 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
844 case STV090x_SEARCH_DVBS1:
845 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
847 switch (state->fec) {
849 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
854 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
859 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
864 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
869 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
874 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
879 case STV090x_SEARCH_DSS:
880 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
882 switch (state->fec) {
884 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
889 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
894 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
899 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
909 dprintk(FE_ERROR, 1, "I/O error");
913 static int stv090x_stop_modcod(struct stv090x_state *state)
915 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
917 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
919 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
921 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
923 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
925 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
927 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
929 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
931 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
933 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
935 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
937 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
939 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
941 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
943 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
945 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
949 dprintk(FE_ERROR, 1, "I/O error");
953 static int stv090x_activate_modcod(struct stv090x_state *state)
955 u32 matype, modcod, f_mod, index;
957 if (state->dev_ver <= 0x11) {
959 modcod = STV090x_READ_DEMOD(state, PLHMODCOD);
960 matype = modcod & 0x03;
961 modcod = (modcod & 0x7f) >> 2;
962 index = STV090x_ADDR_OFFST(state, MODCODLSTF) - (modcod / 2);
981 if (stv090x_write_reg(state, index, 0xf0 | f_mod) < 0)
984 if (stv090x_write_reg(state, index, (f_mod << 4) | 0x0f) < 0)
988 } else if (state->dev_ver >= 0x12) {
989 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
991 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
993 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
995 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
997 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
999 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1001 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1003 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1005 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1007 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1009 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1011 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1013 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1015 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1017 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1019 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1024 dprintk(FE_ERROR, 1, "I/O error");
1028 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1032 switch (state->demod) {
1033 case STV090x_DEMODULATOR_0:
1034 mutex_lock(&demod_lock);
1035 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1036 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1037 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1039 mutex_unlock(&demod_lock);
1042 case STV090x_DEMODULATOR_1:
1043 mutex_lock(&demod_lock);
1044 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1045 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1046 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1048 mutex_unlock(&demod_lock);
1052 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1057 mutex_unlock(&demod_lock);
1058 dprintk(FE_ERROR, 1, "I/O error");
1062 static int stv090x_delivery_search(struct stv090x_state *state)
1066 switch (state->search_mode) {
1067 case STV090x_SEARCH_DVBS1:
1068 case STV090x_SEARCH_DSS:
1069 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1070 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1071 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1072 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1075 /* Activate Viterbi decoder in legacy search, do not use FRESVIT1, might impact VITERBI2 */
1076 if (stv090x_vitclk_ctl(state, 0) < 0)
1079 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1081 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1083 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1086 stv090x_set_vit_thacq(state);
1087 stv090x_set_viterbi(state);
1090 case STV090x_SEARCH_DVBS2:
1091 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1092 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1093 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1094 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1096 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1097 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1098 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1101 if (stv090x_vitclk_ctl(state, 1) < 0)
1104 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1106 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1108 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1111 if (state->demod_mode != STV090x_SINGLE) {
1112 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1113 stv090x_stop_modcod(state);
1115 stv090x_activate_modcod(state);
1119 case STV090x_SEARCH_AUTO:
1121 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1122 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1123 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1124 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1126 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1127 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1128 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1131 if (stv090x_vitclk_ctl(state, 1) < 0)
1134 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1136 if (STV090x_WRITE_DEMOD(state, ACLC, 0x09) < 0)
1138 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1141 if (state->demod_mode != STV090x_SINGLE) {
1142 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1143 stv090x_stop_modcod(state);
1145 stv090x_activate_modcod(state);
1147 stv090x_set_vit_thacq(state);
1148 stv090x_set_viterbi(state);
1153 dprintk(FE_ERROR, 1, "I/O error");
1157 static int stv090x_start_search(struct stv090x_state *state)
1161 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1162 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1163 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1166 if (state->dev_ver == 0x10) {
1167 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1170 if (state->dev_ver < 0x20) {
1171 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1174 if (state->srate <= 5000000) {
1175 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1177 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1179 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
1181 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1183 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1186 /*enlarge the timing bandwith for Low SR*/
1187 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1190 /* If the symbol rate is >5 Msps
1191 Set The carrier search up and low to auto mode */
1192 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1194 /*reduce the timing bandwith for high SR*/
1195 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1198 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1200 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1203 if (state->dev_ver >= 0x20) {
1204 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1206 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1209 if ((state->search_mode == STV090x_DVBS1) ||
1210 (state->search_mode == STV090x_DSS) ||
1211 (state->search_mode == STV090x_SEARCH_AUTO)) {
1213 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1215 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1220 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1222 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1224 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1227 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1228 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1229 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1230 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1232 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1233 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1234 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1237 if (state->dev_ver >= 0x20) { /*Frequency offset detector setting*/
1238 if (state->srate < 10000000) {
1239 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1242 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1246 if (state->srate < 10000000) {
1247 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1250 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1255 switch (state->algo) {
1256 case STV090x_WARM_SEARCH:/*The symbol rate and the exact carrier Frequency are known */
1257 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1259 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1263 case STV090x_COLD_SEARCH:/*The symbol rate is known*/
1264 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1266 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1275 dprintk(FE_ERROR, 1, "I/O error");
1279 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1281 u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
1282 s32 i, j, steps, dir;
1284 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1286 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1287 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1288 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1289 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1292 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1294 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1296 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1298 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1300 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1302 stv090x_set_srate(state, 1000000);
1304 steps = -1 + state->search_range / 1000000;
1306 steps = (2 * steps) + 1;
1311 freq_step = (1000000 * 256) / (state->mclk / 256);
1314 for (i = 0; i < steps; i++) {
1316 freq_init = freq_init + (freq_step * i);
1318 freq_init = freq_init - (freq_step * i);
1322 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1324 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1326 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1328 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1331 for (j = 0; j < 10; j++) {
1332 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1333 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1343 dprintk(FE_ERROR, 1, "I/O error");
1347 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1350 s32 srate, int_1, int_2, tmp_1, tmp_2;
1353 r3 = STV090x_READ_DEMOD(state, SFR3);
1354 r2 = STV090x_READ_DEMOD(state, SFR2);
1355 r1 = STV090x_READ_DEMOD(state, SFR1);
1356 r0 = STV090x_READ_DEMOD(state, SFR0);
1358 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1362 int_2 = srate / pow2;
1365 tmp_2 = srate % pow2;
1367 srate = (int_1 * int_2) +
1368 ((int_1 * tmp_2) / pow2) +
1369 ((int_2 * tmp_1) / pow2);
1374 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1376 struct dvb_frontend *fe = &state->frontend;
1378 int tmg_lock = 0, i;
1379 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1380 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1382 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1383 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1384 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1386 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1388 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1390 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1392 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1393 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1394 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1395 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1398 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1400 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1402 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1404 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1406 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1408 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
1411 if (state->dev_ver >= 0x20) {
1412 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1414 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1417 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1419 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x73) < 0)
1423 if (state->srate <= 2000000)
1425 else if (state->srate <= 5000000)
1427 else if (state->srate <= 12000000)
1432 steps = -1 + ((state->search_range / 1000) / car_step);
1434 steps = (2 * steps) + 1;
1437 else if (steps > 10) {
1439 car_step = (state->search_range / 1000) / 10;
1443 freq = state->frequency;
1445 while ((!tmg_lock) && (cur_step < steps)) {
1446 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1448 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1449 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
1450 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1453 for (i = 0; i < 10; i++) {
1454 reg = STV090x_READ_DEMOD(state, DSTATUS);
1455 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1457 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1458 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1461 srate_coarse = stv090x_get_srate(state, state->mclk);
1464 if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
1466 else if (cur_step < steps) {
1468 freq += cur_step * car_step;
1470 freq -= cur_step * car_step;
1473 stv090x_i2c_gate_ctrl(fe, 1);
1475 if (state->config->tuner_set_frequency)
1476 state->config->tuner_set_frequency(fe, state->frequency);
1478 if (state->config->tuner_set_bandwidth)
1479 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1481 stv090x_i2c_gate_ctrl(fe, 0);
1483 stv090x_i2c_gate_ctrl(fe, 1);
1485 if (state->config->tuner_get_status)
1486 state->config->tuner_get_status(fe, ®);
1489 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1491 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1493 stv090x_i2c_gate_ctrl(fe, 0);
1500 srate_coarse = stv090x_get_srate(state, state->mclk);
1502 return srate_coarse;
1504 dprintk(FE_ERROR, 1, "I/O error");
1508 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1510 u32 srate_coarse, freq_coarse, sym, reg;
1512 srate_coarse = stv090x_get_srate(state, state->mclk);
1513 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1514 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1515 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1517 if (sym < state->srate)
1520 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1522 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
1524 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1526 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1528 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1530 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1531 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1532 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1535 if (state->dev_ver >= 0x20) {
1536 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1539 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1543 if (srate_coarse > 3000000) {
1544 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1545 sym = (sym / 1000) * 65536;
1546 sym /= (state->mclk / 1000);
1547 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1549 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1551 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1552 sym = (sym / 1000) * 65536;
1553 sym /= (state->mclk / 1000);
1554 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1556 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1558 sym = (srate_coarse / 1000) * 65536;
1559 sym /= (state->mclk / 1000);
1560 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1562 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1565 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1566 sym = (sym / 100) * 65536;
1567 sym /= (state->mclk / 100);
1568 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1570 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1572 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1573 sym = (sym / 100) * 65536;
1574 sym /= (state->mclk / 100);
1575 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1577 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1579 sym = (srate_coarse / 100) * 65536;
1580 sym /= (state->mclk / 100);
1581 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1583 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1586 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1588 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1590 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1592 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1596 return srate_coarse;
1599 dprintk(FE_ERROR, 1, "I/O error");
1603 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1605 s32 timer = 0, lock = 0;
1609 while ((timer < timeout) && (!lock)) {
1610 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1611 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1614 case 0: /* searching */
1615 case 1: /* first PLH detected */
1617 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1620 case 2: /* DVB-S2 mode */
1621 case 3: /* DVB-S1/legacy mode */
1622 reg = STV090x_READ_DEMOD(state, DSTATUS);
1623 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1630 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1637 static int stv090x_blind_search(struct stv090x_state *state)
1639 u32 agc2, reg, srate_coarse;
1640 s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
1641 u8 k_ref, k_max, k_min;
1642 int coarse_fail, lock;
1644 if (state->dev_ver < 0x20) {
1652 agc2 = stv090x_get_agc2_min_level(state);
1654 if (agc2 > STV090x_SEARCH_AGC2_TH) {
1657 if (state->dev_ver == 0x10) {
1658 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1661 if (state->dev_ver < 0x20) {
1662 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1666 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1668 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1670 if (state->dev_ver >= 0x20) {
1671 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1673 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1675 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1677 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1683 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
1685 if (stv090x_srate_srch_coarse(state) != 0) {
1686 srate_coarse = stv090x_srate_srch_fine(state);
1687 if (srate_coarse != 0) {
1688 stv090x_get_lock_tmg(state);
1689 lock = stv090x_get_dmdlock(state, timeout_dmd);
1696 for (i = 0; i < 10; i++) {
1697 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1698 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1701 reg = STV090x_READ_DEMOD(state, DSTATUS2);
1702 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
1703 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
1707 if ((cpt_fail > 7) || (agc2_ovflw > 7))
1713 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1719 dprintk(FE_ERROR, 1, "I/O error");
1723 static int stv090x_chk_tmg(struct stv090x_state *state)
1727 u8 freq, tmg_thh, tmg_thl;
1730 freq = STV090x_READ_DEMOD(state, CARFREQ);
1731 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
1732 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
1733 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1735 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1738 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1739 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
1740 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1742 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
1745 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
1747 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
1750 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
1752 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1754 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
1757 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
1761 for (i = 0; i < 10; i++) {
1762 reg = STV090x_READ_DEMOD(state, DSTATUS);
1763 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1770 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1772 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
1774 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
1777 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
1779 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
1781 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
1787 dprintk(FE_ERROR, 1, "I/O error");
1791 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
1793 struct dvb_frontend *fe = &state->frontend;
1796 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
1799 if (state->srate >= 10000000)
1800 timeout_lock = timeout_dmd / 3;
1802 timeout_lock = timeout_dmd / 2;
1804 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
1806 if (state->srate >= 10000000) {
1807 if (stv090x_chk_tmg(state)) {
1808 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1810 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1812 lock = stv090x_get_dmdlock(state, timeout_dmd);
1817 if (state->srate <= 4000000)
1819 else if (state->srate <= 7000000)
1821 else if (state->srate <= 10000000)
1826 steps = (state->search_range / 1000) / car_step;
1828 steps = 2 * (steps + 1);
1831 else if (steps > 12)
1838 freq = state->frequency;
1839 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
1840 while ((cur_step <= steps) && (!lock)) {
1842 freq += cur_step * car_step;
1844 freq -= cur_step * car_step;
1847 stv090x_i2c_gate_ctrl(fe, 1);
1849 if (state->config->tuner_set_frequency)
1850 state->config->tuner_set_frequency(fe, state->frequency);
1852 if (state->config->tuner_set_bandwidth)
1853 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1855 stv090x_i2c_gate_ctrl(fe, 0);
1859 stv090x_i2c_gate_ctrl(fe, 1);
1861 if (state->config->tuner_get_status)
1862 state->config->tuner_get_status(fe, ®);
1865 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1867 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1869 stv090x_i2c_gate_ctrl(fe, 0);
1871 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
1872 if (state->delsys == STV090x_DVBS2) {
1873 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1874 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1875 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1876 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1878 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1879 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1880 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1883 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1885 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1887 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1889 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1891 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
1903 dprintk(FE_ERROR, 1, "I/O error");
1907 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
1909 s32 timeout, inc, steps_max, srate, car_max;
1911 srate = state->srate;
1912 car_max = state->search_range / 1000;
1913 car_max = 65536 * (car_max / 2);
1914 car_max /= (state->mclk / 1000);
1916 if (car_max > 0x4000)
1917 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
1920 inc /= state->mclk / 1000;
1925 switch (state->search_mode) {
1926 case STV090x_SEARCH_DVBS1:
1927 case STV090x_SEARCH_DSS:
1928 inc *= 3; /* freq step = 3% of srate */
1932 case STV090x_SEARCH_DVBS2:
1937 case STV090x_SEARCH_AUTO:
1944 if ((inc > car_max) || (inc < 0))
1945 inc = car_max / 2; /* increment <= 1/8 Mclk */
1947 timeout *= 27500; /* 27.5 Msps reference */
1949 timeout /= (srate / 1000);
1951 if ((timeout > 100) || (timeout < 0))
1954 steps_max = (car_max / inc) + 1; /* min steps = 3 */
1955 if ((steps_max > 100) || (steps_max < 0)) {
1956 steps_max = 100; /* max steps <= 100 */
1957 inc = car_max / steps_max;
1960 *timeout_sw = timeout;
1966 static int stv090x_chk_signal(struct stv090x_state *state)
1968 s32 offst_car, agc2, car_max;
1971 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
1972 offst_car |= STV090x_READ_DEMOD(state, CFR1);
1974 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1975 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1976 car_max = state->search_range / 1000;
1978 car_max += (car_max / 10); /* 10% margin */
1979 car_max = (65536 * car_max / 2);
1980 car_max /= state->mclk / 1000;
1982 if (car_max > 0x4000)
1985 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
1987 dprintk(FE_DEBUG, 1, "No Signal");
1990 dprintk(FE_DEBUG, 1, "Found Signal");
1996 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
1998 int no_signal, lock = 0;
1999 s32 cpt_step, offst_freq, car_max;
2002 car_max = state->search_range / 1000;
2003 car_max += (car_max / 10);
2004 car_max = (65536 * car_max / 2);
2005 car_max /= (state->mclk / 1000);
2006 if (car_max > 0x4000)
2012 offst_freq = -car_max + inc;
2016 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2018 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2020 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2022 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2025 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2026 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2027 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2030 if (state->dev_ver == 0x12) {
2031 reg = STV090x_READ_DEMOD(state, TSCFGH);
2032 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x1);
2033 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2038 if (offst_freq >= 0)
2039 offst_freq = -offst_freq - 2 * inc;
2041 offst_freq = -offst_freq;
2043 offst_freq += 2 * inc;
2046 lock = stv090x_get_dmdlock(state, timeout);
2047 no_signal = stv090x_chk_signal(state);
2051 ((offst_freq - inc) < car_max) &&
2052 ((offst_freq + inc) > -car_max) &&
2053 (cpt_step < steps_max));
2055 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2056 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2057 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2062 dprintk(FE_ERROR, 1, "I/O error");
2066 static int stv090x_sw_algo(struct stv090x_state *state)
2068 int no_signal, zigzag, lock = 0;
2071 s32 dvbs2_fly_wheel;
2072 s32 inc, timeout_step, trials, steps_max;
2074 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); /* get params */
2076 switch (state->search_mode) {
2077 case STV090x_SEARCH_DVBS1:
2078 case STV090x_SEARCH_DSS:
2079 /* accelerate the frequency detector */
2080 if (state->dev_ver >= 0x20) {
2081 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2084 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2087 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2092 case STV090x_SEARCH_DVBS2:
2093 if (state->dev_ver >= 0x20) {
2094 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2097 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2100 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2105 case STV090x_SEARCH_AUTO:
2107 /* accelerate the frequency detector */
2108 if (state->dev_ver >= 0x20) {
2109 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2111 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2114 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2116 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2119 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x69) < 0)
2127 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2128 no_signal = stv090x_chk_signal(state);
2131 /*run the SW search 2 times maximum*/
2132 if (lock || no_signal || (trials == 2)) {
2133 /*Check if the demod is not losing lock in DVBS2*/
2134 if (state->dev_ver >= 0x20) {
2135 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2137 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2140 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
2142 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0)
2146 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2147 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2148 /*Check if the demod is not losing lock in DVBS2*/
2149 msleep(timeout_step);
2150 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2151 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2152 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2153 msleep(timeout_step);
2154 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2155 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2157 if (dvbs2_fly_wheel < 0xd) {
2158 /*FALSE lock, The demod is loosing lock */
2161 if (state->dev_ver >= 0x20) {
2162 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2165 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2168 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2174 } while ((!lock) && (trials < 2) && (!no_signal));
2178 dprintk(FE_ERROR, 1, "I/O error");
2182 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2185 enum stv090x_delsys delsys;
2187 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2188 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2189 delsys = STV090x_DVBS2;
2190 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2191 reg = STV090x_READ_DEMOD(state, FECM);
2192 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2193 delsys = STV090x_DSS;
2195 delsys = STV090x_DVBS1;
2197 delsys = STV090x_ERROR;
2204 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2206 s32 derot, int_1, int_2, tmp_1, tmp_2;
2209 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2210 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2211 derot |= STV090x_READ_DEMOD(state, CFR0);
2213 derot = comp2(derot, 24);
2215 int_1 = state->mclk / pow2;
2216 int_2 = derot / pow2;
2218 tmp_1 = state->mclk % pow2;
2219 tmp_2 = derot % pow2;
2221 derot = (int_1 * int_2) +
2222 ((int_1 * tmp_2) / pow2) +
2223 ((int_1 * tmp_1) / pow2);
2228 static int stv090x_get_viterbi(struct stv090x_state *state)
2232 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2233 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2237 state->fec = STV090x_PR12;
2241 state->fec = STV090x_PR23;
2245 state->fec = STV090x_PR34;
2249 state->fec = STV090x_PR56;
2253 state->fec = STV090x_PR67;
2257 state->fec = STV090x_PR78;
2261 state->fec = STV090x_PRERR;
2268 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2270 struct dvb_frontend *fe = &state->frontend;
2274 s32 i = 0, offst_freq;
2278 if (state->algo == STV090x_BLIND_SEARCH) {
2279 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2280 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2281 while ((i <= 50) && (!tmg) && (tmg != 0xff)) {
2282 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2287 state->delsys = stv090x_get_std(state);
2289 stv090x_i2c_gate_ctrl(fe, 1);
2291 if (state->config->tuner_get_frequency)
2292 state->config->tuner_get_frequency(fe, &state->frequency);
2294 stv090x_i2c_gate_ctrl(fe, 0);
2296 offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
2297 state->frequency += offst_freq;
2298 stv090x_get_viterbi(state);
2299 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2300 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2301 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2302 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2303 reg = STV090x_READ_DEMOD(state, TMGOBS);
2304 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2305 reg = STV090x_READ_DEMOD(state, FECM);
2306 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2308 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2310 stv090x_i2c_gate_ctrl(fe, 1);
2312 if (state->config->tuner_get_frequency)
2313 state->config->tuner_get_frequency(fe, &state->frequency);
2315 stv090x_i2c_gate_ctrl(fe, 0);
2317 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2318 return STV090x_RANGEOK;
2319 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2320 return STV090x_RANGEOK;
2322 return STV090x_OUTOFRANGE; /* Out of Range */
2324 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2325 return STV090x_RANGEOK;
2327 return STV090x_OUTOFRANGE;
2330 return STV090x_OUTOFRANGE;
2333 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2338 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2339 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2340 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2344 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2348 offst_tmg = ((s32) srate * 10) / (pow2 / offst_tmg);
2354 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2358 struct stv090x_long_frame_crloop *car_loop;
2360 if (state->dev_ver <= 0x12)
2361 car_loop = stv090x_s2_crl;
2362 else if (state->dev_ver == 0x20)
2363 car_loop = stv090x_s2_crl_cut20;
2365 car_loop = stv090x_s2_crl;
2368 if (modcod < STV090x_QPSK_12) {
2370 while ((i < 3) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2378 while ((i < 14) && (modcod != car_loop[i].modcod))
2383 while ((i < 11) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2391 if (modcod <= STV090x_QPSK_25) {
2393 if (state->srate <= 3000000)
2394 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_2;
2395 else if (state->srate <= 7000000)
2396 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_5;
2397 else if (state->srate <= 15000000)
2398 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_10;
2399 else if (state->srate <= 25000000)
2400 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_20;
2402 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_30;
2404 if (state->srate <= 3000000)
2405 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_2;
2406 else if (state->srate <= 7000000)
2407 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_5;
2408 else if (state->srate <= 15000000)
2409 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_10;
2410 else if (state->srate <= 25000000)
2411 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_20;
2413 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_30;
2416 } else if (modcod <= STV090x_8PSK_910) {
2418 if (state->srate <= 3000000)
2419 aclc = car_loop[i].crl_pilots_on_2;
2420 else if (state->srate <= 7000000)
2421 aclc = car_loop[i].crl_pilots_on_5;
2422 else if (state->srate <= 15000000)
2423 aclc = car_loop[i].crl_pilots_on_10;
2424 else if (state->srate <= 25000000)
2425 aclc = car_loop[i].crl_pilots_on_20;
2427 aclc = car_loop[i].crl_pilots_on_30;
2429 if (state->srate <= 3000000)
2430 aclc = car_loop[i].crl_pilots_off_2;
2431 else if (state->srate <= 7000000)
2432 aclc = car_loop[i].crl_pilots_off_5;
2433 else if (state->srate <= 15000000)
2434 aclc = car_loop[i].crl_pilots_off_10;
2435 else if (state->srate <= 25000000)
2436 aclc = car_loop[i].crl_pilots_off_20;
2438 aclc = car_loop[i].crl_pilots_off_30;
2440 } else { /* 16APSK and 32APSK */
2441 if (state->srate <= 3000000)
2442 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_2;
2443 else if (state->srate <= 7000000)
2444 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_5;
2445 else if (state->srate <= 15000000)
2446 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_10;
2447 else if (state->srate <= 25000000)
2448 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_20;
2450 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_30;
2456 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2461 switch (state->modulation) {
2469 case STV090x_16APSK:
2472 case STV090x_32APSK:
2477 switch (state->dev_ver) {
2479 if (state->srate <= 3000000)
2480 aclc = stv090x_s2_short_crl[index].crl_cut20_2;
2481 else if (state->srate <= 7000000)
2482 aclc = stv090x_s2_short_crl[index].crl_cut20_5;
2483 else if (state->srate <= 15000000)
2484 aclc = stv090x_s2_short_crl[index].crl_cut20_10;
2485 else if (state->srate <= 25000000)
2486 aclc = stv090x_s2_short_crl[index].crl_cut20_20;
2488 aclc = stv090x_s2_short_crl[index].crl_cut20_30;
2493 if (state->srate <= 3000000)
2494 aclc = stv090x_s2_short_crl[index].crl_cut12_2;
2495 else if (state->srate <= 7000000)
2496 aclc = stv090x_s2_short_crl[index].crl_cut12_5;
2497 else if (state->srate <= 15000000)
2498 aclc = stv090x_s2_short_crl[index].crl_cut12_10;
2499 else if (state->srate <= 25000000)
2500 aclc = stv090x_s2_short_crl[index].crl_cut12_20;
2502 aclc = stv090x_s2_short_crl[index].crl_cut12_30;
2509 static int stv090x_optimize_track(struct stv090x_state *state)
2511 struct dvb_frontend *fe = &state->frontend;
2513 enum stv090x_rolloff rolloff;
2514 enum stv090x_modcod modcod;
2516 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2519 srate = stv090x_get_srate(state, state->mclk);
2520 srate += stv090x_get_tmgoffst(state, srate);
2522 switch (state->delsys) {
2525 if (state->algo == STV090x_SEARCH_AUTO) {
2526 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2527 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2528 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2529 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2532 reg = STV090x_READ_DEMOD(state, DEMOD);
2533 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2534 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2535 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2537 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2542 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2543 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2544 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2545 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2547 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2549 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2551 if (state->frame_len == STV090x_LONG_FRAME) {
2552 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2553 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2554 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2555 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2556 if (modcod <= STV090x_QPSK_910) {
2557 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2558 } else if (modcod <= STV090x_8PSK_910) {
2559 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2561 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2564 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2565 if (modcod <= STV090x_16APSK_910) {
2566 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2568 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2571 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2573 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2578 /*Carrier loop setting for short frame*/
2579 aclc = stv090x_optimize_carloop_short(state);
2580 if (state->modulation == STV090x_QPSK) {
2581 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2583 } else if (state->modulation == STV090x_8PSK) {
2584 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2586 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2588 } else if (state->modulation == STV090x_16APSK) {
2589 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2591 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2593 } else if (state->modulation == STV090x_32APSK) {
2594 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2596 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2600 if (state->dev_ver <= 0x11) {
2601 if (state->demod_mode != STV090x_SINGLE)
2602 stv090x_activate_modcod(state); /* link to LDPC after demod LOCK */
2604 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2607 case STV090x_UNKNOWN:
2609 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2610 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2611 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2612 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2617 f_1 = STV090x_READ_DEMOD(state, CFR2);
2618 f_0 = STV090x_READ_DEMOD(state, CFR1);
2619 reg = STV090x_READ_DEMOD(state, TMGOBS);
2620 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2622 if (state->algo == STV090x_BLIND_SEARCH) {
2623 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2624 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2625 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2626 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2627 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2629 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
2631 stv090x_set_srate(state, srate);
2632 stv090x_set_max_srate(state, state->mclk, srate);
2633 stv090x_set_min_srate(state, state->mclk, srate);
2637 if (state->dev_ver >= 0x20) {
2638 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2639 (state->search_mode == STV090x_SEARCH_DSS) ||
2640 (state->search_mode == STV090x_SEARCH_AUTO)) {
2642 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2644 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2649 if (state->dev_ver < 0x20) {
2650 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x08) < 0)
2653 if (state->dev_ver == 0x10) {
2654 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0x0a) < 0)
2658 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2661 if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
2663 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2665 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2667 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2669 if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
2671 if (state->algo != STV090x_WARM_SEARCH) {
2673 stv090x_i2c_gate_ctrl(fe, 1);
2675 if (state->config->tuner_set_bandwidth)
2676 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2678 stv090x_i2c_gate_ctrl(fe, 0);
2682 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
2683 msleep(50); /* blind search: wait 50ms for SR stabilization */
2687 stv090x_get_lock_tmg(state);
2689 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
2690 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2692 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2694 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2696 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2701 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
2703 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2705 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2707 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2709 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2717 if (state->dev_ver >= 0x20) {
2718 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2721 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
2722 stv090x_set_vit_thtracq(state);
2726 dprintk(FE_ERROR, 1, "I/O error");
2730 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
2732 s32 timer = 0, lock = 0, stat;
2735 while ((timer < timeout) && (!lock)) {
2736 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2737 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
2740 case 0: /* searching */
2741 case 1: /* first PLH detected */
2746 case 2: /* DVB-S2 mode */
2747 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
2748 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
2751 case 3: /* DVB-S1/legacy mode */
2752 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
2753 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
2764 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
2770 lock = stv090x_get_dmdlock(state, timeout_dmd);
2772 lock = stv090x_get_feclock(state, timeout_fec);
2777 while ((timer < timeout_fec) && (!lock)) {
2778 reg = STV090x_READ_DEMOD(state, TSSTATUS);
2779 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
2788 static int stv090x_set_s2rolloff(struct stv090x_state *state)
2793 if (state->dev_ver == 0x10) {
2794 reg = STV090x_READ_DEMOD(state, DEMOD);
2795 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2796 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2798 rolloff = STV090x_READ_DEMOD(state, MATSTR1) & 0x03;
2799 reg = STV090x_READ_DEMOD(state, DEMOD);
2800 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, reg);
2801 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2804 reg = STV090x_READ_DEMOD(state, DEMOD);
2805 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x00);
2806 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2811 dprintk(FE_ERROR, 1, "I/O error");
2815 static enum stv090x_signal_state stv090x_acq_fixs1(struct stv090x_state *state)
2817 s32 srate, f_1, f_2;
2818 enum stv090x_signal_state signal_state = STV090x_NODATA;
2822 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2823 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { /* DVB-S mode */
2824 srate = stv090x_get_srate(state, state->mclk);
2825 srate += stv090x_get_tmgoffst(state, state->srate);
2827 if (state->algo == STV090x_BLIND_SEARCH)
2828 stv090x_set_srate(state, state->srate);
2830 stv090x_get_lock_tmg(state);
2832 f_1 = STV090x_READ_DEMOD(state, CFR2);
2833 f_2 = STV090x_READ_DEMOD(state, CFR1);
2835 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2836 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
2837 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2840 reg = STV090x_READ_DEMOD(state, DEMOD);
2841 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_SWAP);
2842 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2844 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) /* stop demod */
2846 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2848 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2850 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2853 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2855 stv090x_get_sig_params(state);
2856 stv090x_optimize_track(state);
2858 reg = STV090x_READ_DEMOD(state, DEMOD);
2859 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_NORMAL);
2860 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2862 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2864 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2866 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2868 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2870 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2872 signal_state = stv090x_get_sig_params(state);
2873 stv090x_optimize_track(state);
2880 return signal_state;
2883 dprintk(FE_ERROR, 1, "I/O error");
2887 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
2889 struct dvb_frontend *fe = &state->frontend;
2890 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
2892 s32 timeout_dmd = 500, timeout_fec = 50;
2893 int lock = 0, low_sr, no_signal = 0;
2895 reg = STV090x_READ_DEMOD(state, TSCFGH);
2896 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
2897 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2900 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
2903 if (state->dev_ver >= 0x20) {
2904 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
2907 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0) /* cut 1.x */
2911 stv090x_get_lock_tmg(state);
2913 if (state->algo == STV090x_BLIND_SEARCH) {
2914 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
2915 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x00) < 0) /* wider srate scan */
2917 stv090x_set_srate(state, 1000000); /* inital srate = 1Msps */
2920 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
2922 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
2925 if (state->srate >= 10000000) {
2926 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) /* High SR */
2929 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) /* Low SR */
2933 if (state->dev_ver >= 0x20) {
2934 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
2936 if (state->algo == STV090x_COLD_SEARCH)
2937 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 1000000)) / 10;
2938 else if (state->algo == STV090x_WARM_SEARCH)
2939 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
2941 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0xc1) < 0)
2943 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
2945 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) /* narrow srate scan */
2947 stv090x_set_srate(state, state->srate);
2948 stv090x_set_max_srate(state, state->mclk, state->srate);
2949 stv090x_set_min_srate(state, state->mclk, state->srate);
2951 if (state->srate >= 10000000)
2956 stv090x_i2c_gate_ctrl(fe, 1);
2958 if (state->config->tuner_set_bbgain)
2959 state->config->tuner_set_bbgain(fe, 10); /* 10dB */
2961 if (state->config->tuner_set_frequency)
2962 state->config->tuner_set_frequency(fe, state->frequency);
2964 if (state->config->tuner_set_bandwidth)
2965 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2967 stv090x_i2c_gate_ctrl(fe, 0);
2971 stv090x_i2c_gate_ctrl(fe, 1);
2973 if (state->config->tuner_get_status)
2974 state->config->tuner_get_status(fe, ®);
2977 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2979 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2981 stv090x_i2c_gate_ctrl(fe, 0);
2983 reg = STV090x_READ_DEMOD(state, DEMOD);
2984 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
2985 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 1);
2986 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2988 stv090x_delivery_search(state);
2989 if (state->algo == STV090x_BLIND_SEARCH)
2990 stv090x_start_search(state);
2992 if (state->dev_ver == 0x12) {
2993 reg = STV090x_READ_DEMOD(state, TSCFGH);
2994 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
2995 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2998 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
2999 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3001 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3002 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3006 if (state->algo == STV090x_BLIND_SEARCH)
3007 lock = stv090x_blind_search(state);
3008 else if (state->algo == STV090x_COLD_SEARCH)
3009 lock = stv090x_get_coldlock(state, timeout_dmd);
3010 else if (state->algo == STV090x_WARM_SEARCH)
3011 lock = stv090x_get_dmdlock(state, timeout_dmd);
3013 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3015 if (stv090x_chk_tmg(state))
3016 lock = stv090x_sw_algo(state);
3021 signal_state = stv090x_get_sig_params(state);
3023 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3024 stv090x_optimize_track(state);
3025 if (state->dev_ver <= 0x11) { /*workaround for dual DVBS1 cut 1.1 and 1.0 only*/
3026 if (stv090x_get_std(state) == STV090x_DVBS1) {
3028 reg = STV090x_READ_DEMOD(state, TSCFGH);
3029 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3030 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3033 reg = STV090x_READ_DEMOD(state, TSCFGH);
3034 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3035 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3038 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3039 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3041 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3042 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3045 } else if (state->dev_ver == 0x20) { /*cut 2.0 :release TS reset after demod lock and TrackingOptimization*/
3046 reg = STV090x_READ_DEMOD(state, TSCFGH);
3047 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3048 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3051 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3052 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3055 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3056 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3060 if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
3062 if (state->delsys == STV090x_DVBS2) {
3063 stv090x_set_s2rolloff(state);
3064 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x40) < 0)
3066 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x00) < 0) /* RESET counter */
3068 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3071 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3074 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3076 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3080 signal_state = STV090x_NODATA;
3081 no_signal = stv090x_chk_signal(state);
3084 if ((signal_state == STV090x_NODATA) && (!no_signal)) {
3085 if (state->dev_ver <= 0x11) {
3086 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3087 if (((STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD)) == STV090x_DVBS2) && (state->inversion == INVERSION_AUTO))
3088 signal_state = stv090x_acq_fixs1(state);
3091 return signal_state;
3094 dprintk(FE_ERROR, 1, "I/O error");
3098 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3100 struct stv090x_state *state = fe->demodulator_priv;
3101 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3103 state->delsys = props->delivery_system;
3104 state->frequency = p->frequency;
3105 state->srate = p->u.qpsk.symbol_rate;
3107 if (!stv090x_algo(state)) {
3108 dprintk(FE_DEBUG, 1, "Search success!");
3109 return DVBFE_ALGO_SEARCH_SUCCESS;
3111 dprintk(FE_DEBUG, 1, "Search failed!");
3112 return DVBFE_ALGO_SEARCH_FAILED;
3115 return DVBFE_ALGO_SEARCH_ERROR;
3119 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3121 struct stv090x_state *state = fe->demodulator_priv;
3126 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3127 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3129 switch (search_state) {
3130 case 0: /* searching */
3131 case 1: /* first PLH detected */
3133 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3137 case 2: /* DVB-S2 mode */
3138 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3139 reg = STV090x_READ_DEMOD(state, DSTATUS);
3140 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3141 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3142 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3144 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3149 case 3: /* DVB-S1/legacy mode */
3150 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3151 reg = STV090x_READ_DEMOD(state, DSTATUS);
3152 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3153 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3154 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3155 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3156 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3158 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3168 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3170 struct stv090x_state *state = fe->demodulator_priv;
3172 s32 count_4, count_3, count_2, count_1, count_0, count;
3174 enum fe_status status;
3176 if (!stv090x_read_status(fe, &status)) {
3177 *per = 1 << 23; /* Max PER */
3180 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3181 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3183 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3184 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3186 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3187 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3189 *per = ((h << 16) | (m << 8) | l);
3191 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3192 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3193 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3194 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3195 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3197 if ((!count_4) && (!count_3)) {
3198 count = (count_2 & 0xff) << 16;
3199 count |= (count_1 & 0xff) << 8;
3200 count |= count_0 & 0xff;
3207 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3209 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3214 dprintk(FE_ERROR, 1, "I/O error");
3218 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3223 if (val < tab[min].read)
3224 res = tab[min].real;
3225 else if (val >= tab[max].read)
3226 res = tab[max].real;
3228 while ((max - min) > 1) {
3229 med = (max + min) / 2;
3230 if (val >= tab[min].read && val < tab[med].read)
3235 res = ((val - tab[min].read) *
3236 (tab[max].real - tab[min].real) /
3237 (tab[max].read - tab[min].read)) +
3244 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3246 struct stv090x_state *state = fe->demodulator_priv;
3250 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3251 agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3253 *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3254 if (agc > stv090x_rf_tab[0].read)
3256 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3262 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3264 struct stv090x_state *state = fe->demodulator_priv;
3265 u32 reg_0, reg_1, reg, i;
3266 s32 val_0, val_1, val = 0;
3269 switch (state->delsys) {
3271 reg = STV090x_READ_DEMOD(state, DSTATUS);
3272 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3275 for (i = 0; i < 16; i++) {
3276 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3277 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3278 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3279 val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3280 val += MAKEWORD16(val_1, val_0);
3284 *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
3285 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
3292 reg = STV090x_READ_DEMOD(state, DSTATUS);
3293 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3296 for (i = 0; i < 16; i++) {
3297 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3298 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3299 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3300 val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3301 val += MAKEWORD16(val_1, val_0);
3305 *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
3306 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
3317 static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3319 struct stv090x_state *state = fe->demodulator_priv;
3322 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3325 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3326 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3327 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3329 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3330 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3335 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3336 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3337 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3346 dprintk(FE_ERROR, 1, "I/O error");
3351 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3353 return DVBFE_ALGO_CUSTOM;
3356 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3358 struct stv090x_state *state = fe->demodulator_priv;
3359 u32 reg, idle = 0, fifo_full = 1;
3362 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3364 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 2);
3365 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3366 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3368 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3369 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3372 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3373 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3376 for (i = 0; i < cmd->msg_len; i++) {
3379 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3380 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3383 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3386 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3387 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3388 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3393 while ((!idle) && (i < 10)) {
3394 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3395 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3402 dprintk(FE_ERROR, 1, "I/O error");
3406 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3408 struct stv090x_state *state = fe->demodulator_priv;
3409 u32 reg, idle = 0, fifo_full = 1;
3413 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3415 if (burst == SEC_MINI_A) {
3423 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3424 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3425 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3427 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3428 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3431 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3432 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3436 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3437 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3440 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3443 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3444 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3445 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3450 while ((!idle) && (i < 10)) {
3451 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3452 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3459 dprintk(FE_ERROR, 1, "I/O error");
3463 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3465 struct stv090x_state *state = fe->demodulator_priv;
3466 u32 reg = 0, i = 0, rx_end = 0;
3468 while ((rx_end != 1) && (i < 10)) {
3471 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3472 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3476 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3477 for (i = 0; i < reply->msg_len; i++)
3478 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3484 static int stv090x_sleep(struct dvb_frontend *fe)
3486 struct stv090x_state *state = fe->demodulator_priv;
3489 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3490 state->device == STV0900 ? "STV0900" : "STV0903");
3492 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3493 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3494 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3499 dprintk(FE_ERROR, 1, "I/O error");
3503 static int stv090x_wakeup(struct dvb_frontend *fe)
3505 struct stv090x_state *state = fe->demodulator_priv;
3508 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3509 state->device == STV0900 ? "STV0900" : "STV0903");
3511 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3512 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3513 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3518 dprintk(FE_ERROR, 1, "I/O error");
3522 static void stv090x_release(struct dvb_frontend *fe)
3524 struct stv090x_state *state = fe->demodulator_priv;
3529 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3533 switch (ldpc_mode) {
3536 reg = stv090x_read_reg(state, STV090x_GENCFG);
3537 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3538 /* follow LDPC default state */
3539 if (stv090x_write_reg(state, STV090x_GENCFG, reg) < 0)
3541 state->demod_mode = STV090x_DUAL;
3542 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3543 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3544 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3546 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3547 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3552 case STV090x_SINGLE:
3553 if (state->demod == STV090x_DEMODULATOR_1) {
3554 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3557 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3561 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3562 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3563 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3565 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3566 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3569 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3570 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3571 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3573 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3574 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3581 dprintk(FE_ERROR, 1, "I/O error");
3585 /* return (Hz), clk in Hz*/
3586 static u32 stv090x_get_mclk(struct stv090x_state *state)
3588 const struct stv090x_config *config = state->config;
3592 div = stv090x_read_reg(state, STV090x_NCOARSE);
3593 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3594 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
3596 return (div + 1) * config->xtal / ratio; /* kHz */
3599 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
3601 const struct stv090x_config *config = state->config;
3602 u32 reg, div, clk_sel;
3604 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3605 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
3607 div = ((clk_sel * mclk) / config->xtal) - 1;
3609 reg = stv090x_read_reg(state, STV090x_NCOARSE);
3610 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
3611 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
3614 state->mclk = stv090x_get_mclk(state);
3618 dprintk(FE_ERROR, 1, "I/O error");
3622 static int stv090x_set_tspath(struct stv090x_state *state)
3626 if (state->dev_ver >= 0x20) {
3627 switch (state->config->ts1_mode) {
3628 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3629 case STV090x_TSMODE_DVBCI:
3630 switch (state->config->ts2_mode) {
3631 case STV090x_TSMODE_SERIAL_PUNCTURED:
3632 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3634 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
3637 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3638 case STV090x_TSMODE_DVBCI:
3639 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
3641 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3642 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3643 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3645 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
3646 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3647 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
3649 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3651 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3657 case STV090x_TSMODE_SERIAL_PUNCTURED:
3658 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3660 switch (state->config->ts2_mode) {
3661 case STV090x_TSMODE_SERIAL_PUNCTURED:
3662 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3664 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3668 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3669 case STV090x_TSMODE_DVBCI:
3670 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
3677 switch (state->config->ts1_mode) {
3678 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3679 case STV090x_TSMODE_DVBCI:
3680 switch (state->config->ts2_mode) {
3681 case STV090x_TSMODE_SERIAL_PUNCTURED:
3682 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3684 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
3687 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3688 case STV090x_TSMODE_DVBCI:
3689 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
3690 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3691 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3692 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3694 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3695 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
3696 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3698 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3700 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3706 case STV090x_TSMODE_SERIAL_PUNCTURED:
3707 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3709 switch (state->config->ts2_mode) {
3710 case STV090x_TSMODE_SERIAL_PUNCTURED:
3711 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3713 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
3716 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3717 case STV090x_TSMODE_DVBCI:
3718 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
3725 switch (state->config->ts1_mode) {
3726 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3727 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3728 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3729 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3730 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3734 case STV090x_TSMODE_DVBCI:
3735 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3736 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3737 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3738 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3742 case STV090x_TSMODE_SERIAL_PUNCTURED:
3743 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3744 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3745 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3746 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3750 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3751 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3752 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3753 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3754 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3762 switch (state->config->ts2_mode) {
3763 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3764 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3765 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3766 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3767 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3771 case STV090x_TSMODE_DVBCI:
3772 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3773 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3774 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3775 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3779 case STV090x_TSMODE_SERIAL_PUNCTURED:
3780 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3781 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3782 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3783 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3787 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3788 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3789 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3790 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3791 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3798 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
3799 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3800 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3802 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3803 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3806 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3807 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3808 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3810 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3811 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3816 dprintk(FE_ERROR, 1, "I/O error");
3820 static int stv090x_init(struct dvb_frontend *fe)
3822 struct stv090x_state *state = fe->demodulator_priv;
3823 const struct stv090x_config *config = state->config;
3826 stv090x_ldpc_mode(state, state->demod_mode);
3828 reg = STV090x_READ_DEMOD(state, TNRCFG2);
3829 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
3830 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
3832 reg = STV090x_READ_DEMOD(state, DEMOD);
3833 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
3834 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3837 stv090x_i2c_gate_ctrl(fe, 1);
3839 if (config->tuner_init)
3840 config->tuner_init(fe);
3842 stv090x_i2c_gate_ctrl(fe, 0);
3844 stv090x_set_tspath(state);
3848 dprintk(FE_ERROR, 1, "I/O error");
3852 static int stv090x_setup(struct dvb_frontend *fe)
3854 struct stv090x_state *state = fe->demodulator_priv;
3855 const struct stv090x_config *config = state->config;
3856 const struct stv090x_reg *stv090x_initval = NULL;
3857 const struct stv090x_reg *stv090x_cut20_val = NULL;
3858 unsigned long t1_size = 0, t2_size = 0;
3863 if (state->device == STV0900) {
3864 dprintk(FE_DEBUG, 1, "Initializing STV0900");
3865 stv090x_initval = stv0900_initval;
3866 t1_size = ARRAY_SIZE(stv0900_initval);
3867 stv090x_cut20_val = stv0900_cut20_val;
3868 t2_size = ARRAY_SIZE(stv0900_cut20_val);
3869 } else if (state->device == STV0903) {
3870 dprintk(FE_DEBUG, 1, "Initializing STV0903");
3871 stv090x_initval = stv0903_initval;
3872 t1_size = ARRAY_SIZE(stv0903_initval);
3873 stv090x_cut20_val = stv0903_cut20_val;
3874 t2_size = ARRAY_SIZE(stv0903_cut20_val);
3878 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
3883 if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
3886 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
3887 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
3890 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
3893 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
3895 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
3900 for (i = 0; i < t1_size; i++) {
3901 dprintk(FE_DEBUG, 1, "Setting up initial values");
3902 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
3906 if (state->dev_ver >= 0x20) {
3907 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3910 /* write cut20_val*/
3911 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
3912 for (i = 0; i < t2_size; i++) {
3913 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
3918 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
3920 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
3923 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
3925 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
3927 stv090x_get_mclk(state);
3931 dprintk(FE_ERROR, 1, "I/O error");
3935 static struct dvb_frontend_ops stv090x_ops = {
3938 .name = "STV090x Multistandard",
3941 .release = stv090x_release,
3942 .init = stv090x_init,
3944 .sleep = stv090x_sleep,
3945 .get_frontend_algo = stv090x_frontend_algo,
3947 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
3949 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
3950 .diseqc_send_burst = stv090x_send_diseqc_burst,
3951 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
3952 .set_tone = stv090x_set_tone,
3954 .search = stv090x_search,
3955 .read_status = stv090x_read_status,
3956 .read_ber = stv090x_read_per,
3957 .read_signal_strength = stv090x_read_signal_strength,
3958 .read_snr = stv090x_read_cnr
3962 struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
3963 struct i2c_adapter *i2c,
3964 enum stv090x_demodulator demod)
3966 struct stv090x_state *state = NULL;
3968 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
3972 state->verbose = &verbose;
3973 state->config = config;
3975 state->frontend.ops = stv090x_ops;
3976 state->frontend.demodulator_priv = state;
3977 state->demod = demod;
3978 state->demod_mode = config->demod_mode; /* Single or Dual mode */
3979 state->device = config->device;
3980 state->rolloff = 35; /* default */
3982 if (state->demod == STV090x_DEMODULATOR_0)
3983 mutex_init(&demod_lock);
3985 if (stv090x_sleep(&state->frontend) < 0) {
3986 dprintk(FE_ERROR, 1, "Error putting device to sleep");
3990 if (stv090x_setup(&state->frontend) < 0) {
3991 dprintk(FE_ERROR, 1, "Error setting up device");
3994 if (stv090x_wakeup(&state->frontend) < 0) {
3995 dprintk(FE_ERROR, 1, "Error waking device");
3998 state->dev_ver = stv090x_read_reg(state, STV090x_MID);
4000 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
4001 state->device == STV0900 ? "STV0900" : "STV0903",
4005 return &state->frontend;
4011 EXPORT_SYMBOL(stv090x_attach);
4012 MODULE_PARM_DESC(verbose, "Set Verbosity level");
4013 MODULE_AUTHOR("Manu Abraham");
4014 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4015 MODULE_LICENSE("GPL");