2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/mutex.h>
28 #include <linux/dvb/frontend.h>
29 #include "dvb_frontend.h"
31 #include "stv6110x.h" /* for demodulator internal modes */
33 #include "stv090x_reg.h"
35 #include "stv090x_priv.h"
37 static unsigned int verbose;
38 module_param(verbose, int, 0644);
40 /* internal params node */
42 /* pointer for internal params, one for each pair of demods */
43 struct stv090x_internal *internal;
44 struct stv090x_dev *next_dev;
47 /* first internal params */
48 static struct stv090x_dev *stv090x_first_dev;
50 /* find chip by i2c adapter and i2c address */
51 static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
54 struct stv090x_dev *temp_dev = stv090x_first_dev;
57 Search of the last stv0900 chip or
58 find it by i2c adapter and i2c address */
59 while ((temp_dev != NULL) &&
60 ((temp_dev->internal->i2c_adap != i2c_adap) ||
61 (temp_dev->internal->i2c_addr != i2c_addr))) {
63 temp_dev = temp_dev->next_dev;
69 /* deallocating chip */
70 static void remove_dev(struct stv090x_internal *internal)
72 struct stv090x_dev *prev_dev = stv090x_first_dev;
73 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
76 if (del_dev != NULL) {
77 if (del_dev == stv090x_first_dev) {
78 stv090x_first_dev = del_dev->next_dev;
80 while (prev_dev->next_dev != del_dev)
81 prev_dev = prev_dev->next_dev;
83 prev_dev->next_dev = del_dev->next_dev;
90 /* allocating new chip */
91 static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
93 struct stv090x_dev *new_dev;
94 struct stv090x_dev *temp_dev;
96 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
97 if (new_dev != NULL) {
98 new_dev->internal = internal;
99 new_dev->next_dev = NULL;
102 if (stv090x_first_dev == NULL) {
103 stv090x_first_dev = new_dev;
105 temp_dev = stv090x_first_dev;
106 while (temp_dev->next_dev != NULL)
107 temp_dev = temp_dev->next_dev;
109 temp_dev->next_dev = new_dev;
117 /* DVBS1 and DSS C/N Lookup table */
118 static const struct stv090x_tab stv090x_s1cn_tab[] = {
119 { 0, 8917 }, /* 0.0dB */
120 { 5, 8801 }, /* 0.5dB */
121 { 10, 8667 }, /* 1.0dB */
122 { 15, 8522 }, /* 1.5dB */
123 { 20, 8355 }, /* 2.0dB */
124 { 25, 8175 }, /* 2.5dB */
125 { 30, 7979 }, /* 3.0dB */
126 { 35, 7763 }, /* 3.5dB */
127 { 40, 7530 }, /* 4.0dB */
128 { 45, 7282 }, /* 4.5dB */
129 { 50, 7026 }, /* 5.0dB */
130 { 55, 6781 }, /* 5.5dB */
131 { 60, 6514 }, /* 6.0dB */
132 { 65, 6241 }, /* 6.5dB */
133 { 70, 5965 }, /* 7.0dB */
134 { 75, 5690 }, /* 7.5dB */
135 { 80, 5424 }, /* 8.0dB */
136 { 85, 5161 }, /* 8.5dB */
137 { 90, 4902 }, /* 9.0dB */
138 { 95, 4654 }, /* 9.5dB */
139 { 100, 4417 }, /* 10.0dB */
140 { 105, 4186 }, /* 10.5dB */
141 { 110, 3968 }, /* 11.0dB */
142 { 115, 3757 }, /* 11.5dB */
143 { 120, 3558 }, /* 12.0dB */
144 { 125, 3366 }, /* 12.5dB */
145 { 130, 3185 }, /* 13.0dB */
146 { 135, 3012 }, /* 13.5dB */
147 { 140, 2850 }, /* 14.0dB */
148 { 145, 2698 }, /* 14.5dB */
149 { 150, 2550 }, /* 15.0dB */
150 { 160, 2283 }, /* 16.0dB */
151 { 170, 2042 }, /* 17.0dB */
152 { 180, 1827 }, /* 18.0dB */
153 { 190, 1636 }, /* 19.0dB */
154 { 200, 1466 }, /* 20.0dB */
155 { 210, 1315 }, /* 21.0dB */
156 { 220, 1181 }, /* 22.0dB */
157 { 230, 1064 }, /* 23.0dB */
158 { 240, 960 }, /* 24.0dB */
159 { 250, 869 }, /* 25.0dB */
160 { 260, 792 }, /* 26.0dB */
161 { 270, 724 }, /* 27.0dB */
162 { 280, 665 }, /* 28.0dB */
163 { 290, 616 }, /* 29.0dB */
164 { 300, 573 }, /* 30.0dB */
165 { 310, 537 }, /* 31.0dB */
166 { 320, 507 }, /* 32.0dB */
167 { 330, 483 }, /* 33.0dB */
168 { 400, 398 }, /* 40.0dB */
169 { 450, 381 }, /* 45.0dB */
170 { 500, 377 } /* 50.0dB */
173 /* DVBS2 C/N Lookup table */
174 static const struct stv090x_tab stv090x_s2cn_tab[] = {
175 { -30, 13348 }, /* -3.0dB */
176 { -20, 12640 }, /* -2d.0B */
177 { -10, 11883 }, /* -1.0dB */
178 { 0, 11101 }, /* -0.0dB */
179 { 5, 10718 }, /* 0.5dB */
180 { 10, 10339 }, /* 1.0dB */
181 { 15, 9947 }, /* 1.5dB */
182 { 20, 9552 }, /* 2.0dB */
183 { 25, 9183 }, /* 2.5dB */
184 { 30, 8799 }, /* 3.0dB */
185 { 35, 8422 }, /* 3.5dB */
186 { 40, 8062 }, /* 4.0dB */
187 { 45, 7707 }, /* 4.5dB */
188 { 50, 7353 }, /* 5.0dB */
189 { 55, 7025 }, /* 5.5dB */
190 { 60, 6684 }, /* 6.0dB */
191 { 65, 6331 }, /* 6.5dB */
192 { 70, 6036 }, /* 7.0dB */
193 { 75, 5727 }, /* 7.5dB */
194 { 80, 5437 }, /* 8.0dB */
195 { 85, 5164 }, /* 8.5dB */
196 { 90, 4902 }, /* 9.0dB */
197 { 95, 4653 }, /* 9.5dB */
198 { 100, 4408 }, /* 10.0dB */
199 { 105, 4187 }, /* 10.5dB */
200 { 110, 3961 }, /* 11.0dB */
201 { 115, 3751 }, /* 11.5dB */
202 { 120, 3558 }, /* 12.0dB */
203 { 125, 3368 }, /* 12.5dB */
204 { 130, 3191 }, /* 13.0dB */
205 { 135, 3017 }, /* 13.5dB */
206 { 140, 2862 }, /* 14.0dB */
207 { 145, 2710 }, /* 14.5dB */
208 { 150, 2565 }, /* 15.0dB */
209 { 160, 2300 }, /* 16.0dB */
210 { 170, 2058 }, /* 17.0dB */
211 { 180, 1849 }, /* 18.0dB */
212 { 190, 1663 }, /* 19.0dB */
213 { 200, 1495 }, /* 20.0dB */
214 { 210, 1349 }, /* 21.0dB */
215 { 220, 1222 }, /* 22.0dB */
216 { 230, 1110 }, /* 23.0dB */
217 { 240, 1011 }, /* 24.0dB */
218 { 250, 925 }, /* 25.0dB */
219 { 260, 853 }, /* 26.0dB */
220 { 270, 789 }, /* 27.0dB */
221 { 280, 734 }, /* 28.0dB */
222 { 290, 690 }, /* 29.0dB */
223 { 300, 650 }, /* 30.0dB */
224 { 310, 619 }, /* 31.0dB */
225 { 320, 593 }, /* 32.0dB */
226 { 330, 571 }, /* 33.0dB */
227 { 400, 498 }, /* 40.0dB */
228 { 450, 484 }, /* 45.0dB */
229 { 500, 481 } /* 50.0dB */
232 /* RF level C/N lookup table */
233 static const struct stv090x_tab stv090x_rf_tab[] = {
234 { -5, 0xcaa1 }, /* -5dBm */
235 { -10, 0xc229 }, /* -10dBm */
236 { -15, 0xbb08 }, /* -15dBm */
237 { -20, 0xb4bc }, /* -20dBm */
238 { -25, 0xad5a }, /* -25dBm */
239 { -30, 0xa298 }, /* -30dBm */
240 { -35, 0x98a8 }, /* -35dBm */
241 { -40, 0x8389 }, /* -40dBm */
242 { -45, 0x59be }, /* -45dBm */
243 { -50, 0x3a14 }, /* -50dBm */
244 { -55, 0x2d11 }, /* -55dBm */
245 { -60, 0x210d }, /* -60dBm */
246 { -65, 0xa14f }, /* -65dBm */
247 { -70, 0x07aa } /* -70dBm */
251 static struct stv090x_reg stv0900_initval[] = {
253 { STV090x_OUTCFG, 0x00 },
254 { STV090x_MODECFG, 0xff },
255 { STV090x_AGCRF1CFG, 0x11 },
256 { STV090x_AGCRF2CFG, 0x13 },
257 { STV090x_TSGENERAL1X, 0x14 },
258 { STV090x_TSTTNR2, 0x21 },
259 { STV090x_TSTTNR4, 0x21 },
260 { STV090x_P2_DISTXCTL, 0x22 },
261 { STV090x_P2_F22TX, 0xc0 },
262 { STV090x_P2_F22RX, 0xc0 },
263 { STV090x_P2_DISRXCTL, 0x00 },
264 { STV090x_P2_DMDCFGMD, 0xF9 },
265 { STV090x_P2_DEMOD, 0x08 },
266 { STV090x_P2_DMDCFG3, 0xc4 },
267 { STV090x_P2_CARFREQ, 0xed },
268 { STV090x_P2_LDT, 0xd0 },
269 { STV090x_P2_LDT2, 0xb8 },
270 { STV090x_P2_TMGCFG, 0xd2 },
271 { STV090x_P2_TMGTHRISE, 0x20 },
272 { STV090x_P1_TMGCFG, 0xd2 },
274 { STV090x_P2_TMGTHFALL, 0x00 },
275 { STV090x_P2_FECSPY, 0x88 },
276 { STV090x_P2_FSPYDATA, 0x3a },
277 { STV090x_P2_FBERCPT4, 0x00 },
278 { STV090x_P2_FSPYBER, 0x10 },
279 { STV090x_P2_ERRCTRL1, 0x35 },
280 { STV090x_P2_ERRCTRL2, 0xc1 },
281 { STV090x_P2_CFRICFG, 0xf8 },
282 { STV090x_P2_NOSCFG, 0x1c },
283 { STV090x_P2_DMDTOM, 0x20 },
284 { STV090x_P2_CORRELMANT, 0x70 },
285 { STV090x_P2_CORRELABS, 0x88 },
286 { STV090x_P2_AGC2O, 0x5b },
287 { STV090x_P2_AGC2REF, 0x38 },
288 { STV090x_P2_CARCFG, 0xe4 },
289 { STV090x_P2_ACLC, 0x1A },
290 { STV090x_P2_BCLC, 0x09 },
291 { STV090x_P2_CARHDR, 0x08 },
292 { STV090x_P2_KREFTMG, 0xc1 },
293 { STV090x_P2_SFRUPRATIO, 0xf0 },
294 { STV090x_P2_SFRLOWRATIO, 0x70 },
295 { STV090x_P2_SFRSTEP, 0x58 },
296 { STV090x_P2_TMGCFG2, 0x01 },
297 { STV090x_P2_CAR2CFG, 0x26 },
298 { STV090x_P2_BCLC2S2Q, 0x86 },
299 { STV090x_P2_BCLC2S28, 0x86 },
300 { STV090x_P2_SMAPCOEF7, 0x77 },
301 { STV090x_P2_SMAPCOEF6, 0x85 },
302 { STV090x_P2_SMAPCOEF5, 0x77 },
303 { STV090x_P2_TSCFGL, 0x20 },
304 { STV090x_P2_DMDCFG2, 0x3b },
305 { STV090x_P2_MODCODLST0, 0xff },
306 { STV090x_P2_MODCODLST1, 0xff },
307 { STV090x_P2_MODCODLST2, 0xff },
308 { STV090x_P2_MODCODLST3, 0xff },
309 { STV090x_P2_MODCODLST4, 0xff },
310 { STV090x_P2_MODCODLST5, 0xff },
311 { STV090x_P2_MODCODLST6, 0xff },
312 { STV090x_P2_MODCODLST7, 0xcc },
313 { STV090x_P2_MODCODLST8, 0xcc },
314 { STV090x_P2_MODCODLST9, 0xcc },
315 { STV090x_P2_MODCODLSTA, 0xcc },
316 { STV090x_P2_MODCODLSTB, 0xcc },
317 { STV090x_P2_MODCODLSTC, 0xcc },
318 { STV090x_P2_MODCODLSTD, 0xcc },
319 { STV090x_P2_MODCODLSTE, 0xcc },
320 { STV090x_P2_MODCODLSTF, 0xcf },
321 { STV090x_P1_DISTXCTL, 0x22 },
322 { STV090x_P1_F22TX, 0xc0 },
323 { STV090x_P1_F22RX, 0xc0 },
324 { STV090x_P1_DISRXCTL, 0x00 },
325 { STV090x_P1_DMDCFGMD, 0xf9 },
326 { STV090x_P1_DEMOD, 0x08 },
327 { STV090x_P1_DMDCFG3, 0xc4 },
328 { STV090x_P1_DMDTOM, 0x20 },
329 { STV090x_P1_CARFREQ, 0xed },
330 { STV090x_P1_LDT, 0xd0 },
331 { STV090x_P1_LDT2, 0xb8 },
332 { STV090x_P1_TMGCFG, 0xd2 },
333 { STV090x_P1_TMGTHRISE, 0x20 },
334 { STV090x_P1_TMGTHFALL, 0x00 },
335 { STV090x_P1_SFRUPRATIO, 0xf0 },
336 { STV090x_P1_SFRLOWRATIO, 0x70 },
337 { STV090x_P1_TSCFGL, 0x20 },
338 { STV090x_P1_FECSPY, 0x88 },
339 { STV090x_P1_FSPYDATA, 0x3a },
340 { STV090x_P1_FBERCPT4, 0x00 },
341 { STV090x_P1_FSPYBER, 0x10 },
342 { STV090x_P1_ERRCTRL1, 0x35 },
343 { STV090x_P1_ERRCTRL2, 0xc1 },
344 { STV090x_P1_CFRICFG, 0xf8 },
345 { STV090x_P1_NOSCFG, 0x1c },
346 { STV090x_P1_CORRELMANT, 0x70 },
347 { STV090x_P1_CORRELABS, 0x88 },
348 { STV090x_P1_AGC2O, 0x5b },
349 { STV090x_P1_AGC2REF, 0x38 },
350 { STV090x_P1_CARCFG, 0xe4 },
351 { STV090x_P1_ACLC, 0x1A },
352 { STV090x_P1_BCLC, 0x09 },
353 { STV090x_P1_CARHDR, 0x08 },
354 { STV090x_P1_KREFTMG, 0xc1 },
355 { STV090x_P1_SFRSTEP, 0x58 },
356 { STV090x_P1_TMGCFG2, 0x01 },
357 { STV090x_P1_CAR2CFG, 0x26 },
358 { STV090x_P1_BCLC2S2Q, 0x86 },
359 { STV090x_P1_BCLC2S28, 0x86 },
360 { STV090x_P1_SMAPCOEF7, 0x77 },
361 { STV090x_P1_SMAPCOEF6, 0x85 },
362 { STV090x_P1_SMAPCOEF5, 0x77 },
363 { STV090x_P1_DMDCFG2, 0x3b },
364 { STV090x_P1_MODCODLST0, 0xff },
365 { STV090x_P1_MODCODLST1, 0xff },
366 { STV090x_P1_MODCODLST2, 0xff },
367 { STV090x_P1_MODCODLST3, 0xff },
368 { STV090x_P1_MODCODLST4, 0xff },
369 { STV090x_P1_MODCODLST5, 0xff },
370 { STV090x_P1_MODCODLST6, 0xff },
371 { STV090x_P1_MODCODLST7, 0xcc },
372 { STV090x_P1_MODCODLST8, 0xcc },
373 { STV090x_P1_MODCODLST9, 0xcc },
374 { STV090x_P1_MODCODLSTA, 0xcc },
375 { STV090x_P1_MODCODLSTB, 0xcc },
376 { STV090x_P1_MODCODLSTC, 0xcc },
377 { STV090x_P1_MODCODLSTD, 0xcc },
378 { STV090x_P1_MODCODLSTE, 0xcc },
379 { STV090x_P1_MODCODLSTF, 0xcf },
380 { STV090x_GENCFG, 0x1d },
381 { STV090x_NBITER_NF4, 0x37 },
382 { STV090x_NBITER_NF5, 0x29 },
383 { STV090x_NBITER_NF6, 0x37 },
384 { STV090x_NBITER_NF7, 0x33 },
385 { STV090x_NBITER_NF8, 0x31 },
386 { STV090x_NBITER_NF9, 0x2f },
387 { STV090x_NBITER_NF10, 0x39 },
388 { STV090x_NBITER_NF11, 0x3a },
389 { STV090x_NBITER_NF12, 0x29 },
390 { STV090x_NBITER_NF13, 0x37 },
391 { STV090x_NBITER_NF14, 0x33 },
392 { STV090x_NBITER_NF15, 0x2f },
393 { STV090x_NBITER_NF16, 0x39 },
394 { STV090x_NBITER_NF17, 0x3a },
395 { STV090x_NBITERNOERR, 0x04 },
396 { STV090x_GAINLLR_NF4, 0x0C },
397 { STV090x_GAINLLR_NF5, 0x0F },
398 { STV090x_GAINLLR_NF6, 0x11 },
399 { STV090x_GAINLLR_NF7, 0x14 },
400 { STV090x_GAINLLR_NF8, 0x17 },
401 { STV090x_GAINLLR_NF9, 0x19 },
402 { STV090x_GAINLLR_NF10, 0x20 },
403 { STV090x_GAINLLR_NF11, 0x21 },
404 { STV090x_GAINLLR_NF12, 0x0D },
405 { STV090x_GAINLLR_NF13, 0x0F },
406 { STV090x_GAINLLR_NF14, 0x13 },
407 { STV090x_GAINLLR_NF15, 0x1A },
408 { STV090x_GAINLLR_NF16, 0x1F },
409 { STV090x_GAINLLR_NF17, 0x21 },
410 { STV090x_RCCFGH, 0x20 },
411 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
412 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
413 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
414 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
417 static struct stv090x_reg stv0903_initval[] = {
418 { STV090x_OUTCFG, 0x00 },
419 { STV090x_AGCRF1CFG, 0x11 },
420 { STV090x_STOPCLK1, 0x48 },
421 { STV090x_STOPCLK2, 0x14 },
422 { STV090x_TSTTNR1, 0x27 },
423 { STV090x_TSTTNR2, 0x21 },
424 { STV090x_P1_DISTXCTL, 0x22 },
425 { STV090x_P1_F22TX, 0xc0 },
426 { STV090x_P1_F22RX, 0xc0 },
427 { STV090x_P1_DISRXCTL, 0x00 },
428 { STV090x_P1_DMDCFGMD, 0xF9 },
429 { STV090x_P1_DEMOD, 0x08 },
430 { STV090x_P1_DMDCFG3, 0xc4 },
431 { STV090x_P1_CARFREQ, 0xed },
432 { STV090x_P1_TNRCFG2, 0x82 },
433 { STV090x_P1_LDT, 0xd0 },
434 { STV090x_P1_LDT2, 0xb8 },
435 { STV090x_P1_TMGCFG, 0xd2 },
436 { STV090x_P1_TMGTHRISE, 0x20 },
437 { STV090x_P1_TMGTHFALL, 0x00 },
438 { STV090x_P1_SFRUPRATIO, 0xf0 },
439 { STV090x_P1_SFRLOWRATIO, 0x70 },
440 { STV090x_P1_TSCFGL, 0x20 },
441 { STV090x_P1_FECSPY, 0x88 },
442 { STV090x_P1_FSPYDATA, 0x3a },
443 { STV090x_P1_FBERCPT4, 0x00 },
444 { STV090x_P1_FSPYBER, 0x10 },
445 { STV090x_P1_ERRCTRL1, 0x35 },
446 { STV090x_P1_ERRCTRL2, 0xc1 },
447 { STV090x_P1_CFRICFG, 0xf8 },
448 { STV090x_P1_NOSCFG, 0x1c },
449 { STV090x_P1_DMDTOM, 0x20 },
450 { STV090x_P1_CORRELMANT, 0x70 },
451 { STV090x_P1_CORRELABS, 0x88 },
452 { STV090x_P1_AGC2O, 0x5b },
453 { STV090x_P1_AGC2REF, 0x38 },
454 { STV090x_P1_CARCFG, 0xe4 },
455 { STV090x_P1_ACLC, 0x1A },
456 { STV090x_P1_BCLC, 0x09 },
457 { STV090x_P1_CARHDR, 0x08 },
458 { STV090x_P1_KREFTMG, 0xc1 },
459 { STV090x_P1_SFRSTEP, 0x58 },
460 { STV090x_P1_TMGCFG2, 0x01 },
461 { STV090x_P1_CAR2CFG, 0x26 },
462 { STV090x_P1_BCLC2S2Q, 0x86 },
463 { STV090x_P1_BCLC2S28, 0x86 },
464 { STV090x_P1_SMAPCOEF7, 0x77 },
465 { STV090x_P1_SMAPCOEF6, 0x85 },
466 { STV090x_P1_SMAPCOEF5, 0x77 },
467 { STV090x_P1_DMDCFG2, 0x3b },
468 { STV090x_P1_MODCODLST0, 0xff },
469 { STV090x_P1_MODCODLST1, 0xff },
470 { STV090x_P1_MODCODLST2, 0xff },
471 { STV090x_P1_MODCODLST3, 0xff },
472 { STV090x_P1_MODCODLST4, 0xff },
473 { STV090x_P1_MODCODLST5, 0xff },
474 { STV090x_P1_MODCODLST6, 0xff },
475 { STV090x_P1_MODCODLST7, 0xcc },
476 { STV090x_P1_MODCODLST8, 0xcc },
477 { STV090x_P1_MODCODLST9, 0xcc },
478 { STV090x_P1_MODCODLSTA, 0xcc },
479 { STV090x_P1_MODCODLSTB, 0xcc },
480 { STV090x_P1_MODCODLSTC, 0xcc },
481 { STV090x_P1_MODCODLSTD, 0xcc },
482 { STV090x_P1_MODCODLSTE, 0xcc },
483 { STV090x_P1_MODCODLSTF, 0xcf },
484 { STV090x_GENCFG, 0x1c },
485 { STV090x_NBITER_NF4, 0x37 },
486 { STV090x_NBITER_NF5, 0x29 },
487 { STV090x_NBITER_NF6, 0x37 },
488 { STV090x_NBITER_NF7, 0x33 },
489 { STV090x_NBITER_NF8, 0x31 },
490 { STV090x_NBITER_NF9, 0x2f },
491 { STV090x_NBITER_NF10, 0x39 },
492 { STV090x_NBITER_NF11, 0x3a },
493 { STV090x_NBITER_NF12, 0x29 },
494 { STV090x_NBITER_NF13, 0x37 },
495 { STV090x_NBITER_NF14, 0x33 },
496 { STV090x_NBITER_NF15, 0x2f },
497 { STV090x_NBITER_NF16, 0x39 },
498 { STV090x_NBITER_NF17, 0x3a },
499 { STV090x_NBITERNOERR, 0x04 },
500 { STV090x_GAINLLR_NF4, 0x0C },
501 { STV090x_GAINLLR_NF5, 0x0F },
502 { STV090x_GAINLLR_NF6, 0x11 },
503 { STV090x_GAINLLR_NF7, 0x14 },
504 { STV090x_GAINLLR_NF8, 0x17 },
505 { STV090x_GAINLLR_NF9, 0x19 },
506 { STV090x_GAINLLR_NF10, 0x20 },
507 { STV090x_GAINLLR_NF11, 0x21 },
508 { STV090x_GAINLLR_NF12, 0x0D },
509 { STV090x_GAINLLR_NF13, 0x0F },
510 { STV090x_GAINLLR_NF14, 0x13 },
511 { STV090x_GAINLLR_NF15, 0x1A },
512 { STV090x_GAINLLR_NF16, 0x1F },
513 { STV090x_GAINLLR_NF17, 0x21 },
514 { STV090x_RCCFGH, 0x20 },
515 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
516 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
519 static struct stv090x_reg stv0900_cut20_val[] = {
521 { STV090x_P2_DMDCFG3, 0xe8 },
522 { STV090x_P2_DMDCFG4, 0x10 },
523 { STV090x_P2_CARFREQ, 0x38 },
524 { STV090x_P2_CARHDR, 0x20 },
525 { STV090x_P2_KREFTMG, 0x5a },
526 { STV090x_P2_SMAPCOEF7, 0x06 },
527 { STV090x_P2_SMAPCOEF6, 0x00 },
528 { STV090x_P2_SMAPCOEF5, 0x04 },
529 { STV090x_P2_NOSCFG, 0x0c },
530 { STV090x_P1_DMDCFG3, 0xe8 },
531 { STV090x_P1_DMDCFG4, 0x10 },
532 { STV090x_P1_CARFREQ, 0x38 },
533 { STV090x_P1_CARHDR, 0x20 },
534 { STV090x_P1_KREFTMG, 0x5a },
535 { STV090x_P1_SMAPCOEF7, 0x06 },
536 { STV090x_P1_SMAPCOEF6, 0x00 },
537 { STV090x_P1_SMAPCOEF5, 0x04 },
538 { STV090x_P1_NOSCFG, 0x0c },
539 { STV090x_GAINLLR_NF4, 0x21 },
540 { STV090x_GAINLLR_NF5, 0x21 },
541 { STV090x_GAINLLR_NF6, 0x20 },
542 { STV090x_GAINLLR_NF7, 0x1F },
543 { STV090x_GAINLLR_NF8, 0x1E },
544 { STV090x_GAINLLR_NF9, 0x1E },
545 { STV090x_GAINLLR_NF10, 0x1D },
546 { STV090x_GAINLLR_NF11, 0x1B },
547 { STV090x_GAINLLR_NF12, 0x20 },
548 { STV090x_GAINLLR_NF13, 0x20 },
549 { STV090x_GAINLLR_NF14, 0x20 },
550 { STV090x_GAINLLR_NF15, 0x20 },
551 { STV090x_GAINLLR_NF16, 0x20 },
552 { STV090x_GAINLLR_NF17, 0x21 },
555 static struct stv090x_reg stv0903_cut20_val[] = {
556 { STV090x_P1_DMDCFG3, 0xe8 },
557 { STV090x_P1_DMDCFG4, 0x10 },
558 { STV090x_P1_CARFREQ, 0x38 },
559 { STV090x_P1_CARHDR, 0x20 },
560 { STV090x_P1_KREFTMG, 0x5a },
561 { STV090x_P1_SMAPCOEF7, 0x06 },
562 { STV090x_P1_SMAPCOEF6, 0x00 },
563 { STV090x_P1_SMAPCOEF5, 0x04 },
564 { STV090x_P1_NOSCFG, 0x0c },
565 { STV090x_GAINLLR_NF4, 0x21 },
566 { STV090x_GAINLLR_NF5, 0x21 },
567 { STV090x_GAINLLR_NF6, 0x20 },
568 { STV090x_GAINLLR_NF7, 0x1F },
569 { STV090x_GAINLLR_NF8, 0x1E },
570 { STV090x_GAINLLR_NF9, 0x1E },
571 { STV090x_GAINLLR_NF10, 0x1D },
572 { STV090x_GAINLLR_NF11, 0x1B },
573 { STV090x_GAINLLR_NF12, 0x20 },
574 { STV090x_GAINLLR_NF13, 0x20 },
575 { STV090x_GAINLLR_NF14, 0x20 },
576 { STV090x_GAINLLR_NF15, 0x20 },
577 { STV090x_GAINLLR_NF16, 0x20 },
578 { STV090x_GAINLLR_NF17, 0x21 }
581 /* Cut 2.0 Long Frame Tracking CR loop */
582 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
583 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
584 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
585 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
586 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
587 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
588 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
589 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
590 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
591 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
592 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
593 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
594 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
595 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
596 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
597 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
600 /* Cut 3.0 Long Frame Tracking CR loop */
601 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
602 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
603 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
604 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
605 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
606 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
607 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
608 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
609 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
610 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
611 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
612 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
613 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
614 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
615 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
616 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
619 /* Cut 2.0 Long Frame Tracking CR Loop */
620 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
621 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
622 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
623 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
624 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
625 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
626 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
627 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
628 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
629 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
630 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
631 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
632 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
635 /* Cut 3.0 Long Frame Tracking CR Loop */
636 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
637 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
638 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
639 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
640 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
641 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
642 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
643 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
644 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
645 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
646 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
647 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
648 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
651 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
652 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
653 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
654 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
655 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
658 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
659 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
660 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
661 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
662 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
665 /* Cut 2.0 Short Frame Tracking CR Loop */
666 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
667 /* MODCOD 2M 5M 10M 20M 30M */
668 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
669 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
670 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
671 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
674 /* Cut 3.0 Short Frame Tracking CR Loop */
675 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
676 /* MODCOD 2M 5M 10M 20M 30M */
677 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
678 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
679 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
680 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
683 static inline s32 comp2(s32 __x, s32 __width)
688 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
691 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
693 const struct stv090x_config *config = state->config;
696 u8 b0[] = { reg >> 8, reg & 0xff };
699 struct i2c_msg msg[] = {
700 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
701 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
704 ret = i2c_transfer(state->i2c, msg, 2);
706 if (ret != -ERESTARTSYS)
708 "Read error, Reg=[0x%02x], Status=%d",
711 return ret < 0 ? ret : -EREMOTEIO;
713 if (unlikely(*state->verbose >= FE_DEBUGREG))
714 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
717 return (unsigned int) buf;
720 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
722 const struct stv090x_config *config = state->config;
725 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
729 memcpy(&buf[2], data, count);
731 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
734 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
735 for (i = 0; i < count; i++)
736 printk(" %02x", data[i]);
740 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
742 if (ret != -ERESTARTSYS)
743 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
744 reg, data[0], count, ret);
745 return ret < 0 ? ret : -EREMOTEIO;
751 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
753 return stv090x_write_regs(state, reg, &data, 1);
756 static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
758 struct stv090x_state *state = fe->demodulator_priv;
762 mutex_lock(&state->internal->tuner_lock);
764 reg = STV090x_READ_DEMOD(state, I2CRPT);
766 dprintk(FE_DEBUG, 1, "Enable Gate");
767 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
768 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
772 dprintk(FE_DEBUG, 1, "Disable Gate");
773 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
774 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
779 mutex_unlock(&state->internal->tuner_lock);
783 dprintk(FE_ERROR, 1, "I/O error");
784 mutex_unlock(&state->internal->tuner_lock);
788 static void stv090x_get_lock_tmg(struct stv090x_state *state)
790 switch (state->algo) {
791 case STV090x_BLIND_SEARCH:
792 dprintk(FE_DEBUG, 1, "Blind Search");
793 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
794 state->DemodTimeout = 1500;
795 state->FecTimeout = 400;
796 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
797 state->DemodTimeout = 1000;
798 state->FecTimeout = 300;
799 } else { /*SR >20Msps*/
800 state->DemodTimeout = 700;
801 state->FecTimeout = 100;
805 case STV090x_COLD_SEARCH:
806 case STV090x_WARM_SEARCH:
808 dprintk(FE_DEBUG, 1, "Normal Search");
809 if (state->srate <= 1000000) { /*SR <=1Msps*/
810 state->DemodTimeout = 4500;
811 state->FecTimeout = 1700;
812 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
813 state->DemodTimeout = 2500;
814 state->FecTimeout = 1100;
815 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
816 state->DemodTimeout = 1000;
817 state->FecTimeout = 550;
818 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
819 state->DemodTimeout = 700;
820 state->FecTimeout = 250;
821 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
822 state->DemodTimeout = 400;
823 state->FecTimeout = 130;
824 } else { /*SR >20Msps*/
825 state->DemodTimeout = 300;
826 state->FecTimeout = 100;
831 if (state->algo == STV090x_WARM_SEARCH)
832 state->DemodTimeout /= 2;
835 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
839 if (srate > 60000000) {
840 sym = (srate << 4); /* SR * 2^16 / master_clk */
841 sym /= (state->internal->mclk >> 12);
842 } else if (srate > 6000000) {
844 sym /= (state->internal->mclk >> 10);
847 sym /= (state->internal->mclk >> 7);
850 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
852 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
857 dprintk(FE_ERROR, 1, "I/O error");
861 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
865 srate = 105 * (srate / 100);
866 if (srate > 60000000) {
867 sym = (srate << 4); /* SR * 2^16 / master_clk */
868 sym /= (state->internal->mclk >> 12);
869 } else if (srate > 6000000) {
871 sym /= (state->internal->mclk >> 10);
874 sym /= (state->internal->mclk >> 7);
878 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
880 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
883 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
885 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
891 dprintk(FE_ERROR, 1, "I/O error");
895 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
899 srate = 95 * (srate / 100);
900 if (srate > 60000000) {
901 sym = (srate << 4); /* SR * 2^16 / master_clk */
902 sym /= (state->internal->mclk >> 12);
903 } else if (srate > 6000000) {
905 sym /= (state->internal->mclk >> 10);
908 sym /= (state->internal->mclk >> 7);
911 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
913 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
917 dprintk(FE_ERROR, 1, "I/O error");
921 static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
938 return srate + (srate * ro) / 100;
941 static int stv090x_set_vit_thacq(struct stv090x_state *state)
943 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
945 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
947 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
949 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
951 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
953 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
957 dprintk(FE_ERROR, 1, "I/O error");
961 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
963 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
965 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
967 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
969 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
971 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
973 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
977 dprintk(FE_ERROR, 1, "I/O error");
981 static int stv090x_set_viterbi(struct stv090x_state *state)
983 switch (state->search_mode) {
984 case STV090x_SEARCH_AUTO:
985 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
987 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
990 case STV090x_SEARCH_DVBS1:
991 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
993 switch (state->fec) {
995 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1000 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1005 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1010 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1015 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1020 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1025 case STV090x_SEARCH_DSS:
1026 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1028 switch (state->fec) {
1030 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1035 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1040 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1045 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1055 dprintk(FE_ERROR, 1, "I/O error");
1059 static int stv090x_stop_modcod(struct stv090x_state *state)
1061 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1063 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1065 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1067 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1069 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1071 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1073 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1075 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1077 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1079 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1081 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1083 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1085 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1087 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1089 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1091 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1095 dprintk(FE_ERROR, 1, "I/O error");
1099 static int stv090x_activate_modcod(struct stv090x_state *state)
1101 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1103 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1105 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1107 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1109 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1111 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1113 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1115 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1117 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1119 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1121 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1123 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1125 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1127 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1129 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1131 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1136 dprintk(FE_ERROR, 1, "I/O error");
1140 static int stv090x_activate_modcod_single(struct stv090x_state *state)
1143 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1145 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1147 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1149 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1151 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1153 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1155 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1157 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1159 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1161 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1163 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1165 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1167 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1169 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1171 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1173 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1179 dprintk(FE_ERROR, 1, "I/O error");
1183 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1187 switch (state->demod) {
1188 case STV090x_DEMODULATOR_0:
1189 mutex_lock(&state->internal->demod_lock);
1190 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1191 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1192 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1194 mutex_unlock(&state->internal->demod_lock);
1197 case STV090x_DEMODULATOR_1:
1198 mutex_lock(&state->internal->demod_lock);
1199 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1200 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1201 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1203 mutex_unlock(&state->internal->demod_lock);
1207 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1212 mutex_unlock(&state->internal->demod_lock);
1213 dprintk(FE_ERROR, 1, "I/O error");
1217 static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1219 if (state->internal->dev_ver >= 0x30) {
1220 /* Set ACLC BCLC optimised value vs SR */
1221 if (state->srate >= 15000000) {
1222 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1224 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1226 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1227 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1229 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1231 } else if (state->srate < 7000000) {
1232 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1234 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1240 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1242 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1247 dprintk(FE_ERROR, 1, "I/O error");
1251 static int stv090x_delivery_search(struct stv090x_state *state)
1255 switch (state->search_mode) {
1256 case STV090x_SEARCH_DVBS1:
1257 case STV090x_SEARCH_DSS:
1258 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1259 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1260 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1261 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1264 /* Activate Viterbi decoder in legacy search,
1265 * do not use FRESVIT1, might impact VITERBI2
1267 if (stv090x_vitclk_ctl(state, 0) < 0)
1270 if (stv090x_dvbs_track_crl(state) < 0)
1273 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1276 if (stv090x_set_vit_thacq(state) < 0)
1278 if (stv090x_set_viterbi(state) < 0)
1282 case STV090x_SEARCH_DVBS2:
1283 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1284 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1285 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1286 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1288 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1289 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1290 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1293 if (stv090x_vitclk_ctl(state, 1) < 0)
1296 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1298 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1301 if (state->internal->dev_ver <= 0x20) {
1302 /* enable S2 carrier loop */
1303 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1306 /* > Cut 3: Stop carrier 3 */
1307 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1311 if (state->demod_mode != STV090x_SINGLE) {
1312 /* Cut 2: enable link during search */
1313 if (stv090x_activate_modcod(state) < 0)
1316 /* Single demodulator
1317 * Authorize SHORT and LONG frames,
1318 * QPSK, 8PSK, 16APSK and 32APSK
1320 if (stv090x_activate_modcod_single(state) < 0)
1324 if (stv090x_set_vit_thtracq(state) < 0)
1328 case STV090x_SEARCH_AUTO:
1330 /* enable DVB-S2 and DVB-S2 in Auto MODE */
1331 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1332 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1333 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1334 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1336 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1337 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1338 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1341 if (stv090x_vitclk_ctl(state, 0) < 0)
1344 if (stv090x_dvbs_track_crl(state) < 0)
1347 if (state->internal->dev_ver <= 0x20) {
1348 /* enable S2 carrier loop */
1349 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1352 /* > Cut 3: Stop carrier 3 */
1353 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1357 if (state->demod_mode != STV090x_SINGLE) {
1358 /* Cut 2: enable link during search */
1359 if (stv090x_activate_modcod(state) < 0)
1362 /* Single demodulator
1363 * Authorize SHORT and LONG frames,
1364 * QPSK, 8PSK, 16APSK and 32APSK
1366 if (stv090x_activate_modcod_single(state) < 0)
1370 if (stv090x_set_vit_thacq(state) < 0)
1373 if (stv090x_set_viterbi(state) < 0)
1379 dprintk(FE_ERROR, 1, "I/O error");
1383 static int stv090x_start_search(struct stv090x_state *state)
1388 /* Reset demodulator */
1389 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1390 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1391 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1394 if (state->internal->dev_ver <= 0x20) {
1395 if (state->srate <= 5000000) {
1396 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1398 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1400 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1402 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1404 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1407 /*enlarge the timing bandwith for Low SR*/
1408 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1411 /* If the symbol rate is >5 Msps
1412 Set The carrier search up and low to auto mode */
1413 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1415 /*reduce the timing bandwith for high SR*/
1416 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1421 if (state->srate <= 5000000) {
1422 /* enlarge the timing bandwith for Low SR */
1423 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1425 /* reduce timing bandwith for high SR */
1426 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1429 /* Set CFR min and max to manual mode */
1430 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1432 if (state->algo == STV090x_WARM_SEARCH) {
1437 freq_abs = 1000 << 16;
1438 freq_abs /= (state->internal->mclk / 1000);
1439 freq = (s16) freq_abs;
1442 * CFR min =- (SearchRange / 2 + 600KHz)
1443 * CFR max = +(SearchRange / 2 + 600KHz)
1444 * (600KHz for the tuner step size)
1446 freq_abs = (state->search_range / 2000) + 600;
1447 freq_abs = freq_abs << 16;
1448 freq_abs /= (state->internal->mclk / 1000);
1449 freq = (s16) freq_abs;
1452 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1454 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1459 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1461 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1466 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1468 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1471 if (state->internal->dev_ver >= 0x20) {
1472 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1474 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1477 if ((state->search_mode == STV090x_DVBS1) ||
1478 (state->search_mode == STV090x_DSS) ||
1479 (state->search_mode == STV090x_SEARCH_AUTO)) {
1481 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1483 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1488 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1490 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1492 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1495 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1496 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1497 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1498 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1500 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1501 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1502 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1505 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1508 if (state->internal->dev_ver >= 0x20) {
1509 /*Frequency offset detector setting*/
1510 if (state->srate < 2000000) {
1511 if (state->internal->dev_ver <= 0x20) {
1513 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1517 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1520 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1522 } else if (state->srate < 10000000) {
1523 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1525 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1528 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1530 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1534 if (state->srate < 10000000) {
1535 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1538 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1543 switch (state->algo) {
1544 case STV090x_WARM_SEARCH:
1545 /* The symbol rate and the exact
1546 * carrier Frequency are known
1548 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1550 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1554 case STV090x_COLD_SEARCH:
1555 /* The symbol rate is known */
1556 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1558 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1567 dprintk(FE_ERROR, 1, "I/O error");
1571 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1573 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1574 s32 i, j, steps, dir;
1576 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1578 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1579 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1580 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1581 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1584 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1586 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1588 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1590 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1592 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1594 if (stv090x_set_srate(state, 1000000) < 0)
1597 steps = state->search_range / 1000000;
1602 freq_step = (1000000 * 256) / (state->internal->mclk / 256);
1605 for (i = 0; i < steps; i++) {
1607 freq_init = freq_init + (freq_step * i);
1609 freq_init = freq_init - (freq_step * i);
1613 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1615 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1617 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1619 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1624 for (j = 0; j < 10; j++) {
1625 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1626 STV090x_READ_DEMOD(state, AGC2I0);
1629 if (agc2 < agc2_min)
1635 dprintk(FE_ERROR, 1, "I/O error");
1639 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1642 s32 srate, int_1, int_2, tmp_1, tmp_2;
1644 r3 = STV090x_READ_DEMOD(state, SFR3);
1645 r2 = STV090x_READ_DEMOD(state, SFR2);
1646 r1 = STV090x_READ_DEMOD(state, SFR1);
1647 r0 = STV090x_READ_DEMOD(state, SFR0);
1649 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1652 int_2 = srate >> 16;
1654 tmp_1 = clk % 0x10000;
1655 tmp_2 = srate % 0x10000;
1657 srate = (int_1 * int_2) +
1658 ((int_1 * tmp_2) >> 16) +
1659 ((int_2 * tmp_1) >> 16);
1664 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1666 struct dvb_frontend *fe = &state->frontend;
1668 int tmg_lock = 0, i;
1669 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1670 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1673 if (state->internal->dev_ver >= 0x30)
1678 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1679 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1680 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1682 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1684 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1686 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1688 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1690 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1691 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1692 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1693 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1696 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1698 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1700 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1702 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1704 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1706 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1709 if (state->internal->dev_ver >= 0x30) {
1710 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1712 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1715 } else if (state->internal->dev_ver >= 0x20) {
1716 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1718 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1722 if (state->srate <= 2000000)
1724 else if (state->srate <= 5000000)
1726 else if (state->srate <= 12000000)
1731 steps = -1 + ((state->search_range / 1000) / car_step);
1733 steps = (2 * steps) + 1;
1736 else if (steps > 10) {
1738 car_step = (state->search_range / 1000) / 10;
1742 freq = state->frequency;
1744 while ((!tmg_lock) && (cur_step < steps)) {
1745 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1747 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1749 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1751 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1753 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1755 /* trigger acquisition */
1756 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1759 for (i = 0; i < 10; i++) {
1760 reg = STV090x_READ_DEMOD(state, DSTATUS);
1761 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1763 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1764 STV090x_READ_DEMOD(state, AGC2I0);
1767 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1770 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1771 (srate_coarse < 50000000) && (srate_coarse > 850000))
1773 else if (cur_step < steps) {
1775 freq += cur_step * car_step;
1777 freq -= cur_step * car_step;
1780 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1783 if (state->config->tuner_set_frequency) {
1784 if (state->config->tuner_set_frequency(fe, freq) < 0)
1788 if (state->config->tuner_set_bandwidth) {
1789 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1793 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1798 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1801 if (state->config->tuner_get_status) {
1802 if (state->config->tuner_get_status(fe, ®) < 0)
1807 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1809 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1811 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1819 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1821 return srate_coarse;
1824 stv090x_i2c_gate_ctrl(fe, 0);
1826 dprintk(FE_ERROR, 1, "I/O error");
1830 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1832 u32 srate_coarse, freq_coarse, sym, reg;
1834 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1835 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1836 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1837 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1839 if (sym < state->srate)
1842 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1844 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1846 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1848 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1850 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1852 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1853 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1854 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1857 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1860 if (state->internal->dev_ver >= 0x30) {
1861 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1863 } else if (state->internal->dev_ver >= 0x20) {
1864 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1868 if (srate_coarse > 3000000) {
1869 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1870 sym = (sym / 1000) * 65536;
1871 sym /= (state->internal->mclk / 1000);
1872 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1874 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1876 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1877 sym = (sym / 1000) * 65536;
1878 sym /= (state->internal->mclk / 1000);
1879 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1881 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1883 sym = (srate_coarse / 1000) * 65536;
1884 sym /= (state->internal->mclk / 1000);
1885 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1887 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1890 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1891 sym = (sym / 100) * 65536;
1892 sym /= (state->internal->mclk / 100);
1893 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1895 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1897 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1898 sym = (sym / 100) * 65536;
1899 sym /= (state->internal->mclk / 100);
1900 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1902 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1904 sym = (srate_coarse / 100) * 65536;
1905 sym /= (state->internal->mclk / 100);
1906 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1908 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1911 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1913 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1915 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1917 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1921 return srate_coarse;
1924 dprintk(FE_ERROR, 1, "I/O error");
1928 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1930 s32 timer = 0, lock = 0;
1934 while ((timer < timeout) && (!lock)) {
1935 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1936 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1939 case 0: /* searching */
1940 case 1: /* first PLH detected */
1942 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1945 case 2: /* DVB-S2 mode */
1946 case 3: /* DVB-S1/legacy mode */
1947 reg = STV090x_READ_DEMOD(state, DSTATUS);
1948 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1955 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1962 static int stv090x_blind_search(struct stv090x_state *state)
1964 u32 agc2, reg, srate_coarse;
1965 s32 cpt_fail, agc2_ovflw, i;
1966 u8 k_ref, k_max, k_min;
1967 int coarse_fail, lock;
1972 agc2 = stv090x_get_agc2_min_level(state);
1974 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
1978 if (state->internal->dev_ver <= 0x20) {
1979 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1983 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
1987 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1990 if (state->internal->dev_ver >= 0x20) {
1991 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1993 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1995 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1997 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
2003 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2005 if (stv090x_srate_srch_coarse(state) != 0) {
2006 srate_coarse = stv090x_srate_srch_fine(state);
2007 if (srate_coarse != 0) {
2008 stv090x_get_lock_tmg(state);
2009 lock = stv090x_get_dmdlock(state,
2010 state->DemodTimeout);
2017 for (i = 0; i < 10; i++) {
2018 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2019 STV090x_READ_DEMOD(state, AGC2I0);
2022 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2023 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2024 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2028 if ((cpt_fail > 7) || (agc2_ovflw > 7))
2034 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
2040 dprintk(FE_ERROR, 1, "I/O error");
2044 static int stv090x_chk_tmg(struct stv090x_state *state)
2048 u8 freq, tmg_thh, tmg_thl;
2051 freq = STV090x_READ_DEMOD(state, CARFREQ);
2052 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2053 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2054 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2056 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2059 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2060 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2061 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2063 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2066 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2068 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2071 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2073 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2075 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2078 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2082 for (i = 0; i < 10; i++) {
2083 reg = STV090x_READ_DEMOD(state, DSTATUS);
2084 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2091 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2093 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2095 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2098 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2100 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2102 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2108 dprintk(FE_ERROR, 1, "I/O error");
2112 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2114 struct dvb_frontend *fe = &state->frontend;
2117 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2120 if (state->srate >= 10000000)
2121 timeout_lock = timeout_dmd / 3;
2123 timeout_lock = timeout_dmd / 2;
2125 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2127 if (state->srate >= 10000000) {
2128 if (stv090x_chk_tmg(state)) {
2129 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2131 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2133 lock = stv090x_get_dmdlock(state, timeout_dmd);
2138 if (state->srate <= 4000000)
2140 else if (state->srate <= 7000000)
2142 else if (state->srate <= 10000000)
2147 steps = (state->search_range / 1000) / car_step;
2149 steps = 2 * (steps + 1);
2152 else if (steps > 12)
2159 freq = state->frequency;
2160 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2161 while ((cur_step <= steps) && (!lock)) {
2163 freq += cur_step * car_step;
2165 freq -= cur_step * car_step;
2168 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2171 if (state->config->tuner_set_frequency) {
2172 if (state->config->tuner_set_frequency(fe, freq) < 0)
2176 if (state->config->tuner_set_bandwidth) {
2177 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2181 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2186 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2189 if (state->config->tuner_get_status) {
2190 if (state->config->tuner_get_status(fe, ®) < 0)
2195 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2197 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2199 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2202 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2203 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2205 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2207 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2209 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2211 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2223 stv090x_i2c_gate_ctrl(fe, 0);
2225 dprintk(FE_ERROR, 1, "I/O error");
2229 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2231 s32 timeout, inc, steps_max, srate, car_max;
2233 srate = state->srate;
2234 car_max = state->search_range / 1000;
2235 car_max += car_max / 10;
2236 car_max = 65536 * (car_max / 2);
2237 car_max /= (state->internal->mclk / 1000);
2239 if (car_max > 0x4000)
2240 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2243 inc /= state->internal->mclk / 1000;
2248 switch (state->search_mode) {
2249 case STV090x_SEARCH_DVBS1:
2250 case STV090x_SEARCH_DSS:
2251 inc *= 3; /* freq step = 3% of srate */
2255 case STV090x_SEARCH_DVBS2:
2260 case STV090x_SEARCH_AUTO:
2267 if ((inc > car_max) || (inc < 0))
2268 inc = car_max / 2; /* increment <= 1/8 Mclk */
2270 timeout *= 27500; /* 27.5 Msps reference */
2272 timeout /= (srate / 1000);
2274 if ((timeout > 100) || (timeout < 0))
2277 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2278 if ((steps_max > 100) || (steps_max < 0)) {
2279 steps_max = 100; /* max steps <= 100 */
2280 inc = car_max / steps_max;
2283 *timeout_sw = timeout;
2289 static int stv090x_chk_signal(struct stv090x_state *state)
2291 s32 offst_car, agc2, car_max;
2294 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2295 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2296 offst_car = comp2(offst_car, 16);
2298 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2299 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2300 car_max = state->search_range / 1000;
2302 car_max += (car_max / 10); /* 10% margin */
2303 car_max = (65536 * car_max / 2);
2304 car_max /= state->internal->mclk / 1000;
2306 if (car_max > 0x4000)
2309 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2311 dprintk(FE_DEBUG, 1, "No Signal");
2314 dprintk(FE_DEBUG, 1, "Found Signal");
2320 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2322 int no_signal, lock = 0;
2323 s32 cpt_step = 0, offst_freq, car_max;
2326 car_max = state->search_range / 1000;
2327 car_max += (car_max / 10);
2328 car_max = (65536 * car_max / 2);
2329 car_max /= (state->internal->mclk / 1000);
2330 if (car_max > 0x4000)
2336 offst_freq = -car_max + inc;
2339 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2341 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2343 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2345 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2348 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2349 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2350 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2354 if (offst_freq >= 0)
2355 offst_freq = -offst_freq - 2 * inc;
2357 offst_freq = -offst_freq;
2359 offst_freq += 2 * inc;
2364 lock = stv090x_get_dmdlock(state, timeout);
2365 no_signal = stv090x_chk_signal(state);
2369 ((offst_freq - inc) < car_max) &&
2370 ((offst_freq + inc) > -car_max) &&
2371 (cpt_step < steps_max));
2373 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2374 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2375 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2380 dprintk(FE_ERROR, 1, "I/O error");
2384 static int stv090x_sw_algo(struct stv090x_state *state)
2386 int no_signal, zigzag, lock = 0;
2389 s32 dvbs2_fly_wheel;
2390 s32 inc, timeout_step, trials, steps_max;
2393 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2395 switch (state->search_mode) {
2396 case STV090x_SEARCH_DVBS1:
2397 case STV090x_SEARCH_DSS:
2398 /* accelerate the frequency detector */
2399 if (state->internal->dev_ver >= 0x20) {
2400 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2404 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2409 case STV090x_SEARCH_DVBS2:
2410 if (state->internal->dev_ver >= 0x20) {
2411 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2415 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2420 case STV090x_SEARCH_AUTO:
2422 /* accelerate the frequency detector */
2423 if (state->internal->dev_ver >= 0x20) {
2424 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2426 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2430 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2438 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2439 no_signal = stv090x_chk_signal(state);
2442 /*run the SW search 2 times maximum*/
2443 if (lock || no_signal || (trials == 2)) {
2444 /*Check if the demod is not losing lock in DVBS2*/
2445 if (state->internal->dev_ver >= 0x20) {
2446 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2448 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2452 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2453 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2454 /*Check if the demod is not losing lock in DVBS2*/
2455 msleep(timeout_step);
2456 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2457 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2458 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2459 msleep(timeout_step);
2460 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2461 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2463 if (dvbs2_fly_wheel < 0xd) {
2464 /*FALSE lock, The demod is loosing lock */
2467 if (state->internal->dev_ver >= 0x20) {
2468 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2472 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2478 } while ((!lock) && (trials < 2) && (!no_signal));
2482 dprintk(FE_ERROR, 1, "I/O error");
2486 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2489 enum stv090x_delsys delsys;
2491 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2492 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2493 delsys = STV090x_DVBS2;
2494 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2495 reg = STV090x_READ_DEMOD(state, FECM);
2496 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2497 delsys = STV090x_DSS;
2499 delsys = STV090x_DVBS1;
2501 delsys = STV090x_ERROR;
2508 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2510 s32 derot, int_1, int_2, tmp_1, tmp_2;
2512 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2513 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2514 derot |= STV090x_READ_DEMOD(state, CFR0);
2516 derot = comp2(derot, 24);
2518 int_2 = derot >> 12;
2520 /* carrier_frequency = MasterClock * Reg / 2^24 */
2521 tmp_1 = mclk % 0x1000;
2522 tmp_2 = derot % 0x1000;
2524 derot = (int_1 * int_2) +
2525 ((int_1 * tmp_2) >> 12) +
2526 ((int_2 * tmp_1) >> 12);
2531 static int stv090x_get_viterbi(struct stv090x_state *state)
2535 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2536 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2540 state->fec = STV090x_PR12;
2544 state->fec = STV090x_PR23;
2548 state->fec = STV090x_PR34;
2552 state->fec = STV090x_PR56;
2556 state->fec = STV090x_PR67;
2560 state->fec = STV090x_PR78;
2564 state->fec = STV090x_PRERR;
2571 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2573 struct dvb_frontend *fe = &state->frontend;
2577 s32 i = 0, offst_freq;
2581 if (state->algo == STV090x_BLIND_SEARCH) {
2582 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2583 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2584 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
2585 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2590 state->delsys = stv090x_get_std(state);
2592 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2595 if (state->config->tuner_get_frequency) {
2596 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2600 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2603 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
2604 state->frequency += offst_freq;
2606 if (stv090x_get_viterbi(state) < 0)
2609 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2610 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2611 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2612 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2613 reg = STV090x_READ_DEMOD(state, TMGOBS);
2614 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2615 reg = STV090x_READ_DEMOD(state, FECM);
2616 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2618 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2620 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2623 if (state->config->tuner_get_frequency) {
2624 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2628 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2631 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2632 return STV090x_RANGEOK;
2633 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2634 return STV090x_RANGEOK;
2636 return STV090x_OUTOFRANGE; /* Out of Range */
2638 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2639 return STV090x_RANGEOK;
2641 return STV090x_OUTOFRANGE;
2644 return STV090x_OUTOFRANGE;
2647 stv090x_i2c_gate_ctrl(fe, 0);
2649 dprintk(FE_ERROR, 1, "I/O error");
2653 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2657 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2658 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2659 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2661 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2665 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
2671 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2675 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
2677 if (state->internal->dev_ver == 0x20) {
2678 car_loop = stv090x_s2_crl_cut20;
2679 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2680 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2683 car_loop = stv090x_s2_crl_cut30;
2684 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2685 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2688 if (modcod < STV090x_QPSK_12) {
2690 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
2698 while ((i < 14) && (modcod != car_loop[i].modcod))
2703 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
2711 if (modcod <= STV090x_QPSK_25) {
2713 if (state->srate <= 3000000)
2714 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
2715 else if (state->srate <= 7000000)
2716 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
2717 else if (state->srate <= 15000000)
2718 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
2719 else if (state->srate <= 25000000)
2720 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
2722 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
2724 if (state->srate <= 3000000)
2725 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
2726 else if (state->srate <= 7000000)
2727 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
2728 else if (state->srate <= 15000000)
2729 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
2730 else if (state->srate <= 25000000)
2731 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
2733 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
2736 } else if (modcod <= STV090x_8PSK_910) {
2738 if (state->srate <= 3000000)
2739 aclc = car_loop[i].crl_pilots_on_2;
2740 else if (state->srate <= 7000000)
2741 aclc = car_loop[i].crl_pilots_on_5;
2742 else if (state->srate <= 15000000)
2743 aclc = car_loop[i].crl_pilots_on_10;
2744 else if (state->srate <= 25000000)
2745 aclc = car_loop[i].crl_pilots_on_20;
2747 aclc = car_loop[i].crl_pilots_on_30;
2749 if (state->srate <= 3000000)
2750 aclc = car_loop[i].crl_pilots_off_2;
2751 else if (state->srate <= 7000000)
2752 aclc = car_loop[i].crl_pilots_off_5;
2753 else if (state->srate <= 15000000)
2754 aclc = car_loop[i].crl_pilots_off_10;
2755 else if (state->srate <= 25000000)
2756 aclc = car_loop[i].crl_pilots_off_20;
2758 aclc = car_loop[i].crl_pilots_off_30;
2760 } else { /* 16APSK and 32APSK */
2761 if (state->srate <= 3000000)
2762 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
2763 else if (state->srate <= 7000000)
2764 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
2765 else if (state->srate <= 15000000)
2766 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
2767 else if (state->srate <= 25000000)
2768 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
2770 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
2776 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2778 struct stv090x_short_frame_crloop *short_crl = NULL;
2782 switch (state->modulation) {
2790 case STV090x_16APSK:
2793 case STV090x_32APSK:
2798 if (state->internal->dev_ver >= 0x30) {
2799 /* Cut 3.0 and up */
2800 short_crl = stv090x_s2_short_crl_cut30;
2802 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2803 short_crl = stv090x_s2_short_crl_cut20;
2806 if (state->srate <= 3000000)
2807 aclc = short_crl[index].crl_2;
2808 else if (state->srate <= 7000000)
2809 aclc = short_crl[index].crl_5;
2810 else if (state->srate <= 15000000)
2811 aclc = short_crl[index].crl_10;
2812 else if (state->srate <= 25000000)
2813 aclc = short_crl[index].crl_20;
2815 aclc = short_crl[index].crl_30;
2820 static int stv090x_optimize_track(struct stv090x_state *state)
2822 struct dvb_frontend *fe = &state->frontend;
2824 enum stv090x_rolloff rolloff;
2825 enum stv090x_modcod modcod;
2827 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2830 srate = stv090x_get_srate(state, state->internal->mclk);
2831 srate += stv090x_get_tmgoffst(state, srate);
2833 switch (state->delsys) {
2836 if (state->search_mode == STV090x_SEARCH_AUTO) {
2837 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2838 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2839 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2840 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2843 reg = STV090x_READ_DEMOD(state, DEMOD);
2844 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2845 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2846 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2849 if (state->internal->dev_ver >= 0x30) {
2850 if (stv090x_get_viterbi(state) < 0)
2853 if (state->fec == STV090x_PR12) {
2854 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2856 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2859 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2861 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2866 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2871 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2872 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2873 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2874 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2876 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2878 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2880 if (state->frame_len == STV090x_LONG_FRAME) {
2881 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2882 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2883 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2884 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2885 if (modcod <= STV090x_QPSK_910) {
2886 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2887 } else if (modcod <= STV090x_8PSK_910) {
2888 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2890 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2893 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2894 if (modcod <= STV090x_16APSK_910) {
2895 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2897 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2900 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2902 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2907 /*Carrier loop setting for short frame*/
2908 aclc = stv090x_optimize_carloop_short(state);
2909 if (state->modulation == STV090x_QPSK) {
2910 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2912 } else if (state->modulation == STV090x_8PSK) {
2913 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2915 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2917 } else if (state->modulation == STV090x_16APSK) {
2918 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2920 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2922 } else if (state->modulation == STV090x_32APSK) {
2923 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2925 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2930 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2933 case STV090x_UNKNOWN:
2935 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2936 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2937 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2938 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2943 f_1 = STV090x_READ_DEMOD(state, CFR2);
2944 f_0 = STV090x_READ_DEMOD(state, CFR1);
2945 reg = STV090x_READ_DEMOD(state, TMGOBS);
2946 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2948 if (state->algo == STV090x_BLIND_SEARCH) {
2949 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2950 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2951 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2952 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2953 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2955 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2958 if (stv090x_set_srate(state, srate) < 0)
2962 if (stv090x_dvbs_track_crl(state) < 0)
2966 if (state->internal->dev_ver >= 0x20) {
2967 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2968 (state->search_mode == STV090x_SEARCH_DSS) ||
2969 (state->search_mode == STV090x_SEARCH_AUTO)) {
2971 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2973 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2978 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2981 /* AUTO tracking MODE */
2982 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
2984 /* AUTO tracking MODE */
2985 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
2988 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
2989 (state->srate < 10000000)) {
2990 /* update initial carrier freq with the found freq offset */
2991 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2993 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2995 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2997 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
2999 if (state->algo != STV090x_WARM_SEARCH) {
3001 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3004 if (state->config->tuner_set_bandwidth) {
3005 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3009 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3014 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3015 msleep(50); /* blind search: wait 50ms for SR stabilization */
3019 stv090x_get_lock_tmg(state);
3021 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3022 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3024 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3026 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3028 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3033 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3035 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3037 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3039 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3041 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3049 if (state->internal->dev_ver >= 0x20) {
3050 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3054 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3055 stv090x_set_vit_thtracq(state);
3060 stv090x_i2c_gate_ctrl(fe, 0);
3062 dprintk(FE_ERROR, 1, "I/O error");
3066 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3068 s32 timer = 0, lock = 0, stat;
3071 while ((timer < timeout) && (!lock)) {
3072 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3073 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3076 case 0: /* searching */
3077 case 1: /* first PLH detected */
3082 case 2: /* DVB-S2 mode */
3083 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3084 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3087 case 3: /* DVB-S1/legacy mode */
3088 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3089 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3100 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3106 lock = stv090x_get_dmdlock(state, timeout_dmd);
3108 lock = stv090x_get_feclock(state, timeout_fec);
3113 while ((timer < timeout_fec) && (!lock)) {
3114 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3115 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3124 static int stv090x_set_s2rolloff(struct stv090x_state *state)
3128 if (state->internal->dev_ver <= 0x20) {
3129 /* rolloff to auto mode if DVBS2 */
3130 reg = STV090x_READ_DEMOD(state, DEMOD);
3131 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3132 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3135 /* DVB-S2 rolloff to auto mode if DVBS2 */
3136 reg = STV090x_READ_DEMOD(state, DEMOD);
3137 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3138 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3143 dprintk(FE_ERROR, 1, "I/O error");
3148 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3150 struct dvb_frontend *fe = &state->frontend;
3151 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3153 s32 agc1_power, power_iq = 0, i;
3154 int lock = 0, low_sr = 0, no_signal = 0;
3156 reg = STV090x_READ_DEMOD(state, TSCFGH);
3157 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3158 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3161 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3164 if (state->internal->dev_ver >= 0x20) {
3165 if (state->srate > 5000000) {
3166 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3169 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3174 stv090x_get_lock_tmg(state);
3176 if (state->algo == STV090x_BLIND_SEARCH) {
3177 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3178 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3180 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3182 if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
3186 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3188 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3191 if (state->srate < 2000000) {
3193 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3197 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3201 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3204 if (state->internal->dev_ver >= 0x20) {
3205 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3207 if (state->algo == STV090x_COLD_SEARCH)
3208 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3209 else if (state->algo == STV090x_WARM_SEARCH)
3210 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3213 /* if cold start or warm (Symbolrate is known)
3214 * use a Narrow symbol rate scan range
3216 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3219 if (stv090x_set_srate(state, state->srate) < 0)
3222 if (stv090x_set_max_srate(state, state->internal->mclk,
3225 if (stv090x_set_min_srate(state, state->internal->mclk,
3229 if (state->srate >= 10000000)
3236 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3239 if (state->config->tuner_set_bbgain) {
3240 if (state->config->tuner_set_bbgain(fe, 10) < 0) /* 10dB */
3244 if (state->config->tuner_set_frequency) {
3245 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3249 if (state->config->tuner_set_bandwidth) {
3250 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3254 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3259 if (state->config->tuner_get_status) {
3260 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3262 if (state->config->tuner_get_status(fe, ®) < 0)
3264 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3268 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3270 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3271 return STV090x_NOCARRIER;
3276 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3277 STV090x_READ_DEMOD(state, AGCIQIN0));
3279 if (agc1_power == 0) {
3280 /* If AGC1 integrator value is 0
3281 * then read POWERI, POWERQ
3283 for (i = 0; i < 5; i++) {
3284 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3285 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3290 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3291 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3293 signal_state = STV090x_NOAGC1;
3295 reg = STV090x_READ_DEMOD(state, DEMOD);
3296 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3298 if (state->internal->dev_ver <= 0x20) {
3299 /* rolloff to auto mode if DVBS2 */
3300 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3302 /* DVB-S2 rolloff to auto mode if DVBS2 */
3303 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3305 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3308 if (stv090x_delivery_search(state) < 0)
3311 if (state->algo != STV090x_BLIND_SEARCH) {
3312 if (stv090x_start_search(state) < 0)
3317 if (signal_state == STV090x_NOAGC1)
3318 return signal_state;
3320 if (state->algo == STV090x_BLIND_SEARCH)
3321 lock = stv090x_blind_search(state);
3323 else if (state->algo == STV090x_COLD_SEARCH)
3324 lock = stv090x_get_coldlock(state, state->DemodTimeout);
3326 else if (state->algo == STV090x_WARM_SEARCH)
3327 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3329 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3331 if (stv090x_chk_tmg(state))
3332 lock = stv090x_sw_algo(state);
3337 signal_state = stv090x_get_sig_params(state);
3339 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3340 stv090x_optimize_track(state);
3342 if (state->internal->dev_ver >= 0x20) {
3343 /* >= Cut 2.0 :release TS reset after
3344 * demod lock and optimized Tracking
3346 reg = STV090x_READ_DEMOD(state, TSCFGH);
3347 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3348 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3353 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3354 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3357 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3358 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3362 lock = stv090x_get_lock(state, state->FecTimeout,
3365 if (state->delsys == STV090x_DVBS2) {
3366 stv090x_set_s2rolloff(state);
3368 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3369 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3370 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3372 /* Reset DVBS2 packet delinator error counter */
3373 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3374 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3375 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3378 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3381 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3384 /* Reset the Total packet counter */
3385 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3387 /* Reset the packet Error counter2 */
3388 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3391 signal_state = STV090x_NODATA;
3392 no_signal = stv090x_chk_signal(state);
3395 return signal_state;
3398 stv090x_i2c_gate_ctrl(fe, 0);
3400 dprintk(FE_ERROR, 1, "I/O error");
3404 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3406 struct stv090x_state *state = fe->demodulator_priv;
3407 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3409 if (p->frequency == 0)
3410 return DVBFE_ALGO_SEARCH_INVALID;
3412 state->delsys = props->delivery_system;
3413 state->frequency = p->frequency;
3414 state->srate = p->u.qpsk.symbol_rate;
3415 state->search_mode = STV090x_SEARCH_AUTO;
3416 state->algo = STV090x_COLD_SEARCH;
3417 state->fec = STV090x_PRERR;
3418 if (state->srate > 10000000) {
3419 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3420 state->search_range = 10000000;
3422 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3423 state->search_range = 5000000;
3426 if (stv090x_algo(state) == STV090x_RANGEOK) {
3427 dprintk(FE_DEBUG, 1, "Search success!");
3428 return DVBFE_ALGO_SEARCH_SUCCESS;
3430 dprintk(FE_DEBUG, 1, "Search failed!");
3431 return DVBFE_ALGO_SEARCH_FAILED;
3434 return DVBFE_ALGO_SEARCH_ERROR;
3437 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3439 struct stv090x_state *state = fe->demodulator_priv;
3443 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3444 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3446 switch (search_state) {
3447 case 0: /* searching */
3448 case 1: /* first PLH detected */
3450 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3454 case 2: /* DVB-S2 mode */
3455 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3456 reg = STV090x_READ_DEMOD(state, DSTATUS);
3457 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3458 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3459 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3460 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3461 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3462 *status = FE_HAS_SIGNAL |
3472 case 3: /* DVB-S1/legacy mode */
3473 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3474 reg = STV090x_READ_DEMOD(state, DSTATUS);
3475 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3476 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3477 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3478 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3479 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3480 *status = FE_HAS_SIGNAL |
3494 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3496 struct stv090x_state *state = fe->demodulator_priv;
3498 s32 count_4, count_3, count_2, count_1, count_0, count;
3500 enum fe_status status;
3502 stv090x_read_status(fe, &status);
3503 if (!(status & FE_HAS_LOCK)) {
3504 *per = 1 << 23; /* Max PER */
3507 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3508 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3510 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3511 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3513 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3514 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3516 *per = ((h << 16) | (m << 8) | l);
3518 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3519 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3520 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3521 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3522 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3524 if ((!count_4) && (!count_3)) {
3525 count = (count_2 & 0xff) << 16;
3526 count |= (count_1 & 0xff) << 8;
3527 count |= count_0 & 0xff;
3534 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3536 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3541 dprintk(FE_ERROR, 1, "I/O error");
3545 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3550 if ((val >= tab[min].read && val < tab[max].read) ||
3551 (val >= tab[max].read && val < tab[min].read)) {
3552 while ((max - min) > 1) {
3553 med = (max + min) / 2;
3554 if ((val >= tab[min].read && val < tab[med].read) ||
3555 (val >= tab[med].read && val < tab[min].read))
3560 res = ((val - tab[min].read) *
3561 (tab[max].real - tab[min].real) /
3562 (tab[max].read - tab[min].read)) +
3565 if (tab[min].read < tab[max].read) {
3566 if (val < tab[min].read)
3567 res = tab[min].real;
3568 else if (val >= tab[max].read)
3569 res = tab[max].real;
3571 if (val >= tab[min].read)
3572 res = tab[min].real;
3573 else if (val < tab[max].read)
3574 res = tab[max].real;
3581 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3583 struct stv090x_state *state = fe->demodulator_priv;
3585 s32 agc_0, agc_1, agc;
3588 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3589 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3590 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3591 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3592 agc = MAKEWORD16(agc_1, agc_0);
3594 str = stv090x_table_lookup(stv090x_rf_tab,
3595 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3596 if (agc > stv090x_rf_tab[0].read)
3598 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3600 *strength = (str + 100) * 0xFFFF / 100;
3605 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3607 struct stv090x_state *state = fe->demodulator_priv;
3608 u32 reg_0, reg_1, reg, i;
3609 s32 val_0, val_1, val = 0;
3614 switch (state->delsys) {
3616 reg = STV090x_READ_DEMOD(state, DSTATUS);
3617 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3620 for (i = 0; i < 16; i++) {
3621 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3622 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3623 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3624 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3625 val += MAKEWORD16(val_1, val_0);
3629 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3630 div = stv090x_s2cn_tab[0].read -
3631 stv090x_s2cn_tab[last].read;
3632 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3638 reg = STV090x_READ_DEMOD(state, DSTATUS);
3639 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3642 for (i = 0; i < 16; i++) {
3643 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3644 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3645 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3646 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3647 val += MAKEWORD16(val_1, val_0);
3651 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3652 div = stv090x_s1cn_tab[0].read -
3653 stv090x_s1cn_tab[last].read;
3654 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3664 static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3666 struct stv090x_state *state = fe->demodulator_priv;
3669 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3672 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3673 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3674 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3676 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3677 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3682 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3683 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3684 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3693 dprintk(FE_ERROR, 1, "I/O error");
3698 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3700 return DVBFE_ALGO_CUSTOM;
3703 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3705 struct stv090x_state *state = fe->demodulator_priv;
3706 u32 reg, idle = 0, fifo_full = 1;
3709 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3711 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3712 (state->config->diseqc_envelope_mode) ? 4 : 2);
3713 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3714 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3716 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3717 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3720 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3721 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3724 for (i = 0; i < cmd->msg_len; i++) {
3727 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3728 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3731 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3734 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3735 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3736 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3741 while ((!idle) && (i < 10)) {
3742 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3743 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3750 dprintk(FE_ERROR, 1, "I/O error");
3754 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3756 struct stv090x_state *state = fe->demodulator_priv;
3757 u32 reg, idle = 0, fifo_full = 1;
3761 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3763 if (burst == SEC_MINI_A) {
3764 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
3767 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
3771 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3772 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3773 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3775 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3776 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3779 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3780 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3784 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3785 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3788 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3791 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3792 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3793 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3798 while ((!idle) && (i < 10)) {
3799 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3800 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3807 dprintk(FE_ERROR, 1, "I/O error");
3811 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3813 struct stv090x_state *state = fe->demodulator_priv;
3814 u32 reg = 0, i = 0, rx_end = 0;
3816 while ((rx_end != 1) && (i < 10)) {
3819 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3820 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3824 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3825 for (i = 0; i < reply->msg_len; i++)
3826 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3832 static int stv090x_sleep(struct dvb_frontend *fe)
3834 struct stv090x_state *state = fe->demodulator_priv;
3837 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3838 state->device == STV0900 ? "STV0900" : "STV0903");
3840 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3841 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3842 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3845 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3846 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3847 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3852 dprintk(FE_ERROR, 1, "I/O error");
3856 static int stv090x_wakeup(struct dvb_frontend *fe)
3858 struct stv090x_state *state = fe->demodulator_priv;
3861 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3862 state->device == STV0900 ? "STV0900" : "STV0903");
3864 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3865 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3866 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3869 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3870 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
3871 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3876 dprintk(FE_ERROR, 1, "I/O error");
3880 static void stv090x_release(struct dvb_frontend *fe)
3882 struct stv090x_state *state = fe->demodulator_priv;
3884 state->internal->num_used--;
3885 if (state->internal->num_used <= 0) {
3887 dprintk(FE_ERROR, 1, "Actually removing");
3889 remove_dev(state->internal);
3890 kfree(state->internal);
3896 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3900 reg = stv090x_read_reg(state, STV090x_GENCFG);
3902 switch (ldpc_mode) {
3905 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3906 /* set LDPC to dual mode */
3907 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
3910 state->demod_mode = STV090x_DUAL;
3912 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3913 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3914 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3916 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3917 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3920 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
3922 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
3924 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
3926 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
3928 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
3930 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
3932 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
3935 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
3937 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
3939 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
3941 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
3943 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
3945 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
3947 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
3950 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
3952 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
3957 case STV090x_SINGLE:
3958 if (stv090x_stop_modcod(state) < 0)
3960 if (stv090x_activate_modcod_single(state) < 0)
3963 if (state->demod == STV090x_DEMODULATOR_1) {
3964 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3967 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3971 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3972 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3973 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3975 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3976 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3979 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3980 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3981 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3983 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3984 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3991 dprintk(FE_ERROR, 1, "I/O error");
3995 /* return (Hz), clk in Hz*/
3996 static u32 stv090x_get_mclk(struct stv090x_state *state)
3998 const struct stv090x_config *config = state->config;
4002 div = stv090x_read_reg(state, STV090x_NCOARSE);
4003 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4004 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4006 return (div + 1) * config->xtal / ratio; /* kHz */
4009 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4011 const struct stv090x_config *config = state->config;
4012 u32 reg, div, clk_sel;
4014 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4015 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4017 div = ((clk_sel * mclk) / config->xtal) - 1;
4019 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4020 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4021 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4024 state->internal->mclk = stv090x_get_mclk(state);
4026 /*Set the DiseqC frequency to 22KHz */
4027 div = state->internal->mclk / 704000;
4028 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4030 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4035 dprintk(FE_ERROR, 1, "I/O error");
4039 static int stv090x_set_tspath(struct stv090x_state *state)
4043 if (state->internal->dev_ver >= 0x20) {
4044 switch (state->config->ts1_mode) {
4045 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4046 case STV090x_TSMODE_DVBCI:
4047 switch (state->config->ts2_mode) {
4048 case STV090x_TSMODE_SERIAL_PUNCTURED:
4049 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4051 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4054 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4055 case STV090x_TSMODE_DVBCI:
4056 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4058 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4059 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4060 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4062 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4063 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4064 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4066 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4068 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4074 case STV090x_TSMODE_SERIAL_PUNCTURED:
4075 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4077 switch (state->config->ts2_mode) {
4078 case STV090x_TSMODE_SERIAL_PUNCTURED:
4079 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4081 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4085 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4086 case STV090x_TSMODE_DVBCI:
4087 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4094 switch (state->config->ts1_mode) {
4095 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4096 case STV090x_TSMODE_DVBCI:
4097 switch (state->config->ts2_mode) {
4098 case STV090x_TSMODE_SERIAL_PUNCTURED:
4099 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4101 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4104 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4105 case STV090x_TSMODE_DVBCI:
4106 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
4107 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4108 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4109 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4111 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4112 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4113 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4115 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4117 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4123 case STV090x_TSMODE_SERIAL_PUNCTURED:
4124 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4126 switch (state->config->ts2_mode) {
4127 case STV090x_TSMODE_SERIAL_PUNCTURED:
4128 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4130 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4133 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4134 case STV090x_TSMODE_DVBCI:
4135 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4142 switch (state->config->ts1_mode) {
4143 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4144 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4145 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4146 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4147 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4151 case STV090x_TSMODE_DVBCI:
4152 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4153 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4154 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4155 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4159 case STV090x_TSMODE_SERIAL_PUNCTURED:
4160 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4161 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4162 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4163 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4167 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4168 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4169 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4170 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4171 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4179 switch (state->config->ts2_mode) {
4180 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4181 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4182 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4183 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4184 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4188 case STV090x_TSMODE_DVBCI:
4189 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4190 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4191 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4192 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4196 case STV090x_TSMODE_SERIAL_PUNCTURED:
4197 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4198 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4199 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4200 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4204 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4205 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4206 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4207 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4208 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4216 if (state->config->ts1_clk > 0) {
4219 switch (state->config->ts1_mode) {
4220 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4221 case STV090x_TSMODE_DVBCI:
4223 speed = state->internal->mclk /
4224 (state->config->ts1_clk / 4);
4230 case STV090x_TSMODE_SERIAL_PUNCTURED:
4231 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4232 speed = state->internal->mclk /
4233 (state->config->ts1_clk / 32);
4240 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4241 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4242 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4244 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4248 if (state->config->ts2_clk > 0) {
4251 switch (state->config->ts2_mode) {
4252 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4253 case STV090x_TSMODE_DVBCI:
4255 speed = state->internal->mclk /
4256 (state->config->ts2_clk / 4);
4262 case STV090x_TSMODE_SERIAL_PUNCTURED:
4263 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4264 speed = state->internal->mclk /
4265 (state->config->ts2_clk / 32);
4272 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4273 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4274 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4276 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4280 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4281 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4282 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4284 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4285 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4288 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4289 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4290 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4292 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4293 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4298 dprintk(FE_ERROR, 1, "I/O error");
4302 static int stv090x_init(struct dvb_frontend *fe)
4304 struct stv090x_state *state = fe->demodulator_priv;
4305 const struct stv090x_config *config = state->config;
4308 if (state->internal->mclk == 0) {
4309 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4311 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4312 0x20 | config->clk_mode) < 0)
4314 stv090x_get_mclk(state);
4317 if (stv090x_wakeup(fe) < 0) {
4318 dprintk(FE_ERROR, 1, "Error waking device");
4322 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4325 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4326 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4327 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4329 reg = STV090x_READ_DEMOD(state, DEMOD);
4330 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4331 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4334 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
4337 if (config->tuner_set_mode) {
4338 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
4342 if (config->tuner_init) {
4343 if (config->tuner_init(fe) < 0)
4347 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
4350 if (stv090x_set_tspath(state) < 0)
4356 stv090x_i2c_gate_ctrl(fe, 0);
4358 dprintk(FE_ERROR, 1, "I/O error");
4362 static int stv090x_setup(struct dvb_frontend *fe)
4364 struct stv090x_state *state = fe->demodulator_priv;
4365 const struct stv090x_config *config = state->config;
4366 const struct stv090x_reg *stv090x_initval = NULL;
4367 const struct stv090x_reg *stv090x_cut20_val = NULL;
4368 unsigned long t1_size = 0, t2_size = 0;
4373 if (state->device == STV0900) {
4374 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4375 stv090x_initval = stv0900_initval;
4376 t1_size = ARRAY_SIZE(stv0900_initval);
4377 stv090x_cut20_val = stv0900_cut20_val;
4378 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4379 } else if (state->device == STV0903) {
4380 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4381 stv090x_initval = stv0903_initval;
4382 t1_size = ARRAY_SIZE(stv0903_initval);
4383 stv090x_cut20_val = stv0903_cut20_val;
4384 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4390 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4392 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
4397 /* Set No Tuner Mode */
4398 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4400 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
4403 /* I2C repeater OFF */
4404 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4405 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4407 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4410 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4413 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4415 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4420 dprintk(FE_DEBUG, 1, "Setting up initial values");
4421 for (i = 0; i < t1_size; i++) {
4422 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4426 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4427 if (state->internal->dev_ver >= 0x20) {
4428 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4431 /* write cut20_val*/
4432 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4433 for (i = 0; i < t2_size; i++) {
4434 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4438 } else if (state->internal->dev_ver < 0x20) {
4439 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
4440 state->internal->dev_ver);
4443 } else if (state->internal->dev_ver > 0x30) {
4444 /* we shouldn't bail out from here */
4445 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
4446 state->internal->dev_ver);
4449 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4451 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4456 dprintk(FE_ERROR, 1, "I/O error");
4460 static struct dvb_frontend_ops stv090x_ops = {
4463 .name = "STV090x Multistandard",
4465 .frequency_min = 950000,
4466 .frequency_max = 2150000,
4467 .frequency_stepsize = 0,
4468 .frequency_tolerance = 0,
4469 .symbol_rate_min = 1000000,
4470 .symbol_rate_max = 45000000,
4471 .caps = FE_CAN_INVERSION_AUTO |
4474 FE_CAN_2G_MODULATION
4477 .release = stv090x_release,
4478 .init = stv090x_init,
4480 .sleep = stv090x_sleep,
4481 .get_frontend_algo = stv090x_frontend_algo,
4483 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
4485 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
4486 .diseqc_send_burst = stv090x_send_diseqc_burst,
4487 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4488 .set_tone = stv090x_set_tone,
4490 .search = stv090x_search,
4491 .read_status = stv090x_read_status,
4492 .read_ber = stv090x_read_per,
4493 .read_signal_strength = stv090x_read_signal_strength,
4494 .read_snr = stv090x_read_cnr
4498 struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4499 struct i2c_adapter *i2c,
4500 enum stv090x_demodulator demod)
4502 struct stv090x_state *state = NULL;
4503 struct stv090x_dev *temp_int;
4505 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4509 state->verbose = &verbose;
4510 state->config = config;
4512 state->frontend.ops = stv090x_ops;
4513 state->frontend.demodulator_priv = state;
4514 state->demod = demod;
4515 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4516 state->device = config->device;
4517 state->rolloff = STV090x_RO_35; /* default */
4519 temp_int = find_dev(state->i2c,
4520 state->config->address);
4522 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
4523 state->internal = temp_int->internal;
4524 state->internal->num_used++;
4525 dprintk(FE_INFO, 1, "Found Internal Structure!");
4526 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4527 state->device == STV0900 ? "STV0900" : "STV0903",
4529 state->internal->dev_ver);
4530 return &state->frontend;
4532 state->internal = kmalloc(sizeof(struct stv090x_internal),
4534 temp_int = append_internal(state->internal);
4535 state->internal->num_used = 1;
4536 state->internal->mclk = 0;
4537 state->internal->dev_ver = 0;
4538 state->internal->i2c_adap = state->i2c;
4539 state->internal->i2c_addr = state->config->address;
4540 dprintk(FE_INFO, 1, "Create New Internal Structure!");
4543 mutex_init(&state->internal->demod_lock);
4544 mutex_init(&state->internal->tuner_lock);
4546 if (stv090x_sleep(&state->frontend) < 0) {
4547 dprintk(FE_ERROR, 1, "Error putting device to sleep");
4551 if (stv090x_setup(&state->frontend) < 0) {
4552 dprintk(FE_ERROR, 1, "Error setting up device");
4555 if (stv090x_wakeup(&state->frontend) < 0) {
4556 dprintk(FE_ERROR, 1, "Error waking device");
4560 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4561 state->device == STV0900 ? "STV0900" : "STV0903",
4563 state->internal->dev_ver);
4565 return &state->frontend;
4571 EXPORT_SYMBOL(stv090x_attach);
4572 MODULE_PARM_DESC(verbose, "Set Verbosity level");
4573 MODULE_AUTHOR("Manu Abraham");
4574 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4575 MODULE_LICENSE("GPL");