2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/mutex.h>
28 #include <linux/dvb/frontend.h>
29 #include "dvb_frontend.h"
31 #include "stv6110x.h" /* for demodulator internal modes */
33 #include "stv090x_reg.h"
35 #include "stv090x_priv.h"
37 static unsigned int verbose;
38 module_param(verbose, int, 0644);
40 struct mutex demod_lock;
42 /* DVBS1 and DSS C/N Lookup table */
43 static const struct stv090x_tab stv090x_s1cn_tab[] = {
44 { 0, 8917 }, /* 0.0dB */
45 { 5, 8801 }, /* 0.5dB */
46 { 10, 8667 }, /* 1.0dB */
47 { 15, 8522 }, /* 1.5dB */
48 { 20, 8355 }, /* 2.0dB */
49 { 25, 8175 }, /* 2.5dB */
50 { 30, 7979 }, /* 3.0dB */
51 { 35, 7763 }, /* 3.5dB */
52 { 40, 7530 }, /* 4.0dB */
53 { 45, 7282 }, /* 4.5dB */
54 { 50, 7026 }, /* 5.0dB */
55 { 55, 6781 }, /* 5.5dB */
56 { 60, 6514 }, /* 6.0dB */
57 { 65, 6241 }, /* 6.5dB */
58 { 70, 5965 }, /* 7.0dB */
59 { 75, 5690 }, /* 7.5dB */
60 { 80, 5424 }, /* 8.0dB */
61 { 85, 5161 }, /* 8.5dB */
62 { 90, 4902 }, /* 9.0dB */
63 { 95, 4654 }, /* 9.5dB */
64 { 100, 4417 }, /* 10.0dB */
65 { 105, 4186 }, /* 10.5dB */
66 { 110, 3968 }, /* 11.0dB */
67 { 115, 3757 }, /* 11.5dB */
68 { 120, 3558 }, /* 12.0dB */
69 { 125, 3366 }, /* 12.5dB */
70 { 130, 3185 }, /* 13.0dB */
71 { 135, 3012 }, /* 13.5dB */
72 { 140, 2850 }, /* 14.0dB */
73 { 145, 2698 }, /* 14.5dB */
74 { 150, 2550 }, /* 15.0dB */
75 { 160, 2283 }, /* 16.0dB */
76 { 170, 2042 }, /* 17.0dB */
77 { 180, 1827 }, /* 18.0dB */
78 { 190, 1636 }, /* 19.0dB */
79 { 200, 1466 }, /* 20.0dB */
80 { 210, 1315 }, /* 21.0dB */
81 { 220, 1181 }, /* 22.0dB */
82 { 230, 1064 }, /* 23.0dB */
83 { 240, 960 }, /* 24.0dB */
84 { 250, 869 }, /* 25.0dB */
85 { 260, 792 }, /* 26.0dB */
86 { 270, 724 }, /* 27.0dB */
87 { 280, 665 }, /* 28.0dB */
88 { 290, 616 }, /* 29.0dB */
89 { 300, 573 }, /* 30.0dB */
90 { 310, 537 }, /* 31.0dB */
91 { 320, 507 }, /* 32.0dB */
92 { 330, 483 }, /* 33.0dB */
93 { 400, 398 }, /* 40.0dB */
94 { 450, 381 }, /* 45.0dB */
95 { 500, 377 } /* 50.0dB */
98 /* DVBS2 C/N Lookup table */
99 static const struct stv090x_tab stv090x_s2cn_tab[] = {
100 { -30, 13348 }, /* -3.0dB */
101 { -20, 12640 }, /* -2d.0B */
102 { -10, 11883 }, /* -1.0dB */
103 { 0, 11101 }, /* -0.0dB */
104 { 5, 10718 }, /* 0.5dB */
105 { 10, 10339 }, /* 1.0dB */
106 { 15, 9947 }, /* 1.5dB */
107 { 20, 9552 }, /* 2.0dB */
108 { 25, 9183 }, /* 2.5dB */
109 { 30, 8799 }, /* 3.0dB */
110 { 35, 8422 }, /* 3.5dB */
111 { 40, 8062 }, /* 4.0dB */
112 { 45, 7707 }, /* 4.5dB */
113 { 50, 7353 }, /* 5.0dB */
114 { 55, 7025 }, /* 5.5dB */
115 { 60, 6684 }, /* 6.0dB */
116 { 65, 6331 }, /* 6.5dB */
117 { 70, 6036 }, /* 7.0dB */
118 { 75, 5727 }, /* 7.5dB */
119 { 80, 5437 }, /* 8.0dB */
120 { 85, 5164 }, /* 8.5dB */
121 { 90, 4902 }, /* 9.0dB */
122 { 95, 4653 }, /* 9.5dB */
123 { 100, 4408 }, /* 10.0dB */
124 { 105, 4187 }, /* 10.5dB */
125 { 110, 3961 }, /* 11.0dB */
126 { 115, 3751 }, /* 11.5dB */
127 { 120, 3558 }, /* 12.0dB */
128 { 125, 3368 }, /* 12.5dB */
129 { 130, 3191 }, /* 13.0dB */
130 { 135, 3017 }, /* 13.5dB */
131 { 140, 2862 }, /* 14.0dB */
132 { 145, 2710 }, /* 14.5dB */
133 { 150, 2565 }, /* 15.0dB */
134 { 160, 2300 }, /* 16.0dB */
135 { 170, 2058 }, /* 17.0dB */
136 { 180, 1849 }, /* 18.0dB */
137 { 190, 1663 }, /* 19.0dB */
138 { 200, 1495 }, /* 20.0dB */
139 { 210, 1349 }, /* 21.0dB */
140 { 220, 1222 }, /* 22.0dB */
141 { 230, 1110 }, /* 23.0dB */
142 { 240, 1011 }, /* 24.0dB */
143 { 250, 925 }, /* 25.0dB */
144 { 260, 853 }, /* 26.0dB */
145 { 270, 789 }, /* 27.0dB */
146 { 280, 734 }, /* 28.0dB */
147 { 290, 690 }, /* 29.0dB */
148 { 300, 650 }, /* 30.0dB */
149 { 310, 619 }, /* 31.0dB */
150 { 320, 593 }, /* 32.0dB */
151 { 330, 571 }, /* 33.0dB */
152 { 400, 498 }, /* 40.0dB */
153 { 450, 484 }, /* 45.0dB */
154 { 500, 481 } /* 50.0dB */
157 /* RF level C/N lookup table */
158 static const struct stv090x_tab stv090x_rf_tab[] = {
159 { -5, 0xcaa1 }, /* -5dBm */
160 { -10, 0xc229 }, /* -10dBm */
161 { -15, 0xbb08 }, /* -15dBm */
162 { -20, 0xb4bc }, /* -20dBm */
163 { -25, 0xad5a }, /* -25dBm */
164 { -30, 0xa298 }, /* -30dBm */
165 { -35, 0x98a8 }, /* -35dBm */
166 { -40, 0x8389 }, /* -40dBm */
167 { -45, 0x59be }, /* -45dBm */
168 { -50, 0x3a14 }, /* -50dBm */
169 { -55, 0x2d11 }, /* -55dBm */
170 { -60, 0x210d }, /* -60dBm */
171 { -65, 0xa14f }, /* -65dBm */
172 { -70, 0x07aa } /* -70dBm */
176 static struct stv090x_reg stv0900_initval[] = {
178 { STV090x_OUTCFG, 0x00 },
179 { STV090x_MODECFG, 0xff },
180 { STV090x_AGCRF1CFG, 0x11 },
181 { STV090x_AGCRF2CFG, 0x13 },
182 { STV090x_TSGENERAL1X, 0x14 },
183 { STV090x_TSTTNR2, 0x21 },
184 { STV090x_TSTTNR4, 0x21 },
185 { STV090x_P2_DISTXCTL, 0x22 },
186 { STV090x_P2_F22TX, 0xc0 },
187 { STV090x_P2_F22RX, 0xc0 },
188 { STV090x_P2_DISRXCTL, 0x00 },
189 { STV090x_P2_DMDCFGMD, 0xF9 },
190 { STV090x_P2_DEMOD, 0x08 },
191 { STV090x_P2_DMDCFG3, 0xc4 },
192 { STV090x_P2_CARFREQ, 0xed },
193 { STV090x_P2_LDT, 0xd0 },
194 { STV090x_P2_LDT2, 0xb8 },
195 { STV090x_P2_TMGCFG, 0xd2 },
196 { STV090x_P2_TMGTHRISE, 0x20 },
197 { STV090x_P1_TMGCFG, 0xd2 },
199 { STV090x_P2_TMGTHFALL, 0x00 },
200 { STV090x_P2_FECSPY, 0x88 },
201 { STV090x_P2_FSPYDATA, 0x3a },
202 { STV090x_P2_FBERCPT4, 0x00 },
203 { STV090x_P2_FSPYBER, 0x10 },
204 { STV090x_P2_ERRCTRL1, 0x35 },
205 { STV090x_P2_ERRCTRL2, 0xc1 },
206 { STV090x_P2_CFRICFG, 0xf8 },
207 { STV090x_P2_NOSCFG, 0x1c },
208 { STV090x_P2_DMDTOM, 0x20 },
209 { STV090x_P2_CORRELMANT, 0x70 },
210 { STV090x_P2_CORRELABS, 0x88 },
211 { STV090x_P2_AGC2O, 0x5b },
212 { STV090x_P2_AGC2REF, 0x38 },
213 { STV090x_P2_CARCFG, 0xe4 },
214 { STV090x_P2_ACLC, 0x1A },
215 { STV090x_P2_BCLC, 0x09 },
216 { STV090x_P2_CARHDR, 0x08 },
217 { STV090x_P2_KREFTMG, 0xc1 },
218 { STV090x_P2_SFRUPRATIO, 0xf0 },
219 { STV090x_P2_SFRLOWRATIO, 0x70 },
220 { STV090x_P2_SFRSTEP, 0x58 },
221 { STV090x_P2_TMGCFG2, 0x01 },
222 { STV090x_P2_CAR2CFG, 0x26 },
223 { STV090x_P2_BCLC2S2Q, 0x86 },
224 { STV090x_P2_BCLC2S28, 0x86 },
225 { STV090x_P2_SMAPCOEF7, 0x77 },
226 { STV090x_P2_SMAPCOEF6, 0x85 },
227 { STV090x_P2_SMAPCOEF5, 0x77 },
228 { STV090x_P2_TSCFGL, 0x20 },
229 { STV090x_P2_DMDCFG2, 0x3b },
230 { STV090x_P2_MODCODLST0, 0xff },
231 { STV090x_P2_MODCODLST1, 0xff },
232 { STV090x_P2_MODCODLST2, 0xff },
233 { STV090x_P2_MODCODLST3, 0xff },
234 { STV090x_P2_MODCODLST4, 0xff },
235 { STV090x_P2_MODCODLST5, 0xff },
236 { STV090x_P2_MODCODLST6, 0xff },
237 { STV090x_P2_MODCODLST7, 0xcc },
238 { STV090x_P2_MODCODLST8, 0xcc },
239 { STV090x_P2_MODCODLST9, 0xcc },
240 { STV090x_P2_MODCODLSTA, 0xcc },
241 { STV090x_P2_MODCODLSTB, 0xcc },
242 { STV090x_P2_MODCODLSTC, 0xcc },
243 { STV090x_P2_MODCODLSTD, 0xcc },
244 { STV090x_P2_MODCODLSTE, 0xcc },
245 { STV090x_P2_MODCODLSTF, 0xcf },
246 { STV090x_P1_DISTXCTL, 0x22 },
247 { STV090x_P1_F22TX, 0xc0 },
248 { STV090x_P1_F22RX, 0xc0 },
249 { STV090x_P1_DISRXCTL, 0x00 },
250 { STV090x_P1_DMDCFGMD, 0xf9 },
251 { STV090x_P1_DEMOD, 0x08 },
252 { STV090x_P1_DMDCFG3, 0xc4 },
253 { STV090x_P1_DMDTOM, 0x20 },
254 { STV090x_P1_CARFREQ, 0xed },
255 { STV090x_P1_LDT, 0xd0 },
256 { STV090x_P1_LDT2, 0xb8 },
257 { STV090x_P1_TMGCFG, 0xd2 },
258 { STV090x_P1_TMGTHRISE, 0x20 },
259 { STV090x_P1_TMGTHFALL, 0x00 },
260 { STV090x_P1_SFRUPRATIO, 0xf0 },
261 { STV090x_P1_SFRLOWRATIO, 0x70 },
262 { STV090x_P1_TSCFGL, 0x20 },
263 { STV090x_P1_FECSPY, 0x88 },
264 { STV090x_P1_FSPYDATA, 0x3a },
265 { STV090x_P1_FBERCPT4, 0x00 },
266 { STV090x_P1_FSPYBER, 0x10 },
267 { STV090x_P1_ERRCTRL1, 0x35 },
268 { STV090x_P1_ERRCTRL2, 0xc1 },
269 { STV090x_P1_CFRICFG, 0xf8 },
270 { STV090x_P1_NOSCFG, 0x1c },
271 { STV090x_P1_CORRELMANT, 0x70 },
272 { STV090x_P1_CORRELABS, 0x88 },
273 { STV090x_P1_AGC2O, 0x5b },
274 { STV090x_P1_AGC2REF, 0x38 },
275 { STV090x_P1_CARCFG, 0xe4 },
276 { STV090x_P1_ACLC, 0x1A },
277 { STV090x_P1_BCLC, 0x09 },
278 { STV090x_P1_CARHDR, 0x08 },
279 { STV090x_P1_KREFTMG, 0xc1 },
280 { STV090x_P1_SFRSTEP, 0x58 },
281 { STV090x_P1_TMGCFG2, 0x01 },
282 { STV090x_P1_CAR2CFG, 0x26 },
283 { STV090x_P1_BCLC2S2Q, 0x86 },
284 { STV090x_P1_BCLC2S28, 0x86 },
285 { STV090x_P1_SMAPCOEF7, 0x77 },
286 { STV090x_P1_SMAPCOEF6, 0x85 },
287 { STV090x_P1_SMAPCOEF5, 0x77 },
288 { STV090x_P1_DMDCFG2, 0x3b },
289 { STV090x_P1_MODCODLST0, 0xff },
290 { STV090x_P1_MODCODLST1, 0xff },
291 { STV090x_P1_MODCODLST2, 0xff },
292 { STV090x_P1_MODCODLST3, 0xff },
293 { STV090x_P1_MODCODLST4, 0xff },
294 { STV090x_P1_MODCODLST5, 0xff },
295 { STV090x_P1_MODCODLST6, 0xff },
296 { STV090x_P1_MODCODLST7, 0xcc },
297 { STV090x_P1_MODCODLST8, 0xcc },
298 { STV090x_P1_MODCODLST9, 0xcc },
299 { STV090x_P1_MODCODLSTA, 0xcc },
300 { STV090x_P1_MODCODLSTB, 0xcc },
301 { STV090x_P1_MODCODLSTC, 0xcc },
302 { STV090x_P1_MODCODLSTD, 0xcc },
303 { STV090x_P1_MODCODLSTE, 0xcc },
304 { STV090x_P1_MODCODLSTF, 0xcf },
305 { STV090x_GENCFG, 0x1d },
306 { STV090x_NBITER_NF4, 0x37 },
307 { STV090x_NBITER_NF5, 0x29 },
308 { STV090x_NBITER_NF6, 0x37 },
309 { STV090x_NBITER_NF7, 0x33 },
310 { STV090x_NBITER_NF8, 0x31 },
311 { STV090x_NBITER_NF9, 0x2f },
312 { STV090x_NBITER_NF10, 0x39 },
313 { STV090x_NBITER_NF11, 0x3a },
314 { STV090x_NBITER_NF12, 0x29 },
315 { STV090x_NBITER_NF13, 0x37 },
316 { STV090x_NBITER_NF14, 0x33 },
317 { STV090x_NBITER_NF15, 0x2f },
318 { STV090x_NBITER_NF16, 0x39 },
319 { STV090x_NBITER_NF17, 0x3a },
320 { STV090x_NBITERNOERR, 0x04 },
321 { STV090x_GAINLLR_NF4, 0x0C },
322 { STV090x_GAINLLR_NF5, 0x0F },
323 { STV090x_GAINLLR_NF6, 0x11 },
324 { STV090x_GAINLLR_NF7, 0x14 },
325 { STV090x_GAINLLR_NF8, 0x17 },
326 { STV090x_GAINLLR_NF9, 0x19 },
327 { STV090x_GAINLLR_NF10, 0x20 },
328 { STV090x_GAINLLR_NF11, 0x21 },
329 { STV090x_GAINLLR_NF12, 0x0D },
330 { STV090x_GAINLLR_NF13, 0x0F },
331 { STV090x_GAINLLR_NF14, 0x13 },
332 { STV090x_GAINLLR_NF15, 0x1A },
333 { STV090x_GAINLLR_NF16, 0x1F },
334 { STV090x_GAINLLR_NF17, 0x21 },
335 { STV090x_RCCFGH, 0x20 },
336 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
337 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
338 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
339 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
342 static struct stv090x_reg stv0903_initval[] = {
343 { STV090x_OUTCFG, 0x00 },
344 { STV090x_AGCRF1CFG, 0x11 },
345 { STV090x_STOPCLK1, 0x48 },
346 { STV090x_STOPCLK2, 0x14 },
347 { STV090x_TSTTNR1, 0x27 },
348 { STV090x_TSTTNR2, 0x21 },
349 { STV090x_P1_DISTXCTL, 0x22 },
350 { STV090x_P1_F22TX, 0xc0 },
351 { STV090x_P1_F22RX, 0xc0 },
352 { STV090x_P1_DISRXCTL, 0x00 },
353 { STV090x_P1_DMDCFGMD, 0xF9 },
354 { STV090x_P1_DEMOD, 0x08 },
355 { STV090x_P1_DMDCFG3, 0xc4 },
356 { STV090x_P1_CARFREQ, 0xed },
357 { STV090x_P1_TNRCFG2, 0x82 },
358 { STV090x_P1_LDT, 0xd0 },
359 { STV090x_P1_LDT2, 0xb8 },
360 { STV090x_P1_TMGCFG, 0xd2 },
361 { STV090x_P1_TMGTHRISE, 0x20 },
362 { STV090x_P1_TMGTHFALL, 0x00 },
363 { STV090x_P1_SFRUPRATIO, 0xf0 },
364 { STV090x_P1_SFRLOWRATIO, 0x70 },
365 { STV090x_P1_TSCFGL, 0x20 },
366 { STV090x_P1_FECSPY, 0x88 },
367 { STV090x_P1_FSPYDATA, 0x3a },
368 { STV090x_P1_FBERCPT4, 0x00 },
369 { STV090x_P1_FSPYBER, 0x10 },
370 { STV090x_P1_ERRCTRL1, 0x35 },
371 { STV090x_P1_ERRCTRL2, 0xc1 },
372 { STV090x_P1_CFRICFG, 0xf8 },
373 { STV090x_P1_NOSCFG, 0x1c },
374 { STV090x_P1_DMDTOM, 0x20 },
375 { STV090x_P1_CORRELMANT, 0x70 },
376 { STV090x_P1_CORRELABS, 0x88 },
377 { STV090x_P1_AGC2O, 0x5b },
378 { STV090x_P1_AGC2REF, 0x38 },
379 { STV090x_P1_CARCFG, 0xe4 },
380 { STV090x_P1_ACLC, 0x1A },
381 { STV090x_P1_BCLC, 0x09 },
382 { STV090x_P1_CARHDR, 0x08 },
383 { STV090x_P1_KREFTMG, 0xc1 },
384 { STV090x_P1_SFRSTEP, 0x58 },
385 { STV090x_P1_TMGCFG2, 0x01 },
386 { STV090x_P1_CAR2CFG, 0x26 },
387 { STV090x_P1_BCLC2S2Q, 0x86 },
388 { STV090x_P1_BCLC2S28, 0x86 },
389 { STV090x_P1_SMAPCOEF7, 0x77 },
390 { STV090x_P1_SMAPCOEF6, 0x85 },
391 { STV090x_P1_SMAPCOEF5, 0x77 },
392 { STV090x_P1_DMDCFG2, 0x3b },
393 { STV090x_P1_MODCODLST0, 0xff },
394 { STV090x_P1_MODCODLST1, 0xff },
395 { STV090x_P1_MODCODLST2, 0xff },
396 { STV090x_P1_MODCODLST3, 0xff },
397 { STV090x_P1_MODCODLST4, 0xff },
398 { STV090x_P1_MODCODLST5, 0xff },
399 { STV090x_P1_MODCODLST6, 0xff },
400 { STV090x_P1_MODCODLST7, 0xcc },
401 { STV090x_P1_MODCODLST8, 0xcc },
402 { STV090x_P1_MODCODLST9, 0xcc },
403 { STV090x_P1_MODCODLSTA, 0xcc },
404 { STV090x_P1_MODCODLSTB, 0xcc },
405 { STV090x_P1_MODCODLSTC, 0xcc },
406 { STV090x_P1_MODCODLSTD, 0xcc },
407 { STV090x_P1_MODCODLSTE, 0xcc },
408 { STV090x_P1_MODCODLSTF, 0xcf },
409 { STV090x_GENCFG, 0x1c },
410 { STV090x_NBITER_NF4, 0x37 },
411 { STV090x_NBITER_NF5, 0x29 },
412 { STV090x_NBITER_NF6, 0x37 },
413 { STV090x_NBITER_NF7, 0x33 },
414 { STV090x_NBITER_NF8, 0x31 },
415 { STV090x_NBITER_NF9, 0x2f },
416 { STV090x_NBITER_NF10, 0x39 },
417 { STV090x_NBITER_NF11, 0x3a },
418 { STV090x_NBITER_NF12, 0x29 },
419 { STV090x_NBITER_NF13, 0x37 },
420 { STV090x_NBITER_NF14, 0x33 },
421 { STV090x_NBITER_NF15, 0x2f },
422 { STV090x_NBITER_NF16, 0x39 },
423 { STV090x_NBITER_NF17, 0x3a },
424 { STV090x_NBITERNOERR, 0x04 },
425 { STV090x_GAINLLR_NF4, 0x0C },
426 { STV090x_GAINLLR_NF5, 0x0F },
427 { STV090x_GAINLLR_NF6, 0x11 },
428 { STV090x_GAINLLR_NF7, 0x14 },
429 { STV090x_GAINLLR_NF8, 0x17 },
430 { STV090x_GAINLLR_NF9, 0x19 },
431 { STV090x_GAINLLR_NF10, 0x20 },
432 { STV090x_GAINLLR_NF11, 0x21 },
433 { STV090x_GAINLLR_NF12, 0x0D },
434 { STV090x_GAINLLR_NF13, 0x0F },
435 { STV090x_GAINLLR_NF14, 0x13 },
436 { STV090x_GAINLLR_NF15, 0x1A },
437 { STV090x_GAINLLR_NF16, 0x1F },
438 { STV090x_GAINLLR_NF17, 0x21 },
439 { STV090x_RCCFGH, 0x20 },
440 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
441 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
444 static struct stv090x_reg stv0900_cut20_val[] = {
446 { STV090x_P2_DMDCFG3, 0xe8 },
447 { STV090x_P2_DMDCFG4, 0x10 },
448 { STV090x_P2_CARFREQ, 0x38 },
449 { STV090x_P2_CARHDR, 0x20 },
450 { STV090x_P2_KREFTMG, 0x5a },
451 { STV090x_P2_SMAPCOEF7, 0x06 },
452 { STV090x_P2_SMAPCOEF6, 0x00 },
453 { STV090x_P2_SMAPCOEF5, 0x04 },
454 { STV090x_P2_NOSCFG, 0x0c },
455 { STV090x_P1_DMDCFG3, 0xe8 },
456 { STV090x_P1_DMDCFG4, 0x10 },
457 { STV090x_P1_CARFREQ, 0x38 },
458 { STV090x_P1_CARHDR, 0x20 },
459 { STV090x_P1_KREFTMG, 0x5a },
460 { STV090x_P1_SMAPCOEF7, 0x06 },
461 { STV090x_P1_SMAPCOEF6, 0x00 },
462 { STV090x_P1_SMAPCOEF5, 0x04 },
463 { STV090x_P1_NOSCFG, 0x0c },
464 { STV090x_GAINLLR_NF4, 0x21 },
465 { STV090x_GAINLLR_NF5, 0x21 },
466 { STV090x_GAINLLR_NF6, 0x20 },
467 { STV090x_GAINLLR_NF7, 0x1F },
468 { STV090x_GAINLLR_NF8, 0x1E },
469 { STV090x_GAINLLR_NF9, 0x1E },
470 { STV090x_GAINLLR_NF10, 0x1D },
471 { STV090x_GAINLLR_NF11, 0x1B },
472 { STV090x_GAINLLR_NF12, 0x20 },
473 { STV090x_GAINLLR_NF13, 0x20 },
474 { STV090x_GAINLLR_NF14, 0x20 },
475 { STV090x_GAINLLR_NF15, 0x20 },
476 { STV090x_GAINLLR_NF16, 0x20 },
477 { STV090x_GAINLLR_NF17, 0x21 },
480 static struct stv090x_reg stv0903_cut20_val[] = {
481 { STV090x_P1_DMDCFG3, 0xe8 },
482 { STV090x_P1_DMDCFG4, 0x10 },
483 { STV090x_P1_CARFREQ, 0x38 },
484 { STV090x_P1_CARHDR, 0x20 },
485 { STV090x_P1_KREFTMG, 0x5a },
486 { STV090x_P1_SMAPCOEF7, 0x06 },
487 { STV090x_P1_SMAPCOEF6, 0x00 },
488 { STV090x_P1_SMAPCOEF5, 0x04 },
489 { STV090x_P1_NOSCFG, 0x0c },
490 { STV090x_GAINLLR_NF4, 0x21 },
491 { STV090x_GAINLLR_NF5, 0x21 },
492 { STV090x_GAINLLR_NF6, 0x20 },
493 { STV090x_GAINLLR_NF7, 0x1F },
494 { STV090x_GAINLLR_NF8, 0x1E },
495 { STV090x_GAINLLR_NF9, 0x1E },
496 { STV090x_GAINLLR_NF10, 0x1D },
497 { STV090x_GAINLLR_NF11, 0x1B },
498 { STV090x_GAINLLR_NF12, 0x20 },
499 { STV090x_GAINLLR_NF13, 0x20 },
500 { STV090x_GAINLLR_NF14, 0x20 },
501 { STV090x_GAINLLR_NF15, 0x20 },
502 { STV090x_GAINLLR_NF16, 0x20 },
503 { STV090x_GAINLLR_NF17, 0x21 }
506 /* Cut 2.0 Long Frame Tracking CR loop */
507 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
508 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
509 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
510 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
511 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
512 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
513 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
514 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
515 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
516 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
517 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
518 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
519 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
520 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
521 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
522 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
525 /* Cut 3.0 Long Frame Tracking CR loop */
526 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
527 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
528 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
529 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
530 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
531 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
532 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
533 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
534 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
535 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
536 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
537 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
538 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
539 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
540 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
541 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
544 /* Cut 2.0 Long Frame Tracking CR Loop */
545 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
546 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
547 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
548 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
549 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
550 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
551 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
552 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
553 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
554 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
555 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
556 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
557 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
560 /* Cut 3.0 Long Frame Tracking CR Loop */
561 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
562 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
563 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
564 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
565 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
566 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
567 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
568 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
569 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
570 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
571 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
572 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
573 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
576 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
577 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
578 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
579 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
580 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
583 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
584 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
585 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
586 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
587 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
590 /* Cut 2.0 Short Frame Tracking CR Loop */
591 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
592 /* MODCOD 2M 5M 10M 20M 30M */
593 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
594 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
595 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
596 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
599 /* Cut 3.0 Short Frame Tracking CR Loop */
600 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
601 /* MODCOD 2M 5M 10M 20M 30M */
602 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
603 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
604 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
605 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
608 static inline s32 comp2(s32 __x, s32 __width)
613 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
616 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
618 const struct stv090x_config *config = state->config;
621 u8 b0[] = { reg >> 8, reg & 0xff };
624 struct i2c_msg msg[] = {
625 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
626 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
629 ret = i2c_transfer(state->i2c, msg, 2);
631 if (ret != -ERESTARTSYS)
633 "Read error, Reg=[0x%02x], Status=%d",
636 return ret < 0 ? ret : -EREMOTEIO;
638 if (unlikely(*state->verbose >= FE_DEBUGREG))
639 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
642 return (unsigned int) buf;
645 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
647 const struct stv090x_config *config = state->config;
650 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
654 memcpy(&buf[2], data, count);
656 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
659 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
660 for (i = 0; i < count; i++)
661 printk(" %02x", data[i]);
665 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
667 if (ret != -ERESTARTSYS)
668 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
669 reg, data[0], count, ret);
670 return ret < 0 ? ret : -EREMOTEIO;
676 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
678 return stv090x_write_regs(state, reg, &data, 1);
681 static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
683 struct stv090x_state *state = fe->demodulator_priv;
686 reg = STV090x_READ_DEMOD(state, I2CRPT);
688 dprintk(FE_DEBUG, 1, "Enable Gate");
689 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
690 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
694 dprintk(FE_DEBUG, 1, "Disable Gate");
695 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
696 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
701 dprintk(FE_ERROR, 1, "I/O error");
705 static void stv090x_get_lock_tmg(struct stv090x_state *state)
707 switch (state->algo) {
708 case STV090x_BLIND_SEARCH:
709 dprintk(FE_DEBUG, 1, "Blind Search");
710 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
711 state->DemodTimeout = 1500;
712 state->FecTimeout = 400;
713 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
714 state->DemodTimeout = 1000;
715 state->FecTimeout = 300;
716 } else { /*SR >20Msps*/
717 state->DemodTimeout = 700;
718 state->FecTimeout = 100;
722 case STV090x_COLD_SEARCH:
723 case STV090x_WARM_SEARCH:
725 dprintk(FE_DEBUG, 1, "Normal Search");
726 if (state->srate <= 1000000) { /*SR <=1Msps*/
727 state->DemodTimeout = 4500;
728 state->FecTimeout = 1700;
729 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
730 state->DemodTimeout = 2500;
731 state->FecTimeout = 1100;
732 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
733 state->DemodTimeout = 1000;
734 state->FecTimeout = 550;
735 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
736 state->DemodTimeout = 700;
737 state->FecTimeout = 250;
738 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
739 state->DemodTimeout = 400;
740 state->FecTimeout = 130;
741 } else { /*SR >20Msps*/
742 state->DemodTimeout = 300;
743 state->FecTimeout = 100;
748 if (state->algo == STV090x_WARM_SEARCH)
749 state->DemodTimeout /= 2;
752 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
756 if (srate > 60000000) {
757 sym = (srate << 4); /* SR * 2^16 / master_clk */
758 sym /= (state->mclk >> 12);
759 } else if (srate > 6000000) {
761 sym /= (state->mclk >> 10);
764 sym /= (state->mclk >> 7);
767 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
769 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
774 dprintk(FE_ERROR, 1, "I/O error");
778 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
782 srate = 105 * (srate / 100);
783 if (srate > 60000000) {
784 sym = (srate << 4); /* SR * 2^16 / master_clk */
785 sym /= (state->mclk >> 12);
786 } else if (srate > 6000000) {
788 sym /= (state->mclk >> 10);
791 sym /= (state->mclk >> 7);
795 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
797 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
800 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
802 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
808 dprintk(FE_ERROR, 1, "I/O error");
812 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
816 srate = 95 * (srate / 100);
817 if (srate > 60000000) {
818 sym = (srate << 4); /* SR * 2^16 / master_clk */
819 sym /= (state->mclk >> 12);
820 } else if (srate > 6000000) {
822 sym /= (state->mclk >> 10);
825 sym /= (state->mclk >> 7);
828 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
830 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
834 dprintk(FE_ERROR, 1, "I/O error");
838 static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
855 return srate + (srate * ro) / 100;
858 static int stv090x_set_vit_thacq(struct stv090x_state *state)
860 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
862 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
864 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
866 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
868 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
870 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
874 dprintk(FE_ERROR, 1, "I/O error");
878 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
880 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
882 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
884 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
886 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
888 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
890 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
894 dprintk(FE_ERROR, 1, "I/O error");
898 static int stv090x_set_viterbi(struct stv090x_state *state)
900 switch (state->search_mode) {
901 case STV090x_SEARCH_AUTO:
902 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
904 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
907 case STV090x_SEARCH_DVBS1:
908 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
910 switch (state->fec) {
912 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
917 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
922 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
927 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
932 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
937 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
942 case STV090x_SEARCH_DSS:
943 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
945 switch (state->fec) {
947 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
952 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
957 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
962 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
972 dprintk(FE_ERROR, 1, "I/O error");
976 static int stv090x_stop_modcod(struct stv090x_state *state)
978 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
980 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
982 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
984 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
986 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
988 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
990 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
992 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
994 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
996 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
998 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1000 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1002 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1004 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1006 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1008 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1012 dprintk(FE_ERROR, 1, "I/O error");
1016 static int stv090x_activate_modcod(struct stv090x_state *state)
1018 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1020 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1022 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1024 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1026 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1028 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1030 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1032 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1034 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1036 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1038 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1040 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1042 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1044 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1046 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1048 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1053 dprintk(FE_ERROR, 1, "I/O error");
1057 static int stv090x_activate_modcod_single(struct stv090x_state *state)
1060 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1062 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1064 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1066 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1068 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1070 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1072 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1074 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1076 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1078 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1080 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1082 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1084 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1086 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1088 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1090 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1096 dprintk(FE_ERROR, 1, "I/O error");
1100 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1104 switch (state->demod) {
1105 case STV090x_DEMODULATOR_0:
1106 mutex_lock(&demod_lock);
1107 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1108 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1109 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1111 mutex_unlock(&demod_lock);
1114 case STV090x_DEMODULATOR_1:
1115 mutex_lock(&demod_lock);
1116 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1117 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1118 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1120 mutex_unlock(&demod_lock);
1124 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1129 mutex_unlock(&demod_lock);
1130 dprintk(FE_ERROR, 1, "I/O error");
1134 static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1136 if (state->dev_ver >= 0x30) {
1137 /* Set ACLC BCLC optimised value vs SR */
1138 if (state->srate >= 15000000) {
1139 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1141 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1143 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1144 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1146 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1148 } else if (state->srate < 7000000) {
1149 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1151 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1157 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1159 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1164 dprintk(FE_ERROR, 1, "I/O error");
1168 static int stv090x_delivery_search(struct stv090x_state *state)
1172 switch (state->search_mode) {
1173 case STV090x_SEARCH_DVBS1:
1174 case STV090x_SEARCH_DSS:
1175 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1176 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1177 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1178 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1181 /* Activate Viterbi decoder in legacy search,
1182 * do not use FRESVIT1, might impact VITERBI2
1184 if (stv090x_vitclk_ctl(state, 0) < 0)
1187 if (stv090x_dvbs_track_crl(state) < 0)
1190 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1193 if (stv090x_set_vit_thacq(state) < 0)
1195 if (stv090x_set_viterbi(state) < 0)
1199 case STV090x_SEARCH_DVBS2:
1200 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1201 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1202 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1203 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1205 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1206 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1207 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1210 if (stv090x_vitclk_ctl(state, 1) < 0)
1213 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1215 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1218 if (state->dev_ver <= 0x20) {
1219 /* enable S2 carrier loop */
1220 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1223 /* > Cut 3: Stop carrier 3 */
1224 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1228 if (state->demod_mode != STV090x_SINGLE) {
1229 /* Cut 2: enable link during search */
1230 if (stv090x_activate_modcod(state) < 0)
1233 /* Single demodulator
1234 * Authorize SHORT and LONG frames,
1235 * QPSK, 8PSK, 16APSK and 32APSK
1237 if (stv090x_activate_modcod_single(state) < 0)
1241 if (stv090x_set_vit_thtracq(state) < 0)
1245 case STV090x_SEARCH_AUTO:
1247 /* enable DVB-S2 and DVB-S2 in Auto MODE */
1248 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1249 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1250 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1251 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1254 if (stv090x_vitclk_ctl(state, 0) < 0)
1257 if (stv090x_dvbs_track_crl(state) < 0)
1260 if (state->dev_ver <= 0x20) {
1261 /* enable S2 carrier loop */
1262 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1265 /* > Cut 3: Stop carrier 3 */
1266 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1270 if (state->demod_mode != STV090x_SINGLE) {
1271 /* Cut 2: enable link during search */
1272 if (stv090x_activate_modcod(state) < 0)
1275 /* Single demodulator
1276 * Authorize SHORT and LONG frames,
1277 * QPSK, 8PSK, 16APSK and 32APSK
1279 if (stv090x_activate_modcod_single(state) < 0)
1283 if (stv090x_set_vit_thacq(state) < 0)
1286 if (stv090x_set_viterbi(state) < 0)
1292 dprintk(FE_ERROR, 1, "I/O error");
1296 static int stv090x_start_search(struct stv090x_state *state)
1301 /* Reset demodulator */
1302 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1303 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1304 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1307 if (state->dev_ver <= 0x20) {
1308 if (state->srate <= 5000000) {
1309 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1311 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1313 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1315 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1317 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1320 /*enlarge the timing bandwith for Low SR*/
1321 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1324 /* If the symbol rate is >5 Msps
1325 Set The carrier search up and low to auto mode */
1326 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1328 /*reduce the timing bandwith for high SR*/
1329 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1334 if (state->srate <= 5000000) {
1335 /* enlarge the timing bandwith for Low SR */
1336 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1338 /* reduce timing bandwith for high SR */
1339 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1342 /* Set CFR min and max to manual mode */
1343 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1345 if (state->algo == STV090x_WARM_SEARCH) {
1350 freq_abs = 1000 << 16;
1351 freq_abs /= (state->mclk / 1000);
1352 freq = (s16) freq_abs;
1355 * CFR min =- (SearchRange / 2 + 600KHz)
1356 * CFR max = +(SearchRange / 2 + 600KHz)
1357 * (600KHz for the tuner step size)
1359 freq_abs = (state->search_range / 2000) + 600;
1360 freq_abs = freq_abs << 16;
1361 freq_abs /= (state->mclk / 1000);
1362 freq = (s16) freq_abs;
1365 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1367 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1372 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1374 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1379 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1381 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1384 if (state->dev_ver >= 0x20) {
1385 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1387 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1390 if ((state->search_mode == STV090x_DVBS1) ||
1391 (state->search_mode == STV090x_DSS) ||
1392 (state->search_mode == STV090x_SEARCH_AUTO)) {
1394 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1396 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1401 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1403 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1405 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1408 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1409 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1410 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1411 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1413 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1414 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1415 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1418 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1421 if (state->dev_ver >= 0x20) {
1422 /*Frequency offset detector setting*/
1423 if (state->srate < 2000000) {
1424 if (state->dev_ver <= 0x20) {
1426 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1430 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1433 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1435 } else if (state->srate < 10000000) {
1436 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1438 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1441 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1443 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1447 if (state->srate < 10000000) {
1448 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1451 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1456 switch (state->algo) {
1457 case STV090x_WARM_SEARCH:
1458 /* The symbol rate and the exact
1459 * carrier Frequency are known
1461 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1463 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1467 case STV090x_COLD_SEARCH:
1468 /* The symbol rate is known */
1469 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1471 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1480 dprintk(FE_ERROR, 1, "I/O error");
1484 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1486 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1487 s32 i, j, steps, dir;
1489 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1491 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1492 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1493 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1494 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1497 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1499 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1501 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1503 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1505 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1507 if (stv090x_set_srate(state, 1000000) < 0)
1510 steps = state->search_range / 1000000;
1515 freq_step = (1000000 * 256) / (state->mclk / 256);
1518 for (i = 0; i < steps; i++) {
1520 freq_init = freq_init + (freq_step * i);
1522 freq_init = freq_init - (freq_step * i);
1526 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1528 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1530 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1532 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1537 for (j = 0; j < 10; j++) {
1538 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1539 STV090x_READ_DEMOD(state, AGC2I0);
1542 if (agc2 < agc2_min)
1548 dprintk(FE_ERROR, 1, "I/O error");
1552 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1555 s32 srate, int_1, int_2, tmp_1, tmp_2;
1557 r3 = STV090x_READ_DEMOD(state, SFR3);
1558 r2 = STV090x_READ_DEMOD(state, SFR2);
1559 r1 = STV090x_READ_DEMOD(state, SFR1);
1560 r0 = STV090x_READ_DEMOD(state, SFR0);
1562 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1565 int_2 = srate >> 16;
1567 tmp_1 = clk % 0x10000;
1568 tmp_2 = srate % 0x10000;
1570 srate = (int_1 * int_2) +
1571 ((int_1 * tmp_2) >> 16) +
1572 ((int_2 * tmp_1) >> 16);
1577 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1579 struct dvb_frontend *fe = &state->frontend;
1581 int tmg_lock = 0, i;
1582 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1583 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1586 if (state->dev_ver >= 0x30)
1591 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1592 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1593 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1595 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1597 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1599 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1601 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1603 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1604 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1605 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1606 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1609 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1611 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1613 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1615 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1617 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1619 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1622 if (state->dev_ver >= 0x30) {
1623 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1625 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1628 } else if (state->dev_ver >= 0x20) {
1629 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1631 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1635 if (state->srate <= 2000000)
1637 else if (state->srate <= 5000000)
1639 else if (state->srate <= 12000000)
1644 steps = -1 + ((state->search_range / 1000) / car_step);
1646 steps = (2 * steps) + 1;
1649 else if (steps > 10) {
1651 car_step = (state->search_range / 1000) / 10;
1655 freq = state->frequency;
1657 while ((!tmg_lock) && (cur_step < steps)) {
1658 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1660 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1662 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1664 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1666 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1668 /* trigger acquisition */
1669 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1672 for (i = 0; i < 10; i++) {
1673 reg = STV090x_READ_DEMOD(state, DSTATUS);
1674 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1676 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1677 STV090x_READ_DEMOD(state, AGC2I0);
1680 srate_coarse = stv090x_get_srate(state, state->mclk);
1683 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1684 (srate_coarse < 50000000) && (srate_coarse > 850000))
1686 else if (cur_step < steps) {
1688 freq += cur_step * car_step;
1690 freq -= cur_step * car_step;
1693 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1696 if (state->config->tuner_set_frequency) {
1697 if (state->config->tuner_set_frequency(fe, freq) < 0)
1701 if (state->config->tuner_set_bandwidth) {
1702 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1706 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1711 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1714 if (state->config->tuner_get_status) {
1715 if (state->config->tuner_get_status(fe, ®) < 0)
1720 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1722 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1724 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1732 srate_coarse = stv090x_get_srate(state, state->mclk);
1734 return srate_coarse;
1736 dprintk(FE_ERROR, 1, "I/O error");
1740 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1742 u32 srate_coarse, freq_coarse, sym, reg;
1744 srate_coarse = stv090x_get_srate(state, state->mclk);
1745 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1746 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1747 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1749 if (sym < state->srate)
1752 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1754 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1756 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1758 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1760 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1762 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1763 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1764 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1767 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1770 if (state->dev_ver >= 0x30) {
1771 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1773 } else if (state->dev_ver >= 0x20) {
1774 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1778 if (srate_coarse > 3000000) {
1779 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1780 sym = (sym / 1000) * 65536;
1781 sym /= (state->mclk / 1000);
1782 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1784 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1786 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1787 sym = (sym / 1000) * 65536;
1788 sym /= (state->mclk / 1000);
1789 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1791 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1793 sym = (srate_coarse / 1000) * 65536;
1794 sym /= (state->mclk / 1000);
1795 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1797 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1800 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1801 sym = (sym / 100) * 65536;
1802 sym /= (state->mclk / 100);
1803 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1805 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1807 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1808 sym = (sym / 100) * 65536;
1809 sym /= (state->mclk / 100);
1810 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1812 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1814 sym = (srate_coarse / 100) * 65536;
1815 sym /= (state->mclk / 100);
1816 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1818 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1821 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1823 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1825 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1827 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1831 return srate_coarse;
1834 dprintk(FE_ERROR, 1, "I/O error");
1838 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1840 s32 timer = 0, lock = 0;
1844 while ((timer < timeout) && (!lock)) {
1845 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1846 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1849 case 0: /* searching */
1850 case 1: /* first PLH detected */
1852 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1855 case 2: /* DVB-S2 mode */
1856 case 3: /* DVB-S1/legacy mode */
1857 reg = STV090x_READ_DEMOD(state, DSTATUS);
1858 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1865 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1872 static int stv090x_blind_search(struct stv090x_state *state)
1874 u32 agc2, reg, srate_coarse;
1875 s32 cpt_fail, agc2_ovflw, i;
1876 u8 k_ref, k_max, k_min;
1877 int coarse_fail, lock;
1882 agc2 = stv090x_get_agc2_min_level(state);
1884 if (agc2 > STV090x_SEARCH_AGC2_TH(state->dev_ver)) {
1888 if (state->dev_ver <= 0x20) {
1889 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1893 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
1897 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1900 if (state->dev_ver >= 0x20) {
1901 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1903 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1905 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1907 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1913 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
1915 if (stv090x_srate_srch_coarse(state) != 0) {
1916 srate_coarse = stv090x_srate_srch_fine(state);
1917 if (srate_coarse != 0) {
1918 stv090x_get_lock_tmg(state);
1919 lock = stv090x_get_dmdlock(state,
1920 state->DemodTimeout);
1927 for (i = 0; i < 10; i++) {
1928 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1929 STV090x_READ_DEMOD(state, AGC2I0);
1932 reg = STV090x_READ_DEMOD(state, DSTATUS2);
1933 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
1934 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
1938 if ((cpt_fail > 7) || (agc2_ovflw > 7))
1944 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1950 dprintk(FE_ERROR, 1, "I/O error");
1954 static int stv090x_chk_tmg(struct stv090x_state *state)
1958 u8 freq, tmg_thh, tmg_thl;
1961 freq = STV090x_READ_DEMOD(state, CARFREQ);
1962 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
1963 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
1964 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1966 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1969 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1970 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
1971 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1973 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
1976 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
1978 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
1981 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
1983 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1985 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
1988 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
1992 for (i = 0; i < 10; i++) {
1993 reg = STV090x_READ_DEMOD(state, DSTATUS);
1994 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2001 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2003 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2005 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2008 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2010 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2012 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2018 dprintk(FE_ERROR, 1, "I/O error");
2022 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2024 struct dvb_frontend *fe = &state->frontend;
2027 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2030 if (state->srate >= 10000000)
2031 timeout_lock = timeout_dmd / 3;
2033 timeout_lock = timeout_dmd / 2;
2035 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2037 if (state->srate >= 10000000) {
2038 if (stv090x_chk_tmg(state)) {
2039 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2041 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2043 lock = stv090x_get_dmdlock(state, timeout_dmd);
2048 if (state->srate <= 4000000)
2050 else if (state->srate <= 7000000)
2052 else if (state->srate <= 10000000)
2057 steps = (state->search_range / 1000) / car_step;
2059 steps = 2 * (steps + 1);
2062 else if (steps > 12)
2069 freq = state->frequency;
2070 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2071 while ((cur_step <= steps) && (!lock)) {
2073 freq += cur_step * car_step;
2075 freq -= cur_step * car_step;
2078 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2081 if (state->config->tuner_set_frequency) {
2082 if (state->config->tuner_set_frequency(fe, freq) < 0)
2086 if (state->config->tuner_set_bandwidth) {
2087 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2091 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2096 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2099 if (state->config->tuner_get_status) {
2100 if (state->config->tuner_get_status(fe, ®) < 0)
2105 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2107 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2109 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2112 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2113 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2115 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2117 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2119 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2121 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2133 dprintk(FE_ERROR, 1, "I/O error");
2137 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2139 s32 timeout, inc, steps_max, srate, car_max;
2141 srate = state->srate;
2142 car_max = state->search_range / 1000;
2143 car_max += car_max / 10;
2144 car_max = 65536 * (car_max / 2);
2145 car_max /= (state->mclk / 1000);
2147 if (car_max > 0x4000)
2148 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2151 inc /= state->mclk / 1000;
2156 switch (state->search_mode) {
2157 case STV090x_SEARCH_DVBS1:
2158 case STV090x_SEARCH_DSS:
2159 inc *= 3; /* freq step = 3% of srate */
2163 case STV090x_SEARCH_DVBS2:
2168 case STV090x_SEARCH_AUTO:
2175 if ((inc > car_max) || (inc < 0))
2176 inc = car_max / 2; /* increment <= 1/8 Mclk */
2178 timeout *= 27500; /* 27.5 Msps reference */
2180 timeout /= (srate / 1000);
2182 if ((timeout > 100) || (timeout < 0))
2185 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2186 if ((steps_max > 100) || (steps_max < 0)) {
2187 steps_max = 100; /* max steps <= 100 */
2188 inc = car_max / steps_max;
2191 *timeout_sw = timeout;
2197 static int stv090x_chk_signal(struct stv090x_state *state)
2199 s32 offst_car, agc2, car_max;
2202 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2203 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2204 offst_car = comp2(offst_car, 16);
2206 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2207 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2208 car_max = state->search_range / 1000;
2210 car_max += (car_max / 10); /* 10% margin */
2211 car_max = (65536 * car_max / 2);
2212 car_max /= state->mclk / 1000;
2214 if (car_max > 0x4000)
2217 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2219 dprintk(FE_DEBUG, 1, "No Signal");
2222 dprintk(FE_DEBUG, 1, "Found Signal");
2228 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2230 int no_signal, lock = 0;
2231 s32 cpt_step = 0, offst_freq, car_max;
2234 car_max = state->search_range / 1000;
2235 car_max += (car_max / 10);
2236 car_max = (65536 * car_max / 2);
2237 car_max /= (state->mclk / 1000);
2238 if (car_max > 0x4000)
2244 offst_freq = -car_max + inc;
2247 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2249 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2251 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2253 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2256 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2257 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2258 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2262 if (offst_freq >= 0)
2263 offst_freq = -offst_freq - 2 * inc;
2265 offst_freq = -offst_freq;
2267 offst_freq += 2 * inc;
2272 lock = stv090x_get_dmdlock(state, timeout);
2273 no_signal = stv090x_chk_signal(state);
2277 ((offst_freq - inc) < car_max) &&
2278 ((offst_freq + inc) > -car_max) &&
2279 (cpt_step < steps_max));
2281 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2282 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2283 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2288 dprintk(FE_ERROR, 1, "I/O error");
2292 static int stv090x_sw_algo(struct stv090x_state *state)
2294 int no_signal, zigzag, lock = 0;
2297 s32 dvbs2_fly_wheel;
2298 s32 inc, timeout_step, trials, steps_max;
2301 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2303 switch (state->search_mode) {
2304 case STV090x_SEARCH_DVBS1:
2305 case STV090x_SEARCH_DSS:
2306 /* accelerate the frequency detector */
2307 if (state->dev_ver >= 0x20) {
2308 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2312 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2317 case STV090x_SEARCH_DVBS2:
2318 if (state->dev_ver >= 0x20) {
2319 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2323 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2328 case STV090x_SEARCH_AUTO:
2330 /* accelerate the frequency detector */
2331 if (state->dev_ver >= 0x20) {
2332 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2334 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2338 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2346 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2347 no_signal = stv090x_chk_signal(state);
2350 /*run the SW search 2 times maximum*/
2351 if (lock || no_signal || (trials == 2)) {
2352 /*Check if the demod is not losing lock in DVBS2*/
2353 if (state->dev_ver >= 0x20) {
2354 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2356 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2360 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2361 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2362 /*Check if the demod is not losing lock in DVBS2*/
2363 msleep(timeout_step);
2364 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2365 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2366 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2367 msleep(timeout_step);
2368 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2369 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2371 if (dvbs2_fly_wheel < 0xd) {
2372 /*FALSE lock, The demod is loosing lock */
2375 if (state->dev_ver >= 0x20) {
2376 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2380 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2386 } while ((!lock) && (trials < 2) && (!no_signal));
2390 dprintk(FE_ERROR, 1, "I/O error");
2394 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2397 enum stv090x_delsys delsys;
2399 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2400 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2401 delsys = STV090x_DVBS2;
2402 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2403 reg = STV090x_READ_DEMOD(state, FECM);
2404 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2405 delsys = STV090x_DSS;
2407 delsys = STV090x_DVBS1;
2409 delsys = STV090x_ERROR;
2416 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2418 s32 derot, int_1, int_2, tmp_1, tmp_2;
2420 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2421 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2422 derot |= STV090x_READ_DEMOD(state, CFR0);
2424 derot = comp2(derot, 24);
2425 int_1 = state->mclk >> 12;
2426 int_2 = derot >> 12;
2428 /* carrier_frequency = MasterClock * Reg / 2^24 */
2429 tmp_1 = state->mclk % 0x1000;
2430 tmp_2 = derot % 0x1000;
2432 derot = (int_1 * int_2) +
2433 ((int_1 * tmp_2) >> 12) +
2434 ((int_2 * tmp_1) >> 12);
2439 static int stv090x_get_viterbi(struct stv090x_state *state)
2443 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2444 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2448 state->fec = STV090x_PR12;
2452 state->fec = STV090x_PR23;
2456 state->fec = STV090x_PR34;
2460 state->fec = STV090x_PR56;
2464 state->fec = STV090x_PR67;
2468 state->fec = STV090x_PR78;
2472 state->fec = STV090x_PRERR;
2479 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2481 struct dvb_frontend *fe = &state->frontend;
2485 s32 i = 0, offst_freq;
2489 if (state->algo == STV090x_BLIND_SEARCH) {
2490 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2491 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2492 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
2493 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2498 state->delsys = stv090x_get_std(state);
2500 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2503 if (state->config->tuner_get_frequency) {
2504 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2508 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2511 offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
2512 state->frequency += offst_freq;
2514 if (stv090x_get_viterbi(state) < 0)
2517 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2518 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2519 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2520 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2521 reg = STV090x_READ_DEMOD(state, TMGOBS);
2522 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2523 reg = STV090x_READ_DEMOD(state, FECM);
2524 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2526 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2528 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2531 if (state->config->tuner_get_frequency) {
2532 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2536 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2539 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2540 return STV090x_RANGEOK;
2541 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2542 return STV090x_RANGEOK;
2544 return STV090x_OUTOFRANGE; /* Out of Range */
2546 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2547 return STV090x_RANGEOK;
2549 return STV090x_OUTOFRANGE;
2552 return STV090x_OUTOFRANGE;
2554 dprintk(FE_ERROR, 1, "I/O error");
2558 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2562 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2563 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2564 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2566 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2570 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
2576 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2580 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
2582 if (state->dev_ver == 0x20) {
2583 car_loop = stv090x_s2_crl_cut20;
2584 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2585 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2588 car_loop = stv090x_s2_crl_cut30;
2589 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2590 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2593 if (modcod < STV090x_QPSK_12) {
2595 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
2603 while ((i < 14) && (modcod != car_loop[i].modcod))
2608 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
2616 if (modcod <= STV090x_QPSK_25) {
2618 if (state->srate <= 3000000)
2619 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
2620 else if (state->srate <= 7000000)
2621 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
2622 else if (state->srate <= 15000000)
2623 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
2624 else if (state->srate <= 25000000)
2625 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
2627 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
2629 if (state->srate <= 3000000)
2630 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
2631 else if (state->srate <= 7000000)
2632 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
2633 else if (state->srate <= 15000000)
2634 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
2635 else if (state->srate <= 25000000)
2636 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
2638 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
2641 } else if (modcod <= STV090x_8PSK_910) {
2643 if (state->srate <= 3000000)
2644 aclc = car_loop[i].crl_pilots_on_2;
2645 else if (state->srate <= 7000000)
2646 aclc = car_loop[i].crl_pilots_on_5;
2647 else if (state->srate <= 15000000)
2648 aclc = car_loop[i].crl_pilots_on_10;
2649 else if (state->srate <= 25000000)
2650 aclc = car_loop[i].crl_pilots_on_20;
2652 aclc = car_loop[i].crl_pilots_on_30;
2654 if (state->srate <= 3000000)
2655 aclc = car_loop[i].crl_pilots_off_2;
2656 else if (state->srate <= 7000000)
2657 aclc = car_loop[i].crl_pilots_off_5;
2658 else if (state->srate <= 15000000)
2659 aclc = car_loop[i].crl_pilots_off_10;
2660 else if (state->srate <= 25000000)
2661 aclc = car_loop[i].crl_pilots_off_20;
2663 aclc = car_loop[i].crl_pilots_off_30;
2665 } else { /* 16APSK and 32APSK */
2666 if (state->srate <= 3000000)
2667 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
2668 else if (state->srate <= 7000000)
2669 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
2670 else if (state->srate <= 15000000)
2671 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
2672 else if (state->srate <= 25000000)
2673 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
2675 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
2681 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2683 struct stv090x_short_frame_crloop *short_crl = NULL;
2687 switch (state->modulation) {
2695 case STV090x_16APSK:
2698 case STV090x_32APSK:
2703 if (state->dev_ver >= 0x30) {
2704 /* Cut 3.0 and up */
2705 short_crl = stv090x_s2_short_crl_cut30;
2707 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2708 short_crl = stv090x_s2_short_crl_cut20;
2711 if (state->srate <= 3000000)
2712 aclc = short_crl[index].crl_2;
2713 else if (state->srate <= 7000000)
2714 aclc = short_crl[index].crl_5;
2715 else if (state->srate <= 15000000)
2716 aclc = short_crl[index].crl_10;
2717 else if (state->srate <= 25000000)
2718 aclc = short_crl[index].crl_20;
2720 aclc = short_crl[index].crl_30;
2725 static int stv090x_optimize_track(struct stv090x_state *state)
2727 struct dvb_frontend *fe = &state->frontend;
2729 enum stv090x_rolloff rolloff;
2730 enum stv090x_modcod modcod;
2732 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2735 srate = stv090x_get_srate(state, state->mclk);
2736 srate += stv090x_get_tmgoffst(state, srate);
2738 switch (state->delsys) {
2741 if (state->search_mode == STV090x_SEARCH_AUTO) {
2742 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2743 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2744 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2745 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2748 reg = STV090x_READ_DEMOD(state, DEMOD);
2749 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2750 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2751 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2754 if (state->dev_ver >= 0x30) {
2755 if (stv090x_get_viterbi(state) < 0)
2758 if (state->fec == STV090x_PR12) {
2759 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2761 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2764 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2766 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2771 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2776 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2777 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2778 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2779 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2781 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2783 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2785 if (state->frame_len == STV090x_LONG_FRAME) {
2786 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2787 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2788 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2789 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2790 if (modcod <= STV090x_QPSK_910) {
2791 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2792 } else if (modcod <= STV090x_8PSK_910) {
2793 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2795 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2798 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2799 if (modcod <= STV090x_16APSK_910) {
2800 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2802 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2805 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2807 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2812 /*Carrier loop setting for short frame*/
2813 aclc = stv090x_optimize_carloop_short(state);
2814 if (state->modulation == STV090x_QPSK) {
2815 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2817 } else if (state->modulation == STV090x_8PSK) {
2818 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2820 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2822 } else if (state->modulation == STV090x_16APSK) {
2823 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2825 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2827 } else if (state->modulation == STV090x_32APSK) {
2828 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2830 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2835 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2838 case STV090x_UNKNOWN:
2840 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2841 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2842 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2843 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2848 f_1 = STV090x_READ_DEMOD(state, CFR2);
2849 f_0 = STV090x_READ_DEMOD(state, CFR1);
2850 reg = STV090x_READ_DEMOD(state, TMGOBS);
2851 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2853 if (state->algo == STV090x_BLIND_SEARCH) {
2854 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2855 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2856 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2857 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2858 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2860 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2863 if (stv090x_set_srate(state, srate) < 0)
2867 if (stv090x_dvbs_track_crl(state) < 0)
2871 if (state->dev_ver >= 0x20) {
2872 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2873 (state->search_mode == STV090x_SEARCH_DSS) ||
2874 (state->search_mode == STV090x_SEARCH_AUTO)) {
2876 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2878 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2883 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2886 /* AUTO tracking MODE */
2887 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
2889 /* AUTO tracking MODE */
2890 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
2893 if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
2894 /* update initial carrier freq with the found freq offset */
2895 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2897 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2899 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2901 if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
2903 if (state->algo != STV090x_WARM_SEARCH) {
2905 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2908 if (state->config->tuner_set_bandwidth) {
2909 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2913 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2918 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
2919 msleep(50); /* blind search: wait 50ms for SR stabilization */
2923 stv090x_get_lock_tmg(state);
2925 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
2926 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2928 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2930 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2932 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2937 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
2939 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2941 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2943 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2945 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2953 if (state->dev_ver >= 0x20) {
2954 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2958 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
2959 stv090x_set_vit_thtracq(state);
2963 dprintk(FE_ERROR, 1, "I/O error");
2967 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
2969 s32 timer = 0, lock = 0, stat;
2972 while ((timer < timeout) && (!lock)) {
2973 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2974 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
2977 case 0: /* searching */
2978 case 1: /* first PLH detected */
2983 case 2: /* DVB-S2 mode */
2984 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
2985 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
2988 case 3: /* DVB-S1/legacy mode */
2989 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
2990 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3001 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3007 lock = stv090x_get_dmdlock(state, timeout_dmd);
3009 lock = stv090x_get_feclock(state, timeout_fec);
3014 while ((timer < timeout_fec) && (!lock)) {
3015 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3016 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3025 static int stv090x_set_s2rolloff(struct stv090x_state *state)
3029 if (state->dev_ver <= 0x20) {
3030 /* rolloff to auto mode if DVBS2 */
3031 reg = STV090x_READ_DEMOD(state, DEMOD);
3032 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3033 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3036 /* DVB-S2 rolloff to auto mode if DVBS2 */
3037 reg = STV090x_READ_DEMOD(state, DEMOD);
3038 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3039 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3044 dprintk(FE_ERROR, 1, "I/O error");
3049 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3051 struct dvb_frontend *fe = &state->frontend;
3052 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3054 s32 agc1_power, power_iq = 0, i;
3055 int lock = 0, low_sr = 0, no_signal = 0;
3057 reg = STV090x_READ_DEMOD(state, TSCFGH);
3058 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3059 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3062 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3065 if (state->dev_ver >= 0x20) {
3066 if (state->srate > 5000000) {
3067 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3070 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3075 stv090x_get_lock_tmg(state);
3077 if (state->algo == STV090x_BLIND_SEARCH) {
3078 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3079 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3081 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3083 if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
3087 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3089 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3092 if (state->srate < 2000000) {
3094 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3098 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3102 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3105 if (state->dev_ver >= 0x20) {
3106 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3108 if (state->algo == STV090x_COLD_SEARCH)
3109 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3110 else if (state->algo == STV090x_WARM_SEARCH)
3111 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3114 /* if cold start or warm (Symbolrate is known)
3115 * use a Narrow symbol rate scan range
3117 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3120 if (stv090x_set_srate(state, state->srate) < 0)
3123 if (stv090x_set_max_srate(state, state->mclk, state->srate) < 0)
3125 if (stv090x_set_min_srate(state, state->mclk, state->srate) < 0)
3128 if (state->srate >= 10000000)
3135 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3138 if (state->config->tuner_set_bbgain) {
3139 if (state->config->tuner_set_bbgain(fe, 10) < 0) /* 10dB */
3143 if (state->config->tuner_set_frequency) {
3144 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3148 if (state->config->tuner_set_bandwidth) {
3149 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3153 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3158 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3161 if (state->config->tuner_get_status) {
3162 if (state->config->tuner_get_status(fe, ®) < 0)
3167 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3169 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3171 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3175 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3176 STV090x_READ_DEMOD(state, AGCIQIN0));
3178 if (agc1_power == 0) {
3179 /* If AGC1 integrator value is 0
3180 * then read POWERI, POWERQ
3182 for (i = 0; i < 5; i++) {
3183 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3184 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3189 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3190 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3192 signal_state = STV090x_NOAGC1;
3194 reg = STV090x_READ_DEMOD(state, DEMOD);
3195 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3197 if (state->dev_ver <= 0x20) {
3198 /* rolloff to auto mode if DVBS2 */
3199 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3201 /* DVB-S2 rolloff to auto mode if DVBS2 */
3202 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3204 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3207 if (stv090x_delivery_search(state) < 0)
3210 if (state->algo != STV090x_BLIND_SEARCH) {
3211 if (stv090x_start_search(state) < 0)
3216 if (signal_state == STV090x_NOAGC1)
3217 return signal_state;
3219 if (state->algo == STV090x_BLIND_SEARCH)
3220 lock = stv090x_blind_search(state);
3222 else if (state->algo == STV090x_COLD_SEARCH)
3223 lock = stv090x_get_coldlock(state, state->DemodTimeout);
3225 else if (state->algo == STV090x_WARM_SEARCH)
3226 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3228 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3230 if (stv090x_chk_tmg(state))
3231 lock = stv090x_sw_algo(state);
3236 signal_state = stv090x_get_sig_params(state);
3238 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3239 stv090x_optimize_track(state);
3241 if (state->dev_ver >= 0x20) {
3242 /* >= Cut 2.0 :release TS reset after
3243 * demod lock and optimized Tracking
3245 reg = STV090x_READ_DEMOD(state, TSCFGH);
3246 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3247 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3252 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3253 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3256 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3257 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3261 lock = stv090x_get_lock(state, state->FecTimeout,
3264 if (state->delsys == STV090x_DVBS2) {
3265 stv090x_set_s2rolloff(state);
3267 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3268 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3269 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3271 /* Reset DVBS2 packet delinator error counter */
3272 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3273 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3274 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3277 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3280 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3283 /* Reset the Total packet counter */
3284 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3286 /* Reset the packet Error counter2 */
3287 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3290 signal_state = STV090x_NODATA;
3291 no_signal = stv090x_chk_signal(state);
3294 return signal_state;
3297 dprintk(FE_ERROR, 1, "I/O error");
3301 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3303 struct stv090x_state *state = fe->demodulator_priv;
3304 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3306 state->delsys = props->delivery_system;
3307 state->frequency = p->frequency;
3308 state->srate = p->u.qpsk.symbol_rate;
3309 state->search_mode = STV090x_SEARCH_AUTO;
3310 state->algo = STV090x_COLD_SEARCH;
3311 state->fec = STV090x_PRERR;
3312 if (state->srate > 10000000) {
3313 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3314 state->search_range = 10000000;
3316 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3317 state->search_range = 5000000;
3320 if (stv090x_algo(state) == STV090x_RANGEOK) {
3321 dprintk(FE_DEBUG, 1, "Search success!");
3322 return DVBFE_ALGO_SEARCH_SUCCESS;
3324 dprintk(FE_DEBUG, 1, "Search failed!");
3325 return DVBFE_ALGO_SEARCH_FAILED;
3328 return DVBFE_ALGO_SEARCH_ERROR;
3331 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3333 struct stv090x_state *state = fe->demodulator_priv;
3337 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3338 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3340 switch (search_state) {
3341 case 0: /* searching */
3342 case 1: /* first PLH detected */
3344 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3348 case 2: /* DVB-S2 mode */
3349 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3350 reg = STV090x_READ_DEMOD(state, DSTATUS);
3351 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3352 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3353 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3354 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3355 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3356 *status = FE_HAS_CARRIER |
3365 case 3: /* DVB-S1/legacy mode */
3366 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3367 reg = STV090x_READ_DEMOD(state, DSTATUS);
3368 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3369 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3370 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3371 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3372 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3373 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3383 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3385 struct stv090x_state *state = fe->demodulator_priv;
3387 s32 count_4, count_3, count_2, count_1, count_0, count;
3389 enum fe_status status;
3391 stv090x_read_status(fe, &status);
3392 if (!(status & FE_HAS_LOCK)) {
3393 *per = 1 << 23; /* Max PER */
3396 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3397 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3399 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3400 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3402 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3403 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3405 *per = ((h << 16) | (m << 8) | l);
3407 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3408 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3409 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3410 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3411 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3413 if ((!count_4) && (!count_3)) {
3414 count = (count_2 & 0xff) << 16;
3415 count |= (count_1 & 0xff) << 8;
3416 count |= count_0 & 0xff;
3423 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3425 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3430 dprintk(FE_ERROR, 1, "I/O error");
3434 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3439 if ((val >= tab[min].read && val < tab[max].read) ||
3440 (val >= tab[max].read && val < tab[min].read)) {
3441 while ((max - min) > 1) {
3442 med = (max + min) / 2;
3443 if ((val >= tab[min].read && val < tab[med].read) ||
3444 (val >= tab[med].read && val < tab[min].read))
3449 res = ((val - tab[min].read) *
3450 (tab[max].real - tab[min].real) /
3451 (tab[max].read - tab[min].read)) +
3454 if (tab[min].read < tab[max].read) {
3455 if (val < tab[min].read)
3456 res = tab[min].real;
3457 else if (val >= tab[max].read)
3458 res = tab[max].real;
3460 if (val >= tab[min].read)
3461 res = tab[min].real;
3462 else if (val < tab[max].read)
3463 res = tab[max].real;
3470 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3472 struct stv090x_state *state = fe->demodulator_priv;
3474 s32 agc_0, agc_1, agc;
3477 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3478 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3479 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3480 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3481 agc = MAKEWORD16(agc_1, agc_0);
3483 str = stv090x_table_lookup(stv090x_rf_tab,
3484 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3485 if (agc > stv090x_rf_tab[0].read)
3487 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3489 *strength = (str + 100) * 0xFFFF / 100;
3494 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3496 struct stv090x_state *state = fe->demodulator_priv;
3497 u32 reg_0, reg_1, reg, i;
3498 s32 val_0, val_1, val = 0;
3503 switch (state->delsys) {
3505 reg = STV090x_READ_DEMOD(state, DSTATUS);
3506 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3509 for (i = 0; i < 16; i++) {
3510 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3511 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3512 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3513 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3514 val += MAKEWORD16(val_1, val_0);
3518 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3519 div = stv090x_s2cn_tab[0].read -
3520 stv090x_s2cn_tab[last].read;
3521 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3527 reg = STV090x_READ_DEMOD(state, DSTATUS);
3528 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3531 for (i = 0; i < 16; i++) {
3532 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3533 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3534 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3535 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3536 val += MAKEWORD16(val_1, val_0);
3540 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3541 div = stv090x_s1cn_tab[0].read -
3542 stv090x_s1cn_tab[last].read;
3543 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3553 static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3555 struct stv090x_state *state = fe->demodulator_priv;
3558 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3561 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3562 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3563 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3565 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3566 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3571 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3572 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3573 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3582 dprintk(FE_ERROR, 1, "I/O error");
3587 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3589 return DVBFE_ALGO_CUSTOM;
3592 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3594 struct stv090x_state *state = fe->demodulator_priv;
3595 u32 reg, idle = 0, fifo_full = 1;
3598 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3600 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3601 (state->config->diseqc_envelope_mode) ? 4 : 2);
3602 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3603 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3605 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3606 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3609 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3610 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3613 for (i = 0; i < cmd->msg_len; i++) {
3616 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3617 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3620 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3623 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3624 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3625 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3630 while ((!idle) && (i < 10)) {
3631 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3632 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3639 dprintk(FE_ERROR, 1, "I/O error");
3643 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3645 struct stv090x_state *state = fe->demodulator_priv;
3646 u32 reg, idle = 0, fifo_full = 1;
3650 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3652 if (burst == SEC_MINI_A) {
3653 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
3656 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
3660 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3661 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3662 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3664 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3665 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3668 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3669 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3673 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3674 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3677 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3680 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3681 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3682 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3687 while ((!idle) && (i < 10)) {
3688 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3689 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3696 dprintk(FE_ERROR, 1, "I/O error");
3700 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3702 struct stv090x_state *state = fe->demodulator_priv;
3703 u32 reg = 0, i = 0, rx_end = 0;
3705 while ((rx_end != 1) && (i < 10)) {
3708 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3709 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3713 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3714 for (i = 0; i < reply->msg_len; i++)
3715 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3721 static int stv090x_sleep(struct dvb_frontend *fe)
3723 struct stv090x_state *state = fe->demodulator_priv;
3726 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3727 state->device == STV0900 ? "STV0900" : "STV0903");
3729 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3730 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3731 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3734 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3735 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3736 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3741 dprintk(FE_ERROR, 1, "I/O error");
3745 static int stv090x_wakeup(struct dvb_frontend *fe)
3747 struct stv090x_state *state = fe->demodulator_priv;
3750 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3751 state->device == STV0900 ? "STV0900" : "STV0903");
3753 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3754 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3755 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3758 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3759 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
3760 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3765 dprintk(FE_ERROR, 1, "I/O error");
3769 static void stv090x_release(struct dvb_frontend *fe)
3771 struct stv090x_state *state = fe->demodulator_priv;
3776 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3780 reg = stv090x_read_reg(state, STV090x_GENCFG);
3782 switch (ldpc_mode) {
3785 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3786 /* set LDPC to dual mode */
3787 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
3790 state->demod_mode = STV090x_DUAL;
3792 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3793 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3794 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3796 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3797 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3800 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
3802 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
3804 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
3806 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
3808 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
3810 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
3812 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
3815 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
3817 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
3819 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
3821 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
3823 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
3825 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
3827 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
3830 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
3832 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
3837 case STV090x_SINGLE:
3838 if (stv090x_stop_modcod(state) < 0)
3840 if (stv090x_activate_modcod_single(state) < 0)
3843 if (state->demod == STV090x_DEMODULATOR_1) {
3844 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3847 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3851 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3852 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3853 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3855 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3856 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3859 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3860 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3861 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3863 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3864 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3871 dprintk(FE_ERROR, 1, "I/O error");
3875 /* return (Hz), clk in Hz*/
3876 static u32 stv090x_get_mclk(struct stv090x_state *state)
3878 const struct stv090x_config *config = state->config;
3882 div = stv090x_read_reg(state, STV090x_NCOARSE);
3883 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3884 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
3886 return (div + 1) * config->xtal / ratio; /* kHz */
3889 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
3891 const struct stv090x_config *config = state->config;
3892 u32 reg, div, clk_sel;
3894 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3895 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
3897 div = ((clk_sel * mclk) / config->xtal) - 1;
3899 reg = stv090x_read_reg(state, STV090x_NCOARSE);
3900 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
3901 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
3904 state->mclk = stv090x_get_mclk(state);
3906 /*Set the DiseqC frequency to 22KHz */
3907 div = state->mclk / 704000;
3908 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
3910 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
3915 dprintk(FE_ERROR, 1, "I/O error");
3919 static int stv090x_set_tspath(struct stv090x_state *state)
3923 if (state->dev_ver >= 0x20) {
3924 switch (state->config->ts1_mode) {
3925 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3926 case STV090x_TSMODE_DVBCI:
3927 switch (state->config->ts2_mode) {
3928 case STV090x_TSMODE_SERIAL_PUNCTURED:
3929 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3931 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
3934 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3935 case STV090x_TSMODE_DVBCI:
3936 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
3938 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3939 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3940 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3942 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
3943 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3944 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
3946 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3948 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3954 case STV090x_TSMODE_SERIAL_PUNCTURED:
3955 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3957 switch (state->config->ts2_mode) {
3958 case STV090x_TSMODE_SERIAL_PUNCTURED:
3959 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3961 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3965 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3966 case STV090x_TSMODE_DVBCI:
3967 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
3974 switch (state->config->ts1_mode) {
3975 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3976 case STV090x_TSMODE_DVBCI:
3977 switch (state->config->ts2_mode) {
3978 case STV090x_TSMODE_SERIAL_PUNCTURED:
3979 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3981 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
3984 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3985 case STV090x_TSMODE_DVBCI:
3986 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
3987 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3988 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3989 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3991 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3992 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
3993 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3995 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3997 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4003 case STV090x_TSMODE_SERIAL_PUNCTURED:
4004 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4006 switch (state->config->ts2_mode) {
4007 case STV090x_TSMODE_SERIAL_PUNCTURED:
4008 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4010 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4013 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4014 case STV090x_TSMODE_DVBCI:
4015 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4022 switch (state->config->ts1_mode) {
4023 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4024 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4025 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4026 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4027 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4031 case STV090x_TSMODE_DVBCI:
4032 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4033 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4034 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4035 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4039 case STV090x_TSMODE_SERIAL_PUNCTURED:
4040 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4041 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4042 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4043 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4047 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4048 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4049 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4050 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4051 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4059 switch (state->config->ts2_mode) {
4060 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4061 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4062 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4063 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4064 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4068 case STV090x_TSMODE_DVBCI:
4069 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4070 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4071 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4072 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4076 case STV090x_TSMODE_SERIAL_PUNCTURED:
4077 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4078 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4079 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4080 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4084 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4085 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4086 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4087 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4088 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4095 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4096 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4097 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4099 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4100 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4103 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4104 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4105 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4107 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4108 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4113 dprintk(FE_ERROR, 1, "I/O error");
4117 static int stv090x_init(struct dvb_frontend *fe)
4119 struct stv090x_state *state = fe->demodulator_priv;
4120 const struct stv090x_config *config = state->config;
4123 if (stv090x_wakeup(fe) < 0) {
4124 dprintk(FE_ERROR, 1, "Error waking device");
4128 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4131 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4132 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4133 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4135 reg = STV090x_READ_DEMOD(state, DEMOD);
4136 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4137 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4140 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
4143 if (config->tuner_set_mode) {
4144 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
4148 if (config->tuner_init) {
4149 if (config->tuner_init(fe) < 0)
4153 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
4156 if (stv090x_set_tspath(state) < 0)
4161 dprintk(FE_ERROR, 1, "I/O error");
4165 static int stv090x_setup(struct dvb_frontend *fe)
4167 struct stv090x_state *state = fe->demodulator_priv;
4168 const struct stv090x_config *config = state->config;
4169 const struct stv090x_reg *stv090x_initval = NULL;
4170 const struct stv090x_reg *stv090x_cut20_val = NULL;
4171 unsigned long t1_size = 0, t2_size = 0;
4176 if (state->device == STV0900) {
4177 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4178 stv090x_initval = stv0900_initval;
4179 t1_size = ARRAY_SIZE(stv0900_initval);
4180 stv090x_cut20_val = stv0900_cut20_val;
4181 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4182 } else if (state->device == STV0903) {
4183 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4184 stv090x_initval = stv0903_initval;
4185 t1_size = ARRAY_SIZE(stv0903_initval);
4186 stv090x_cut20_val = stv0903_cut20_val;
4187 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4191 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
4196 if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
4199 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4200 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
4203 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4206 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4208 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4213 dprintk(FE_DEBUG, 1, "Setting up initial values");
4214 for (i = 0; i < t1_size; i++) {
4215 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4219 state->dev_ver = stv090x_read_reg(state, STV090x_MID);
4220 if (state->dev_ver >= 0x20) {
4221 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4224 /* write cut20_val*/
4225 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4226 for (i = 0; i < t2_size; i++) {
4227 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4231 } else if (state->dev_ver < 0x20) {
4232 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
4236 } else if (state->dev_ver > 0x30) {
4237 /* we shouldn't bail out from here */
4238 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
4242 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4244 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4247 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4249 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
4251 stv090x_get_mclk(state);
4255 dprintk(FE_ERROR, 1, "I/O error");
4259 static struct dvb_frontend_ops stv090x_ops = {
4262 .name = "STV090x Multistandard",
4264 .frequency_min = 950000,
4265 .frequency_max = 2150000,
4266 .frequency_stepsize = 0,
4267 .frequency_tolerance = 0,
4268 .symbol_rate_min = 1000000,
4269 .symbol_rate_max = 45000000,
4270 .caps = FE_CAN_INVERSION_AUTO |
4273 FE_CAN_2G_MODULATION
4276 .release = stv090x_release,
4277 .init = stv090x_init,
4279 .sleep = stv090x_sleep,
4280 .get_frontend_algo = stv090x_frontend_algo,
4282 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
4284 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
4285 .diseqc_send_burst = stv090x_send_diseqc_burst,
4286 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4287 .set_tone = stv090x_set_tone,
4289 .search = stv090x_search,
4290 .read_status = stv090x_read_status,
4291 .read_ber = stv090x_read_per,
4292 .read_signal_strength = stv090x_read_signal_strength,
4293 .read_snr = stv090x_read_cnr
4297 struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4298 struct i2c_adapter *i2c,
4299 enum stv090x_demodulator demod)
4301 struct stv090x_state *state = NULL;
4303 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4307 state->verbose = &verbose;
4308 state->config = config;
4310 state->frontend.ops = stv090x_ops;
4311 state->frontend.demodulator_priv = state;
4312 state->demod = demod;
4313 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4314 state->device = config->device;
4315 state->rolloff = STV090x_RO_35; /* default */
4317 if (state->demod == STV090x_DEMODULATOR_0)
4318 mutex_init(&demod_lock);
4320 if (stv090x_sleep(&state->frontend) < 0) {
4321 dprintk(FE_ERROR, 1, "Error putting device to sleep");
4325 if (stv090x_setup(&state->frontend) < 0) {
4326 dprintk(FE_ERROR, 1, "Error setting up device");
4329 if (stv090x_wakeup(&state->frontend) < 0) {
4330 dprintk(FE_ERROR, 1, "Error waking device");
4334 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
4335 state->device == STV0900 ? "STV0900" : "STV0903",
4339 return &state->frontend;
4345 EXPORT_SYMBOL(stv090x_attach);
4346 MODULE_PARM_DESC(verbose, "Set Verbosity level");
4347 MODULE_AUTHOR("Manu Abraham");
4348 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4349 MODULE_LICENSE("GPL");