2 Driver for Philips tda1004xh OFDM Demodulator
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware
27 * or /lib/firmware (depending on configuration of firmware hotplug).
29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/device.h>
36 #include <linux/jiffies.h>
37 #include <linux/string.h>
38 #include <linux/slab.h>
40 #include "dvb_frontend.h"
44 TDA1004X_DEMOD_TDA10045,
45 TDA1004X_DEMOD_TDA10046,
48 struct tda1004x_state {
49 struct i2c_adapter* i2c;
50 const struct tda1004x_config* config;
51 struct dvb_frontend frontend;
53 /* private demod data */
54 enum tda1004x_demod demod_type;
58 #define dprintk(args...) \
60 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
63 #define TDA1004X_CHIPID 0x00
64 #define TDA1004X_AUTO 0x01
65 #define TDA1004X_IN_CONF1 0x02
66 #define TDA1004X_IN_CONF2 0x03
67 #define TDA1004X_OUT_CONF1 0x04
68 #define TDA1004X_OUT_CONF2 0x05
69 #define TDA1004X_STATUS_CD 0x06
70 #define TDA1004X_CONFC4 0x07
71 #define TDA1004X_DSSPARE2 0x0C
72 #define TDA10045H_CODE_IN 0x0D
73 #define TDA10045H_FWPAGE 0x0E
74 #define TDA1004X_SCAN_CPT 0x10
75 #define TDA1004X_DSP_CMD 0x11
76 #define TDA1004X_DSP_ARG 0x12
77 #define TDA1004X_DSP_DATA1 0x13
78 #define TDA1004X_DSP_DATA2 0x14
79 #define TDA1004X_CONFADC1 0x15
80 #define TDA1004X_CONFC1 0x16
81 #define TDA10045H_S_AGC 0x1a
82 #define TDA10046H_AGC_TUN_LEVEL 0x1a
83 #define TDA1004X_SNR 0x1c
84 #define TDA1004X_CONF_TS1 0x1e
85 #define TDA1004X_CONF_TS2 0x1f
86 #define TDA1004X_CBER_RESET 0x20
87 #define TDA1004X_CBER_MSB 0x21
88 #define TDA1004X_CBER_LSB 0x22
89 #define TDA1004X_CVBER_LUT 0x23
90 #define TDA1004X_VBER_MSB 0x24
91 #define TDA1004X_VBER_MID 0x25
92 #define TDA1004X_VBER_LSB 0x26
93 #define TDA1004X_UNCOR 0x27
95 #define TDA10045H_CONFPLL_P 0x2D
96 #define TDA10045H_CONFPLL_M_MSB 0x2E
97 #define TDA10045H_CONFPLL_M_LSB 0x2F
98 #define TDA10045H_CONFPLL_N 0x30
100 #define TDA10046H_CONFPLL1 0x2D
101 #define TDA10046H_CONFPLL2 0x2F
102 #define TDA10046H_CONFPLL3 0x30
103 #define TDA10046H_TIME_WREF1 0x31
104 #define TDA10046H_TIME_WREF2 0x32
105 #define TDA10046H_TIME_WREF3 0x33
106 #define TDA10046H_TIME_WREF4 0x34
107 #define TDA10046H_TIME_WREF5 0x35
109 #define TDA10045H_UNSURW_MSB 0x31
110 #define TDA10045H_UNSURW_LSB 0x32
111 #define TDA10045H_WREF_MSB 0x33
112 #define TDA10045H_WREF_MID 0x34
113 #define TDA10045H_WREF_LSB 0x35
114 #define TDA10045H_MUXOUT 0x36
115 #define TDA1004X_CONFADC2 0x37
117 #define TDA10045H_IOFFSET 0x38
119 #define TDA10046H_CONF_TRISTATE1 0x3B
120 #define TDA10046H_CONF_TRISTATE2 0x3C
121 #define TDA10046H_CONF_POLARITY 0x3D
122 #define TDA10046H_FREQ_OFFSET 0x3E
123 #define TDA10046H_GPIO_OUT_SEL 0x41
124 #define TDA10046H_GPIO_SELECT 0x42
125 #define TDA10046H_AGC_CONF 0x43
126 #define TDA10046H_AGC_THR 0x44
127 #define TDA10046H_AGC_RENORM 0x45
128 #define TDA10046H_AGC_GAINS 0x46
129 #define TDA10046H_AGC_TUN_MIN 0x47
130 #define TDA10046H_AGC_TUN_MAX 0x48
131 #define TDA10046H_AGC_IF_MIN 0x49
132 #define TDA10046H_AGC_IF_MAX 0x4A
134 #define TDA10046H_FREQ_PHY2_MSB 0x4D
135 #define TDA10046H_FREQ_PHY2_LSB 0x4E
137 #define TDA10046H_CVBER_CTRL 0x4F
138 #define TDA10046H_AGC_IF_LEVEL 0x52
139 #define TDA10046H_CODE_CPT 0x57
140 #define TDA10046H_CODE_IN 0x58
143 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
146 u8 buf[] = { reg, data };
147 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
149 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
151 msg.addr = state->config->demod_address;
152 ret = i2c_transfer(state->i2c, &msg, 1);
155 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
156 __FUNCTION__, reg, data, ret);
158 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
160 return (ret != 1) ? -1 : 0;
163 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
168 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
169 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
171 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
173 msg[0].addr = state->config->demod_address;
174 msg[1].addr = state->config->demod_address;
175 ret = i2c_transfer(state->i2c, msg, 2);
178 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
183 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
188 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
191 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
194 // read a byte and check
195 val = tda1004x_read_byte(state, reg);
203 // write it out again
204 return tda1004x_write_byteI(state, reg, val);
207 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
212 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
215 for (i = 0; i < len; i++) {
216 result = tda1004x_write_byteI(state, reg + i, buf[i]);
224 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
227 dprintk("%s\n", __FUNCTION__);
229 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
234 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
236 dprintk("%s\n", __FUNCTION__);
238 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
241 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
242 fe_bandwidth_t bandwidth)
244 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
245 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
246 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
249 case BANDWIDTH_6_MHZ:
250 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
253 case BANDWIDTH_7_MHZ:
254 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
257 case BANDWIDTH_8_MHZ:
258 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
265 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
270 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
271 fe_bandwidth_t bandwidth)
273 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
274 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
275 static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
277 static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
278 static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
279 static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
282 if ((state->config->if_freq == TDA10046_FREQ_045) ||
283 (state->config->if_freq == TDA10046_FREQ_052))
288 case BANDWIDTH_6_MHZ:
290 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
291 sizeof(bandwidth_6mhz_53M));
293 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
294 sizeof(bandwidth_6mhz_48M));
295 if (state->config->if_freq == TDA10046_FREQ_045) {
296 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
297 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
301 case BANDWIDTH_7_MHZ:
303 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
304 sizeof(bandwidth_7mhz_53M));
306 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
307 sizeof(bandwidth_7mhz_48M));
308 if (state->config->if_freq == TDA10046_FREQ_045) {
309 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
310 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
314 case BANDWIDTH_8_MHZ:
316 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
317 sizeof(bandwidth_8mhz_53M));
319 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
320 sizeof(bandwidth_8mhz_48M));
321 if (state->config->if_freq == TDA10046_FREQ_045) {
322 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
323 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
334 static int tda1004x_do_upload(struct tda1004x_state *state,
335 unsigned char *mem, unsigned int len,
336 u8 dspCodeCounterReg, u8 dspCodeInReg)
339 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
343 /* clear code counter */
344 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
345 fw_msg.addr = state->config->demod_address;
347 buf[0] = dspCodeInReg;
349 // work out how much to send this time
355 memcpy(buf + 1, mem + pos, tx_size);
356 fw_msg.len = tx_size + 1;
357 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
358 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
363 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
365 // give the DSP a chance to settle 03/10/05 Hac
371 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
374 unsigned long timeout;
376 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
377 timeout = jiffies + 2 * HZ;
378 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
379 if (time_after(jiffies, timeout)) {
380 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
388 // check upload was OK
389 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
390 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
392 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
393 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
394 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
395 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
398 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
402 static int tda10045_fwupload(struct dvb_frontend* fe)
404 struct tda1004x_state* state = fe->demodulator_priv;
406 const struct firmware *fw;
408 /* don't re-upload unless necessary */
409 if (tda1004x_check_upload_ok(state) == 0)
412 /* request the firmware, this will block until someone uploads it */
413 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
414 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
416 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
421 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
422 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
423 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
427 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
429 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
430 release_firmware(fw);
433 printk(KERN_INFO "tda1004x: firmware upload complete\n");
435 /* wait for DSP to initialise */
436 /* DSPREADY doesn't seem to work on the TDA10045H */
439 return tda1004x_check_upload_ok(state);
442 static void tda10046_init_plls(struct dvb_frontend* fe)
444 struct tda1004x_state* state = fe->demodulator_priv;
447 if ((state->config->if_freq == TDA10046_FREQ_045) ||
448 (state->config->if_freq == TDA10046_FREQ_052))
453 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
454 if(tda10046_clk53m) {
455 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
456 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
458 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
459 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
461 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
462 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
463 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
465 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
466 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
469 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
471 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
472 /* Note clock frequency is handled implicitly */
473 switch (state->config->if_freq) {
474 case TDA10046_FREQ_045:
475 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
476 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
478 case TDA10046_FREQ_052:
479 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
480 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
482 case TDA10046_FREQ_3617:
483 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
484 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
486 case TDA10046_FREQ_3613:
487 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
488 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
491 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
492 /* let the PLLs settle */
496 static int tda10046_fwupload(struct dvb_frontend* fe)
498 struct tda1004x_state* state = fe->demodulator_priv;
500 const struct firmware *fw;
502 /* reset + wake up chip */
503 if (state->config->xtal_freq == TDA10046_XTAL_4M) {
504 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
506 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
507 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
509 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
510 /* let the clocks recover from sleep */
513 /* The PLLs need to be reprogrammed after sleep */
514 tda10046_init_plls(fe);
516 /* don't re-upload unless necessary */
517 if (tda1004x_check_upload_ok(state) == 0)
520 if (state->config->request_firmware != NULL) {
521 /* request the firmware, this will block until someone uploads it */
522 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
523 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
525 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
528 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
529 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
530 release_firmware(fw);
534 /* boot from firmware eeprom */
535 printk(KERN_INFO "tda1004x: booting from eeprom\n");
536 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
539 return tda1004x_check_upload_ok(state);
542 static int tda1004x_encode_fec(int fec)
544 // convert known FEC values
562 static int tda1004x_decode_fec(int tdafec)
564 // convert known FEC values
582 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
584 struct tda1004x_state* state = fe->demodulator_priv;
586 return tda1004x_write_byteI(state, reg, data);
589 static int tda10045_init(struct dvb_frontend* fe)
591 struct tda1004x_state* state = fe->demodulator_priv;
593 dprintk("%s\n", __FUNCTION__);
595 if (tda10045_fwupload(fe)) {
596 printk("tda1004x: firmware upload failed\n");
600 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
603 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
604 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
605 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
606 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
607 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
608 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
609 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
610 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
611 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
612 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
613 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
615 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
620 static int tda10046_init(struct dvb_frontend* fe)
622 struct tda1004x_state* state = fe->demodulator_priv;
623 dprintk("%s\n", __FUNCTION__);
625 if (tda10046_fwupload(fe)) {
626 printk("tda1004x: firmware upload failed\n");
631 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
632 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
633 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
635 switch (state->config->agc_config) {
636 case TDA10046_AGC_DEFAULT:
637 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
638 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
640 case TDA10046_AGC_IFO_AUTO_NEG:
641 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
642 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
644 case TDA10046_AGC_IFO_AUTO_POS:
645 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
646 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
648 case TDA10046_AGC_TDA827X:
649 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
650 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
651 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
652 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
654 case TDA10046_AGC_TDA827X_GPL:
655 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
656 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
657 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
658 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
661 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
662 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
663 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
664 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
665 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
666 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
667 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
668 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
669 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
670 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
671 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
672 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
677 static int tda1004x_set_fe(struct dvb_frontend* fe,
678 struct dvb_frontend_parameters *fe_params)
680 struct tda1004x_state* state = fe->demodulator_priv;
684 dprintk("%s\n", __FUNCTION__);
686 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
688 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
689 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
690 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
692 // disable agc_conf[2]
693 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
697 if (fe->ops.tuner_ops.set_params) {
698 fe->ops.tuner_ops.set_params(fe, fe_params);
699 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
702 // Hardcoded to use auto as much as possible on the TDA10045 as it
703 // is very unreliable if AUTO mode is _not_ used.
704 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
705 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
706 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
707 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
710 // Set standard params.. or put them to auto
711 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
712 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
713 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
714 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
715 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
716 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
717 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
718 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
720 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
723 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
726 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
729 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
732 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
735 switch (fe_params->u.ofdm.constellation) {
737 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
741 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
745 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
753 switch (fe_params->u.ofdm.hierarchy_information) {
755 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
759 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
763 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
767 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
776 switch (state->demod_type) {
777 case TDA1004X_DEMOD_TDA10045:
778 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
781 case TDA1004X_DEMOD_TDA10046:
782 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
787 inversion = fe_params->inversion;
788 if (state->config->invert)
789 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
792 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
796 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
803 // set guard interval
804 switch (fe_params->u.ofdm.guard_interval) {
805 case GUARD_INTERVAL_1_32:
806 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
807 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
810 case GUARD_INTERVAL_1_16:
811 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
812 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
815 case GUARD_INTERVAL_1_8:
816 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
817 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
820 case GUARD_INTERVAL_1_4:
821 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
822 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
825 case GUARD_INTERVAL_AUTO:
826 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
827 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
834 // set transmission mode
835 switch (fe_params->u.ofdm.transmission_mode) {
836 case TRANSMISSION_MODE_2K:
837 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
838 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
841 case TRANSMISSION_MODE_8K:
842 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
843 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
846 case TRANSMISSION_MODE_AUTO:
847 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
848 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
856 switch (state->demod_type) {
857 case TDA1004X_DEMOD_TDA10045:
858 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
859 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
862 case TDA1004X_DEMOD_TDA10046:
863 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
865 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
874 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
876 struct tda1004x_state* state = fe->demodulator_priv;
878 dprintk("%s\n", __FUNCTION__);
881 fe_params->inversion = INVERSION_OFF;
882 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
883 fe_params->inversion = INVERSION_ON;
884 if (state->config->invert)
885 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
888 switch (state->demod_type) {
889 case TDA1004X_DEMOD_TDA10045:
890 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
892 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
895 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
898 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
902 case TDA1004X_DEMOD_TDA10046:
903 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
906 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
910 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
914 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
921 fe_params->u.ofdm.code_rate_HP =
922 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
923 fe_params->u.ofdm.code_rate_LP =
924 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
927 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
929 fe_params->u.ofdm.constellation = QPSK;
932 fe_params->u.ofdm.constellation = QAM_16;
935 fe_params->u.ofdm.constellation = QAM_64;
940 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
941 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
942 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
945 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
947 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
950 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
953 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
956 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
961 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
963 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
966 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
969 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
972 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
979 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
981 struct tda1004x_state* state = fe->demodulator_priv;
986 dprintk("%s\n", __FUNCTION__);
989 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
996 *fe_status |= FE_HAS_SIGNAL;
998 *fe_status |= FE_HAS_CARRIER;
1000 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1002 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1003 // is getting anything valid
1004 if (!(*fe_status & FE_HAS_VITERBI)) {
1006 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1009 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1012 cber |= (status << 8);
1013 // The address 0x20 should be read to cope with a TDA10046 bug
1014 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1017 *fe_status |= FE_HAS_VITERBI;
1020 // if we DO have some valid VITERBI output, but don't already have SYNC
1021 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1022 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1024 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1027 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1030 vber |= (status << 8);
1031 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1034 vber |= (status & 0x0f) << 16;
1035 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1036 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1038 // if RS has passed some valid TS packets, then we must be
1039 // getting some SYNC bytes
1041 *fe_status |= FE_HAS_SYNC;
1045 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1049 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1051 struct tda1004x_state* state = fe->demodulator_priv;
1055 dprintk("%s\n", __FUNCTION__);
1057 // determine the register to use
1058 switch (state->demod_type) {
1059 case TDA1004X_DEMOD_TDA10045:
1060 reg = TDA10045H_S_AGC;
1063 case TDA1004X_DEMOD_TDA10046:
1064 reg = TDA10046H_AGC_IF_LEVEL;
1069 tmp = tda1004x_read_byte(state, reg);
1073 *signal = (tmp << 8) | tmp;
1074 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1078 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1080 struct tda1004x_state* state = fe->demodulator_priv;
1083 dprintk("%s\n", __FUNCTION__);
1086 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1091 *snr = ((tmp << 8) | tmp);
1092 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1096 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1098 struct tda1004x_state* state = fe->demodulator_priv;
1103 dprintk("%s\n", __FUNCTION__);
1105 // read the UCBLOCKS and reset
1107 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1111 while (counter++ < 5) {
1112 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1113 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1114 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1116 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1120 if ((tmp2 < tmp) || (tmp2 == 0))
1127 *ucblocks = 0xffffffff;
1129 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1133 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1135 struct tda1004x_state* state = fe->demodulator_priv;
1138 dprintk("%s\n", __FUNCTION__);
1141 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1145 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1149 // The address 0x20 should be read to cope with a TDA10046 bug
1150 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1152 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1156 static int tda1004x_sleep(struct dvb_frontend* fe)
1158 struct tda1004x_state* state = fe->demodulator_priv;
1160 switch (state->demod_type) {
1161 case TDA1004X_DEMOD_TDA10045:
1162 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1165 case TDA1004X_DEMOD_TDA10046:
1166 /* set outputs to tristate */
1167 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1168 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1175 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1177 struct tda1004x_state* state = fe->demodulator_priv;
1180 return tda1004x_enable_tuner_i2c(state);
1182 return tda1004x_disable_tuner_i2c(state);
1186 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1188 fesettings->min_delay_ms = 800;
1189 /* Drift compensation makes no sense for DVB-T */
1190 fesettings->step_size = 0;
1191 fesettings->max_drift = 0;
1195 static void tda1004x_release(struct dvb_frontend* fe)
1197 struct tda1004x_state *state = fe->demodulator_priv;
1201 static struct dvb_frontend_ops tda10045_ops = {
1203 .name = "Philips TDA10045H DVB-T",
1205 .frequency_min = 51000000,
1206 .frequency_max = 858000000,
1207 .frequency_stepsize = 166667,
1209 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1210 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1211 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1212 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1215 .release = tda1004x_release,
1217 .init = tda10045_init,
1218 .sleep = tda1004x_sleep,
1219 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1221 .set_frontend = tda1004x_set_fe,
1222 .get_frontend = tda1004x_get_fe,
1223 .get_tune_settings = tda1004x_get_tune_settings,
1225 .read_status = tda1004x_read_status,
1226 .read_ber = tda1004x_read_ber,
1227 .read_signal_strength = tda1004x_read_signal_strength,
1228 .read_snr = tda1004x_read_snr,
1229 .read_ucblocks = tda1004x_read_ucblocks,
1232 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1233 struct i2c_adapter* i2c)
1235 struct tda1004x_state *state;
1237 /* allocate memory for the internal state */
1238 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1242 /* setup the state */
1243 state->config = config;
1245 state->demod_type = TDA1004X_DEMOD_TDA10045;
1247 /* check if the demod is there */
1248 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1253 /* create dvb_frontend */
1254 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1255 state->frontend.demodulator_priv = state;
1256 return &state->frontend;
1259 static struct dvb_frontend_ops tda10046_ops = {
1261 .name = "Philips TDA10046H DVB-T",
1263 .frequency_min = 51000000,
1264 .frequency_max = 858000000,
1265 .frequency_stepsize = 166667,
1267 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1268 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1269 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1270 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1273 .release = tda1004x_release,
1275 .init = tda10046_init,
1276 .sleep = tda1004x_sleep,
1277 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1279 .set_frontend = tda1004x_set_fe,
1280 .get_frontend = tda1004x_get_fe,
1281 .get_tune_settings = tda1004x_get_tune_settings,
1283 .read_status = tda1004x_read_status,
1284 .read_ber = tda1004x_read_ber,
1285 .read_signal_strength = tda1004x_read_signal_strength,
1286 .read_snr = tda1004x_read_snr,
1287 .read_ucblocks = tda1004x_read_ucblocks,
1290 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1291 struct i2c_adapter* i2c)
1293 struct tda1004x_state *state;
1295 /* allocate memory for the internal state */
1296 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1300 /* setup the state */
1301 state->config = config;
1303 state->demod_type = TDA1004X_DEMOD_TDA10046;
1305 /* check if the demod is there */
1306 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1311 /* create dvb_frontend */
1312 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1313 state->frontend.demodulator_priv = state;
1314 return &state->frontend;
1317 module_param(debug, int, 0644);
1318 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1320 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1321 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1322 MODULE_LICENSE("GPL");
1324 EXPORT_SYMBOL(tda10045_attach);
1325 EXPORT_SYMBOL(tda10046_attach);
1326 EXPORT_SYMBOL(tda1004x_write_byte);