drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware
  27  * or /lib/firmware (depending on configuration of firmware hotplug).
  28  */
  29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  31
  32 #include <linux/init.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/device.h>
  36 #include <linux/jiffies.h>
  37 #include <linux/string.h>
  38 #include <linux/slab.h>
  39
  40 #include "dvb_frontend.h"
  41 #include "tda1004x.h"
  42
  43 static int debug;
  44 #define dprintk(args...) \
  45         do { \
  46                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  47         } while (0)
  48
  49 #define TDA1004X_CHIPID          0x00
  50 #define TDA1004X_AUTO            0x01
  51 #define TDA1004X_IN_CONF1        0x02
  52 #define TDA1004X_IN_CONF2        0x03
  53 #define TDA1004X_OUT_CONF1       0x04
  54 #define TDA1004X_OUT_CONF2       0x05
  55 #define TDA1004X_STATUS_CD       0x06
  56 #define TDA1004X_CONFC4          0x07
  57 #define TDA1004X_DSSPARE2        0x0C
  58 #define TDA10045H_CODE_IN        0x0D
  59 #define TDA10045H_FWPAGE         0x0E
  60 #define TDA1004X_SCAN_CPT        0x10
  61 #define TDA1004X_DSP_CMD         0x11
  62 #define TDA1004X_DSP_ARG         0x12
  63 #define TDA1004X_DSP_DATA1       0x13
  64 #define TDA1004X_DSP_DATA2       0x14
  65 #define TDA1004X_CONFADC1        0x15
  66 #define TDA1004X_CONFC1          0x16
  67 #define TDA10045H_S_AGC          0x1a
  68 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  69 #define TDA1004X_SNR             0x1c
  70 #define TDA1004X_CONF_TS1        0x1e
  71 #define TDA1004X_CONF_TS2        0x1f
  72 #define TDA1004X_CBER_RESET      0x20
  73 #define TDA1004X_CBER_MSB        0x21
  74 #define TDA1004X_CBER_LSB        0x22
  75 #define TDA1004X_CVBER_LUT       0x23
  76 #define TDA1004X_VBER_MSB        0x24
  77 #define TDA1004X_VBER_MID        0x25
  78 #define TDA1004X_VBER_LSB        0x26
  79 #define TDA1004X_UNCOR           0x27
  80
  81 #define TDA10045H_CONFPLL_P      0x2D
  82 #define TDA10045H_CONFPLL_M_MSB  0x2E
  83 #define TDA10045H_CONFPLL_M_LSB  0x2F
  84 #define TDA10045H_CONFPLL_N      0x30
  85
  86 #define TDA10046H_CONFPLL1       0x2D
  87 #define TDA10046H_CONFPLL2       0x2F
  88 #define TDA10046H_CONFPLL3       0x30
  89 #define TDA10046H_TIME_WREF1     0x31
  90 #define TDA10046H_TIME_WREF2     0x32
  91 #define TDA10046H_TIME_WREF3     0x33
  92 #define TDA10046H_TIME_WREF4     0x34
  93 #define TDA10046H_TIME_WREF5     0x35
  94
  95 #define TDA10045H_UNSURW_MSB     0x31
  96 #define TDA10045H_UNSURW_LSB     0x32
  97 #define TDA10045H_WREF_MSB       0x33
  98 #define TDA10045H_WREF_MID       0x34
  99 #define TDA10045H_WREF_LSB       0x35
 100 #define TDA10045H_MUXOUT         0x36
 101 #define TDA1004X_CONFADC2        0x37
 102
 103 #define TDA10045H_IOFFSET        0x38
 104
 105 #define TDA10046H_CONF_TRISTATE1 0x3B
 106 #define TDA10046H_CONF_TRISTATE2 0x3C
 107 #define TDA10046H_CONF_POLARITY  0x3D
 108 #define TDA10046H_FREQ_OFFSET    0x3E
 109 #define TDA10046H_GPIO_OUT_SEL   0x41
 110 #define TDA10046H_GPIO_SELECT    0x42
 111 #define TDA10046H_AGC_CONF       0x43
 112 #define TDA10046H_AGC_THR        0x44
 113 #define TDA10046H_AGC_RENORM     0x45
 114 #define TDA10046H_AGC_GAINS      0x46
 115 #define TDA10046H_AGC_TUN_MIN    0x47
 116 #define TDA10046H_AGC_TUN_MAX    0x48
 117 #define TDA10046H_AGC_IF_MIN     0x49
 118 #define TDA10046H_AGC_IF_MAX     0x4A
 119
 120 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 121 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 122
 123 #define TDA10046H_CVBER_CTRL     0x4F
 124 #define TDA10046H_AGC_IF_LEVEL   0x52
 125 #define TDA10046H_CODE_CPT       0x57
 126 #define TDA10046H_CODE_IN        0x58
 127
 128
 129 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 130 {
 131         int ret;
 132         u8 buf[] = { reg, data };
 133         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 134
 135         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 136
 137         msg.addr = state->config->demod_address;
 138         ret = i2c_transfer(state->i2c, &msg, 1);
 139
 140         if (ret != 1)
 141                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 142                         __FUNCTION__, reg, data, ret);
 143
 144         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 145                 reg, data, ret);
 146         return (ret != 1) ? -1 : 0;
 147 }
 148
 149 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 150 {
 151         int ret;
 152         u8 b0[] = { reg };
 153         u8 b1[] = { 0 };
 154         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 155                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 156
 157         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 158
 159         msg[0].addr = state->config->demod_address;
 160         msg[1].addr = state->config->demod_address;
 161         ret = i2c_transfer(state->i2c, msg, 2);
 162
 163         if (ret != 2) {
 164                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 165                         ret);
 166                 return -1;
 167         }
 168
 169         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 170                 reg, b1[0], ret);
 171         return b1[0];
 172 }
 173
 174 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 175 {
 176         int val;
 177         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 178                 mask, data);
 179
 180         // read a byte and check
 181         val = tda1004x_read_byte(state, reg);
 182         if (val < 0)
 183                 return val;
 184
 185         // mask if off
 186         val = val & ~mask;
 187         val |= data & 0xff;
 188
 189         // write it out again
 190         return tda1004x_write_byteI(state, reg, val);
 191 }
 192
 193 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 194 {
 195         int i;
 196         int result;
 197
 198         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 199
 200         result = 0;
 201         for (i = 0; i < len; i++) {
 202                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 203                 if (result != 0)
 204                         break;
 205         }
 206
 207         return result;
 208 }
 209
 210 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 211 {
 212         int result;
 213         dprintk("%s\n", __FUNCTION__);
 214
 215         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 216         msleep(20);
 217         return result;
 218 }
 219
 220 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 221 {
 222         dprintk("%s\n", __FUNCTION__);
 223
 224         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 225 }
 226
 227 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 228                                    fe_bandwidth_t bandwidth)
 229 {
 230         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 231         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 232         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 233
 234         switch (bandwidth) {
 235         case BANDWIDTH_6_MHZ:
 236                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 237                 break;
 238
 239         case BANDWIDTH_7_MHZ:
 240                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 241                 break;
 242
 243         case BANDWIDTH_8_MHZ:
 244                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 245                 break;
 246
 247         default:
 248                 return -EINVAL;
 249         }
 250
 251         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 252
 253         return 0;
 254 }
 255
 256 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 257                                    fe_bandwidth_t bandwidth)
 258 {
 259         static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
 260         static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
 261         static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
 262
 263         static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
 264         static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
 265         static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
 266         int tda10046_clk53m;
 267
 268         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 269             (state->config->if_freq == TDA10046_FREQ_052))
 270                 tda10046_clk53m = 0;
 271         else
 272                 tda10046_clk53m = 1;
 273         switch (bandwidth) {
 274         case BANDWIDTH_6_MHZ:
 275                 if (tda10046_clk53m)
 276                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
 277                                                   sizeof(bandwidth_6mhz_53M));
 278                 else
 279                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
 280                                                   sizeof(bandwidth_6mhz_48M));
 281                 if (state->config->if_freq == TDA10046_FREQ_045) {
 282                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
 283                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
 284                 }
 285                 break;
 286
 287         case BANDWIDTH_7_MHZ:
 288                 if (tda10046_clk53m)
 289                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
 290                                                   sizeof(bandwidth_7mhz_53M));
 291                 else
 292                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
 293                                                   sizeof(bandwidth_7mhz_48M));
 294                 if (state->config->if_freq == TDA10046_FREQ_045) {
 295                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 296                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 297                 }
 298                 break;
 299
 300         case BANDWIDTH_8_MHZ:
 301                 if (tda10046_clk53m)
 302                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
 303                                                   sizeof(bandwidth_8mhz_53M));
 304                 else
 305                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
 306                                                   sizeof(bandwidth_8mhz_48M));
 307                 if (state->config->if_freq == TDA10046_FREQ_045) {
 308                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 309                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
 310                 }
 311                 break;
 312
 313         default:
 314                 return -EINVAL;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int tda1004x_do_upload(struct tda1004x_state *state,
 321                               unsigned char *mem, unsigned int len,
 322                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 323 {
 324         u8 buf[65];
 325         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 326         int tx_size;
 327         int pos = 0;
 328
 329         /* clear code counter */
 330         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 331         fw_msg.addr = state->config->demod_address;
 332
 333         buf[0] = dspCodeInReg;
 334         while (pos != len) {
 335                 // work out how much to send this time
 336                 tx_size = len - pos;
 337                 if (tx_size > 0x10)
 338                         tx_size = 0x10;
 339
 340                 // send the chunk
 341                 memcpy(buf + 1, mem + pos, tx_size);
 342                 fw_msg.len = tx_size + 1;
 343                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 344                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
 345                         return -EIO;
 346                 }
 347                 pos += tx_size;
 348
 349                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
 350         }
 351         // give the DSP a chance to settle 03/10/05 Hac
 352         msleep(100);
 353
 354         return 0;
 355 }
 356
 357 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
 358 {
 359         u8 data1, data2;
 360         unsigned long timeout;
 361
 362         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 363                 timeout = jiffies + 2 * HZ;
 364                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 365                         if (time_after(jiffies, timeout)) {
 366                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
 367                                 break;
 368                         }
 369                         msleep(1);
 370                 }
 371         } else
 372                 msleep(100);
 373
 374         // check upload was OK
 375         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 376         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 377
 378         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 379         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 380         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
 381                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
 382                 return -EIO;
 383         }
 384         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
 385         return 0;
 386 }
 387
 388 static int tda10045_fwupload(struct dvb_frontend* fe)
 389 {
 390         struct tda1004x_state* state = fe->demodulator_priv;
 391         int ret;
 392         const struct firmware *fw;
 393
 394         /* don't re-upload unless necessary */
 395         if (tda1004x_check_upload_ok(state) == 0)
 396                 return 0;
 397
 398         /* request the firmware, this will block until someone uploads it */
 399         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
 400         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 401         if (ret) {
 402                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 403                 return ret;
 404         }
 405
 406         /* reset chip */
 407         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 408         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 409         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 410         msleep(10);
 411
 412         /* set parameters */
 413         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 414
 415         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 416         release_firmware(fw);
 417         if (ret)
 418                 return ret;
 419         printk(KERN_INFO "tda1004x: firmware upload complete\n");
 420
 421         /* wait for DSP to initialise */
 422         /* DSPREADY doesn't seem to work on the TDA10045H */
 423         msleep(100);
 424
 425         return tda1004x_check_upload_ok(state);
 426 }
 427
 428 static void tda10046_init_plls(struct dvb_frontend* fe)
 429 {
 430         struct tda1004x_state* state = fe->demodulator_priv;
 431         int tda10046_clk53m;
 432
 433         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 434             (state->config->if_freq == TDA10046_FREQ_052))
 435                 tda10046_clk53m = 0;
 436         else
 437                 tda10046_clk53m = 1;
 438
 439         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
 440         if(tda10046_clk53m) {
 441                 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
 442                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
 443         } else {
 444                 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
 445                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
 446         }
 447         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
 448                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
 449                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 450         } else {
 451                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
 452                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
 453         }
 454         if(tda10046_clk53m)
 455                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
 456         else
 457                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
 458         /* Note clock frequency is handled implicitly */
 459         switch (state->config->if_freq) {
 460         case TDA10046_FREQ_045:
 461                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 462                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 463                 break;
 464         case TDA10046_FREQ_052:
 465                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 466                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
 467                 break;
 468         case TDA10046_FREQ_3617:
 469                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 470                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
 471                 break;
 472         case TDA10046_FREQ_3613:
 473                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 474                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
 475                 break;
 476         }
 477         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 478         /* let the PLLs settle */
 479         msleep(120);
 480 }
 481
 482 static int tda10046_fwupload(struct dvb_frontend* fe)
 483 {
 484         struct tda1004x_state* state = fe->demodulator_priv;
 485         int ret;
 486         const struct firmware *fw;
 487
 488         /* reset + wake up chip */
 489         if (state->config->xtal_freq == TDA10046_XTAL_4M) {
 490                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
 491         } else {
 492                 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
 493                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
 494         }
 495         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 496         /* set GPIO 1 and 3 */
 497         if (state->config->gpio_config != TDA10046_GPTRI) {
 498                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
 499                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
 500         }
 501         /* let the clocks recover from sleep */
 502         msleep(10);
 503
 504         /* The PLLs need to be reprogrammed after sleep */
 505         tda10046_init_plls(fe);
 506
 507         /* don't re-upload unless necessary */
 508         if (tda1004x_check_upload_ok(state) == 0)
 509                 return 0;
 510
 511         printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
 512         tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
 513         msleep(300);
 514         /* don't re-upload unless necessary */
 515         if (tda1004x_check_upload_ok(state) == 0)
 516                 return 0;
 517
 518         if (state->config->request_firmware != NULL) {
 519                 /* request the firmware, this will block until someone uploads it */
 520                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
 521                 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 522                 if (ret) {
 523                         /* remain compatible to old bug: try to load with tda10045 image name */
 524                         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 525                         if (ret) {
 526                                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 527                                 return ret;
 528                         } else {
 529                                 printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
 530                                                   TDA10046_DEFAULT_FIRMWARE);
 531                         }
 532                 }
 533         } else {
 534                 printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
 535                 return -EIO;
 536         }
 537         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 538         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 539         release_firmware(fw);
 540         return tda1004x_check_upload_ok(state);
 541 }
 542
 543 static int tda1004x_encode_fec(int fec)
 544 {
 545         // convert known FEC values
 546         switch (fec) {
 547         case FEC_1_2:
 548                 return 0;
 549         case FEC_2_3:
 550                 return 1;
 551         case FEC_3_4:
 552                 return 2;
 553         case FEC_5_6:
 554                 return 3;
 555         case FEC_7_8:
 556                 return 4;
 557         }
 558
 559         // unsupported
 560         return -EINVAL;
 561 }
 562
 563 static int tda1004x_decode_fec(int tdafec)
 564 {
 565         // convert known FEC values
 566         switch (tdafec) {
 567         case 0:
 568                 return FEC_1_2;
 569         case 1:
 570                 return FEC_2_3;
 571         case 2:
 572                 return FEC_3_4;
 573         case 3:
 574                 return FEC_5_6;
 575         case 4:
 576                 return FEC_7_8;
 577         }
 578
 579         // unsupported
 580         return -1;
 581 }
 582
 583 static int tda1004x_write(struct dvb_frontend* fe, u8 *buf, int len)
 584 {
 585         struct tda1004x_state* state = fe->demodulator_priv;
 586
 587         if (len != 2)
 588                 return -EINVAL;
 589
 590         return tda1004x_write_byteI(state, buf[0], buf[1]);
 591 }
 592
 593 static int tda10045_init(struct dvb_frontend* fe)
 594 {
 595         struct tda1004x_state* state = fe->demodulator_priv;
 596
 597         dprintk("%s\n", __FUNCTION__);
 598
 599         if (tda10045_fwupload(fe)) {
 600                 printk("tda1004x: firmware upload failed\n");
 601                 return -EIO;
 602         }
 603
 604         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 605
 606         // tda setup
 607         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 608         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 609         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 610         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 611         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 612         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 613         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 614         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 615         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 616         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 617         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 618
 619         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 620
 621         return 0;
 622 }
 623
 624 static int tda10046_init(struct dvb_frontend* fe)
 625 {
 626         struct tda1004x_state* state = fe->demodulator_priv;
 627         dprintk("%s\n", __FUNCTION__);
 628
 629         if (tda10046_fwupload(fe)) {
 630                 printk("tda1004x: firmware upload failed\n");
 631                         return -EIO;
 632         }
 633
 634         // tda setup
 635         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 636         tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
 637         tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88);      // enable pulse killer
 638
 639         switch (state->config->agc_config) {
 640         case TDA10046_AGC_DEFAULT:
 641                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
 642                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 643                 break;
 644         case TDA10046_AGC_IFO_AUTO_NEG:
 645                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 646                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 647                 break;
 648         case TDA10046_AGC_IFO_AUTO_POS:
 649                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 650                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00);  // set AGC polarities
 651                 break;
 652         case TDA10046_AGC_TDA827X:
 653                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 654                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 655                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 656                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 657                 break;
 658         }
 659         tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
 660         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x79); // Turn IF AGC output on
 661         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 662         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 663         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 664         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 665         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
 666         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
 667         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 668         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
 669         // tda1004x_write_mask(state, 0x50, 0x80, 0x80);         // handle out of guard echoes
 670         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 671
 672         return 0;
 673 }
 674
 675 static int tda1004x_set_fe(struct dvb_frontend* fe,
 676                            struct dvb_frontend_parameters *fe_params)
 677 {
 678         struct tda1004x_state* state = fe->demodulator_priv;
 679         int tmp;
 680         int inversion;
 681
 682         dprintk("%s\n", __FUNCTION__);
 683
 684         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 685                 // setup auto offset
 686                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 687                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 688                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 689
 690                 // disable agc_conf[2]
 691                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 692         }
 693
 694         // set frequency
 695         if (fe->ops.tuner_ops.set_params) {
 696                 fe->ops.tuner_ops.set_params(fe, fe_params);
 697                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 698         }
 699
 700         // Hardcoded to use auto as much as possible on the TDA10045 as it
 701         // is very unreliable if AUTO mode is _not_ used.
 702         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 703                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 704                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 705                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 706         }
 707
 708         // Set standard params.. or put them to auto
 709         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 710                 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 711                 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 712                 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 713                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 714                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 715                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 716                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 717         } else {
 718                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 719
 720                 // set HP FEC
 721                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 722                 if (tmp < 0)
 723                         return tmp;
 724                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 725
 726                 // set LP FEC
 727                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 728                 if (tmp < 0)
 729                         return tmp;
 730                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 731
 732                 // set constellation
 733                 switch (fe_params->u.ofdm.constellation) {
 734                 case QPSK:
 735                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 736                         break;
 737
 738                 case QAM_16:
 739                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 740                         break;
 741
 742                 case QAM_64:
 743                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 744                         break;
 745
 746                 default:
 747                         return -EINVAL;
 748                 }
 749
 750                 // set hierarchy
 751                 switch (fe_params->u.ofdm.hierarchy_information) {
 752                 case HIERARCHY_NONE:
 753                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 754                         break;
 755
 756                 case HIERARCHY_1:
 757                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 758                         break;
 759
 760                 case HIERARCHY_2:
 761                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 762                         break;
 763
 764                 case HIERARCHY_4:
 765                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 766                         break;
 767
 768                 default:
 769                         return -EINVAL;
 770                 }
 771         }
 772
 773         // set bandwidth
 774         switch (state->demod_type) {
 775         case TDA1004X_DEMOD_TDA10045:
 776                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 777                 break;
 778
 779         case TDA1004X_DEMOD_TDA10046:
 780                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 781                 break;
 782         }
 783
 784         // set inversion
 785         inversion = fe_params->inversion;
 786         if (state->config->invert)
 787                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 788         switch (inversion) {
 789         case INVERSION_OFF:
 790                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 791                 break;
 792
 793         case INVERSION_ON:
 794                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 795                 break;
 796
 797         default:
 798                 return -EINVAL;
 799         }
 800
 801         // set guard interval
 802         switch (fe_params->u.ofdm.guard_interval) {
 803         case GUARD_INTERVAL_1_32:
 804                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 805                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 806                 break;
 807
 808         case GUARD_INTERVAL_1_16:
 809                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 810                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 811                 break;
 812
 813         case GUARD_INTERVAL_1_8:
 814                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 815                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 816                 break;
 817
 818         case GUARD_INTERVAL_1_4:
 819                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 820                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 821                 break;
 822
 823         case GUARD_INTERVAL_AUTO:
 824                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 825                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 826                 break;
 827
 828         default:
 829                 return -EINVAL;
 830         }
 831
 832         // set transmission mode
 833         switch (fe_params->u.ofdm.transmission_mode) {
 834         case TRANSMISSION_MODE_2K:
 835                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 836                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 837                 break;
 838
 839         case TRANSMISSION_MODE_8K:
 840                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 841                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 842                 break;
 843
 844         case TRANSMISSION_MODE_AUTO:
 845                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 846                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 847                 break;
 848
 849         default:
 850                 return -EINVAL;
 851         }
 852
 853         // start the lock
 854         switch (state->demod_type) {
 855         case TDA1004X_DEMOD_TDA10045:
 856                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 857                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 858                 break;
 859
 860         case TDA1004X_DEMOD_TDA10046:
 861                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 862                 msleep(1);
 863                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
 864                 break;
 865         }
 866
 867         msleep(10);
 868
 869         return 0;
 870 }
 871
 872 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 873 {
 874         struct tda1004x_state* state = fe->demodulator_priv;
 875
 876         dprintk("%s\n", __FUNCTION__);
 877
 878         // inversion status
 879         fe_params->inversion = INVERSION_OFF;
 880         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 881                 fe_params->inversion = INVERSION_ON;
 882         if (state->config->invert)
 883                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 884
 885         // bandwidth
 886         switch (state->demod_type) {
 887         case TDA1004X_DEMOD_TDA10045:
 888                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 889                 case 0x14:
 890                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 891                         break;
 892                 case 0xdb:
 893                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 894                         break;
 895                 case 0x4f:
 896                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 897                         break;
 898                 }
 899                 break;
 900         case TDA1004X_DEMOD_TDA10046:
 901                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 902                 case 0x5c:
 903                 case 0x54:
 904                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 905                         break;
 906                 case 0x6a:
 907                 case 0x60:
 908                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 909                         break;
 910                 case 0x7b:
 911                 case 0x70:
 912                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 913                         break;
 914                 }
 915                 break;
 916         }
 917
 918         // FEC
 919         fe_params->u.ofdm.code_rate_HP =
 920             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 921         fe_params->u.ofdm.code_rate_LP =
 922             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 923
 924         // constellation
 925         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 926         case 0:
 927                 fe_params->u.ofdm.constellation = QPSK;
 928                 break;
 929         case 1:
 930                 fe_params->u.ofdm.constellation = QAM_16;
 931                 break;
 932         case 2:
 933                 fe_params->u.ofdm.constellation = QAM_64;
 934                 break;
 935         }
 936
 937         // transmission mode
 938         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 939         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 940                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 941
 942         // guard interval
 943         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 944         case 0:
 945                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 946                 break;
 947         case 1:
 948                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 949                 break;
 950         case 2:
 951                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 952                 break;
 953         case 3:
 954                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 955                 break;
 956         }
 957
 958         // hierarchy
 959         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 960         case 0:
 961                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 962                 break;
 963         case 1:
 964                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 965                 break;
 966         case 2:
 967                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 968                 break;
 969         case 3:
 970                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
 971                 break;
 972         }
 973
 974         return 0;
 975 }
 976
 977 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
 978 {
 979         struct tda1004x_state* state = fe->demodulator_priv;
 980         int status;
 981         int cber;
 982         int vber;
 983
 984         dprintk("%s\n", __FUNCTION__);
 985
 986         // read status
 987         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 988         if (status == -1)
 989                 return -EIO;
 990
 991         // decode
 992         *fe_status = 0;
 993         if (status & 4)
 994                 *fe_status |= FE_HAS_SIGNAL;
 995         if (status & 2)
 996                 *fe_status |= FE_HAS_CARRIER;
 997         if (status & 8)
 998                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 999
1000         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1001         // is getting anything valid
1002         if (!(*fe_status & FE_HAS_VITERBI)) {
1003                 // read the CBER
1004                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1005                 if (cber == -1)
1006                         return -EIO;
1007                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1008                 if (status == -1)
1009                         return -EIO;
1010                 cber |= (status << 8);
1011                 // The address 0x20 should be read to cope with a TDA10046 bug
1012                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1013
1014                 if (cber != 65535)
1015                         *fe_status |= FE_HAS_VITERBI;
1016         }
1017
1018         // if we DO have some valid VITERBI output, but don't already have SYNC
1019         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1020         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1021                 // read the VBER
1022                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1023                 if (vber == -1)
1024                         return -EIO;
1025                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1026                 if (status == -1)
1027                         return -EIO;
1028                 vber |= (status << 8);
1029                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1030                 if (status == -1)
1031                         return -EIO;
1032                 vber |= (status & 0x0f) << 16;
1033                 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1034                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1035
1036                 // if RS has passed some valid TS packets, then we must be
1037                 // getting some SYNC bytes
1038                 if (vber < 16632)
1039                         *fe_status |= FE_HAS_SYNC;
1040         }
1041
1042         // success
1043         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1044         return 0;
1045 }
1046
1047 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1048 {
1049         struct tda1004x_state* state = fe->demodulator_priv;
1050         int tmp;
1051         int reg = 0;
1052
1053         dprintk("%s\n", __FUNCTION__);
1054
1055         // determine the register to use
1056         switch (state->demod_type) {
1057         case TDA1004X_DEMOD_TDA10045:
1058                 reg = TDA10045H_S_AGC;
1059                 break;
1060
1061         case TDA1004X_DEMOD_TDA10046:
1062                 reg = TDA10046H_AGC_IF_LEVEL;
1063                 break;
1064         }
1065
1066         // read it
1067         tmp = tda1004x_read_byte(state, reg);
1068         if (tmp < 0)
1069                 return -EIO;
1070
1071         *signal = (tmp << 8) | tmp;
1072         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1073         return 0;
1074 }
1075
1076 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1077 {
1078         struct tda1004x_state* state = fe->demodulator_priv;
1079         int tmp;
1080
1081         dprintk("%s\n", __FUNCTION__);
1082
1083         // read it
1084         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1085         if (tmp < 0)
1086                 return -EIO;
1087         tmp = 255 - tmp;
1088
1089         *snr = ((tmp << 8) | tmp);
1090         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1091         return 0;
1092 }
1093
1094 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1095 {
1096         struct tda1004x_state* state = fe->demodulator_priv;
1097         int tmp;
1098         int tmp2;
1099         int counter;
1100
1101         dprintk("%s\n", __FUNCTION__);
1102
1103         // read the UCBLOCKS and reset
1104         counter = 0;
1105         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1106         if (tmp < 0)
1107                 return -EIO;
1108         tmp &= 0x7f;
1109         while (counter++ < 5) {
1110                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1111                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1112                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1113
1114                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1115                 if (tmp2 < 0)
1116                         return -EIO;
1117                 tmp2 &= 0x7f;
1118                 if ((tmp2 < tmp) || (tmp2 == 0))
1119                         break;
1120         }
1121
1122         if (tmp != 0x7f)
1123                 *ucblocks = tmp;
1124         else
1125                 *ucblocks = 0xffffffff;
1126
1127         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1128         return 0;
1129 }
1130
1131 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1132 {
1133         struct tda1004x_state* state = fe->demodulator_priv;
1134         int tmp;
1135
1136         dprintk("%s\n", __FUNCTION__);
1137
1138         // read it in
1139         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1140         if (tmp < 0)
1141                 return -EIO;
1142         *ber = tmp << 1;
1143         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1144         if (tmp < 0)
1145                 return -EIO;
1146         *ber |= (tmp << 9);
1147         // The address 0x20 should be read to cope with a TDA10046 bug
1148         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1149
1150         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1151         return 0;
1152 }
1153
1154 static int tda1004x_sleep(struct dvb_frontend* fe)
1155 {
1156         struct tda1004x_state* state = fe->demodulator_priv;
1157         int gpio_conf;
1158
1159         switch (state->demod_type) {
1160         case TDA1004X_DEMOD_TDA10045:
1161                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1162                 break;
1163
1164         case TDA1004X_DEMOD_TDA10046:
1165                 /* set outputs to tristate */
1166                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1167                 /* invert GPIO 1 and 3 if desired*/
1168                 gpio_conf = state->config->gpio_config;
1169                 if (gpio_conf >= TDA10046_GP00_I)
1170                         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1171                                                         (gpio_conf & 0x0f) ^ 0x0a);
1172
1173                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1174                 break;
1175         }
1176
1177         return 0;
1178 }
1179
1180 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1181 {
1182         struct tda1004x_state* state = fe->demodulator_priv;
1183
1184         if (enable) {
1185                 return tda1004x_enable_tuner_i2c(state);
1186         } else {
1187                 return tda1004x_disable_tuner_i2c(state);
1188         }
1189 }
1190
1191 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1192 {
1193         fesettings->min_delay_ms = 800;
1194         /* Drift compensation makes no sense for DVB-T */
1195         fesettings->step_size = 0;
1196         fesettings->max_drift = 0;
1197         return 0;
1198 }
1199
1200 static void tda1004x_release(struct dvb_frontend* fe)
1201 {
1202         struct tda1004x_state *state = fe->demodulator_priv;
1203         kfree(state);
1204 }
1205
1206 static struct dvb_frontend_ops tda10045_ops = {
1207         .info = {
1208                 .name = "Philips TDA10045H DVB-T",
1209                 .type = FE_OFDM,
1210                 .frequency_min = 51000000,
1211                 .frequency_max = 858000000,
1212                 .frequency_stepsize = 166667,
1213                 .caps =
1214                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1215                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1216                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1217                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1218         },
1219
1220         .release = tda1004x_release,
1221
1222         .init = tda10045_init,
1223         .sleep = tda1004x_sleep,
1224         .write = tda1004x_write,
1225         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1226
1227         .set_frontend = tda1004x_set_fe,
1228         .get_frontend = tda1004x_get_fe,
1229         .get_tune_settings = tda1004x_get_tune_settings,
1230
1231         .read_status = tda1004x_read_status,
1232         .read_ber = tda1004x_read_ber,
1233         .read_signal_strength = tda1004x_read_signal_strength,
1234         .read_snr = tda1004x_read_snr,
1235         .read_ucblocks = tda1004x_read_ucblocks,
1236 };
1237
1238 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1239                                      struct i2c_adapter* i2c)
1240 {
1241         struct tda1004x_state *state;
1242
1243         /* allocate memory for the internal state */
1244         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1245         if (!state)
1246                 return NULL;
1247
1248         /* setup the state */
1249         state->config = config;
1250         state->i2c = i2c;
1251         state->demod_type = TDA1004X_DEMOD_TDA10045;
1252
1253         /* check if the demod is there */
1254         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1255                 kfree(state);
1256                 return NULL;
1257         }
1258
1259         /* create dvb_frontend */
1260         memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1261         state->frontend.demodulator_priv = state;
1262         return &state->frontend;
1263 }
1264
1265 static struct dvb_frontend_ops tda10046_ops = {
1266         .info = {
1267                 .name = "Philips TDA10046H DVB-T",
1268                 .type = FE_OFDM,
1269                 .frequency_min = 51000000,
1270                 .frequency_max = 858000000,
1271                 .frequency_stepsize = 166667,
1272                 .caps =
1273                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1274                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1275                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1276                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1277         },
1278
1279         .release = tda1004x_release,
1280
1281         .init = tda10046_init,
1282         .sleep = tda1004x_sleep,
1283         .write = tda1004x_write,
1284         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1285
1286         .set_frontend = tda1004x_set_fe,
1287         .get_frontend = tda1004x_get_fe,
1288         .get_tune_settings = tda1004x_get_tune_settings,
1289
1290         .read_status = tda1004x_read_status,
1291         .read_ber = tda1004x_read_ber,
1292         .read_signal_strength = tda1004x_read_signal_strength,
1293         .read_snr = tda1004x_read_snr,
1294         .read_ucblocks = tda1004x_read_ucblocks,
1295 };
1296
1297 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1298                                      struct i2c_adapter* i2c)
1299 {
1300         struct tda1004x_state *state;
1301
1302         /* allocate memory for the internal state */
1303         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1304         if (!state)
1305                 return NULL;
1306
1307         /* setup the state */
1308         state->config = config;
1309         state->i2c = i2c;
1310         state->demod_type = TDA1004X_DEMOD_TDA10046;
1311
1312         /* check if the demod is there */
1313         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1314                 kfree(state);
1315                 return NULL;
1316         }
1317
1318         /* create dvb_frontend */
1319         memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1320         state->frontend.demodulator_priv = state;
1321         return &state->frontend;
1322 }
1323
1324 module_param(debug, int, 0644);
1325 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1326
1327 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1328 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1329 MODULE_LICENSE("GPL");
1330
1331 EXPORT_SYMBOL(tda10045_attach);
1332 EXPORT_SYMBOL(tda10046_attach);