2 * Afatech AF9033 demodulator driver
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "af9033_priv.h"
24 /* Max transfer size done by I2C transfer functions */
25 #define MAX_XFER_SIZE 64
28 struct i2c_adapter *i2c;
29 struct dvb_frontend fe;
30 struct af9033_config cfg;
33 bool ts_mode_parallel;
38 unsigned long last_stat_check;
41 /* write multiple registers */
42 static int af9033_wr_regs(struct af9033_dev *dev, u32 reg, const u8 *val,
46 u8 buf[MAX_XFER_SIZE];
47 struct i2c_msg msg[1] = {
49 .addr = dev->cfg.i2c_addr,
56 if (3 + len > sizeof(buf)) {
57 dev_warn(&dev->i2c->dev,
58 "%s: i2c wr reg=%04x: len=%d is too big!\n",
59 KBUILD_MODNAME, reg, len);
63 buf[0] = (reg >> 16) & 0xff;
64 buf[1] = (reg >> 8) & 0xff;
65 buf[2] = (reg >> 0) & 0xff;
66 memcpy(&buf[3], val, len);
68 ret = i2c_transfer(dev->i2c, msg, 1);
72 dev_warn(&dev->i2c->dev,
73 "%s: i2c wr failed=%d reg=%06x len=%d\n",
74 KBUILD_MODNAME, ret, reg, len);
81 /* read multiple registers */
82 static int af9033_rd_regs(struct af9033_dev *dev, u32 reg, u8 *val, int len)
85 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff,
87 struct i2c_msg msg[2] = {
89 .addr = dev->cfg.i2c_addr,
94 .addr = dev->cfg.i2c_addr,
101 ret = i2c_transfer(dev->i2c, msg, 2);
105 dev_warn(&dev->i2c->dev,
106 "%s: i2c rd failed=%d reg=%06x len=%d\n",
107 KBUILD_MODNAME, ret, reg, len);
115 /* write single register */
116 static int af9033_wr_reg(struct af9033_dev *dev, u32 reg, u8 val)
118 return af9033_wr_regs(dev, reg, &val, 1);
121 /* read single register */
122 static int af9033_rd_reg(struct af9033_dev *dev, u32 reg, u8 *val)
124 return af9033_rd_regs(dev, reg, val, 1);
127 /* write single register with mask */
128 static int af9033_wr_reg_mask(struct af9033_dev *dev, u32 reg, u8 val,
134 /* no need for read if whole reg is written */
136 ret = af9033_rd_regs(dev, reg, &tmp, 1);
145 return af9033_wr_regs(dev, reg, &val, 1);
148 /* read single register with mask */
149 static int af9033_rd_reg_mask(struct af9033_dev *dev, u32 reg, u8 *val,
155 ret = af9033_rd_regs(dev, reg, &tmp, 1);
161 /* find position of the first bit */
162 for (i = 0; i < 8; i++) {
163 if ((mask >> i) & 0x01)
171 /* write reg val table using reg addr auto increment */
172 static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
173 const struct reg_val *tab, int tab_len)
175 #define MAX_TAB_LEN 212
177 u8 buf[1 + MAX_TAB_LEN];
179 dev_dbg(&dev->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
181 if (tab_len > sizeof(buf)) {
182 dev_warn(&dev->i2c->dev, "%s: tab len %d is too big\n",
183 KBUILD_MODNAME, tab_len);
187 for (i = 0, j = 0; i < tab_len; i++) {
190 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
191 ret = af9033_wr_regs(dev, tab[i].reg - j, buf, j + 1);
204 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
209 static u32 af9033_div(struct af9033_dev *dev, u32 a, u32 b, u32 x)
213 dev_dbg(&dev->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x);
220 for (i = 0; i < x; i++) {
228 r = (c << (u32)x) + r;
230 dev_dbg(&dev->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n",
231 __func__, a, b, x, r, r);
236 static void af9033_release(struct dvb_frontend *fe)
238 struct af9033_dev *dev = fe->demodulator_priv;
243 static int af9033_init(struct dvb_frontend *fe)
245 struct af9033_dev *dev = fe->demodulator_priv;
247 const struct reg_val *init;
249 u32 adc_cw, clock_cw;
250 struct reg_val_mask tab[] = {
251 { 0x80fb24, 0x00, 0x08 },
252 { 0x80004c, 0x00, 0xff },
253 { 0x00f641, dev->cfg.tuner, 0xff },
254 { 0x80f5ca, 0x01, 0x01 },
255 { 0x80f715, 0x01, 0x01 },
256 { 0x00f41f, 0x04, 0x04 },
257 { 0x00f41a, 0x01, 0x01 },
258 { 0x80f731, 0x00, 0x01 },
259 { 0x00d91e, 0x00, 0x01 },
260 { 0x00d919, 0x00, 0x01 },
261 { 0x80f732, 0x00, 0x01 },
262 { 0x00d91f, 0x00, 0x01 },
263 { 0x00d91a, 0x00, 0x01 },
264 { 0x80f730, 0x00, 0x01 },
265 { 0x80f778, 0x00, 0xff },
266 { 0x80f73c, 0x01, 0x01 },
267 { 0x80f776, 0x00, 0x01 },
268 { 0x00d8fd, 0x01, 0xff },
269 { 0x00d830, 0x01, 0xff },
270 { 0x00d831, 0x00, 0xff },
271 { 0x00d832, 0x00, 0xff },
272 { 0x80f985, dev->ts_mode_serial, 0x01 },
273 { 0x80f986, dev->ts_mode_parallel, 0x01 },
274 { 0x00d827, 0x00, 0xff },
275 { 0x00d829, 0x00, 0xff },
276 { 0x800045, dev->cfg.adc_multiplier, 0xff },
279 /* program clock control */
280 clock_cw = af9033_div(dev, dev->cfg.clock, 1000000ul, 19ul);
281 buf[0] = (clock_cw >> 0) & 0xff;
282 buf[1] = (clock_cw >> 8) & 0xff;
283 buf[2] = (clock_cw >> 16) & 0xff;
284 buf[3] = (clock_cw >> 24) & 0xff;
286 dev_dbg(&dev->i2c->dev, "%s: clock=%d clock_cw=%08x\n",
287 __func__, dev->cfg.clock, clock_cw);
289 ret = af9033_wr_regs(dev, 0x800025, buf, 4);
293 /* program ADC control */
294 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
295 if (clock_adc_lut[i].clock == dev->cfg.clock)
299 adc_cw = af9033_div(dev, clock_adc_lut[i].adc, 1000000ul, 19ul);
300 buf[0] = (adc_cw >> 0) & 0xff;
301 buf[1] = (adc_cw >> 8) & 0xff;
302 buf[2] = (adc_cw >> 16) & 0xff;
304 dev_dbg(&dev->i2c->dev, "%s: adc=%d adc_cw=%06x\n",
305 __func__, clock_adc_lut[i].adc, adc_cw);
307 ret = af9033_wr_regs(dev, 0x80f1cd, buf, 3);
311 /* program register table */
312 for (i = 0; i < ARRAY_SIZE(tab); i++) {
313 ret = af9033_wr_reg_mask(dev, tab[i].reg, tab[i].val,
320 if (dev->cfg.dyn0_clk) {
321 ret = af9033_wr_reg(dev, 0x80fba8, 0x00);
326 /* settings for TS interface */
327 if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
328 ret = af9033_wr_reg_mask(dev, 0x80f9a5, 0x00, 0x01);
332 ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x01, 0x01);
336 ret = af9033_wr_reg_mask(dev, 0x80f990, 0x00, 0x01);
340 ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x00, 0x01);
345 /* load OFSM settings */
346 dev_dbg(&dev->i2c->dev, "%s: load ofsm settings\n", __func__);
347 switch (dev->cfg.tuner) {
348 case AF9033_TUNER_IT9135_38:
349 case AF9033_TUNER_IT9135_51:
350 case AF9033_TUNER_IT9135_52:
351 len = ARRAY_SIZE(ofsm_init_it9135_v1);
352 init = ofsm_init_it9135_v1;
354 case AF9033_TUNER_IT9135_60:
355 case AF9033_TUNER_IT9135_61:
356 case AF9033_TUNER_IT9135_62:
357 len = ARRAY_SIZE(ofsm_init_it9135_v2);
358 init = ofsm_init_it9135_v2;
361 len = ARRAY_SIZE(ofsm_init);
366 ret = af9033_wr_reg_val_tab(dev, init, len);
370 /* load tuner specific settings */
371 dev_dbg(&dev->i2c->dev, "%s: load tuner specific settings\n",
373 switch (dev->cfg.tuner) {
374 case AF9033_TUNER_TUA9001:
375 len = ARRAY_SIZE(tuner_init_tua9001);
376 init = tuner_init_tua9001;
378 case AF9033_TUNER_FC0011:
379 len = ARRAY_SIZE(tuner_init_fc0011);
380 init = tuner_init_fc0011;
382 case AF9033_TUNER_MXL5007T:
383 len = ARRAY_SIZE(tuner_init_mxl5007t);
384 init = tuner_init_mxl5007t;
386 case AF9033_TUNER_TDA18218:
387 len = ARRAY_SIZE(tuner_init_tda18218);
388 init = tuner_init_tda18218;
390 case AF9033_TUNER_FC2580:
391 len = ARRAY_SIZE(tuner_init_fc2580);
392 init = tuner_init_fc2580;
394 case AF9033_TUNER_FC0012:
395 len = ARRAY_SIZE(tuner_init_fc0012);
396 init = tuner_init_fc0012;
398 case AF9033_TUNER_IT9135_38:
399 len = ARRAY_SIZE(tuner_init_it9135_38);
400 init = tuner_init_it9135_38;
402 case AF9033_TUNER_IT9135_51:
403 len = ARRAY_SIZE(tuner_init_it9135_51);
404 init = tuner_init_it9135_51;
406 case AF9033_TUNER_IT9135_52:
407 len = ARRAY_SIZE(tuner_init_it9135_52);
408 init = tuner_init_it9135_52;
410 case AF9033_TUNER_IT9135_60:
411 len = ARRAY_SIZE(tuner_init_it9135_60);
412 init = tuner_init_it9135_60;
414 case AF9033_TUNER_IT9135_61:
415 len = ARRAY_SIZE(tuner_init_it9135_61);
416 init = tuner_init_it9135_61;
418 case AF9033_TUNER_IT9135_62:
419 len = ARRAY_SIZE(tuner_init_it9135_62);
420 init = tuner_init_it9135_62;
423 dev_dbg(&dev->i2c->dev, "%s: unsupported tuner ID=%d\n",
424 __func__, dev->cfg.tuner);
429 ret = af9033_wr_reg_val_tab(dev, init, len);
433 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
434 ret = af9033_wr_reg_mask(dev, 0x00d91c, 0x01, 0x01);
438 ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01);
442 ret = af9033_wr_reg_mask(dev, 0x00d916, 0x00, 0x01);
447 switch (dev->cfg.tuner) {
448 case AF9033_TUNER_IT9135_60:
449 case AF9033_TUNER_IT9135_61:
450 case AF9033_TUNER_IT9135_62:
451 ret = af9033_wr_reg(dev, 0x800000, 0x01);
456 dev->bandwidth_hz = 0; /* force to program all parameters */
461 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
466 static int af9033_sleep(struct dvb_frontend *fe)
468 struct af9033_dev *dev = fe->demodulator_priv;
472 ret = af9033_wr_reg(dev, 0x80004c, 1);
476 ret = af9033_wr_reg(dev, 0x800000, 0);
480 for (i = 100, tmp = 1; i && tmp; i--) {
481 ret = af9033_rd_reg(dev, 0x80004c, &tmp);
485 usleep_range(200, 10000);
488 dev_dbg(&dev->i2c->dev, "%s: loop=%d\n", __func__, i);
495 ret = af9033_wr_reg_mask(dev, 0x80fb24, 0x08, 0x08);
499 /* prevent current leak (?) */
500 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
501 /* enable parallel TS */
502 ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01);
506 ret = af9033_wr_reg_mask(dev, 0x00d916, 0x01, 0x01);
514 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
519 static int af9033_get_tune_settings(struct dvb_frontend *fe,
520 struct dvb_frontend_tune_settings *fesettings)
522 /* 800 => 2000 because IT9135 v2 is slow to gain lock */
523 fesettings->min_delay_ms = 2000;
524 fesettings->step_size = 0;
525 fesettings->max_drift = 0;
530 static int af9033_set_frontend(struct dvb_frontend *fe)
532 struct af9033_dev *dev = fe->demodulator_priv;
533 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
534 int ret, i, spec_inv, sampling_freq;
535 u8 tmp, buf[3], bandwidth_reg_val;
536 u32 if_frequency, freq_cw, adc_freq;
538 dev_dbg(&dev->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n",
539 __func__, c->frequency, c->bandwidth_hz);
541 /* check bandwidth */
542 switch (c->bandwidth_hz) {
544 bandwidth_reg_val = 0x00;
547 bandwidth_reg_val = 0x01;
550 bandwidth_reg_val = 0x02;
553 dev_dbg(&dev->i2c->dev, "%s: invalid bandwidth_hz\n",
560 if (fe->ops.tuner_ops.set_params)
561 fe->ops.tuner_ops.set_params(fe);
563 /* program CFOE coefficients */
564 if (c->bandwidth_hz != dev->bandwidth_hz) {
565 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
566 if (coeff_lut[i].clock == dev->cfg.clock &&
567 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
571 ret = af9033_wr_regs(dev, 0x800001,
572 coeff_lut[i].val, sizeof(coeff_lut[i].val));
575 /* program frequency control */
576 if (c->bandwidth_hz != dev->bandwidth_hz) {
577 spec_inv = dev->cfg.spec_inv ? -1 : 1;
579 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
580 if (clock_adc_lut[i].clock == dev->cfg.clock)
583 adc_freq = clock_adc_lut[i].adc;
585 /* get used IF frequency */
586 if (fe->ops.tuner_ops.get_if_frequency)
587 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
591 sampling_freq = if_frequency;
593 while (sampling_freq > (adc_freq / 2))
594 sampling_freq -= adc_freq;
596 if (sampling_freq >= 0)
601 freq_cw = af9033_div(dev, sampling_freq, adc_freq, 23ul);
604 freq_cw = 0x800000 - freq_cw;
606 if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
609 buf[0] = (freq_cw >> 0) & 0xff;
610 buf[1] = (freq_cw >> 8) & 0xff;
611 buf[2] = (freq_cw >> 16) & 0x7f;
613 /* FIXME: there seems to be calculation error here... */
614 if (if_frequency == 0)
617 ret = af9033_wr_regs(dev, 0x800029, buf, 3);
621 dev->bandwidth_hz = c->bandwidth_hz;
624 ret = af9033_wr_reg_mask(dev, 0x80f904, bandwidth_reg_val, 0x03);
628 ret = af9033_wr_reg(dev, 0x800040, 0x00);
632 ret = af9033_wr_reg(dev, 0x800047, 0x00);
636 ret = af9033_wr_reg_mask(dev, 0x80f999, 0x00, 0x01);
640 if (c->frequency <= 230000000)
641 tmp = 0x00; /* VHF */
643 tmp = 0x01; /* UHF */
645 ret = af9033_wr_reg(dev, 0x80004b, tmp);
649 ret = af9033_wr_reg(dev, 0x800000, 0x00);
656 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
661 static int af9033_get_frontend(struct dvb_frontend *fe)
663 struct af9033_dev *dev = fe->demodulator_priv;
664 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
668 dev_dbg(&dev->i2c->dev, "%s:\n", __func__);
670 /* read all needed registers */
671 ret = af9033_rd_regs(dev, 0x80f900, buf, sizeof(buf));
675 switch ((buf[0] >> 0) & 3) {
677 c->transmission_mode = TRANSMISSION_MODE_2K;
680 c->transmission_mode = TRANSMISSION_MODE_8K;
684 switch ((buf[1] >> 0) & 3) {
686 c->guard_interval = GUARD_INTERVAL_1_32;
689 c->guard_interval = GUARD_INTERVAL_1_16;
692 c->guard_interval = GUARD_INTERVAL_1_8;
695 c->guard_interval = GUARD_INTERVAL_1_4;
699 switch ((buf[2] >> 0) & 7) {
701 c->hierarchy = HIERARCHY_NONE;
704 c->hierarchy = HIERARCHY_1;
707 c->hierarchy = HIERARCHY_2;
710 c->hierarchy = HIERARCHY_4;
714 switch ((buf[3] >> 0) & 3) {
716 c->modulation = QPSK;
719 c->modulation = QAM_16;
722 c->modulation = QAM_64;
726 switch ((buf[4] >> 0) & 3) {
728 c->bandwidth_hz = 6000000;
731 c->bandwidth_hz = 7000000;
734 c->bandwidth_hz = 8000000;
738 switch ((buf[6] >> 0) & 7) {
740 c->code_rate_HP = FEC_1_2;
743 c->code_rate_HP = FEC_2_3;
746 c->code_rate_HP = FEC_3_4;
749 c->code_rate_HP = FEC_5_6;
752 c->code_rate_HP = FEC_7_8;
755 c->code_rate_HP = FEC_NONE;
759 switch ((buf[7] >> 0) & 7) {
761 c->code_rate_LP = FEC_1_2;
764 c->code_rate_LP = FEC_2_3;
767 c->code_rate_LP = FEC_3_4;
770 c->code_rate_LP = FEC_5_6;
773 c->code_rate_LP = FEC_7_8;
776 c->code_rate_LP = FEC_NONE;
783 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
788 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status)
790 struct af9033_dev *dev = fe->demodulator_priv;
796 /* radio channel status, 0=no result, 1=has signal, 2=no signal */
797 ret = af9033_rd_reg(dev, 0x800047, &tmp);
803 *status |= FE_HAS_SIGNAL;
807 ret = af9033_rd_reg_mask(dev, 0x80f5a9, &tmp, 0x01);
812 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
816 ret = af9033_rd_reg_mask(dev, 0x80f999, &tmp, 0x01);
821 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
822 FE_HAS_VITERBI | FE_HAS_SYNC |
829 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
834 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
836 struct af9033_dev *dev = fe->demodulator_priv;
840 const struct val_snr *snr_lut;
843 ret = af9033_rd_regs(dev, 0x80002c, buf, 3);
847 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0];
849 /* read current modulation */
850 ret = af9033_rd_reg(dev, 0x80f903, &tmp);
854 switch ((tmp >> 0) & 3) {
856 len = ARRAY_SIZE(qpsk_snr_lut);
857 snr_lut = qpsk_snr_lut;
860 len = ARRAY_SIZE(qam16_snr_lut);
861 snr_lut = qam16_snr_lut;
864 len = ARRAY_SIZE(qam64_snr_lut);
865 snr_lut = qam64_snr_lut;
871 for (i = 0; i < len; i++) {
872 tmp = snr_lut[i].snr;
874 if (snr_val < snr_lut[i].val)
878 *snr = tmp * 10; /* dB/10 */
883 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
888 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
890 struct af9033_dev *dev = fe->demodulator_priv;
894 /* read signal strength of 0-100 scale */
895 ret = af9033_rd_reg(dev, 0x800048, &strength2);
899 /* scale value to 0x0000-0xffff */
900 *strength = strength2 * 0xffff / 100;
905 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
910 static int af9033_update_ch_stat(struct af9033_dev *dev)
913 u32 err_cnt, bit_cnt;
917 /* only update data every half second */
918 if (time_after(jiffies, dev->last_stat_check + msecs_to_jiffies(500))) {
919 ret = af9033_rd_regs(dev, 0x800032, buf, sizeof(buf));
922 /* in 8 byte packets? */
923 abort_cnt = (buf[1] << 8) + buf[0];
925 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2];
926 /* in 8 byte packets? always(?) 0x2710 = 10000 */
927 bit_cnt = (buf[6] << 8) + buf[5];
929 if (bit_cnt < abort_cnt) {
931 dev->ber = 0xffffffff;
934 * 8 byte packets, that have not been rejected already
936 bit_cnt -= (u32)abort_cnt;
938 dev->ber = 0xffffffff;
940 err_cnt -= (u32)abort_cnt * 8 * 8;
942 dev->ber = err_cnt * (0xffffffff / bit_cnt);
945 dev->ucb += abort_cnt;
946 dev->last_stat_check = jiffies;
951 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
956 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
958 struct af9033_dev *dev = fe->demodulator_priv;
961 ret = af9033_update_ch_stat(dev);
970 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
972 struct af9033_dev *dev = fe->demodulator_priv;
975 ret = af9033_update_ch_stat(dev);
979 *ucblocks = dev->ucb;
984 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
986 struct af9033_dev *dev = fe->demodulator_priv;
989 dev_dbg(&dev->i2c->dev, "%s: enable=%d\n", __func__, enable);
991 ret = af9033_wr_reg_mask(dev, 0x00fa04, enable, 0x01);
998 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
1003 static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1005 struct af9033_dev *dev = fe->demodulator_priv;
1008 dev_dbg(&dev->i2c->dev, "%s: onoff=%d\n", __func__, onoff);
1010 ret = af9033_wr_reg_mask(dev, 0x80f993, onoff, 0x01);
1017 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
1022 static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
1025 struct af9033_dev *dev = fe->demodulator_priv;
1027 u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
1029 dev_dbg(&dev->i2c->dev, "%s: index=%d pid=%04x onoff=%d\n",
1030 __func__, index, pid, onoff);
1035 ret = af9033_wr_regs(dev, 0x80f996, wbuf, 2);
1039 ret = af9033_wr_reg(dev, 0x80f994, onoff);
1043 ret = af9033_wr_reg(dev, 0x80f995, index);
1050 dev_dbg(&dev->i2c->dev, "%s: failed=%d\n", __func__, ret);
1055 static struct dvb_frontend_ops af9033_ops;
1057 struct dvb_frontend *af9033_attach(const struct af9033_config *config,
1058 struct i2c_adapter *i2c,
1059 struct af9033_ops *ops)
1062 struct af9033_dev *dev;
1066 dev_dbg(&i2c->dev, "%s:\n", __func__);
1068 /* allocate memory for the internal state */
1069 dev = kzalloc(sizeof(struct af9033_dev), GFP_KERNEL);
1073 /* setup the state */
1075 memcpy(&dev->cfg, config, sizeof(struct af9033_config));
1077 if (dev->cfg.clock != 12000000) {
1078 dev_err(&dev->i2c->dev,
1079 "%s: af9033: unsupported clock=%d, only 12000000 Hz is supported currently\n",
1080 KBUILD_MODNAME, dev->cfg.clock);
1084 /* firmware version */
1085 switch (dev->cfg.tuner) {
1086 case AF9033_TUNER_IT9135_38:
1087 case AF9033_TUNER_IT9135_51:
1088 case AF9033_TUNER_IT9135_52:
1089 case AF9033_TUNER_IT9135_60:
1090 case AF9033_TUNER_IT9135_61:
1091 case AF9033_TUNER_IT9135_62:
1099 ret = af9033_rd_regs(dev, reg, &buf[0], 4);
1103 ret = af9033_rd_regs(dev, 0x804191, &buf[4], 4);
1107 dev_info(&dev->i2c->dev,
1108 "%s: firmware version: LINK=%d.%d.%d.%d OFDM=%d.%d.%d.%d\n",
1109 KBUILD_MODNAME, buf[0], buf[1], buf[2], buf[3], buf[4],
1110 buf[5], buf[6], buf[7]);
1113 switch (dev->cfg.tuner) {
1114 case AF9033_TUNER_IT9135_38:
1115 case AF9033_TUNER_IT9135_51:
1116 case AF9033_TUNER_IT9135_52:
1117 case AF9033_TUNER_IT9135_60:
1118 case AF9033_TUNER_IT9135_61:
1119 case AF9033_TUNER_IT9135_62:
1120 /* IT9135 did not like to sleep at that early */
1123 ret = af9033_wr_reg(dev, 0x80004c, 1);
1127 ret = af9033_wr_reg(dev, 0x800000, 0);
1132 /* configure internal TS mode */
1133 switch (dev->cfg.ts_mode) {
1134 case AF9033_TS_MODE_PARALLEL:
1135 dev->ts_mode_parallel = true;
1137 case AF9033_TS_MODE_SERIAL:
1138 dev->ts_mode_serial = true;
1140 case AF9033_TS_MODE_USB:
1141 /* usb mode for AF9035 */
1146 /* create dvb_frontend */
1147 memcpy(&dev->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops));
1148 dev->fe.demodulator_priv = dev;
1151 ops->pid_filter = af9033_pid_filter;
1152 ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
1161 EXPORT_SYMBOL(af9033_attach);
1163 static struct dvb_frontend_ops af9033_ops = {
1164 .delsys = { SYS_DVBT },
1166 .name = "Afatech AF9033 (DVB-T)",
1167 .frequency_min = 174000000,
1168 .frequency_max = 862000000,
1169 .frequency_stepsize = 250000,
1170 .frequency_tolerance = 0,
1171 .caps = FE_CAN_FEC_1_2 |
1181 FE_CAN_TRANSMISSION_MODE_AUTO |
1182 FE_CAN_GUARD_INTERVAL_AUTO |
1183 FE_CAN_HIERARCHY_AUTO |
1188 .release = af9033_release,
1190 .init = af9033_init,
1191 .sleep = af9033_sleep,
1193 .get_tune_settings = af9033_get_tune_settings,
1194 .set_frontend = af9033_set_frontend,
1195 .get_frontend = af9033_get_frontend,
1197 .read_status = af9033_read_status,
1198 .read_snr = af9033_read_snr,
1199 .read_signal_strength = af9033_read_signal_strength,
1200 .read_ber = af9033_read_ber,
1201 .read_ucblocks = af9033_read_ucblocks,
1203 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1206 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1207 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1208 MODULE_LICENSE("GPL");