2 * Afatech AF9033 demodulator driver
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "af9033_priv.h"
24 /* Max transfer size done by I2C transfer functions */
25 #define MAX_XFER_SIZE 64
28 struct i2c_client *client;
29 struct dvb_frontend fe;
30 struct af9033_config cfg;
35 bool ts_mode_parallel;
38 fe_status_t fe_status;
41 u64 error_block_count;
42 u64 total_block_count;
43 struct delayed_work stat_work;
44 unsigned long last_stat_check;
47 /* write multiple registers */
48 static int af9033_wr_regs(struct af9033_dev *dev, u32 reg, const u8 *val,
52 u8 buf[MAX_XFER_SIZE];
53 struct i2c_msg msg[1] = {
55 .addr = dev->client->addr,
62 if (3 + len > sizeof(buf)) {
63 dev_warn(&dev->client->dev,
64 "i2c wr reg=%04x: len=%d is too big!\n",
69 buf[0] = (reg >> 16) & 0xff;
70 buf[1] = (reg >> 8) & 0xff;
71 buf[2] = (reg >> 0) & 0xff;
72 memcpy(&buf[3], val, len);
74 ret = i2c_transfer(dev->client->adapter, msg, 1);
78 dev_warn(&dev->client->dev, "i2c wr failed=%d reg=%06x len=%d\n",
86 /* read multiple registers */
87 static int af9033_rd_regs(struct af9033_dev *dev, u32 reg, u8 *val, int len)
90 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff,
92 struct i2c_msg msg[2] = {
94 .addr = dev->client->addr,
99 .addr = dev->client->addr,
106 ret = i2c_transfer(dev->client->adapter, msg, 2);
110 dev_warn(&dev->client->dev, "i2c rd failed=%d reg=%06x len=%d\n",
119 /* write single register */
120 static int af9033_wr_reg(struct af9033_dev *dev, u32 reg, u8 val)
122 return af9033_wr_regs(dev, reg, &val, 1);
125 /* read single register */
126 static int af9033_rd_reg(struct af9033_dev *dev, u32 reg, u8 *val)
128 return af9033_rd_regs(dev, reg, val, 1);
131 /* write single register with mask */
132 static int af9033_wr_reg_mask(struct af9033_dev *dev, u32 reg, u8 val,
138 /* no need for read if whole reg is written */
140 ret = af9033_rd_regs(dev, reg, &tmp, 1);
149 return af9033_wr_regs(dev, reg, &val, 1);
152 /* read single register with mask */
153 static int af9033_rd_reg_mask(struct af9033_dev *dev, u32 reg, u8 *val,
159 ret = af9033_rd_regs(dev, reg, &tmp, 1);
165 /* find position of the first bit */
166 for (i = 0; i < 8; i++) {
167 if ((mask >> i) & 0x01)
175 /* write reg val table using reg addr auto increment */
176 static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
177 const struct reg_val *tab, int tab_len)
179 #define MAX_TAB_LEN 212
181 u8 buf[1 + MAX_TAB_LEN];
183 dev_dbg(&dev->client->dev, "tab_len=%d\n", tab_len);
185 if (tab_len > sizeof(buf)) {
186 dev_warn(&dev->client->dev, "tab len %d is too big\n", tab_len);
190 for (i = 0, j = 0; i < tab_len; i++) {
193 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
194 ret = af9033_wr_regs(dev, tab[i].reg - j, buf, j + 1);
207 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
212 static u32 af9033_div(struct af9033_dev *dev, u32 a, u32 b, u32 x)
216 dev_dbg(&dev->client->dev, "a=%d b=%d x=%d\n", a, b, x);
223 for (i = 0; i < x; i++) {
231 r = (c << (u32)x) + r;
233 dev_dbg(&dev->client->dev, "a=%d b=%d x=%d r=%d r=%x\n", a, b, x, r, r);
238 static int af9033_init(struct dvb_frontend *fe)
240 struct af9033_dev *dev = fe->demodulator_priv;
242 const struct reg_val *init;
244 u32 adc_cw, clock_cw;
245 struct reg_val_mask tab[] = {
246 { 0x80fb24, 0x00, 0x08 },
247 { 0x80004c, 0x00, 0xff },
248 { 0x00f641, dev->cfg.tuner, 0xff },
249 { 0x80f5ca, 0x01, 0x01 },
250 { 0x80f715, 0x01, 0x01 },
251 { 0x00f41f, 0x04, 0x04 },
252 { 0x00f41a, 0x01, 0x01 },
253 { 0x80f731, 0x00, 0x01 },
254 { 0x00d91e, 0x00, 0x01 },
255 { 0x00d919, 0x00, 0x01 },
256 { 0x80f732, 0x00, 0x01 },
257 { 0x00d91f, 0x00, 0x01 },
258 { 0x00d91a, 0x00, 0x01 },
259 { 0x80f730, 0x00, 0x01 },
260 { 0x80f778, 0x00, 0xff },
261 { 0x80f73c, 0x01, 0x01 },
262 { 0x80f776, 0x00, 0x01 },
263 { 0x00d8fd, 0x01, 0xff },
264 { 0x00d830, 0x01, 0xff },
265 { 0x00d831, 0x00, 0xff },
266 { 0x00d832, 0x00, 0xff },
267 { 0x80f985, dev->ts_mode_serial, 0x01 },
268 { 0x80f986, dev->ts_mode_parallel, 0x01 },
269 { 0x00d827, 0x00, 0xff },
270 { 0x00d829, 0x00, 0xff },
271 { 0x800045, dev->cfg.adc_multiplier, 0xff },
274 /* program clock control */
275 clock_cw = af9033_div(dev, dev->cfg.clock, 1000000ul, 19ul);
276 buf[0] = (clock_cw >> 0) & 0xff;
277 buf[1] = (clock_cw >> 8) & 0xff;
278 buf[2] = (clock_cw >> 16) & 0xff;
279 buf[3] = (clock_cw >> 24) & 0xff;
281 dev_dbg(&dev->client->dev, "clock=%d clock_cw=%08x\n",
282 dev->cfg.clock, clock_cw);
284 ret = af9033_wr_regs(dev, 0x800025, buf, 4);
288 /* program ADC control */
289 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
290 if (clock_adc_lut[i].clock == dev->cfg.clock)
294 adc_cw = af9033_div(dev, clock_adc_lut[i].adc, 1000000ul, 19ul);
295 buf[0] = (adc_cw >> 0) & 0xff;
296 buf[1] = (adc_cw >> 8) & 0xff;
297 buf[2] = (adc_cw >> 16) & 0xff;
299 dev_dbg(&dev->client->dev, "adc=%d adc_cw=%06x\n",
300 clock_adc_lut[i].adc, adc_cw);
302 ret = af9033_wr_regs(dev, 0x80f1cd, buf, 3);
306 /* program register table */
307 for (i = 0; i < ARRAY_SIZE(tab); i++) {
308 ret = af9033_wr_reg_mask(dev, tab[i].reg, tab[i].val,
315 if (dev->cfg.dyn0_clk) {
316 ret = af9033_wr_reg(dev, 0x80fba8, 0x00);
321 /* settings for TS interface */
322 if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
323 ret = af9033_wr_reg_mask(dev, 0x80f9a5, 0x00, 0x01);
327 ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x01, 0x01);
331 ret = af9033_wr_reg_mask(dev, 0x80f990, 0x00, 0x01);
335 ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x00, 0x01);
340 /* load OFSM settings */
341 dev_dbg(&dev->client->dev, "load ofsm settings\n");
342 switch (dev->cfg.tuner) {
343 case AF9033_TUNER_IT9135_38:
344 case AF9033_TUNER_IT9135_51:
345 case AF9033_TUNER_IT9135_52:
346 len = ARRAY_SIZE(ofsm_init_it9135_v1);
347 init = ofsm_init_it9135_v1;
349 case AF9033_TUNER_IT9135_60:
350 case AF9033_TUNER_IT9135_61:
351 case AF9033_TUNER_IT9135_62:
352 len = ARRAY_SIZE(ofsm_init_it9135_v2);
353 init = ofsm_init_it9135_v2;
356 len = ARRAY_SIZE(ofsm_init);
361 ret = af9033_wr_reg_val_tab(dev, init, len);
365 /* load tuner specific settings */
366 dev_dbg(&dev->client->dev, "load tuner specific settings\n");
367 switch (dev->cfg.tuner) {
368 case AF9033_TUNER_TUA9001:
369 len = ARRAY_SIZE(tuner_init_tua9001);
370 init = tuner_init_tua9001;
372 case AF9033_TUNER_FC0011:
373 len = ARRAY_SIZE(tuner_init_fc0011);
374 init = tuner_init_fc0011;
376 case AF9033_TUNER_MXL5007T:
377 len = ARRAY_SIZE(tuner_init_mxl5007t);
378 init = tuner_init_mxl5007t;
380 case AF9033_TUNER_TDA18218:
381 len = ARRAY_SIZE(tuner_init_tda18218);
382 init = tuner_init_tda18218;
384 case AF9033_TUNER_FC2580:
385 len = ARRAY_SIZE(tuner_init_fc2580);
386 init = tuner_init_fc2580;
388 case AF9033_TUNER_FC0012:
389 len = ARRAY_SIZE(tuner_init_fc0012);
390 init = tuner_init_fc0012;
392 case AF9033_TUNER_IT9135_38:
393 len = ARRAY_SIZE(tuner_init_it9135_38);
394 init = tuner_init_it9135_38;
396 case AF9033_TUNER_IT9135_51:
397 len = ARRAY_SIZE(tuner_init_it9135_51);
398 init = tuner_init_it9135_51;
400 case AF9033_TUNER_IT9135_52:
401 len = ARRAY_SIZE(tuner_init_it9135_52);
402 init = tuner_init_it9135_52;
404 case AF9033_TUNER_IT9135_60:
405 len = ARRAY_SIZE(tuner_init_it9135_60);
406 init = tuner_init_it9135_60;
408 case AF9033_TUNER_IT9135_61:
409 len = ARRAY_SIZE(tuner_init_it9135_61);
410 init = tuner_init_it9135_61;
412 case AF9033_TUNER_IT9135_62:
413 len = ARRAY_SIZE(tuner_init_it9135_62);
414 init = tuner_init_it9135_62;
417 dev_dbg(&dev->client->dev, "unsupported tuner ID=%d\n",
423 ret = af9033_wr_reg_val_tab(dev, init, len);
427 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
428 ret = af9033_wr_reg_mask(dev, 0x00d91c, 0x01, 0x01);
432 ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01);
436 ret = af9033_wr_reg_mask(dev, 0x00d916, 0x00, 0x01);
441 switch (dev->cfg.tuner) {
442 case AF9033_TUNER_IT9135_60:
443 case AF9033_TUNER_IT9135_61:
444 case AF9033_TUNER_IT9135_62:
445 ret = af9033_wr_reg(dev, 0x800000, 0x01);
450 dev->bandwidth_hz = 0; /* force to program all parameters */
451 /* start statistics polling */
452 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
457 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
462 static int af9033_sleep(struct dvb_frontend *fe)
464 struct af9033_dev *dev = fe->demodulator_priv;
468 /* stop statistics polling */
469 cancel_delayed_work_sync(&dev->stat_work);
471 ret = af9033_wr_reg(dev, 0x80004c, 1);
475 ret = af9033_wr_reg(dev, 0x800000, 0);
479 for (i = 100, tmp = 1; i && tmp; i--) {
480 ret = af9033_rd_reg(dev, 0x80004c, &tmp);
484 usleep_range(200, 10000);
487 dev_dbg(&dev->client->dev, "loop=%d\n", i);
494 ret = af9033_wr_reg_mask(dev, 0x80fb24, 0x08, 0x08);
498 /* prevent current leak (?) */
499 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
500 /* enable parallel TS */
501 ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01);
505 ret = af9033_wr_reg_mask(dev, 0x00d916, 0x01, 0x01);
513 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
518 static int af9033_get_tune_settings(struct dvb_frontend *fe,
519 struct dvb_frontend_tune_settings *fesettings)
521 /* 800 => 2000 because IT9135 v2 is slow to gain lock */
522 fesettings->min_delay_ms = 2000;
523 fesettings->step_size = 0;
524 fesettings->max_drift = 0;
529 static int af9033_set_frontend(struct dvb_frontend *fe)
531 struct af9033_dev *dev = fe->demodulator_priv;
532 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
533 int ret, i, spec_inv, sampling_freq;
534 u8 tmp, buf[3], bandwidth_reg_val;
535 u32 if_frequency, freq_cw, adc_freq;
537 dev_dbg(&dev->client->dev, "frequency=%d bandwidth_hz=%d\n",
538 c->frequency, c->bandwidth_hz);
540 /* check bandwidth */
541 switch (c->bandwidth_hz) {
543 bandwidth_reg_val = 0x00;
546 bandwidth_reg_val = 0x01;
549 bandwidth_reg_val = 0x02;
552 dev_dbg(&dev->client->dev, "invalid bandwidth_hz\n");
558 if (fe->ops.tuner_ops.set_params)
559 fe->ops.tuner_ops.set_params(fe);
561 /* program CFOE coefficients */
562 if (c->bandwidth_hz != dev->bandwidth_hz) {
563 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
564 if (coeff_lut[i].clock == dev->cfg.clock &&
565 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
569 ret = af9033_wr_regs(dev, 0x800001,
570 coeff_lut[i].val, sizeof(coeff_lut[i].val));
573 /* program frequency control */
574 if (c->bandwidth_hz != dev->bandwidth_hz) {
575 spec_inv = dev->cfg.spec_inv ? -1 : 1;
577 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
578 if (clock_adc_lut[i].clock == dev->cfg.clock)
581 adc_freq = clock_adc_lut[i].adc;
583 /* get used IF frequency */
584 if (fe->ops.tuner_ops.get_if_frequency)
585 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
589 sampling_freq = if_frequency;
591 while (sampling_freq > (adc_freq / 2))
592 sampling_freq -= adc_freq;
594 if (sampling_freq >= 0)
599 freq_cw = af9033_div(dev, sampling_freq, adc_freq, 23ul);
602 freq_cw = 0x800000 - freq_cw;
604 if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
607 buf[0] = (freq_cw >> 0) & 0xff;
608 buf[1] = (freq_cw >> 8) & 0xff;
609 buf[2] = (freq_cw >> 16) & 0x7f;
611 /* FIXME: there seems to be calculation error here... */
612 if (if_frequency == 0)
615 ret = af9033_wr_regs(dev, 0x800029, buf, 3);
619 dev->bandwidth_hz = c->bandwidth_hz;
622 ret = af9033_wr_reg_mask(dev, 0x80f904, bandwidth_reg_val, 0x03);
626 ret = af9033_wr_reg(dev, 0x800040, 0x00);
630 ret = af9033_wr_reg(dev, 0x800047, 0x00);
634 ret = af9033_wr_reg_mask(dev, 0x80f999, 0x00, 0x01);
638 if (c->frequency <= 230000000)
639 tmp = 0x00; /* VHF */
641 tmp = 0x01; /* UHF */
643 ret = af9033_wr_reg(dev, 0x80004b, tmp);
647 ret = af9033_wr_reg(dev, 0x800000, 0x00);
654 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
659 static int af9033_get_frontend(struct dvb_frontend *fe)
661 struct af9033_dev *dev = fe->demodulator_priv;
662 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
666 dev_dbg(&dev->client->dev, "\n");
668 /* read all needed registers */
669 ret = af9033_rd_regs(dev, 0x80f900, buf, sizeof(buf));
673 switch ((buf[0] >> 0) & 3) {
675 c->transmission_mode = TRANSMISSION_MODE_2K;
678 c->transmission_mode = TRANSMISSION_MODE_8K;
682 switch ((buf[1] >> 0) & 3) {
684 c->guard_interval = GUARD_INTERVAL_1_32;
687 c->guard_interval = GUARD_INTERVAL_1_16;
690 c->guard_interval = GUARD_INTERVAL_1_8;
693 c->guard_interval = GUARD_INTERVAL_1_4;
697 switch ((buf[2] >> 0) & 7) {
699 c->hierarchy = HIERARCHY_NONE;
702 c->hierarchy = HIERARCHY_1;
705 c->hierarchy = HIERARCHY_2;
708 c->hierarchy = HIERARCHY_4;
712 switch ((buf[3] >> 0) & 3) {
714 c->modulation = QPSK;
717 c->modulation = QAM_16;
720 c->modulation = QAM_64;
724 switch ((buf[4] >> 0) & 3) {
726 c->bandwidth_hz = 6000000;
729 c->bandwidth_hz = 7000000;
732 c->bandwidth_hz = 8000000;
736 switch ((buf[6] >> 0) & 7) {
738 c->code_rate_HP = FEC_1_2;
741 c->code_rate_HP = FEC_2_3;
744 c->code_rate_HP = FEC_3_4;
747 c->code_rate_HP = FEC_5_6;
750 c->code_rate_HP = FEC_7_8;
753 c->code_rate_HP = FEC_NONE;
757 switch ((buf[7] >> 0) & 7) {
759 c->code_rate_LP = FEC_1_2;
762 c->code_rate_LP = FEC_2_3;
765 c->code_rate_LP = FEC_3_4;
768 c->code_rate_LP = FEC_5_6;
771 c->code_rate_LP = FEC_7_8;
774 c->code_rate_LP = FEC_NONE;
781 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
786 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status)
788 struct af9033_dev *dev = fe->demodulator_priv;
794 /* radio channel status, 0=no result, 1=has signal, 2=no signal */
795 ret = af9033_rd_reg(dev, 0x800047, &tmp);
801 *status |= FE_HAS_SIGNAL;
805 ret = af9033_rd_reg_mask(dev, 0x80f5a9, &tmp, 0x01);
810 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
814 ret = af9033_rd_reg_mask(dev, 0x80f999, &tmp, 0x01);
819 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
820 FE_HAS_VITERBI | FE_HAS_SYNC |
824 dev->fe_status = *status;
829 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
834 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
836 struct af9033_dev *dev = fe->demodulator_priv;
837 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
840 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
841 *snr = div_s64(c->cnr.stat[0].svalue, 100); /* 1000x => 10x */
848 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
850 struct af9033_dev *dev = fe->demodulator_priv;
854 /* read signal strength of 0-100 scale */
855 ret = af9033_rd_reg(dev, 0x800048, &strength2);
859 /* scale value to 0x0000-0xffff */
860 *strength = strength2 * 0xffff / 100;
865 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
870 static int af9033_update_ch_stat(struct af9033_dev *dev)
873 u32 err_cnt, bit_cnt;
877 /* only update data every half second */
878 if (time_after(jiffies, dev->last_stat_check + msecs_to_jiffies(500))) {
879 ret = af9033_rd_regs(dev, 0x800032, buf, sizeof(buf));
882 /* in 8 byte packets? */
883 abort_cnt = (buf[1] << 8) + buf[0];
885 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2];
886 /* in 8 byte packets? always(?) 0x2710 = 10000 */
887 bit_cnt = (buf[6] << 8) + buf[5];
889 if (bit_cnt < abort_cnt) {
891 dev->ber = 0xffffffff;
894 * 8 byte packets, that have not been rejected already
896 bit_cnt -= (u32)abort_cnt;
898 dev->ber = 0xffffffff;
900 err_cnt -= (u32)abort_cnt * 8 * 8;
902 dev->ber = err_cnt * (0xffffffff / bit_cnt);
905 dev->ucb += abort_cnt;
906 dev->last_stat_check = jiffies;
911 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
916 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
918 struct af9033_dev *dev = fe->demodulator_priv;
921 ret = af9033_update_ch_stat(dev);
930 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
932 struct af9033_dev *dev = fe->demodulator_priv;
935 ret = af9033_update_ch_stat(dev);
939 *ucblocks = dev->ucb;
944 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
946 struct af9033_dev *dev = fe->demodulator_priv;
949 dev_dbg(&dev->client->dev, "enable=%d\n", enable);
951 ret = af9033_wr_reg_mask(dev, 0x00fa04, enable, 0x01);
958 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
963 static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
965 struct af9033_dev *dev = fe->demodulator_priv;
968 dev_dbg(&dev->client->dev, "onoff=%d\n", onoff);
970 ret = af9033_wr_reg_mask(dev, 0x80f993, onoff, 0x01);
977 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
982 static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
985 struct af9033_dev *dev = fe->demodulator_priv;
987 u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
989 dev_dbg(&dev->client->dev, "index=%d pid=%04x onoff=%d\n",
995 ret = af9033_wr_regs(dev, 0x80f996, wbuf, 2);
999 ret = af9033_wr_reg(dev, 0x80f994, onoff);
1003 ret = af9033_wr_reg(dev, 0x80f995, index);
1010 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
1015 static void af9033_stat_work(struct work_struct *work)
1017 struct af9033_dev *dev = container_of(work, struct af9033_dev, stat_work.work);
1018 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
1019 int ret, tmp, i, len;
1022 dev_dbg(&dev->client->dev, "\n");
1024 /* signal strength */
1025 if (dev->fe_status & FE_HAS_SIGNAL) {
1026 if (dev->is_af9035) {
1027 ret = af9033_rd_reg(dev, 0x80004a, &u8tmp);
1028 tmp = -u8tmp * 1000;
1030 ret = af9033_rd_reg(dev, 0x8000f7, &u8tmp);
1031 tmp = (u8tmp - 100) * 1000;
1036 c->strength.len = 1;
1037 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1038 c->strength.stat[0].svalue = tmp;
1040 c->strength.len = 1;
1041 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1045 if (dev->fe_status & FE_HAS_VITERBI) {
1047 const struct val_snr *snr_lut;
1050 ret = af9033_rd_regs(dev, 0x80002c, buf, 3);
1054 snr_val = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0);
1056 /* read current modulation */
1057 ret = af9033_rd_reg(dev, 0x80f903, &u8tmp);
1061 switch ((u8tmp >> 0) & 3) {
1063 len = ARRAY_SIZE(qpsk_snr_lut);
1064 snr_lut = qpsk_snr_lut;
1067 len = ARRAY_SIZE(qam16_snr_lut);
1068 snr_lut = qam16_snr_lut;
1071 len = ARRAY_SIZE(qam64_snr_lut);
1072 snr_lut = qam64_snr_lut;
1075 goto err_schedule_delayed_work;
1078 for (i = 0; i < len; i++) {
1079 tmp = snr_lut[i].snr * 1000;
1080 if (snr_val < snr_lut[i].val)
1085 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1086 c->cnr.stat[0].svalue = tmp;
1089 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1093 if (dev->fe_status & FE_HAS_LOCK) {
1094 /* outer FEC, 204 byte packets */
1095 u16 abort_packet_count, rsd_packet_count;
1098 * Packet count used for measurement is 10000
1099 * (rsd_packet_count). Maybe it should be increased?
1102 ret = af9033_rd_regs(dev, 0x800032, buf, 7);
1106 abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
1107 rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
1109 dev->error_block_count += abort_packet_count;
1110 dev->total_block_count += rsd_packet_count;
1112 c->block_count.len = 1;
1113 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1114 c->block_count.stat[0].uvalue = dev->total_block_count;
1116 c->block_error.len = 1;
1117 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1118 c->block_error.stat[0].uvalue = dev->error_block_count;
1121 err_schedule_delayed_work:
1122 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
1125 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
1128 static struct dvb_frontend_ops af9033_ops = {
1129 .delsys = { SYS_DVBT },
1131 .name = "Afatech AF9033 (DVB-T)",
1132 .frequency_min = 174000000,
1133 .frequency_max = 862000000,
1134 .frequency_stepsize = 250000,
1135 .frequency_tolerance = 0,
1136 .caps = FE_CAN_FEC_1_2 |
1146 FE_CAN_TRANSMISSION_MODE_AUTO |
1147 FE_CAN_GUARD_INTERVAL_AUTO |
1148 FE_CAN_HIERARCHY_AUTO |
1153 .init = af9033_init,
1154 .sleep = af9033_sleep,
1156 .get_tune_settings = af9033_get_tune_settings,
1157 .set_frontend = af9033_set_frontend,
1158 .get_frontend = af9033_get_frontend,
1160 .read_status = af9033_read_status,
1161 .read_snr = af9033_read_snr,
1162 .read_signal_strength = af9033_read_signal_strength,
1163 .read_ber = af9033_read_ber,
1164 .read_ucblocks = af9033_read_ucblocks,
1166 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1169 static int af9033_probe(struct i2c_client *client,
1170 const struct i2c_device_id *id)
1172 struct af9033_config *cfg = client->dev.platform_data;
1173 struct af9033_dev *dev;
1178 /* allocate memory for the internal state */
1179 dev = kzalloc(sizeof(struct af9033_dev), GFP_KERNEL);
1182 dev_err(&client->dev, "Could not allocate memory for state\n");
1186 /* setup the state */
1187 dev->client = client;
1188 INIT_DELAYED_WORK(&dev->stat_work, af9033_stat_work);
1189 memcpy(&dev->cfg, cfg, sizeof(struct af9033_config));
1191 if (dev->cfg.clock != 12000000) {
1193 dev_err(&dev->client->dev,
1194 "unsupported clock %d Hz, only 12000000 Hz is supported currently\n",
1199 /* firmware version */
1200 switch (dev->cfg.tuner) {
1201 case AF9033_TUNER_IT9135_38:
1202 case AF9033_TUNER_IT9135_51:
1203 case AF9033_TUNER_IT9135_52:
1204 case AF9033_TUNER_IT9135_60:
1205 case AF9033_TUNER_IT9135_61:
1206 case AF9033_TUNER_IT9135_62:
1207 dev->is_it9135 = true;
1211 dev->is_af9035 = true;
1216 ret = af9033_rd_regs(dev, reg, &buf[0], 4);
1220 ret = af9033_rd_regs(dev, 0x804191, &buf[4], 4);
1224 dev_info(&dev->client->dev,
1225 "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
1226 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
1230 switch (dev->cfg.tuner) {
1231 case AF9033_TUNER_IT9135_38:
1232 case AF9033_TUNER_IT9135_51:
1233 case AF9033_TUNER_IT9135_52:
1234 case AF9033_TUNER_IT9135_60:
1235 case AF9033_TUNER_IT9135_61:
1236 case AF9033_TUNER_IT9135_62:
1237 /* IT9135 did not like to sleep at that early */
1240 ret = af9033_wr_reg(dev, 0x80004c, 1);
1244 ret = af9033_wr_reg(dev, 0x800000, 0);
1249 /* configure internal TS mode */
1250 switch (dev->cfg.ts_mode) {
1251 case AF9033_TS_MODE_PARALLEL:
1252 dev->ts_mode_parallel = true;
1254 case AF9033_TS_MODE_SERIAL:
1255 dev->ts_mode_serial = true;
1257 case AF9033_TS_MODE_USB:
1258 /* usb mode for AF9035 */
1263 /* create dvb_frontend */
1264 memcpy(&dev->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops));
1265 dev->fe.demodulator_priv = dev;
1266 *cfg->fe = &dev->fe;
1268 cfg->ops->pid_filter = af9033_pid_filter;
1269 cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
1271 i2c_set_clientdata(client, dev);
1273 dev_info(&dev->client->dev, "Afatech AF9033 successfully attached\n");
1278 dev_dbg(&client->dev, "failed=%d\n", ret);
1282 static int af9033_remove(struct i2c_client *client)
1284 struct af9033_dev *dev = i2c_get_clientdata(client);
1286 dev_dbg(&dev->client->dev, "\n");
1288 dev->fe.ops.release = NULL;
1289 dev->fe.demodulator_priv = NULL;
1295 static const struct i2c_device_id af9033_id_table[] = {
1299 MODULE_DEVICE_TABLE(i2c, af9033_id_table);
1301 static struct i2c_driver af9033_driver = {
1303 .owner = THIS_MODULE,
1306 .probe = af9033_probe,
1307 .remove = af9033_remove,
1308 .id_table = af9033_id_table,
1311 module_i2c_driver(af9033_driver);
1313 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1314 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1315 MODULE_LICENSE("GPL");