2 * Afatech AF9033 demodulator driver
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include "af9033_priv.h"
21 struct i2c_client *client;
22 struct regmap *regmap;
23 struct dvb_frontend fe;
24 struct af9033_config cfg;
29 bool ts_mode_parallel;
32 enum fe_status fe_status;
33 u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */
36 u64 error_block_count;
37 u64 total_block_count;
40 /* Write reg val table using reg addr auto increment */
41 static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
42 const struct reg_val *tab, int tab_len)
44 struct i2c_client *client = dev->client;
45 #define MAX_TAB_LEN 212
47 u8 buf[1 + MAX_TAB_LEN];
49 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
51 if (tab_len > sizeof(buf)) {
52 dev_warn(&client->dev, "tab len %d is too big\n", tab_len);
56 for (i = 0, j = 0; i < tab_len; i++) {
59 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
60 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j,
73 dev_dbg(&client->dev, "failed=%d\n", ret);
77 static int af9033_init(struct dvb_frontend *fe)
79 struct af9033_dev *dev = fe->demodulator_priv;
80 struct i2c_client *client = dev->client;
81 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
84 const struct reg_val *init;
86 struct reg_val_mask tab[] = {
87 { 0x80fb24, 0x00, 0x08 },
88 { 0x80004c, 0x00, 0xff },
89 { 0x00f641, dev->cfg.tuner, 0xff },
90 { 0x80f5ca, 0x01, 0x01 },
91 { 0x80f715, 0x01, 0x01 },
92 { 0x00f41f, 0x04, 0x04 },
93 { 0x00f41a, 0x01, 0x01 },
94 { 0x80f731, 0x00, 0x01 },
95 { 0x00d91e, 0x00, 0x01 },
96 { 0x00d919, 0x00, 0x01 },
97 { 0x80f732, 0x00, 0x01 },
98 { 0x00d91f, 0x00, 0x01 },
99 { 0x00d91a, 0x00, 0x01 },
100 { 0x80f730, 0x00, 0x01 },
101 { 0x80f778, 0x00, 0xff },
102 { 0x80f73c, 0x01, 0x01 },
103 { 0x80f776, 0x00, 0x01 },
104 { 0x00d8fd, 0x01, 0xff },
105 { 0x00d830, 0x01, 0xff },
106 { 0x00d831, 0x00, 0xff },
107 { 0x00d832, 0x00, 0xff },
108 { 0x80f985, dev->ts_mode_serial, 0x01 },
109 { 0x80f986, dev->ts_mode_parallel, 0x01 },
110 { 0x00d827, 0x00, 0xff },
111 { 0x00d829, 0x00, 0xff },
112 { 0x800045, dev->cfg.adc_multiplier, 0xff },
115 dev_dbg(&client->dev, "\n");
117 /* Main clk control */
118 utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000);
119 buf[0] = (utmp >> 0) & 0xff;
120 buf[1] = (utmp >> 8) & 0xff;
121 buf[2] = (utmp >> 16) & 0xff;
122 buf[3] = (utmp >> 24) & 0xff;
123 ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4);
127 dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp);
129 /* ADC clk control */
130 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
131 if (clock_adc_lut[i].clock == dev->cfg.clock)
134 if (i == ARRAY_SIZE(clock_adc_lut)) {
135 dev_err(&client->dev, "Couldn't find ADC config for clock %d\n",
140 utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000);
141 buf[0] = (utmp >> 0) & 0xff;
142 buf[1] = (utmp >> 8) & 0xff;
143 buf[2] = (utmp >> 16) & 0xff;
144 ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3);
148 dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n",
149 clock_adc_lut[i].adc, utmp);
151 /* Config register table */
152 for (i = 0; i < ARRAY_SIZE(tab); i++) {
153 ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask,
159 /* Demod clk output */
160 if (dev->cfg.dyn0_clk) {
161 ret = regmap_write(dev->regmap, 0x80fba8, 0x00);
167 if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
168 ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00);
171 ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01);
175 ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00);
178 ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00);
183 /* Demod core settings */
184 dev_dbg(&client->dev, "load ofsm settings\n");
185 switch (dev->cfg.tuner) {
186 case AF9033_TUNER_IT9135_38:
187 case AF9033_TUNER_IT9135_51:
188 case AF9033_TUNER_IT9135_52:
189 len = ARRAY_SIZE(ofsm_init_it9135_v1);
190 init = ofsm_init_it9135_v1;
192 case AF9033_TUNER_IT9135_60:
193 case AF9033_TUNER_IT9135_61:
194 case AF9033_TUNER_IT9135_62:
195 len = ARRAY_SIZE(ofsm_init_it9135_v2);
196 init = ofsm_init_it9135_v2;
199 len = ARRAY_SIZE(ofsm_init);
204 ret = af9033_wr_reg_val_tab(dev, init, len);
208 /* Demod tuner specific settings */
209 dev_dbg(&client->dev, "load tuner specific settings\n");
210 switch (dev->cfg.tuner) {
211 case AF9033_TUNER_TUA9001:
212 len = ARRAY_SIZE(tuner_init_tua9001);
213 init = tuner_init_tua9001;
215 case AF9033_TUNER_FC0011:
216 len = ARRAY_SIZE(tuner_init_fc0011);
217 init = tuner_init_fc0011;
219 case AF9033_TUNER_MXL5007T:
220 len = ARRAY_SIZE(tuner_init_mxl5007t);
221 init = tuner_init_mxl5007t;
223 case AF9033_TUNER_TDA18218:
224 len = ARRAY_SIZE(tuner_init_tda18218);
225 init = tuner_init_tda18218;
227 case AF9033_TUNER_FC2580:
228 len = ARRAY_SIZE(tuner_init_fc2580);
229 init = tuner_init_fc2580;
231 case AF9033_TUNER_FC0012:
232 len = ARRAY_SIZE(tuner_init_fc0012);
233 init = tuner_init_fc0012;
235 case AF9033_TUNER_IT9135_38:
236 len = ARRAY_SIZE(tuner_init_it9135_38);
237 init = tuner_init_it9135_38;
239 case AF9033_TUNER_IT9135_51:
240 len = ARRAY_SIZE(tuner_init_it9135_51);
241 init = tuner_init_it9135_51;
243 case AF9033_TUNER_IT9135_52:
244 len = ARRAY_SIZE(tuner_init_it9135_52);
245 init = tuner_init_it9135_52;
247 case AF9033_TUNER_IT9135_60:
248 len = ARRAY_SIZE(tuner_init_it9135_60);
249 init = tuner_init_it9135_60;
251 case AF9033_TUNER_IT9135_61:
252 len = ARRAY_SIZE(tuner_init_it9135_61);
253 init = tuner_init_it9135_61;
255 case AF9033_TUNER_IT9135_62:
256 len = ARRAY_SIZE(tuner_init_it9135_62);
257 init = tuner_init_it9135_62;
260 dev_dbg(&client->dev, "unsupported tuner ID=%d\n",
266 ret = af9033_wr_reg_val_tab(dev, init, len);
270 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
271 ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01);
274 ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
277 ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00);
282 switch (dev->cfg.tuner) {
283 case AF9033_TUNER_IT9135_60:
284 case AF9033_TUNER_IT9135_61:
285 case AF9033_TUNER_IT9135_62:
286 ret = regmap_write(dev->regmap, 0x800000, 0x01);
291 dev->bandwidth_hz = 0; /* Force to program all parameters */
292 /* Init stats here in order signal app which stats are supported */
294 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
296 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
297 c->block_count.len = 1;
298 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
299 c->block_error.len = 1;
300 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
301 c->post_bit_count.len = 1;
302 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
303 c->post_bit_error.len = 1;
304 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
308 dev_dbg(&client->dev, "failed=%d\n", ret);
312 static int af9033_sleep(struct dvb_frontend *fe)
314 struct af9033_dev *dev = fe->demodulator_priv;
315 struct i2c_client *client = dev->client;
319 dev_dbg(&client->dev, "\n");
321 ret = regmap_write(dev->regmap, 0x80004c, 0x01);
324 ret = regmap_write(dev->regmap, 0x800000, 0x00);
327 ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0,
331 ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08);
335 /* Prevent current leak by setting TS interface to parallel mode */
336 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
337 /* Enable parallel TS */
338 ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
341 ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01);
348 dev_dbg(&client->dev, "failed=%d\n", ret);
352 static int af9033_get_tune_settings(struct dvb_frontend *fe,
353 struct dvb_frontend_tune_settings *fesettings)
355 /* 800 => 2000 because IT9135 v2 is slow to gain lock */
356 fesettings->min_delay_ms = 2000;
357 fesettings->step_size = 0;
358 fesettings->max_drift = 0;
363 static int af9033_set_frontend(struct dvb_frontend *fe)
365 struct af9033_dev *dev = fe->demodulator_priv;
366 struct i2c_client *client = dev->client;
367 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
369 unsigned int utmp, adc_freq;
370 u8 tmp, buf[3], bandwidth_reg_val;
373 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n",
374 c->frequency, c->bandwidth_hz);
376 /* Check bandwidth */
377 switch (c->bandwidth_hz) {
379 bandwidth_reg_val = 0x00;
382 bandwidth_reg_val = 0x01;
385 bandwidth_reg_val = 0x02;
388 dev_dbg(&client->dev, "invalid bandwidth_hz\n");
394 if (fe->ops.tuner_ops.set_params)
395 fe->ops.tuner_ops.set_params(fe);
398 if (c->bandwidth_hz != dev->bandwidth_hz) {
399 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
400 if (coeff_lut[i].clock == dev->cfg.clock &&
401 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
405 if (i == ARRAY_SIZE(coeff_lut)) {
406 dev_err(&client->dev,
407 "Couldn't find config for clock %u\n",
413 ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val,
414 sizeof(coeff_lut[i].val));
419 /* IF frequency control */
420 if (c->bandwidth_hz != dev->bandwidth_hz) {
421 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
422 if (clock_adc_lut[i].clock == dev->cfg.clock)
425 if (i == ARRAY_SIZE(clock_adc_lut)) {
426 dev_err(&client->dev,
427 "Couldn't find ADC clock for clock %u\n",
432 adc_freq = clock_adc_lut[i].adc;
434 if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
435 adc_freq = 2 * adc_freq;
437 /* Get used IF frequency */
438 if (fe->ops.tuner_ops.get_if_frequency)
439 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
443 utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000,
446 if (!dev->cfg.spec_inv && if_frequency)
447 utmp = 0x800000 - utmp;
449 buf[0] = (utmp >> 0) & 0xff;
450 buf[1] = (utmp >> 8) & 0xff;
451 buf[2] = (utmp >> 16) & 0xff;
452 ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3);
456 dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp);
458 dev->bandwidth_hz = c->bandwidth_hz;
461 ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03,
465 ret = regmap_write(dev->regmap, 0x800040, 0x00);
468 ret = regmap_write(dev->regmap, 0x800047, 0x00);
471 ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00);
475 if (c->frequency <= 230000000)
476 tmp = 0x00; /* VHF */
478 tmp = 0x01; /* UHF */
480 ret = regmap_write(dev->regmap, 0x80004b, tmp);
484 ret = regmap_write(dev->regmap, 0x800000, 0x00);
490 dev_dbg(&client->dev, "failed=%d\n", ret);
494 static int af9033_get_frontend(struct dvb_frontend *fe,
495 struct dtv_frontend_properties *c)
497 struct af9033_dev *dev = fe->demodulator_priv;
498 struct i2c_client *client = dev->client;
502 dev_dbg(&client->dev, "\n");
504 /* Read all needed TPS registers */
505 ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8);
509 switch ((buf[0] >> 0) & 3) {
511 c->transmission_mode = TRANSMISSION_MODE_2K;
514 c->transmission_mode = TRANSMISSION_MODE_8K;
518 switch ((buf[1] >> 0) & 3) {
520 c->guard_interval = GUARD_INTERVAL_1_32;
523 c->guard_interval = GUARD_INTERVAL_1_16;
526 c->guard_interval = GUARD_INTERVAL_1_8;
529 c->guard_interval = GUARD_INTERVAL_1_4;
533 switch ((buf[2] >> 0) & 7) {
535 c->hierarchy = HIERARCHY_NONE;
538 c->hierarchy = HIERARCHY_1;
541 c->hierarchy = HIERARCHY_2;
544 c->hierarchy = HIERARCHY_4;
548 switch ((buf[3] >> 0) & 3) {
550 c->modulation = QPSK;
553 c->modulation = QAM_16;
556 c->modulation = QAM_64;
560 switch ((buf[4] >> 0) & 3) {
562 c->bandwidth_hz = 6000000;
565 c->bandwidth_hz = 7000000;
568 c->bandwidth_hz = 8000000;
572 switch ((buf[6] >> 0) & 7) {
574 c->code_rate_HP = FEC_1_2;
577 c->code_rate_HP = FEC_2_3;
580 c->code_rate_HP = FEC_3_4;
583 c->code_rate_HP = FEC_5_6;
586 c->code_rate_HP = FEC_7_8;
589 c->code_rate_HP = FEC_NONE;
593 switch ((buf[7] >> 0) & 7) {
595 c->code_rate_LP = FEC_1_2;
598 c->code_rate_LP = FEC_2_3;
601 c->code_rate_LP = FEC_3_4;
604 c->code_rate_LP = FEC_5_6;
607 c->code_rate_LP = FEC_7_8;
610 c->code_rate_LP = FEC_NONE;
616 dev_dbg(&client->dev, "failed=%d\n", ret);
620 static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status)
622 struct af9033_dev *dev = fe->demodulator_priv;
623 struct i2c_client *client = dev->client;
624 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
627 unsigned int utmp, utmp1;
629 dev_dbg(&client->dev, "\n");
633 /* Radio channel status: 0=no result, 1=has signal, 2=no signal */
634 ret = regmap_read(dev->regmap, 0x800047, &utmp);
640 *status |= FE_HAS_SIGNAL;
644 ret = regmap_read(dev->regmap, 0x80f5a9, &utmp);
648 if ((utmp >> 0) & 0x01)
649 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
653 ret = regmap_read(dev->regmap, 0x80f999, &utmp);
657 if ((utmp >> 0) & 0x01)
658 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
659 FE_HAS_VITERBI | FE_HAS_SYNC |
663 dev->fe_status = *status;
665 /* Signal strength */
666 if (dev->fe_status & FE_HAS_SIGNAL) {
667 if (dev->is_af9035) {
668 ret = regmap_read(dev->regmap, 0x80004a, &utmp);
673 ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
676 tmp = (utmp - 100) * 1000;
680 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
681 c->strength.stat[0].svalue = tmp;
684 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
688 if (dev->fe_status & FE_HAS_VITERBI) {
689 /* Read raw SNR value */
690 ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3);
694 utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
696 /* Read superframe number */
697 ret = regmap_read(dev->regmap, 0x80f78b, &utmp);
704 /* Read current transmission mode */
705 ret = regmap_read(dev->regmap, 0x80f900, &utmp);
709 switch ((utmp >> 0) & 3) {
727 /* Read current modulation */
728 ret = regmap_read(dev->regmap, 0x80f903, &utmp);
732 switch ((utmp >> 0) & 3) {
736 * CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
737 * value [653799, 1689999], 2.6 / 13 = 3355443
739 utmp1 = clamp(utmp1, 653799U, 1689999U);
740 utmp1 = ((u64)(intlog10(utmp1)
741 - intlog10(1690000 - utmp1)
742 + 3355443) * 13 * 1000) >> 24;
747 * CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
748 * value [371105, 827999], 15.7 / 6 = 43900382
750 utmp1 = clamp(utmp1, 371105U, 827999U);
751 utmp1 = ((u64)(intlog10(utmp1 - 370000)
752 - intlog10(828000 - utmp1)
753 + 43900382) * 6 * 1000) >> 24;
758 * CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
759 * value [193246, 424999], 23.8 / 8 = 49912218
761 utmp1 = clamp(utmp1, 193246U, 424999U);
762 utmp1 = ((u64)(intlog10(utmp1 - 193000)
763 - intlog10(425000 - utmp1)
764 + 49912218) * 8 * 1000) >> 24;
771 dev_dbg(&client->dev, "cnr=%u\n", utmp1);
773 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
774 c->cnr.stat[0].svalue = utmp1;
776 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
780 if (dev->fe_status & FE_HAS_LOCK) {
781 /* Outer FEC, 204 byte packets */
782 u16 abort_packet_count, rsd_packet_count;
783 /* Inner FEC, bits */
784 u32 rsd_bit_err_count;
787 * Packet count used for measurement is 10000
788 * (rsd_packet_count). Maybe it should be increased?
791 ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7);
795 abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
796 rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2];
797 rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
799 dev->error_block_count += abort_packet_count;
800 dev->total_block_count += rsd_packet_count;
801 dev->post_bit_error += rsd_bit_err_count;
802 dev->post_bit_count += rsd_packet_count * 204 * 8;
804 c->block_count.len = 1;
805 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
806 c->block_count.stat[0].uvalue = dev->total_block_count;
808 c->block_error.len = 1;
809 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
810 c->block_error.stat[0].uvalue = dev->error_block_count;
812 c->post_bit_count.len = 1;
813 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
814 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
816 c->post_bit_error.len = 1;
817 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
818 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
823 dev_dbg(&client->dev, "failed=%d\n", ret);
827 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
829 struct af9033_dev *dev = fe->demodulator_priv;
830 struct i2c_client *client = dev->client;
831 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
835 dev_dbg(&client->dev, "\n");
838 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) {
839 /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */
840 if (dev->is_af9035) {
841 /* 1000x => 10x (0.1 dB) */
842 *snr = div_s64(c->cnr.stat[0].svalue, 100);
844 /* 1000x => 1x (1 dB) */
845 *snr = div_s64(c->cnr.stat[0].svalue, 1000);
847 /* Read current modulation */
848 ret = regmap_read(dev->regmap, 0x80f903, &utmp);
852 /* scale value to 0x0000-0xffff */
853 switch ((utmp >> 0) & 3) {
855 *snr = *snr * 0xffff / 23;
858 *snr = *snr * 0xffff / 26;
861 *snr = *snr * 0xffff / 32;
873 dev_dbg(&client->dev, "failed=%d\n", ret);
877 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
879 struct af9033_dev *dev = fe->demodulator_priv;
880 struct i2c_client *client = dev->client;
881 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
882 int ret, tmp, power_real;
884 u8 gain_offset, buf[7];
886 dev_dbg(&client->dev, "\n");
888 if (dev->is_af9035) {
889 /* Read signal strength of 0-100 scale */
890 ret = regmap_read(dev->regmap, 0x800048, &utmp);
894 /* Scale value to 0x0000-0xffff */
895 *strength = utmp * 0xffff / 100;
897 ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
901 ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7);
905 if (c->frequency <= 300000000)
906 gain_offset = 7; /* VHF */
908 gain_offset = 4; /* UHF */
910 power_real = (utmp - 100 - gain_offset) -
911 power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)];
913 if (power_real < -15)
915 else if ((power_real >= -15) && (power_real < 0))
916 tmp = (2 * (power_real + 15)) / 3;
917 else if ((power_real >= 0) && (power_real < 20))
918 tmp = 4 * power_real + 10;
919 else if ((power_real >= 20) && (power_real < 35))
920 tmp = (2 * (power_real - 20)) / 3 + 90;
924 /* Scale value to 0x0000-0xffff */
925 *strength = tmp * 0xffff / 100;
930 dev_dbg(&client->dev, "failed=%d\n", ret);
934 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
936 struct af9033_dev *dev = fe->demodulator_priv;
938 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
939 dev->post_bit_error_prev = dev->post_bit_error;
944 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
946 struct af9033_dev *dev = fe->demodulator_priv;
948 *ucblocks = dev->error_block_count;
953 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
955 struct af9033_dev *dev = fe->demodulator_priv;
956 struct i2c_client *client = dev->client;
959 dev_dbg(&client->dev, "enable=%d\n", enable);
961 ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable);
967 dev_dbg(&client->dev, "failed=%d\n", ret);
971 static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
973 struct af9033_dev *dev = fe->demodulator_priv;
974 struct i2c_client *client = dev->client;
977 dev_dbg(&client->dev, "onoff=%d\n", onoff);
979 ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff);
985 dev_dbg(&client->dev, "failed=%d\n", ret);
989 static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
992 struct af9033_dev *dev = fe->demodulator_priv;
993 struct i2c_client *client = dev->client;
995 u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
997 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
1003 ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2);
1006 ret = regmap_write(dev->regmap, 0x80f994, onoff);
1009 ret = regmap_write(dev->regmap, 0x80f995, index);
1015 dev_dbg(&client->dev, "failed=%d\n", ret);
1019 static const struct dvb_frontend_ops af9033_ops = {
1020 .delsys = {SYS_DVBT},
1022 .name = "Afatech AF9033 (DVB-T)",
1023 .frequency_min = 174000000,
1024 .frequency_max = 862000000,
1025 .frequency_stepsize = 250000,
1026 .frequency_tolerance = 0,
1027 .caps = FE_CAN_FEC_1_2 |
1037 FE_CAN_TRANSMISSION_MODE_AUTO |
1038 FE_CAN_GUARD_INTERVAL_AUTO |
1039 FE_CAN_HIERARCHY_AUTO |
1044 .init = af9033_init,
1045 .sleep = af9033_sleep,
1047 .get_tune_settings = af9033_get_tune_settings,
1048 .set_frontend = af9033_set_frontend,
1049 .get_frontend = af9033_get_frontend,
1051 .read_status = af9033_read_status,
1052 .read_snr = af9033_read_snr,
1053 .read_signal_strength = af9033_read_signal_strength,
1054 .read_ber = af9033_read_ber,
1055 .read_ucblocks = af9033_read_ucblocks,
1057 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1060 static int af9033_probe(struct i2c_client *client,
1061 const struct i2c_device_id *id)
1063 struct af9033_config *cfg = client->dev.platform_data;
1064 struct af9033_dev *dev;
1068 static const struct regmap_config regmap_config = {
1073 /* Allocate memory for the internal state */
1074 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1080 /* Setup the state */
1081 dev->client = client;
1082 memcpy(&dev->cfg, cfg, sizeof(dev->cfg));
1083 switch (dev->cfg.ts_mode) {
1084 case AF9033_TS_MODE_PARALLEL:
1085 dev->ts_mode_parallel = true;
1087 case AF9033_TS_MODE_SERIAL:
1088 dev->ts_mode_serial = true;
1090 case AF9033_TS_MODE_USB:
1091 /* USB mode for AF9035 */
1096 if (dev->cfg.clock != 12000000) {
1098 dev_err(&client->dev,
1099 "Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n",
1105 dev->regmap = regmap_init_i2c(client, ®map_config);
1106 if (IS_ERR(dev->regmap)) {
1107 ret = PTR_ERR(dev->regmap);
1111 /* Firmware version */
1112 switch (dev->cfg.tuner) {
1113 case AF9033_TUNER_IT9135_38:
1114 case AF9033_TUNER_IT9135_51:
1115 case AF9033_TUNER_IT9135_52:
1116 case AF9033_TUNER_IT9135_60:
1117 case AF9033_TUNER_IT9135_61:
1118 case AF9033_TUNER_IT9135_62:
1119 dev->is_it9135 = true;
1123 dev->is_af9035 = true;
1128 ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4);
1130 goto err_regmap_exit;
1131 ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4);
1133 goto err_regmap_exit;
1135 dev_info(&client->dev,
1136 "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
1137 buf[0], buf[1], buf[2], buf[3],
1138 buf[4], buf[5], buf[6], buf[7]);
1140 /* Sleep as chip seems to be partly active by default */
1141 switch (dev->cfg.tuner) {
1142 case AF9033_TUNER_IT9135_38:
1143 case AF9033_TUNER_IT9135_51:
1144 case AF9033_TUNER_IT9135_52:
1145 case AF9033_TUNER_IT9135_60:
1146 case AF9033_TUNER_IT9135_61:
1147 case AF9033_TUNER_IT9135_62:
1148 /* IT9135 did not like to sleep at that early */
1151 ret = regmap_write(dev->regmap, 0x80004c, 0x01);
1153 goto err_regmap_exit;
1154 ret = regmap_write(dev->regmap, 0x800000, 0x00);
1156 goto err_regmap_exit;
1159 /* Create dvb frontend */
1160 memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops));
1161 dev->fe.demodulator_priv = dev;
1162 *cfg->fe = &dev->fe;
1164 cfg->ops->pid_filter = af9033_pid_filter;
1165 cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
1167 cfg->regmap = dev->regmap;
1168 i2c_set_clientdata(client, dev);
1170 dev_info(&client->dev, "Afatech AF9033 successfully attached\n");
1174 regmap_exit(dev->regmap);
1178 dev_dbg(&client->dev, "failed=%d\n", ret);
1182 static int af9033_remove(struct i2c_client *client)
1184 struct af9033_dev *dev = i2c_get_clientdata(client);
1186 dev_dbg(&client->dev, "\n");
1188 regmap_exit(dev->regmap);
1194 static const struct i2c_device_id af9033_id_table[] = {
1198 MODULE_DEVICE_TABLE(i2c, af9033_id_table);
1200 static struct i2c_driver af9033_driver = {
1203 .suppress_bind_attrs = true,
1205 .probe = af9033_probe,
1206 .remove = af9033_remove,
1207 .id_table = af9033_id_table,
1210 module_i2c_driver(af9033_driver);
1212 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1213 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1214 MODULE_LICENSE("GPL");