drivers/media/dvb-frontends/cxd2841er.c

   1 /*
   2  * cxd2841er.c
   3  *
   4  * Sony digital demodulator driver for
   5  *      CXD2441ER - DVB-S/S2/T/T2/C/C2
   6  *      CXD2454ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   7  *
   8  * Copyright 2012 Sony Corporation
   9  * Copyright (C) 2014 NetUP Inc.
  10  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  11  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22   */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/bitops.h>
  29 #include <linux/math64.h>
  30 #include <linux/log2.h>
  31 #include <linux/dynamic_debug.h>
  32
  33 #include "dvb_math.h"
  34 #include "dvb_frontend.h"
  35 #include "cxd2841er.h"
  36 #include "cxd2841er_priv.h"
  37
  38 #define MAX_WRITE_REGSIZE       16
  39
  40 enum cxd2841er_state {
  41         STATE_SHUTDOWN = 0,
  42         STATE_SLEEP_S,
  43         STATE_ACTIVE_S,
  44         STATE_SLEEP_TC,
  45         STATE_ACTIVE_TC
  46 };
  47
  48 struct cxd2841er_priv {
  49         struct dvb_frontend             frontend;
  50         struct i2c_adapter              *i2c;
  51         u8                              i2c_addr_slvx;
  52         u8                              i2c_addr_slvt;
  53         const struct cxd2841er_config   *config;
  54         enum cxd2841er_state            state;
  55         u8                              system;
  56         enum cxd2841er_xtal             xtal;
  57 };
  58
  59 static const struct cxd2841er_cnr_data s_cn_data[] = {
  60         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  61         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  62         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  63         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  64         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  65         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  66         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  67         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  68         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  69         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  70         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  71         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  72         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  73         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  74         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  75         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  76         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  77         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  78         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  79         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  80         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  81         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  82         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  83         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  84         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  85         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
  86         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
  87         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
  88         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
  89         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
  90         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
  91         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
  92         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
  93         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
  94         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
  95         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
  96         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
  97         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
  98         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
  99         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 100         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 101         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 102         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 103         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 104         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 105         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 106         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 107         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 108         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 109         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 110         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 111         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 112         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 113         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 114         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 115         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 116         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 117         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 118         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 119         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 120         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 121         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 122         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 123         { 0x0015, 19900 }, { 0x0014, 20000 },
 124 };
 125
 126 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 127         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 128         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 129         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 130         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 131         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 132         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 133         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 134         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 135         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 136         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 137         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 138         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 139         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 140         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 141         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 142         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 143         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 144         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 145         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 146         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 147         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 148         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 149         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 150         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 151         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 152         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 153         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 154         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 155         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 156         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 157         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 158         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 159         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 160         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 161         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 162         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 163         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 164         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 165         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 166         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 167         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 168         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 169         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 170         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 171         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 172         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 173         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 174         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 175         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 176         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 177         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 178         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 179         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 180         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 181         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 182         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 183         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 184         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 185         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 186         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 187         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 188         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 189         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 190         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 191 };
 192
 193 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 194 #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
 195                 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
 196                 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 197
 198 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 199                                 u8 addr, u8 reg, u8 write,
 200                                 const u8 *data, u32 len)
 201 {
 202         dev_dbg(&priv->i2c->dev,
 203                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
 204                 (write == 0 ? "read" : "write"), addr, reg, len);
 205         print_hex_dump_bytes("cxd2841er: I2C data: ",
 206                 DUMP_PREFIX_OFFSET, data, len);
 207 }
 208
 209 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 210                                 u8 addr, u8 reg, const u8 *data, u32 len)
 211 {
 212         int ret;
 213         u8 buf[MAX_WRITE_REGSIZE + 1];
 214         u8 i2c_addr = (addr == I2C_SLVX ?
 215                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 216         struct i2c_msg msg[1] = {
 217                 {
 218                         .addr = i2c_addr,
 219                         .flags = 0,
 220                         .len = len + 1,
 221                         .buf = buf,
 222                 }
 223         };
 224
 225         if (len + 1 >= sizeof(buf)) {
 226                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 227                          reg, len + 1);
 228                 return -E2BIG;
 229         }
 230
 231         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 232         buf[0] = reg;
 233         memcpy(&buf[1], data, len);
 234
 235         ret = i2c_transfer(priv->i2c, msg, 1);
 236         if (ret >= 0 && ret != 1)
 237                 ret = -EIO;
 238         if (ret < 0) {
 239                 dev_warn(&priv->i2c->dev,
 240                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 241                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 242                 return ret;
 243         }
 244         return 0;
 245 }
 246
 247 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 248                                u8 addr, u8 reg, u8 val)
 249 {
 250         return cxd2841er_write_regs(priv, addr, reg, &val, 1);
 251 }
 252
 253 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 254                                u8 addr, u8 reg, u8 *val, u32 len)
 255 {
 256         int ret;
 257         u8 i2c_addr = (addr == I2C_SLVX ?
 258                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 259         struct i2c_msg msg[2] = {
 260                 {
 261                         .addr = i2c_addr,
 262                         .flags = 0,
 263                         .len = 1,
 264                         .buf = &reg,
 265                 }, {
 266                         .addr = i2c_addr,
 267                         .flags = I2C_M_RD,
 268                         .len = len,
 269                         .buf = val,
 270                 }
 271         };
 272
 273         ret = i2c_transfer(priv->i2c, &msg[0], 1);
 274         if (ret >= 0 && ret != 1)
 275                 ret = -EIO;
 276         if (ret < 0) {
 277                 dev_warn(&priv->i2c->dev,
 278                         "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
 279                         KBUILD_MODNAME, ret, i2c_addr, reg);
 280                 return ret;
 281         }
 282         ret = i2c_transfer(priv->i2c, &msg[1], 1);
 283         if (ret >= 0 && ret != 1)
 284                 ret = -EIO;
 285         if (ret < 0) {
 286                 dev_warn(&priv->i2c->dev,
 287                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 288                         KBUILD_MODNAME, ret, i2c_addr, reg);
 289                 return ret;
 290         }
 291         return 0;
 292 }
 293
 294 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 295                               u8 addr, u8 reg, u8 *val)
 296 {
 297         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 298 }
 299
 300 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 301                                   u8 addr, u8 reg, u8 data, u8 mask)
 302 {
 303         int res;
 304         u8 rdata;
 305
 306         if (mask != 0xff) {
 307                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 308                 if (res)
 309                         return res;
 310                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 311         }
 312         return cxd2841er_write_reg(priv, addr, reg, data);
 313 }
 314
 315 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 316                                            u32 symbol_rate)
 317 {
 318         u32 reg_value = 0;
 319         u8 data[3] = {0, 0, 0};
 320
 321         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 322         /*
 323          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 324          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 325          *          = ((symbolRateKSps * 16384) + 500) / 1000
 326          */
 327         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 328         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 329                 dev_err(&priv->i2c->dev,
 330                         "%s(): reg_value is out of range\n", __func__);
 331                 return -EINVAL;
 332         }
 333         data[0] = (u8)((reg_value >> 16) & 0x0F);
 334         data[1] = (u8)((reg_value >>  8) & 0xFF);
 335         data[2] = (u8)(reg_value & 0xFF);
 336         /* Set SLV-T Bank : 0xAE */
 337         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 338         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 339         return 0;
 340 }
 341
 342 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 343                                         u8 system);
 344
 345 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 346                                          u8 system, u32 symbol_rate)
 347 {
 348         int ret;
 349         u8 data[4] = { 0, 0, 0, 0 };
 350
 351         if (priv->state != STATE_SLEEP_S) {
 352                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 353                         __func__, (int)priv->state);
 354                 return -EINVAL;
 355         }
 356         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 357         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 358         /* Set demod mode */
 359         if (system == SYS_DVBS) {
 360                 data[0] = 0x0A;
 361         } else if (system == SYS_DVBS2) {
 362                 data[0] = 0x0B;
 363         } else {
 364                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 365                         __func__, system);
 366                 return -EINVAL;
 367         }
 368         /* Set SLV-X Bank : 0x00 */
 369         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 370         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 371         /* DVB-S/S2 */
 372         data[0] = 0x00;
 373         /* Set SLV-T Bank : 0x00 */
 374         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 375         /* Enable S/S2 auto detection 1 */
 376         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 377         /* Set SLV-T Bank : 0xAE */
 378         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 379         /* Enable S/S2 auto detection 2 */
 380         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 381         /* Set SLV-T Bank : 0x00 */
 382         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 383         /* Enable demod clock */
 384         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 385         /* Enable ADC clock */
 386         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 387         /* Enable ADC 1 */
 388         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 389         /* Enable ADC 2 */
 390         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 391         /* Set SLV-X Bank : 0x00 */
 392         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 393         /* Enable ADC 3 */
 394         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 395         /* Set SLV-T Bank : 0xA3 */
 396         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 397         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 398         data[0] = 0x07;
 399         data[1] = 0x3B;
 400         data[2] = 0x08;
 401         data[3] = 0xC5;
 402         /* Set SLV-T Bank : 0xAB */
 403         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 404         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 405         data[0] = 0x05;
 406         data[1] = 0x80;
 407         data[2] = 0x0A;
 408         data[3] = 0x80;
 409         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 410         data[0] = 0x0C;
 411         data[1] = 0xCC;
 412         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 413         /* Set demod parameter */
 414         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 415         if (ret != 0)
 416                 return ret;
 417         /* Set SLV-T Bank : 0x00 */
 418         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 419         /* disable Hi-Z setting 1 */
 420         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 421         /* disable Hi-Z setting 2 */
 422         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 423         priv->state = STATE_ACTIVE_S;
 424         return 0;
 425 }
 426
 427 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 428                                                u32 bandwidth);
 429
 430 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 431                                                 u32 bandwidth);
 432
 433 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 434                                                u32 bandwidth);
 435
 436 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 437                 u32 bandwidth);
 438
 439 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 440
 441 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 442
 443 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 444
 445 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 446                                    struct dtv_frontend_properties *p)
 447 {
 448         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 449         if (priv->state != STATE_ACTIVE_S &&
 450                         priv->state != STATE_ACTIVE_TC) {
 451                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 452                         __func__, priv->state);
 453                 return -EINVAL;
 454         }
 455         /* Set SLV-T Bank : 0x00 */
 456         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 457         /* disable TS output */
 458         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 459         if (priv->state == STATE_ACTIVE_S)
 460                 return cxd2841er_dvbs2_set_symbol_rate(
 461                                 priv, p->symbol_rate / 1000);
 462         else if (priv->state == STATE_ACTIVE_TC) {
 463                 switch (priv->system) {
 464                 case SYS_DVBT:
 465                         return cxd2841er_sleep_tc_to_active_t_band(
 466                                         priv, p->bandwidth_hz);
 467                 case SYS_DVBT2:
 468                         return cxd2841er_sleep_tc_to_active_t2_band(
 469                                         priv, p->bandwidth_hz);
 470                 case SYS_DVBC_ANNEX_A:
 471                         return cxd2841er_sleep_tc_to_active_c_band(
 472                                         priv, p->bandwidth_hz);
 473                 case SYS_ISDBT:
 474                         cxd2841er_active_i_to_sleep_tc(priv);
 475                         cxd2841er_sleep_tc_to_shutdown(priv);
 476                         cxd2841er_shutdown_to_sleep_tc(priv);
 477                         return cxd2841er_sleep_tc_to_active_i(
 478                                         priv, p->bandwidth_hz);
 479                 }
 480         }
 481         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 482                 __func__, priv->system);
 483         return -EINVAL;
 484 }
 485
 486 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 487 {
 488         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 489         if (priv->state != STATE_ACTIVE_S) {
 490                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 491                         __func__, priv->state);
 492                 return -EINVAL;
 493         }
 494         /* Set SLV-T Bank : 0x00 */
 495         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 496         /* disable TS output */
 497         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 498         /* enable Hi-Z setting 1 */
 499         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 500         /* enable Hi-Z setting 2 */
 501         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 502         /* Set SLV-X Bank : 0x00 */
 503         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 504         /* disable ADC 1 */
 505         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 506         /* Set SLV-T Bank : 0x00 */
 507         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 508         /* disable ADC clock */
 509         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 510         /* disable ADC 2 */
 511         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 512         /* disable ADC 3 */
 513         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 514         /* SADC Bias ON */
 515         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 516         /* disable demod clock */
 517         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 518         /* Set SLV-T Bank : 0xAE */
 519         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 520         /* disable S/S2 auto detection1 */
 521         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 522         /* Set SLV-T Bank : 0x00 */
 523         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 524         /* disable S/S2 auto detection2 */
 525         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 526         priv->state = STATE_SLEEP_S;
 527         return 0;
 528 }
 529
 530 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 531 {
 532         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 533         if (priv->state != STATE_SLEEP_S) {
 534                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 535                         __func__, priv->state);
 536                 return -EINVAL;
 537         }
 538         /* Set SLV-T Bank : 0x00 */
 539         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 540         /* Disable DSQOUT */
 541         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 542         /* Disable DSQIN */
 543         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 544         /* Set SLV-X Bank : 0x00 */
 545         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 546         /* Disable oscillator */
 547         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 548         /* Set demod mode */
 549         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 550         priv->state = STATE_SHUTDOWN;
 551         return 0;
 552 }
 553
 554 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 555 {
 556         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 557         if (priv->state != STATE_SLEEP_TC) {
 558                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 559                         __func__, priv->state);
 560                 return -EINVAL;
 561         }
 562         /* Set SLV-X Bank : 0x00 */
 563         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 564         /* Disable oscillator */
 565         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 566         /* Set demod mode */
 567         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 568         priv->state = STATE_SHUTDOWN;
 569         return 0;
 570 }
 571
 572 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 573 {
 574         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 575         if (priv->state != STATE_ACTIVE_TC) {
 576                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 577                         __func__, priv->state);
 578                 return -EINVAL;
 579         }
 580         /* Set SLV-T Bank : 0x00 */
 581         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 582         /* disable TS output */
 583         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 584         /* enable Hi-Z setting 1 */
 585         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 586         /* enable Hi-Z setting 2 */
 587         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 588         /* Set SLV-X Bank : 0x00 */
 589         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 590         /* disable ADC 1 */
 591         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 592         /* Set SLV-T Bank : 0x00 */
 593         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 594         /* Disable ADC 2 */
 595         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 596         /* Disable ADC 3 */
 597         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 598         /* Disable ADC clock */
 599         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 600         /* Disable RF level monitor */
 601         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 602         /* Disable demod clock */
 603         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 604         priv->state = STATE_SLEEP_TC;
 605         return 0;
 606 }
 607
 608 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 609 {
 610         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 611         if (priv->state != STATE_ACTIVE_TC) {
 612                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 613                         __func__, priv->state);
 614                 return -EINVAL;
 615         }
 616         /* Set SLV-T Bank : 0x00 */
 617         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 618         /* disable TS output */
 619         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 620         /* enable Hi-Z setting 1 */
 621         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 622         /* enable Hi-Z setting 2 */
 623         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 624         /* Cancel DVB-T2 setting */
 625         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 626         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 627         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 628         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 629         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 630         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 631         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 632         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 633         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 634         /* Set SLV-X Bank : 0x00 */
 635         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 636         /* disable ADC 1 */
 637         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 638         /* Set SLV-T Bank : 0x00 */
 639         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 640         /* Disable ADC 2 */
 641         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 642         /* Disable ADC 3 */
 643         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 644         /* Disable ADC clock */
 645         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 646         /* Disable RF level monitor */
 647         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 648         /* Disable demod clock */
 649         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 650         priv->state = STATE_SLEEP_TC;
 651         return 0;
 652 }
 653
 654 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 655 {
 656         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 657         if (priv->state != STATE_ACTIVE_TC) {
 658                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 659                         __func__, priv->state);
 660                 return -EINVAL;
 661         }
 662         /* Set SLV-T Bank : 0x00 */
 663         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 664         /* disable TS output */
 665         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 666         /* enable Hi-Z setting 1 */
 667         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 668         /* enable Hi-Z setting 2 */
 669         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 670         /* Cancel DVB-C setting */
 671         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 672         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 673         /* Set SLV-X Bank : 0x00 */
 674         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 675         /* disable ADC 1 */
 676         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 677         /* Set SLV-T Bank : 0x00 */
 678         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 679         /* Disable ADC 2 */
 680         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 681         /* Disable ADC 3 */
 682         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 683         /* Disable ADC clock */
 684         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 685         /* Disable RF level monitor */
 686         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 687         /* Disable demod clock */
 688         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 689         priv->state = STATE_SLEEP_TC;
 690         return 0;
 691 }
 692
 693 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 694 {
 695         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 696         if (priv->state != STATE_ACTIVE_TC) {
 697                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 698                                 __func__, priv->state);
 699                 return -EINVAL;
 700         }
 701         /* Set SLV-T Bank : 0x00 */
 702         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 703         /* disable TS output */
 704         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 705         /* enable Hi-Z setting 1 */
 706         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 707         /* enable Hi-Z setting 2 */
 708         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 709
 710         /* TODO: Cancel demod parameter */
 711
 712         /* Set SLV-X Bank : 0x00 */
 713         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 714         /* disable ADC 1 */
 715         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 716         /* Set SLV-T Bank : 0x00 */
 717         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 718         /* Disable ADC 2 */
 719         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 720         /* Disable ADC 3 */
 721         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 722         /* Disable ADC clock */
 723         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 724         /* Disable RF level monitor */
 725         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 726         /* Disable demod clock */
 727         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 728         priv->state = STATE_SLEEP_TC;
 729         return 0;
 730 }
 731
 732 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 733 {
 734         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 735         if (priv->state != STATE_SHUTDOWN) {
 736                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 737                         __func__, priv->state);
 738                 return -EINVAL;
 739         }
 740         /* Set SLV-X Bank : 0x00 */
 741         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 742         /* Clear all demodulator registers */
 743         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 744         usleep_range(3000, 5000);
 745         /* Set SLV-X Bank : 0x00 */
 746         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 747         /* Set demod SW reset */
 748         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 749
 750         switch (priv->xtal) {
 751         case SONY_XTAL_20500:
 752                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 753                 break;
 754         case SONY_XTAL_24000:
 755                 /* Select demod frequency */
 756                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 757                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 758                 break;
 759         case SONY_XTAL_41000:
 760                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 761                 break;
 762         default:
 763                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 764                                 __func__, priv->xtal);
 765                 return -EINVAL;
 766         }
 767
 768         /* Set demod mode */
 769         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 770         /* Clear demod SW reset */
 771         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 772         usleep_range(1000, 2000);
 773         /* Set SLV-T Bank : 0x00 */
 774         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 775         /* enable DSQOUT */
 776         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 777         /* enable DSQIN */
 778         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 779         /* TADC Bias On */
 780         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 781         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 782         /* SADC Bias On */
 783         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 784         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 785         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 786         priv->state = STATE_SLEEP_S;
 787         return 0;
 788 }
 789
 790 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 791 {
 792         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 793         if (priv->state != STATE_SHUTDOWN) {
 794                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 795                         __func__, priv->state);
 796                 return -EINVAL;
 797         }
 798         /* Set SLV-X Bank : 0x00 */
 799         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 800         /* Clear all demodulator registers */
 801         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 802         usleep_range(3000, 5000);
 803         /* Set SLV-X Bank : 0x00 */
 804         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 805         /* Set demod SW reset */
 806         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 807         /* Set X'tal clock to 20.5Mhz */
 808         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 809         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 810         /* Clear demod SW reset */
 811         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 812         usleep_range(1000, 2000);
 813         /* Set SLV-T Bank : 0x00 */
 814         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 815         /* TADC Bias On */
 816         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 817         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 818         /* SADC Bias On */
 819         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 820         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 821         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 822         priv->state = STATE_SLEEP_TC;
 823         return 0;
 824 }
 825
 826 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 827 {
 828         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 829         /* Set SLV-T Bank : 0x00 */
 830         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 831         /* SW Reset */
 832         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 833         /* Enable TS output */
 834         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 835         return 0;
 836 }
 837
 838 /* Set TS parallel mode */
 839 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 840                                         u8 system)
 841 {
 842         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 843
 844         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 845         /* Set SLV-T Bank : 0x00 */
 846         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 847         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 848         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 849         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 850         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 851                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 852
 853         /*
 854          * slave    Bank    Addr    Bit    default    Name
 855          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 856          */
 857         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 858         /*
 859          * Disable TS IF Clock
 860          * slave    Bank    Addr    Bit    default    Name
 861          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 862          */
 863         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 864         /*
 865          * slave    Bank    Addr    Bit    default    Name
 866          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 867          */
 868         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
 869         /*
 870          * Enable TS IF Clock
 871          * slave    Bank    Addr    Bit    default    Name
 872          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 873          */
 874         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 875
 876         if (system == SYS_DVBT) {
 877                 /* Enable parity period for DVB-T */
 878                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 879                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 880         } else if (system == SYS_DVBC_ANNEX_A) {
 881                 /* Enable parity period for DVB-C */
 882                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 883                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 884         }
 885 }
 886
 887 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 888 {
 889         u8 chip_id = 0;
 890
 891         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 892         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 893                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 894         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 895                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 896
 897         return chip_id;
 898 }
 899
 900 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 901                                    enum fe_status *status)
 902 {
 903         u8 reg = 0;
 904         struct cxd2841er_priv *priv = fe->demodulator_priv;
 905
 906         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 907         *status = 0;
 908         if (priv->state != STATE_ACTIVE_S) {
 909                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 910                         __func__, priv->state);
 911                 return -EINVAL;
 912         }
 913         /* Set SLV-T Bank : 0xA0 */
 914         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 915         /*
 916          *  slave     Bank      Addr      Bit      Signal name
 917          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 918          */
 919         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 920         if (reg & 0x04) {
 921                 *status = FE_HAS_SIGNAL
 922                         | FE_HAS_CARRIER
 923                         | FE_HAS_VITERBI
 924                         | FE_HAS_SYNC
 925                         | FE_HAS_LOCK;
 926         }
 927         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
 928         return 0;
 929 }
 930
 931 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
 932                                       u8 *sync, u8 *tslock, u8 *unlock)
 933 {
 934         u8 data = 0;
 935
 936         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 937         if (priv->state != STATE_ACTIVE_TC)
 938                 return -EINVAL;
 939         if (priv->system == SYS_DVBT) {
 940                 /* Set SLV-T Bank : 0x10 */
 941                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 942         } else {
 943                 /* Set SLV-T Bank : 0x20 */
 944                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
 945         }
 946         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 947         if ((data & 0x07) == 0x07) {
 948                 dev_dbg(&priv->i2c->dev,
 949                         "%s(): invalid hardware state detected\n", __func__);
 950                 *sync = 0;
 951                 *tslock = 0;
 952                 *unlock = 0;
 953         } else {
 954                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
 955                 *tslock = ((data & 0x20) ? 1 : 0);
 956                 *unlock = ((data & 0x10) ? 1 : 0);
 957         }
 958         return 0;
 959 }
 960
 961 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
 962 {
 963         u8 data;
 964
 965         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 966         if (priv->state != STATE_ACTIVE_TC)
 967                 return -EINVAL;
 968         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 969         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
 970         if ((data & 0x01) == 0) {
 971                 *tslock = 0;
 972         } else {
 973                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 974                 *tslock = ((data & 0x20) ? 1 : 0);
 975         }
 976         return 0;
 977 }
 978
 979 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
 980                 u8 *sync, u8 *tslock, u8 *unlock)
 981 {
 982         u8 data = 0;
 983
 984         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 985         if (priv->state != STATE_ACTIVE_TC)
 986                 return -EINVAL;
 987         /* Set SLV-T Bank : 0x60 */
 988         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
 989         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 990         dev_dbg(&priv->i2c->dev,
 991                         "%s(): lock=0x%x\n", __func__, data);
 992         *sync = ((data & 0x02) ? 1 : 0);
 993         *tslock = ((data & 0x01) ? 1 : 0);
 994         *unlock = ((data & 0x10) ? 1 : 0);
 995         return 0;
 996 }
 997
 998 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
 999                                     enum fe_status *status)
1000 {
1001         int ret = 0;
1002         u8 sync = 0;
1003         u8 tslock = 0;
1004         u8 unlock = 0;
1005         struct cxd2841er_priv *priv = fe->demodulator_priv;
1006
1007         *status = 0;
1008         if (priv->state == STATE_ACTIVE_TC) {
1009                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1010                         ret = cxd2841er_read_status_t_t2(
1011                                 priv, &sync, &tslock, &unlock);
1012                         if (ret)
1013                                 goto done;
1014                         if (unlock)
1015                                 goto done;
1016                         if (sync)
1017                                 *status = FE_HAS_SIGNAL |
1018                                         FE_HAS_CARRIER |
1019                                         FE_HAS_VITERBI |
1020                                         FE_HAS_SYNC;
1021                         if (tslock)
1022                                 *status |= FE_HAS_LOCK;
1023                 } else if (priv->system == SYS_ISDBT) {
1024                         ret = cxd2841er_read_status_i(
1025                                         priv, &sync, &tslock, &unlock);
1026                         if (ret)
1027                                 goto done;
1028                         if (unlock)
1029                                 goto done;
1030                         if (sync)
1031                                 *status = FE_HAS_SIGNAL |
1032                                         FE_HAS_CARRIER |
1033                                         FE_HAS_VITERBI |
1034                                         FE_HAS_SYNC;
1035                         if (tslock)
1036                                 *status |= FE_HAS_LOCK;
1037                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1038                         ret = cxd2841er_read_status_c(priv, &tslock);
1039                         if (ret)
1040                                 goto done;
1041                         if (tslock)
1042                                 *status = FE_HAS_SIGNAL |
1043                                         FE_HAS_CARRIER |
1044                                         FE_HAS_VITERBI |
1045                                         FE_HAS_SYNC |
1046                                         FE_HAS_LOCK;
1047                 }
1048         }
1049 done:
1050         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1051         return ret;
1052 }
1053
1054 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1055                                              int *offset)
1056 {
1057         u8 data[3];
1058         u8 is_hs_mode;
1059         s32 cfrl_ctrlval;
1060         s32 temp_div, temp_q, temp_r;
1061
1062         if (priv->state != STATE_ACTIVE_S) {
1063                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1064                         __func__, priv->state);
1065                 return -EINVAL;
1066         }
1067         /*
1068          * Get High Sampling Rate mode
1069          *  slave     Bank      Addr      Bit      Signal name
1070          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1071          */
1072         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1073         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1074         if (data[0] & 0x01) {
1075                 /*
1076                  *  slave     Bank      Addr      Bit      Signal name
1077                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1078                  */
1079                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1080                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1081         } else {
1082                 dev_dbg(&priv->i2c->dev,
1083                         "%s(): unable to detect sampling rate mode\n",
1084                         __func__);
1085                 return -EINVAL;
1086         }
1087         /*
1088          *  slave     Bank      Addr      Bit      Signal name
1089          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1090          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1091          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1092          */
1093         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1094         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1095                                 (((u32)data[1] & 0xFF) <<  8) |
1096                                 ((u32)data[2] & 0xFF), 20);
1097         temp_div = (is_hs_mode ? 1048576 : 1572864);
1098         if (cfrl_ctrlval > 0) {
1099                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1100                         temp_div, &temp_r);
1101         } else {
1102                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1103                         temp_div, &temp_r);
1104         }
1105         if (temp_r >= temp_div / 2)
1106                 temp_q++;
1107         if (cfrl_ctrlval > 0)
1108                 temp_q *= -1;
1109         *offset = temp_q;
1110         return 0;
1111 }
1112
1113 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1114                                            u32 bandwidth, int *offset)
1115 {
1116         u8 data[4];
1117
1118         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1119         if (priv->state != STATE_ACTIVE_TC) {
1120                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1121                         __func__, priv->state);
1122                 return -EINVAL;
1123         }
1124         if (priv->system != SYS_ISDBT) {
1125                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1126                         __func__, priv->system);
1127                 return -EINVAL;
1128         }
1129         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1130         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1131         *offset = -1 * sign_extend32(
1132                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1133                 ((u32)data[2] << 8) | (u32)data[3], 29);
1134
1135         switch (bandwidth) {
1136         case 6000000:
1137                 *offset = -1 * ((*offset) * 8/264);
1138                 break;
1139         case 7000000:
1140                 *offset = -1 * ((*offset) * 8/231);
1141                 break;
1142         case 8000000:
1143                 *offset = -1 * ((*offset) * 8/198);
1144                 break;
1145         default:
1146                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1147                                 __func__, bandwidth);
1148                 return -EINVAL;
1149         }
1150
1151         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1152                         __func__, bandwidth, *offset);
1153
1154         return 0;
1155 }
1156
1157 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1158                                            u32 bandwidth, int *offset)
1159 {
1160         u8 data[4];
1161
1162         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1163         if (priv->state != STATE_ACTIVE_TC) {
1164                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1165                         __func__, priv->state);
1166                 return -EINVAL;
1167         }
1168         if (priv->system != SYS_DVBT) {
1169                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1170                         __func__, priv->system);
1171                 return -EINVAL;
1172         }
1173         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1174         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1175         *offset = -1 * sign_extend32(
1176                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1177                 ((u32)data[2] << 8) | (u32)data[3], 29);
1178     *offset *= (bandwidth / 1000000);
1179     *offset /= 235;
1180         return 0;
1181 }
1182
1183 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1184                                            u32 bandwidth, int *offset)
1185 {
1186         u8 data[4];
1187
1188         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1189         if (priv->state != STATE_ACTIVE_TC) {
1190                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1191                         __func__, priv->state);
1192                 return -EINVAL;
1193         }
1194         if (priv->system != SYS_DVBT2) {
1195                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1196                         __func__, priv->system);
1197                 return -EINVAL;
1198         }
1199         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1200         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1201         *offset = -1 * sign_extend32(
1202                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1203                 ((u32)data[2] << 8) | (u32)data[3], 27);
1204         switch (bandwidth) {
1205         case 1712000:
1206                 *offset /= 582;
1207                 break;
1208         case 5000000:
1209         case 6000000:
1210         case 7000000:
1211         case 8000000:
1212                 *offset *= (bandwidth / 1000000);
1213                 *offset /= 940;
1214                 break;
1215         default:
1216                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1217                         __func__, bandwidth);
1218                 return -EINVAL;
1219         }
1220         return 0;
1221 }
1222
1223 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1224                                           int *offset)
1225 {
1226         u8 data[2];
1227
1228         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1229         if (priv->state != STATE_ACTIVE_TC) {
1230                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1231                         __func__, priv->state);
1232                 return -EINVAL;
1233         }
1234         if (priv->system != SYS_DVBC_ANNEX_A) {
1235                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1236                         __func__, priv->system);
1237                 return -EINVAL;
1238         }
1239         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1240         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1241         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1242                                                 | (u32)data[1], 13), 16384);
1243         return 0;
1244 }
1245
1246 static int cxd2841er_read_packet_errors_t(
1247                 struct cxd2841er_priv *priv, u32 *penum)
1248 {
1249         u8 data[3];
1250
1251         *penum = 0;
1252         if (priv->state != STATE_ACTIVE_TC) {
1253                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1254                         __func__, priv->state);
1255                 return -EINVAL;
1256         }
1257         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1258         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1259         if (data[2] & 0x01)
1260                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1261         return 0;
1262 }
1263
1264 static int cxd2841er_read_packet_errors_t2(
1265                 struct cxd2841er_priv *priv, u32 *penum)
1266 {
1267         u8 data[3];
1268
1269         *penum = 0;
1270         if (priv->state != STATE_ACTIVE_TC) {
1271                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1272                         __func__, priv->state);
1273                 return -EINVAL;
1274         }
1275         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1276         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1277         if (data[0] & 0x01)
1278                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1279         return 0;
1280 }
1281
1282 static int cxd2841er_read_packet_errors_i(
1283                 struct cxd2841er_priv *priv, u32 *penum)
1284 {
1285         u8 data[2];
1286
1287         *penum = 0;
1288         if (priv->state != STATE_ACTIVE_TC) {
1289                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1290                                 __func__, priv->state);
1291                 return -EINVAL;
1292         }
1293         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1294         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1295
1296         if (!(data[0] & 0x01))
1297                 return 0;
1298
1299         /* Layer A */
1300         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1301         *penum = ((u32)data[0] << 8) | (u32)data[1];
1302
1303         /* Layer B */
1304         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1305         *penum += ((u32)data[0] << 8) | (u32)data[1];
1306
1307         /* Layer C */
1308         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1309         *penum += ((u32)data[0] << 8) | (u32)data[1];
1310
1311         return 0;
1312 }
1313
1314 static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1315 {
1316         u8 data[11];
1317         u32 bit_error, bit_count;
1318         u32 temp_q, temp_r;
1319
1320         /* Set SLV-T Bank : 0xA0 */
1321         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1322         /*
1323          *  slave     Bank      Addr      Bit      Signal name
1324          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1325          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1326          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1327          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1328          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1329          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1330          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1331          */
1332         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1333         if (data[0] & 0x01) {
1334                 bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1335                         ((u32)(data[2]  & 0xFF) <<  8) |
1336                         (u32)(data[3]  & 0xFF);
1337                 bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1338                         ((u32)(data[9]  & 0xFF) <<  8) |
1339                         (u32)(data[10] & 0xFF);
1340                 /*
1341                  *      BER = bitError / bitCount
1342                  *      = (bitError * 10^7) / bitCount
1343                  *      = ((bitError * 625 * 125 * 128) / bitCount
1344                  */
1345                 if ((bit_count == 0) || (bit_error > bit_count)) {
1346                         dev_dbg(&priv->i2c->dev,
1347                                 "%s(): invalid bit_error %d, bit_count %d\n",
1348                                 __func__, bit_error, bit_count);
1349                         return 0;
1350                 }
1351                 temp_q = div_u64_rem(10000000ULL * bit_error,
1352                                                 bit_count, &temp_r);
1353                 if (bit_count != 1 && temp_r >= bit_count / 2)
1354                         temp_q++;
1355                 return temp_q;
1356         }
1357         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1358         return 0;
1359 }
1360
1361
1362 static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1363 {
1364         u8 data[5];
1365         u32 bit_error, period;
1366         u32 temp_q, temp_r;
1367         u32 result = 0;
1368
1369         /* Set SLV-T Bank : 0xB2 */
1370         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1371         /*
1372          *  slave     Bank      Addr      Bit      Signal name
1373          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1374          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1375          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1376          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1377          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1378          */
1379         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1380         if (data[0] & 0x01) {
1381                 /* Bit error count */
1382                 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1383                         ((u32)(data[2] & 0xFF) << 16) |
1384                         ((u32)(data[3] & 0xFF) <<  8) |
1385                         (u32)(data[4] & 0xFF);
1386
1387                 /* Set SLV-T Bank : 0xA0 */
1388                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1389                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1390                 /* Measurement period */
1391                 period = (u32)(1 << (data[0] & 0x0F));
1392                 if (period == 0) {
1393                         dev_dbg(&priv->i2c->dev,
1394                                 "%s(): period is 0\n", __func__);
1395                         return 0;
1396                 }
1397                 if (bit_error > (period * 64800)) {
1398                         dev_dbg(&priv->i2c->dev,
1399                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1400                                 __func__, bit_error, period);
1401                         return 0;
1402                 }
1403                 /*
1404                  * BER = bitError / (period * 64800)
1405                  *      = (bitError * 10^7) / (period * 64800)
1406                  *      = (bitError * 10^5) / (period * 648)
1407                  *      = (bitError * 12500) / (period * 81)
1408                  *      = (bitError * 10) * 1250 / (period * 81)
1409                  */
1410                 temp_q = div_u64_rem(12500ULL * bit_error,
1411                                         period * 81, &temp_r);
1412                 if (temp_r >= period * 40)
1413                         temp_q++;
1414                 result = temp_q;
1415         } else {
1416                 dev_dbg(&priv->i2c->dev,
1417                         "%s(): no data available\n", __func__);
1418         }
1419         return result;
1420 }
1421
1422 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1423 {
1424         u8 data[4];
1425         u32 div, q, r;
1426         u32 bit_err, period_exp, n_ldpc;
1427
1428         *ber = 0;
1429         if (priv->state != STATE_ACTIVE_TC) {
1430                 dev_dbg(&priv->i2c->dev,
1431                         "%s(): invalid state %d\n", __func__, priv->state);
1432                 return -EINVAL;
1433         }
1434         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1435         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1436         if (!(data[0] & 0x10)) {
1437                 dev_dbg(&priv->i2c->dev,
1438                         "%s(): no valid BER data\n", __func__);
1439                 return 0;
1440         }
1441         bit_err = ((u32)(data[0] & 0x0f) << 24) |
1442                 ((u32)data[1] << 16) |
1443                 ((u32)data[2] << 8) |
1444                 (u32)data[3];
1445         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1446         period_exp = data[0] & 0x0f;
1447         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1448         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1449         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1450         if (bit_err > ((1U << period_exp) * n_ldpc)) {
1451                 dev_dbg(&priv->i2c->dev,
1452                         "%s(): invalid BER value\n", __func__);
1453                 return -EINVAL;
1454         }
1455         if (period_exp >= 4) {
1456                 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1457                 q = div_u64_rem(3125ULL * bit_err, div, &r);
1458         } else {
1459                 div = (1U << period_exp) * (n_ldpc / 200);
1460                 q = div_u64_rem(50000ULL * bit_err, div, &r);
1461         }
1462         *ber = (r >= div / 2) ? q + 1 : q;
1463         return 0;
1464 }
1465
1466 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1467 {
1468         u8 data[2];
1469         u32 div, q, r;
1470         u32 bit_err, period;
1471
1472         *ber = 0;
1473         if (priv->state != STATE_ACTIVE_TC) {
1474                 dev_dbg(&priv->i2c->dev,
1475                         "%s(): invalid state %d\n", __func__, priv->state);
1476                 return -EINVAL;
1477         }
1478         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1479         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1480         if (!(data[0] & 0x01)) {
1481                 dev_dbg(&priv->i2c->dev,
1482                         "%s(): no valid BER data\n", __func__);
1483                 return 0;
1484         }
1485         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1486         bit_err = ((u32)data[0] << 8) | (u32)data[1];
1487         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1488         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1489         div = period / 128;
1490         q = div_u64_rem(78125ULL * bit_err, div, &r);
1491         *ber = (r >= div / 2) ? q + 1 : q;
1492         return 0;
1493 }
1494
1495 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1496 {
1497         u8 data[3];
1498         u32 res = 0, value;
1499         int min_index, max_index, index;
1500         static const struct cxd2841er_cnr_data *cn_data;
1501
1502         /* Set SLV-T Bank : 0xA1 */
1503         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1504         /*
1505          *  slave     Bank      Addr      Bit     Signal name
1506          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1507          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1508          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1509          */
1510         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1511         if (data[0] & 0x01) {
1512                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1513                 min_index = 0;
1514                 if (delsys == SYS_DVBS) {
1515                         cn_data = s_cn_data;
1516                         max_index = sizeof(s_cn_data) /
1517                                 sizeof(s_cn_data[0]) - 1;
1518                 } else {
1519                         cn_data = s2_cn_data;
1520                         max_index = sizeof(s2_cn_data) /
1521                                 sizeof(s2_cn_data[0]) - 1;
1522                 }
1523                 if (value >= cn_data[min_index].value) {
1524                         res = cn_data[min_index].cnr_x1000;
1525                         goto done;
1526                 }
1527                 if (value <= cn_data[max_index].value) {
1528                         res = cn_data[max_index].cnr_x1000;
1529                         goto done;
1530                 }
1531                 while ((max_index - min_index) > 1) {
1532                         index = (max_index + min_index) / 2;
1533                         if (value == cn_data[index].value) {
1534                                 res = cn_data[index].cnr_x1000;
1535                                 goto done;
1536                         } else if (value > cn_data[index].value)
1537                                 max_index = index;
1538                         else
1539                                 min_index = index;
1540                         if ((max_index - min_index) <= 1) {
1541                                 if (value == cn_data[max_index].value) {
1542                                         res = cn_data[max_index].cnr_x1000;
1543                                         goto done;
1544                                 } else {
1545                                         res = cn_data[min_index].cnr_x1000;
1546                                         goto done;
1547                                 }
1548                         }
1549                 }
1550         } else {
1551                 dev_dbg(&priv->i2c->dev,
1552                         "%s(): no data available\n", __func__);
1553         }
1554 done:
1555         return res;
1556 }
1557
1558 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1559 {
1560         u32 reg;
1561         u8 data[2];
1562
1563         *snr = 0;
1564         if (priv->state != STATE_ACTIVE_TC) {
1565                 dev_dbg(&priv->i2c->dev,
1566                         "%s(): invalid state %d\n", __func__, priv->state);
1567                 return -EINVAL;
1568         }
1569         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1570         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1571         reg = ((u32)data[0] << 8) | (u32)data[1];
1572         if (reg == 0) {
1573                 dev_dbg(&priv->i2c->dev,
1574                         "%s(): reg value out of range\n", __func__);
1575                 return 0;
1576         }
1577         if (reg > 4996)
1578                 reg = 4996;
1579         *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1580         return 0;
1581 }
1582
1583 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1584 {
1585         u32 reg;
1586         u8 data[2];
1587
1588         *snr = 0;
1589         if (priv->state != STATE_ACTIVE_TC) {
1590                 dev_dbg(&priv->i2c->dev,
1591                         "%s(): invalid state %d\n", __func__, priv->state);
1592                 return -EINVAL;
1593         }
1594         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1595         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1596         reg = ((u32)data[0] << 8) | (u32)data[1];
1597         if (reg == 0) {
1598                 dev_dbg(&priv->i2c->dev,
1599                         "%s(): reg value out of range\n", __func__);
1600                 return 0;
1601         }
1602         if (reg > 10876)
1603                 reg = 10876;
1604         *snr = 10000 * ((intlog10(reg) -
1605                 intlog10(12600 - reg)) >> 24) + 32000;
1606         return 0;
1607 }
1608
1609 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1610 {
1611         u32 reg;
1612         u8 data[2];
1613
1614         *snr = 0;
1615         if (priv->state != STATE_ACTIVE_TC) {
1616                 dev_dbg(&priv->i2c->dev,
1617                                 "%s(): invalid state %d\n", __func__,
1618                                 priv->state);
1619                 return -EINVAL;
1620         }
1621
1622         /* Freeze all registers */
1623         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1624
1625
1626         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1627         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1628         reg = ((u32)data[0] << 8) | (u32)data[1];
1629         if (reg == 0) {
1630                 dev_dbg(&priv->i2c->dev,
1631                                 "%s(): reg value out of range\n", __func__);
1632                 return 0;
1633         }
1634         if (reg > 4996)
1635                 reg = 4996;
1636         *snr = 100 * intlog10(reg) - 9031;
1637         return 0;
1638 }
1639
1640 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1641                                         u8 delsys)
1642 {
1643         u8 data[2];
1644
1645         cxd2841er_write_reg(
1646                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1647         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1648         dev_dbg(&priv->i2c->dev,
1649                         "%s(): AGC value=%u\n",
1650                         __func__, (((u16)data[0] & 0x0F) << 8) |
1651                         (u16)(data[1] & 0xFF));
1652         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1653 }
1654
1655 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1656                 u8 delsys)
1657 {
1658         u8 data[2];
1659
1660         cxd2841er_write_reg(
1661                         priv, I2C_SLVT, 0x00, 0x60);
1662         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1663
1664         dev_dbg(&priv->i2c->dev,
1665                         "%s(): AGC value=%u\n",
1666                         __func__, (((u16)data[0] & 0x0F) << 8) |
1667                         (u16)(data[1] & 0xFF));
1668         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1669 }
1670
1671 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1672 {
1673         u8 data[2];
1674
1675         /* Set SLV-T Bank : 0xA0 */
1676         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1677         /*
1678          *  slave     Bank      Addr      Bit       Signal name
1679          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1680          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1681          */
1682         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1683         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1684 }
1685
1686 static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1687 {
1688         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1689         struct cxd2841er_priv *priv = fe->demodulator_priv;
1690
1691         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1692         *ber = 0;
1693         switch (p->delivery_system) {
1694         case SYS_DVBS:
1695                 *ber = cxd2841er_mon_read_ber_s(priv);
1696                 break;
1697         case SYS_DVBS2:
1698                 *ber = cxd2841er_mon_read_ber_s2(priv);
1699                 break;
1700         case SYS_DVBT:
1701                 return cxd2841er_read_ber_t(priv, ber);
1702         case SYS_DVBT2:
1703                 return cxd2841er_read_ber_t2(priv, ber);
1704         default:
1705                 *ber = 0;
1706                 break;
1707         }
1708         return 0;
1709 }
1710
1711 static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1712                                           u16 *strength)
1713 {
1714         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1715         struct cxd2841er_priv *priv = fe->demodulator_priv;
1716
1717         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1718         switch (p->delivery_system) {
1719         case SYS_DVBT:
1720         case SYS_DVBT2:
1721                 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1722                         priv, p->delivery_system);
1723                 break;
1724         case SYS_ISDBT:
1725                 *strength = 65535 - cxd2841er_read_agc_gain_i(
1726                                 priv, p->delivery_system);
1727                 break;
1728         case SYS_DVBS:
1729         case SYS_DVBS2:
1730                 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1731                 break;
1732         default:
1733                 *strength = 0;
1734                 break;
1735         }
1736         return 0;
1737 }
1738
1739 static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1740 {
1741         u32 tmp = 0;
1742         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1743         struct cxd2841er_priv *priv = fe->demodulator_priv;
1744
1745         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1746         switch (p->delivery_system) {
1747         case SYS_DVBT:
1748                 cxd2841er_read_snr_t(priv, &tmp);
1749                 break;
1750         case SYS_DVBT2:
1751                 cxd2841er_read_snr_t2(priv, &tmp);
1752                 break;
1753         case SYS_ISDBT:
1754                 cxd2841er_read_snr_i(priv, &tmp);
1755                 break;
1756         case SYS_DVBS:
1757         case SYS_DVBS2:
1758                 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1759                 break;
1760         default:
1761                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1762                         __func__, p->delivery_system);
1763                 break;
1764         }
1765         *snr = tmp & 0xffff;
1766         return 0;
1767 }
1768
1769 static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1770 {
1771         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1772         struct cxd2841er_priv *priv = fe->demodulator_priv;
1773
1774         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1775         switch (p->delivery_system) {
1776         case SYS_DVBT:
1777                 cxd2841er_read_packet_errors_t(priv, ucblocks);
1778                 break;
1779         case SYS_DVBT2:
1780                 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1781                 break;
1782         case SYS_ISDBT:
1783                 cxd2841er_read_packet_errors_i(priv, ucblocks);
1784                 break;
1785         default:
1786                 *ucblocks = 0;
1787                 break;
1788         }
1789         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1790         return 0;
1791 }
1792
1793 static int cxd2841er_dvbt2_set_profile(
1794         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1795 {
1796         u8 tune_mode;
1797         u8 seq_not2d_time;
1798
1799         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1800         switch (profile) {
1801         case DVBT2_PROFILE_BASE:
1802                 tune_mode = 0x01;
1803                 seq_not2d_time = 12;
1804                 break;
1805         case DVBT2_PROFILE_LITE:
1806                 tune_mode = 0x05;
1807                 seq_not2d_time = 40;
1808                 break;
1809         case DVBT2_PROFILE_ANY:
1810                 tune_mode = 0x00;
1811                 seq_not2d_time = 40;
1812                 break;
1813         default:
1814                 return -EINVAL;
1815         }
1816         /* Set SLV-T Bank : 0x2E */
1817         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1818         /* Set profile and tune mode */
1819         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1820         /* Set SLV-T Bank : 0x2B */
1821         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1822         /* Set early unlock detection time */
1823         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1824         return 0;
1825 }
1826
1827 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1828                                           u8 is_auto, u8 plp_id)
1829 {
1830         if (is_auto) {
1831                 dev_dbg(&priv->i2c->dev,
1832                         "%s() using auto PLP selection\n", __func__);
1833         } else {
1834                 dev_dbg(&priv->i2c->dev,
1835                         "%s() using manual PLP selection, ID %d\n",
1836                         __func__, plp_id);
1837         }
1838         /* Set SLV-T Bank : 0x23 */
1839         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1840         if (!is_auto) {
1841                 /* Manual PLP selection mode. Set the data PLP Id. */
1842                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1843         }
1844         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1845         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1846         return 0;
1847 }
1848
1849 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1850                                                 u32 bandwidth)
1851 {
1852         u32 iffreq;
1853         u8 b20_9f[5];
1854         u8 b10_a6[14];
1855         u8 b10_b6[3];
1856         u8 b10_d7;
1857
1858         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1859         switch (bandwidth) {
1860         case 8000000:
1861                 /* bank 0x20, reg 0x9f */
1862                 b20_9f[0] = 0x11;
1863                 b20_9f[1] = 0xf0;
1864                 b20_9f[2] = 0x00;
1865                 b20_9f[3] = 0x00;
1866                 b20_9f[4] = 0x00;
1867                 /* bank 0x10, reg 0xa6 */
1868                 b10_a6[0] = 0x26;
1869                 b10_a6[1] = 0xaf;
1870                 b10_a6[2] = 0x06;
1871                 b10_a6[3] = 0xcd;
1872                 b10_a6[4] = 0x13;
1873                 b10_a6[5] = 0xbb;
1874                 b10_a6[6] = 0x28;
1875                 b10_a6[7] = 0xba;
1876                 b10_a6[8] = 0x23;
1877                 b10_a6[9] = 0xa9;
1878                 b10_a6[10] = 0x1f;
1879                 b10_a6[11] = 0xa8;
1880                 b10_a6[12] = 0x2c;
1881                 b10_a6[13] = 0xc8;
1882                 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1883                 b10_d7 = 0x00;
1884                 break;
1885         case 7000000:
1886                 /* bank 0x20, reg 0x9f */
1887                 b20_9f[0] = 0x14;
1888                 b20_9f[1] = 0x80;
1889                 b20_9f[2] = 0x00;
1890                 b20_9f[3] = 0x00;
1891                 b20_9f[4] = 0x00;
1892                 /* bank 0x10, reg 0xa6 */
1893                 b10_a6[0] = 0x2C;
1894                 b10_a6[1] = 0xBD;
1895                 b10_a6[2] = 0x02;
1896                 b10_a6[3] = 0xCF;
1897                 b10_a6[4] = 0x04;
1898                 b10_a6[5] = 0xF8;
1899                 b10_a6[6] = 0x23;
1900                 b10_a6[7] = 0xA6;
1901                 b10_a6[8] = 0x29;
1902                 b10_a6[9] = 0xB0;
1903                 b10_a6[10] = 0x26;
1904                 b10_a6[11] = 0xA9;
1905                 b10_a6[12] = 0x21;
1906                 b10_a6[13] = 0xA5;
1907                 iffreq = MAKE_IFFREQ_CONFIG(4.2);
1908                 b10_d7 = 0x02;
1909                 break;
1910         case 6000000:
1911                 /* bank 0x20, reg 0x9f */
1912                 b20_9f[0] = 0x17;
1913                 b20_9f[1] = 0xEA;
1914                 b20_9f[2] = 0xAA;
1915                 b20_9f[3] = 0xAA;
1916                 b20_9f[4] = 0xAA;
1917                 /* bank 0x10, reg 0xa6 */
1918                 b10_a6[0] = 0x27;
1919                 b10_a6[1] = 0xA7;
1920                 b10_a6[2] = 0x28;
1921                 b10_a6[3] = 0xB3;
1922                 b10_a6[4] = 0x02;
1923                 b10_a6[5] = 0xF0;
1924                 b10_a6[6] = 0x01;
1925                 b10_a6[7] = 0xE8;
1926                 b10_a6[8] = 0x00;
1927                 b10_a6[9] = 0xCF;
1928                 b10_a6[10] = 0x00;
1929                 b10_a6[11] = 0xE6;
1930                 b10_a6[12] = 0x23;
1931                 b10_a6[13] = 0xA4;
1932                 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1933                 b10_d7 = 0x04;
1934                 break;
1935         case 5000000:
1936                 /* bank 0x20, reg 0x9f */
1937                 b20_9f[0] = 0x1C;
1938                 b20_9f[1] = 0xB3;
1939                 b20_9f[2] = 0x33;
1940                 b20_9f[3] = 0x33;
1941                 b20_9f[4] = 0x33;
1942                 /* bank 0x10, reg 0xa6 */
1943                 b10_a6[0] = 0x27;
1944                 b10_a6[1] = 0xA7;
1945                 b10_a6[2] = 0x28;
1946                 b10_a6[3] = 0xB3;
1947                 b10_a6[4] = 0x02;
1948                 b10_a6[5] = 0xF0;
1949                 b10_a6[6] = 0x01;
1950                 b10_a6[7] = 0xE8;
1951                 b10_a6[8] = 0x00;
1952                 b10_a6[9] = 0xCF;
1953                 b10_a6[10] = 0x00;
1954                 b10_a6[11] = 0xE6;
1955                 b10_a6[12] = 0x23;
1956                 b10_a6[13] = 0xA4;
1957                 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1958                 b10_d7 = 0x06;
1959                 break;
1960         case 1712000:
1961                 /* bank 0x20, reg 0x9f */
1962                 b20_9f[0] = 0x58;
1963                 b20_9f[1] = 0xE2;
1964                 b20_9f[2] = 0xAF;
1965                 b20_9f[3] = 0xE0;
1966                 b20_9f[4] = 0xBC;
1967                 /* bank 0x10, reg 0xa6 */
1968                 b10_a6[0] = 0x25;
1969                 b10_a6[1] = 0xA0;
1970                 b10_a6[2] = 0x36;
1971                 b10_a6[3] = 0x8D;
1972                 b10_a6[4] = 0x2E;
1973                 b10_a6[5] = 0x94;
1974                 b10_a6[6] = 0x28;
1975                 b10_a6[7] = 0x9B;
1976                 b10_a6[8] = 0x32;
1977                 b10_a6[9] = 0x90;
1978                 b10_a6[10] = 0x2C;
1979                 b10_a6[11] = 0x9D;
1980                 b10_a6[12] = 0x29;
1981                 b10_a6[13] = 0x99;
1982                 iffreq = MAKE_IFFREQ_CONFIG(3.5);
1983                 b10_d7 = 0x03;
1984                 break;
1985         default:
1986                 return -EINVAL;
1987         }
1988         /* Set SLV-T Bank : 0x20 */
1989         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x20);
1990         cxd2841er_write_regs(priv, I2C_SLVT, 0x9f, b20_9f, sizeof(b20_9f));
1991         /* Set SLV-T Bank : 0x27 */
1992         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1993         cxd2841er_set_reg_bits(
1994                 priv, I2C_SLVT, 0x7a,
1995                 (bandwidth == 1712000 ? 0x03 : 0x00), 0x0f);
1996         /* Set SLV-T Bank : 0x10 */
1997         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1998         /* Group delay equaliser sett. for ASCOT2E */
1999         cxd2841er_write_regs(priv, I2C_SLVT, 0xa6, b10_a6, sizeof(b10_a6));
2000         /* <IF freq setting> */
2001         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2002         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2003         b10_b6[2] = (u8)(iffreq & 0xff);
2004         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2005         /* System bandwidth setting */
2006         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, b10_d7, 0x07);
2007         return 0;
2008 }
2009
2010 static int cxd2841er_sleep_tc_to_active_t_band(
2011                 struct cxd2841er_priv *priv, u32 bandwidth)
2012 {
2013         u8 data[MAX_WRITE_REGSIZE];
2014         u32 iffreq;
2015         u8 nominalRate8bw[3][5] = {
2016                 /* TRCG Nominal Rate [37:0] */
2017                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2018                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2019                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2020         };
2021         u8 nominalRate7bw[3][5] = {
2022                 /* TRCG Nominal Rate [37:0] */
2023                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2024                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2025                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2026         };
2027         u8 nominalRate6bw[3][5] = {
2028                 /* TRCG Nominal Rate [37:0] */
2029                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2030                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2031                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2032         };
2033         u8 nominalRate5bw[3][5] = {
2034                 /* TRCG Nominal Rate [37:0] */
2035                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2036                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2037                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2038         };
2039
2040         u8 itbCoef8bw[3][14] = {
2041                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2042                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2043                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2044                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2045                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2046                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2047         };
2048         u8 itbCoef7bw[3][14] = {
2049                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2050                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2051                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2052                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2053                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2054                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2055         };
2056         u8 itbCoef6bw[3][14] = {
2057                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2058                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2059                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2060                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2061                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2062                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2063         };
2064         u8 itbCoef5bw[3][14] = {
2065                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2066                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2067                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2068                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2069                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2070                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2071         };
2072
2073         /* Set SLV-T Bank : 0x13 */
2074         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2075         /* Echo performance optimization setting */
2076         data[0] = 0x01;
2077         data[1] = 0x14;
2078         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2079
2080         /* Set SLV-T Bank : 0x10 */
2081         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2082
2083         switch (bandwidth) {
2084         case 8000000:
2085                 /* <Timing Recovery setting> */
2086                 cxd2841er_write_regs(priv, I2C_SLVT,
2087                                 0x9F, nominalRate8bw[priv->xtal], 5);
2088                 /* Group delay equaliser settings for
2089                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2090                 */
2091                 cxd2841er_write_regs(priv, I2C_SLVT,
2092                                 0xA6, itbCoef8bw[priv->xtal], 14);
2093                 /* <IF freq setting> */
2094                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2095                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2096                 data[1] = (u8)((iffreq >> 8) & 0xff);
2097                 data[2] = (u8)(iffreq & 0xff);
2098                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2099                 /* System bandwidth setting */
2100                 cxd2841er_set_reg_bits(
2101                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2102
2103                 /* Demod core latency setting */
2104                 if (priv->xtal == SONY_XTAL_24000) {
2105                         data[0] = 0x15;
2106                         data[1] = 0x28;
2107                 } else {
2108                         data[0] = 0x01;
2109                         data[1] = 0xE0;
2110                 }
2111                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2112
2113                 /* Notch filter setting */
2114                 data[0] = 0x01;
2115                 data[1] = 0x02;
2116                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2117                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2118                 break;
2119         case 7000000:
2120                 /* <Timing Recovery setting> */
2121                 cxd2841er_write_regs(priv, I2C_SLVT,
2122                                 0x9F, nominalRate7bw[priv->xtal], 5);
2123                 /* Group delay equaliser settings for
2124                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2125                 */
2126                 cxd2841er_write_regs(priv, I2C_SLVT,
2127                                 0xA6, itbCoef7bw[priv->xtal], 14);
2128                 /* <IF freq setting> */
2129                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2130                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2131                 data[1] = (u8)((iffreq >> 8) & 0xff);
2132                 data[2] = (u8)(iffreq & 0xff);
2133                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2134                 /* System bandwidth setting */
2135                 cxd2841er_set_reg_bits(
2136                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2137
2138                 /* Demod core latency setting */
2139                 if (priv->xtal == SONY_XTAL_24000) {
2140                         data[0] = 0x1F;
2141                         data[1] = 0xF8;
2142                 } else {
2143                         data[0] = 0x12;
2144                         data[1] = 0xF8;
2145                 }
2146                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2147
2148                 /* Notch filter setting */
2149                 data[0] = 0x00;
2150                 data[1] = 0x03;
2151                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2152                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2153                 break;
2154         case 6000000:
2155                 /* <Timing Recovery setting> */
2156                 cxd2841er_write_regs(priv, I2C_SLVT,
2157                                 0x9F, nominalRate6bw[priv->xtal], 5);
2158                 /* Group delay equaliser settings for
2159                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2160                 */
2161                 cxd2841er_write_regs(priv, I2C_SLVT,
2162                                 0xA6, itbCoef6bw[priv->xtal], 14);
2163                 /* <IF freq setting> */
2164                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2165                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2166                 data[1] = (u8)((iffreq >> 8) & 0xff);
2167                 data[2] = (u8)(iffreq & 0xff);
2168                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2169                 /* System bandwidth setting */
2170                 cxd2841er_set_reg_bits(
2171                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2172
2173                 /* Demod core latency setting */
2174                 if (priv->xtal == SONY_XTAL_24000) {
2175                         data[0] = 0x25;
2176                         data[1] = 0x4C;
2177                 } else {
2178                         data[0] = 0x1F;
2179                         data[1] = 0xDC;
2180                 }
2181                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2182
2183                 /* Notch filter setting */
2184                 data[0] = 0x00;
2185                 data[1] = 0x03;
2186                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2187                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2188                 break;
2189         case 5000000:
2190                 /* <Timing Recovery setting> */
2191                 cxd2841er_write_regs(priv, I2C_SLVT,
2192                                 0x9F, nominalRate5bw[priv->xtal], 5);
2193                 /* Group delay equaliser settings for
2194                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2195                 */
2196                 cxd2841er_write_regs(priv, I2C_SLVT,
2197                                 0xA6, itbCoef5bw[priv->xtal], 14);
2198                 /* <IF freq setting> */
2199                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2200                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2201                 data[1] = (u8)((iffreq >> 8) & 0xff);
2202                 data[2] = (u8)(iffreq & 0xff);
2203                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2204                 /* System bandwidth setting */
2205                 cxd2841er_set_reg_bits(
2206                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2207
2208                 /* Demod core latency setting */
2209                 if (priv->xtal == SONY_XTAL_24000) {
2210                         data[0] = 0x2C;
2211                         data[1] = 0xC2;
2212                 } else {
2213                         data[0] = 0x26;
2214                         data[1] = 0x3C;
2215                 }
2216                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2217
2218                 /* Notch filter setting */
2219                 data[0] = 0x00;
2220                 data[1] = 0x03;
2221                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2222                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2223                 break;
2224         }
2225
2226         return 0;
2227 }
2228
2229 static int cxd2841er_sleep_tc_to_active_i_band(
2230                 struct cxd2841er_priv *priv, u32 bandwidth)
2231 {
2232         u32 iffreq;
2233         u8 data[3];
2234
2235         /* TRCG Nominal Rate */
2236         u8 nominalRate8bw[3][5] = {
2237                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2238                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2239                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2240         };
2241
2242         u8 nominalRate7bw[3][5] = {
2243                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2244                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2245                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2246         };
2247
2248         u8 nominalRate6bw[3][5] = {
2249                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2250                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2251                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2252         };
2253
2254         u8 itbCoef8bw[3][14] = {
2255                 {0x00}, /* 20.5MHz XTal */
2256                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2257                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2258                 {0x0}, /* 41MHz XTal   */
2259         };
2260
2261         u8 itbCoef7bw[3][14] = {
2262                 {0x00}, /* 20.5MHz XTal */
2263                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2264                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2265                 {0x00}, /* 41MHz XTal   */
2266         };
2267
2268         u8 itbCoef6bw[3][14] = {
2269                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2270                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2271                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2272                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2273                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2274                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2275         };
2276
2277         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2278         /* Set SLV-T Bank : 0x10 */
2279         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2280
2281         /*  20.5/41MHz Xtal support is not available
2282          *  on ISDB-T 7MHzBW and 8MHzBW
2283         */
2284         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2285                 dev_err(&priv->i2c->dev,
2286                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2287                         __func__, bandwidth);
2288                 return -EINVAL;
2289         }
2290
2291         switch (bandwidth) {
2292         case 8000000:
2293                 /* TRCG Nominal Rate */
2294                 cxd2841er_write_regs(priv, I2C_SLVT,
2295                                 0x9F, nominalRate8bw[priv->xtal], 5);
2296                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2297                 cxd2841er_write_regs(priv, I2C_SLVT,
2298                                 0xA6, itbCoef8bw[priv->xtal], 14);
2299
2300                 /* IF freq setting */
2301                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2302                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2303                 data[1] = (u8)((iffreq >> 8) & 0xff);
2304                 data[2] = (u8)(iffreq & 0xff);
2305                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2306
2307                 /* System bandwidth setting */
2308                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2309
2310                 /* Demod core latency setting */
2311                 data[0] = 0x13;
2312                 data[1] = 0xFC;
2313                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2314
2315                 /* Acquisition optimization setting */
2316                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2317                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2318                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2319                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2320                 break;
2321         case 7000000:
2322                 /* TRCG Nominal Rate */
2323                 cxd2841er_write_regs(priv, I2C_SLVT,
2324                                 0x9F, nominalRate7bw[priv->xtal], 5);
2325                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2326                 cxd2841er_write_regs(priv, I2C_SLVT,
2327                                 0xA6, itbCoef7bw[priv->xtal], 14);
2328
2329                 /* IF freq setting */
2330                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2331                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2332                 data[1] = (u8)((iffreq >> 8) & 0xff);
2333                 data[2] = (u8)(iffreq & 0xff);
2334                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2335
2336                 /* System bandwidth setting */
2337                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2338
2339                 /* Demod core latency setting */
2340                 data[0] = 0x1A;
2341                 data[1] = 0xFA;
2342                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2343
2344                 /* Acquisition optimization setting */
2345                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2346                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2347                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2348                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2349                 break;
2350         case 6000000:
2351                 /* TRCG Nominal Rate */
2352                 cxd2841er_write_regs(priv, I2C_SLVT,
2353                                 0x9F, nominalRate6bw[priv->xtal], 5);
2354                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2355                 cxd2841er_write_regs(priv, I2C_SLVT,
2356                                 0xA6, itbCoef6bw[priv->xtal], 14);
2357
2358                 /* IF freq setting */
2359                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2360                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2361                 data[1] = (u8)((iffreq >> 8) & 0xff);
2362                 data[2] = (u8)(iffreq & 0xff);
2363                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2364
2365                 /* System bandwidth setting */
2366                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2367
2368                 /* Demod core latency setting */
2369                 if (priv->xtal == SONY_XTAL_24000) {
2370                         data[0] = 0x1F;
2371                         data[1] = 0x79;
2372                 } else {
2373                         data[0] = 0x1A;
2374                         data[1] = 0xE2;
2375                 }
2376                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2377
2378                 /* Acquisition optimization setting */
2379                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2380                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2381                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2382                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2383                 break;
2384         default:
2385                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2386                                 __func__, bandwidth);
2387                 return -EINVAL;
2388         }
2389         return 0;
2390 }
2391
2392 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2393                                                u32 bandwidth)
2394 {
2395         u8 bw7_8mhz_b10_a6[] = {
2396                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2397                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2398         u8 bw6mhz_b10_a6[] = {
2399                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2400                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2401         u8 b10_b6[3];
2402         u32 iffreq;
2403
2404         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2405         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2406         switch (bandwidth) {
2407         case 8000000:
2408         case 7000000:
2409                 cxd2841er_write_regs(
2410                         priv, I2C_SLVT, 0xa6,
2411                         bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2412                 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2413                 break;
2414         case 6000000:
2415                 cxd2841er_write_regs(
2416                         priv, I2C_SLVT, 0xa6,
2417                         bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2418                 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2419                 break;
2420         default:
2421                 dev_dbg(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2422                         __func__, bandwidth);
2423                 return -EINVAL;
2424         }
2425         /* <IF freq setting> */
2426         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2427         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2428         b10_b6[2] = (u8)(iffreq & 0xff);
2429         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2430         /* Set SLV-T Bank : 0x11 */
2431         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2432         switch (bandwidth) {
2433         case 8000000:
2434         case 7000000:
2435                 cxd2841er_set_reg_bits(
2436                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2437                 break;
2438         case 6000000:
2439                 cxd2841er_set_reg_bits(
2440                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2441                 break;
2442         }
2443         /* Set SLV-T Bank : 0x40 */
2444         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2445         switch (bandwidth) {
2446         case 8000000:
2447                 cxd2841er_set_reg_bits(
2448                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2449                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2450                 break;
2451         case 7000000:
2452                 cxd2841er_set_reg_bits(
2453                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2454                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2455                 break;
2456         case 6000000:
2457                 cxd2841er_set_reg_bits(
2458                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2459                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2460                 break;
2461         }
2462         return 0;
2463 }
2464
2465 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2466                                           u32 bandwidth)
2467 {
2468         u8 data[2] = { 0x09, 0x54 };
2469         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2470
2471         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2472         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2473         /* Set SLV-X Bank : 0x00 */
2474         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2475         /* Set demod mode */
2476         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2477         /* Set SLV-T Bank : 0x00 */
2478         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2479         /* Enable demod clock */
2480         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2481         /* Disable RF level monitor */
2482         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2483         /* Enable ADC clock */
2484         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2485         /* Enable ADC 1 */
2486         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2487         /* Enable ADC 2 & 3 */
2488         if (priv->xtal == SONY_XTAL_41000) {
2489                 data[0] = 0x0A;
2490                 data[1] = 0xD4;
2491         }
2492         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2493         /* Enable ADC 4 */
2494         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2495         /* Set SLV-T Bank : 0x10 */
2496         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2497         /* IFAGC gain settings */
2498         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2499         /* Set SLV-T Bank : 0x11 */
2500         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2501         /* BBAGC TARGET level setting */
2502         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2503         /* Set SLV-T Bank : 0x10 */
2504         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2505         /* ASCOT setting ON */
2506         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2507         /* Set SLV-T Bank : 0x18 */
2508         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2509         /* Pre-RS BER moniter setting */
2510         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2511         /* FEC Auto Recovery setting */
2512         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2513         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2514         /* Set SLV-T Bank : 0x00 */
2515         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2516         /* TSIF setting */
2517         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2518         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2519
2520         if (priv->xtal == SONY_XTAL_24000) {
2521                 /* Set SLV-T Bank : 0x10 */
2522                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2523                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2524                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2525                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2526         }
2527
2528         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2529         /* Set SLV-T Bank : 0x00 */
2530         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2531         /* Disable HiZ Setting 1 */
2532         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2533         /* Disable HiZ Setting 2 */
2534         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2535         priv->state = STATE_ACTIVE_TC;
2536         return 0;
2537 }
2538
2539 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2540                                            u32 bandwidth)
2541 {
2542         u8 data[2] = { 0x09, 0x54 };
2543
2544         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2545         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2546         /* Set SLV-X Bank : 0x00 */
2547         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2548         /* Set demod mode */
2549         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2550         /* Set SLV-T Bank : 0x00 */
2551         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2552         /* Enable demod clock */
2553         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2554         /* Disable RF level monitor */
2555         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2556         /* Enable ADC clock */
2557         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2558         /* Enable ADC 1 */
2559         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2560         /* xtal freq 20.5MHz */
2561         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2562         /* Enable ADC 4 */
2563         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2564         /* Set SLV-T Bank : 0x10 */
2565         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2566         /* IFAGC gain settings */
2567         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2568         /* Set SLV-T Bank : 0x11 */
2569         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2570         /* BBAGC TARGET level setting */
2571         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2572         /* Set SLV-T Bank : 0x10 */
2573         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2574         /* ASCOT setting ON */
2575         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2576         /* Set SLV-T Bank : 0x20 */
2577         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2578         /* Acquisition optimization setting */
2579         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2580         /* Set SLV-T Bank : 0x2b */
2581         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2582         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2583         /* Set SLV-T Bank : 0x00 */
2584         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2585         /* TSIF setting */
2586         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2587         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2588         /* DVB-T2 initial setting */
2589         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2590         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2591         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2592         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2593         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2594         /* Set SLV-T Bank : 0x2a */
2595         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2596         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2597         /* Set SLV-T Bank : 0x2b */
2598         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2599         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2600
2601         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2602
2603         /* Set SLV-T Bank : 0x00 */
2604         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2605         /* Disable HiZ Setting 1 */
2606         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2607         /* Disable HiZ Setting 2 */
2608         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2609         priv->state = STATE_ACTIVE_TC;
2610         return 0;
2611 }
2612
2613 /* ISDB-Tb part */
2614 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2615                 u32 bandwidth)
2616 {
2617         u8 data[2] = { 0x09, 0x54 };
2618         u8 data24m[2] = {0x60, 0x00};
2619         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2620
2621         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2622         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2623         /* Set SLV-X Bank : 0x00 */
2624         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2625         /* Set demod mode */
2626         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2627         /* Set SLV-T Bank : 0x00 */
2628         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2629         /* Enable demod clock */
2630         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2631         /* Enable RF level monitor */
2632         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2633         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2634         /* Enable ADC clock */
2635         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2636         /* Enable ADC 1 */
2637         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2638         /* xtal freq 20.5MHz or 24M */
2639         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2640         /* Enable ADC 4 */
2641         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2642         /* ASCOT setting ON */
2643         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2644         /* FEC Auto Recovery setting */
2645         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2646         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2647         /* ISDB-T initial setting */
2648         /* Set SLV-T Bank : 0x00 */
2649         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2650         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2651         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2652         /* Set SLV-T Bank : 0x10 */
2653         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2654         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2655         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2656         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2657         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2658         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2659         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2660         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2661         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2662         /* Set SLV-T Bank : 0x15 */
2663         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2664         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2665         /* Set SLV-T Bank : 0x1E */
2666         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2667         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2668         /* Set SLV-T Bank : 0x63 */
2669         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2670         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2671
2672         /* for xtal 24MHz */
2673         /* Set SLV-T Bank : 0x10 */
2674         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2675         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2676         /* Set SLV-T Bank : 0x60 */
2677         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2678         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2679
2680         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2681         /* Set SLV-T Bank : 0x00 */
2682         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2683         /* Disable HiZ Setting 1 */
2684         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2685         /* Disable HiZ Setting 2 */
2686         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2687         priv->state = STATE_ACTIVE_TC;
2688         return 0;
2689 }
2690
2691 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2692                                           u32 bandwidth)
2693 {
2694         u8 data[2] = { 0x09, 0x54 };
2695
2696         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2697         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2698         /* Set SLV-X Bank : 0x00 */
2699         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2700         /* Set demod mode */
2701         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2702         /* Set SLV-T Bank : 0x00 */
2703         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2704         /* Enable demod clock */
2705         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2706         /* Disable RF level monitor */
2707         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2708         /* Enable ADC clock */
2709         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2710         /* Enable ADC 1 */
2711         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2712         /* xtal freq 20.5MHz */
2713         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2714         /* Enable ADC 4 */
2715         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2716         /* Set SLV-T Bank : 0x10 */
2717         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2718         /* IFAGC gain settings */
2719         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2720         /* Set SLV-T Bank : 0x11 */
2721         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2722         /* BBAGC TARGET level setting */
2723         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2724         /* Set SLV-T Bank : 0x10 */
2725         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2726         /* ASCOT setting ON */
2727         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2728         /* Set SLV-T Bank : 0x40 */
2729         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2730         /* Demod setting */
2731         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2732         /* Set SLV-T Bank : 0x00 */
2733         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2734         /* TSIF setting */
2735         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2736         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2737
2738         cxd2841er_sleep_tc_to_active_c_band(priv, 8000000);
2739         /* Set SLV-T Bank : 0x00 */
2740         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2741         /* Disable HiZ Setting 1 */
2742         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2743         /* Disable HiZ Setting 2 */
2744         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2745         priv->state = STATE_ACTIVE_TC;
2746         return 0;
2747 }
2748
2749 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2750                                   struct dtv_frontend_properties *p)
2751 {
2752         enum fe_status status = 0;
2753         u16 strength = 0, snr = 0;
2754         u32 errors = 0, ber = 0;
2755         struct cxd2841er_priv *priv = fe->demodulator_priv;
2756
2757         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2758         if (priv->state == STATE_ACTIVE_S)
2759                 cxd2841er_read_status_s(fe, &status);
2760         else if (priv->state == STATE_ACTIVE_TC)
2761                 cxd2841er_read_status_tc(fe, &status);
2762
2763         if (status & FE_HAS_LOCK) {
2764                 cxd2841er_read_signal_strength(fe, &strength);
2765                 p->strength.len = 1;
2766                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2767                 p->strength.stat[0].uvalue = strength;
2768                 cxd2841er_read_snr(fe, &snr);
2769                 p->cnr.len = 1;
2770                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2771                 p->cnr.stat[0].svalue = snr;
2772                 cxd2841er_read_ucblocks(fe, &errors);
2773                 p->block_error.len = 1;
2774                 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2775                 p->block_error.stat[0].uvalue = errors;
2776                 cxd2841er_read_ber(fe, &ber);
2777                 p->post_bit_error.len = 1;
2778                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2779                 p->post_bit_error.stat[0].uvalue = ber;
2780         } else {
2781                 p->strength.len = 1;
2782                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2783                 p->cnr.len = 1;
2784                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2785                 p->block_error.len = 1;
2786                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2787                 p->post_bit_error.len = 1;
2788                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2789         }
2790         return 0;
2791 }
2792
2793 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2794 {
2795         int ret = 0, i, timeout, carr_offset;
2796         enum fe_status status;
2797         struct cxd2841er_priv *priv = fe->demodulator_priv;
2798         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2799         u32 symbol_rate = p->symbol_rate/1000;
2800
2801         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
2802                 __func__,
2803                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
2804                  p->frequency, symbol_rate, priv->xtal);
2805         switch (priv->state) {
2806         case STATE_SLEEP_S:
2807                 ret = cxd2841er_sleep_s_to_active_s(
2808                         priv, p->delivery_system, symbol_rate);
2809                 break;
2810         case STATE_ACTIVE_S:
2811                 ret = cxd2841er_retune_active(priv, p);
2812                 break;
2813         default:
2814                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2815                         __func__, priv->state);
2816                 ret = -EINVAL;
2817                 goto done;
2818         }
2819         if (ret) {
2820                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2821                 goto done;
2822         }
2823         if (fe->ops.i2c_gate_ctrl)
2824                 fe->ops.i2c_gate_ctrl(fe, 1);
2825         if (fe->ops.tuner_ops.set_params)
2826                 fe->ops.tuner_ops.set_params(fe);
2827         if (fe->ops.i2c_gate_ctrl)
2828                 fe->ops.i2c_gate_ctrl(fe, 0);
2829         cxd2841er_tune_done(priv);
2830         timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
2831         for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
2832                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
2833                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
2834                 cxd2841er_read_status_s(fe, &status);
2835                 if (status & FE_HAS_LOCK)
2836                         break;
2837         }
2838         if (status & FE_HAS_LOCK) {
2839                 if (cxd2841er_get_carrier_offset_s_s2(
2840                                 priv, &carr_offset)) {
2841                         ret = -EINVAL;
2842                         goto done;
2843                 }
2844                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
2845                         __func__, carr_offset);
2846         }
2847 done:
2848         return ret;
2849 }
2850
2851 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
2852 {
2853         int ret = 0, timeout;
2854         enum fe_status status;
2855         struct cxd2841er_priv *priv = fe->demodulator_priv;
2856         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2857
2858         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2859         if (p->delivery_system == SYS_DVBT) {
2860                 priv->system = SYS_DVBT;
2861                 switch (priv->state) {
2862                 case STATE_SLEEP_TC:
2863                         ret = cxd2841er_sleep_tc_to_active_t(
2864                                 priv, p->bandwidth_hz);
2865                         break;
2866                 case STATE_ACTIVE_TC:
2867                         ret = cxd2841er_retune_active(priv, p);
2868                         break;
2869                 default:
2870                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2871                                 __func__, priv->state);
2872                         ret = -EINVAL;
2873                 }
2874         } else if (p->delivery_system == SYS_DVBT2) {
2875                 priv->system = SYS_DVBT2;
2876                 cxd2841er_dvbt2_set_plp_config(priv,
2877                         (int)(p->stream_id > 255), p->stream_id);
2878                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
2879                 switch (priv->state) {
2880                 case STATE_SLEEP_TC:
2881                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
2882                                 p->bandwidth_hz);
2883                         break;
2884                 case STATE_ACTIVE_TC:
2885                         ret = cxd2841er_retune_active(priv, p);
2886                         break;
2887                 default:
2888                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2889                                 __func__, priv->state);
2890                         ret = -EINVAL;
2891                 }
2892         } else if (p->delivery_system == SYS_ISDBT) {
2893                 priv->system = SYS_ISDBT;
2894                 switch (priv->state) {
2895                 case STATE_SLEEP_TC:
2896                         ret = cxd2841er_sleep_tc_to_active_i(
2897                                         priv, p->bandwidth_hz);
2898                         break;
2899                 case STATE_ACTIVE_TC:
2900                         ret = cxd2841er_retune_active(priv, p);
2901                         break;
2902                 default:
2903                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2904                                         __func__, priv->state);
2905                         ret = -EINVAL;
2906                 }
2907         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
2908                         p->delivery_system == SYS_DVBC_ANNEX_C) {
2909                 priv->system = SYS_DVBC_ANNEX_A;
2910                 switch (priv->state) {
2911                 case STATE_SLEEP_TC:
2912                         ret = cxd2841er_sleep_tc_to_active_c(
2913                                 priv, p->bandwidth_hz);
2914                         break;
2915                 case STATE_ACTIVE_TC:
2916                         ret = cxd2841er_retune_active(priv, p);
2917                         break;
2918                 default:
2919                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2920                                 __func__, priv->state);
2921                         ret = -EINVAL;
2922                 }
2923         } else {
2924                 dev_dbg(&priv->i2c->dev,
2925                         "%s(): invalid delivery system %d\n",
2926                         __func__, p->delivery_system);
2927                 ret = -EINVAL;
2928         }
2929         if (ret)
2930                 goto done;
2931         if (fe->ops.i2c_gate_ctrl)
2932                 fe->ops.i2c_gate_ctrl(fe, 1);
2933         if (fe->ops.tuner_ops.set_params)
2934                 fe->ops.tuner_ops.set_params(fe);
2935         if (fe->ops.i2c_gate_ctrl)
2936                 fe->ops.i2c_gate_ctrl(fe, 0);
2937         cxd2841er_tune_done(priv);
2938         timeout = 2500;
2939         while (timeout > 0) {
2940                 ret = cxd2841er_read_status_tc(fe, &status);
2941                 if (ret)
2942                         goto done;
2943                 if (status & FE_HAS_LOCK)
2944                         break;
2945                 msleep(20);
2946                 timeout -= 20;
2947         }
2948         if (timeout < 0)
2949                 dev_dbg(&priv->i2c->dev,
2950                         "%s(): LOCK wait timeout\n", __func__);
2951 done:
2952         return ret;
2953 }
2954
2955 static int cxd2841er_tune_s(struct dvb_frontend *fe,
2956                             bool re_tune,
2957                             unsigned int mode_flags,
2958                             unsigned int *delay,
2959                             enum fe_status *status)
2960 {
2961         int ret, carrier_offset;
2962         struct cxd2841er_priv *priv = fe->demodulator_priv;
2963         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2964
2965         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
2966         if (re_tune) {
2967                 ret = cxd2841er_set_frontend_s(fe);
2968                 if (ret)
2969                         return ret;
2970                 cxd2841er_read_status_s(fe, status);
2971                 if (*status & FE_HAS_LOCK) {
2972                         if (cxd2841er_get_carrier_offset_s_s2(
2973                                         priv, &carrier_offset))
2974                                 return -EINVAL;
2975                         p->frequency += carrier_offset;
2976                         ret = cxd2841er_set_frontend_s(fe);
2977                         if (ret)
2978                                 return ret;
2979                 }
2980         }
2981         *delay = HZ / 5;
2982         return cxd2841er_read_status_s(fe, status);
2983 }
2984
2985 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
2986                              bool re_tune,
2987                              unsigned int mode_flags,
2988                              unsigned int *delay,
2989                              enum fe_status *status)
2990 {
2991         int ret, carrier_offset;
2992         struct cxd2841er_priv *priv = fe->demodulator_priv;
2993         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2994
2995         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d\n", __func__, re_tune);
2996         if (re_tune) {
2997                 ret = cxd2841er_set_frontend_tc(fe);
2998                 if (ret)
2999                         return ret;
3000                 cxd2841er_read_status_tc(fe, status);
3001                 if (*status & FE_HAS_LOCK) {
3002                         switch (priv->system) {
3003                         case SYS_ISDBT:
3004                                 ret = cxd2841er_get_carrier_offset_i(
3005                                                 priv, p->bandwidth_hz,
3006                                                 &carrier_offset);
3007                                 break;
3008                         case SYS_DVBT:
3009                                 ret = cxd2841er_get_carrier_offset_t(
3010                                         priv, p->bandwidth_hz,
3011                                         &carrier_offset);
3012                                 break;
3013                         case SYS_DVBT2:
3014                                 ret = cxd2841er_get_carrier_offset_t2(
3015                                         priv, p->bandwidth_hz,
3016                                         &carrier_offset);
3017                                 break;
3018                         case SYS_DVBC_ANNEX_A:
3019                                 ret = cxd2841er_get_carrier_offset_c(
3020                                         priv, &carrier_offset);
3021                                 break;
3022                         default:
3023                                 dev_dbg(&priv->i2c->dev,
3024                                         "%s(): invalid delivery system %d\n",
3025                                         __func__, priv->system);
3026                                 return -EINVAL;
3027                         }
3028                         if (ret)
3029                                 return ret;
3030                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3031                                 __func__, carrier_offset);
3032                         p->frequency += carrier_offset;
3033                         ret = cxd2841er_set_frontend_tc(fe);
3034                         if (ret)
3035                                 return ret;
3036                 }
3037         }
3038         *delay = HZ / 5;
3039         return cxd2841er_read_status_tc(fe, status);
3040 }
3041
3042 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3043 {
3044         struct cxd2841er_priv *priv = fe->demodulator_priv;
3045
3046         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3047         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3048         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3049         return 0;
3050 }
3051
3052 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3053 {
3054         struct cxd2841er_priv *priv = fe->demodulator_priv;
3055
3056         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3057         if (priv->state == STATE_ACTIVE_TC) {
3058                 switch (priv->system) {
3059                 case SYS_DVBT:
3060                         cxd2841er_active_t_to_sleep_tc(priv);
3061                         break;
3062                 case SYS_DVBT2:
3063                         cxd2841er_active_t2_to_sleep_tc(priv);
3064                         break;
3065                 case SYS_ISDBT:
3066                         cxd2841er_active_i_to_sleep_tc(priv);
3067                         break;
3068                 case SYS_DVBC_ANNEX_A:
3069                         cxd2841er_active_c_to_sleep_tc(priv);
3070                         break;
3071                 default:
3072                         dev_warn(&priv->i2c->dev,
3073                                 "%s(): unknown delivery system %d\n",
3074                                 __func__, priv->system);
3075                 }
3076         }
3077         if (priv->state != STATE_SLEEP_TC) {
3078                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3079                         __func__, priv->state);
3080                 return -EINVAL;
3081         }
3082         cxd2841er_sleep_tc_to_shutdown(priv);
3083         return 0;
3084 }
3085
3086 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3087                                 enum fe_sec_mini_cmd burst)
3088 {
3089         u8 data;
3090         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3091
3092         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3093                 (burst == SEC_MINI_A ? "A" : "B"));
3094         if (priv->state != STATE_SLEEP_S &&
3095                         priv->state != STATE_ACTIVE_S) {
3096                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3097                         __func__, priv->state);
3098                 return -EINVAL;
3099         }
3100         data = (burst == SEC_MINI_A ? 0 : 1);
3101         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3102         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3103         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3104         return 0;
3105 }
3106
3107 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3108                               enum fe_sec_tone_mode tone)
3109 {
3110         u8 data;
3111         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3112
3113         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3114                 (tone == SEC_TONE_ON ? "On" : "Off"));
3115         if (priv->state != STATE_SLEEP_S &&
3116                         priv->state != STATE_ACTIVE_S) {
3117                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3118                         __func__, priv->state);
3119                 return -EINVAL;
3120         }
3121         data = (tone == SEC_TONE_ON ? 1 : 0);
3122         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3123         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3124         return 0;
3125 }
3126
3127 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3128                                      struct dvb_diseqc_master_cmd *cmd)
3129 {
3130         int i;
3131         u8 data[12];
3132         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3133
3134         if (priv->state != STATE_SLEEP_S &&
3135                         priv->state != STATE_ACTIVE_S) {
3136                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3137                         __func__, priv->state);
3138                 return -EINVAL;
3139         }
3140         dev_dbg(&priv->i2c->dev,
3141                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3142         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3143         /* DiDEqC enable */
3144         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3145         /* cmd1 length & data */
3146         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3147         memset(data, 0, sizeof(data));
3148         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3149                 data[i] = cmd->msg[i];
3150         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3151         /* repeat count for cmd1 */
3152         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3153         /* repeat count for cmd2: always 0 */
3154         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3155         /* start transmit */
3156         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3157         /* wait for 1 sec timeout */
3158         for (i = 0; i < 50; i++) {
3159                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3160                 if (!data[0]) {
3161                         dev_dbg(&priv->i2c->dev,
3162                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3163                         return 0;
3164                 }
3165                 msleep(20);
3166         }
3167         dev_dbg(&priv->i2c->dev,
3168                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3169         return -ETIMEDOUT;
3170 }
3171
3172 static void cxd2841er_release(struct dvb_frontend *fe)
3173 {
3174         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3175
3176         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3177         kfree(priv);
3178 }
3179
3180 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3181 {
3182         struct cxd2841er_priv *priv = fe->demodulator_priv;
3183
3184         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3185         cxd2841er_set_reg_bits(
3186                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3187         return 0;
3188 }
3189
3190 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3191 {
3192         struct cxd2841er_priv *priv = fe->demodulator_priv;
3193
3194         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3195         return DVBFE_ALGO_HW;
3196 }
3197
3198 static int cxd2841er_init_s(struct dvb_frontend *fe)
3199 {
3200         struct cxd2841er_priv *priv = fe->demodulator_priv;
3201
3202         /* sanity. force demod to SHUTDOWN state */
3203         if (priv->state == STATE_SLEEP_S) {
3204                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3205                                 __func__);
3206                 cxd2841er_sleep_s_to_shutdown(priv);
3207         } else if (priv->state == STATE_ACTIVE_S) {
3208                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3209                                 __func__);
3210                 cxd2841er_active_s_to_sleep_s(priv);
3211                 cxd2841er_sleep_s_to_shutdown(priv);
3212         }
3213
3214         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3215         cxd2841er_shutdown_to_sleep_s(priv);
3216         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3217         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3218         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3219         return 0;
3220 }
3221
3222 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3223 {
3224         struct cxd2841er_priv *priv = fe->demodulator_priv;
3225
3226         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3227         cxd2841er_shutdown_to_sleep_tc(priv);
3228         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3229         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3230         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3231         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3232         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3233         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3234         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3235         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3236         return 0;
3237 }
3238
3239 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3240 static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops;
3241 static struct dvb_frontend_ops cxd2841er_dvbc_ops;
3242 static struct dvb_frontend_ops cxd2841er_isdbt_ops;
3243
3244 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3245                                              struct i2c_adapter *i2c,
3246                                              u8 system)
3247 {
3248         u8 chip_id = 0;
3249         const char *type;
3250         struct cxd2841er_priv *priv = NULL;
3251
3252         /* allocate memory for the internal state */
3253         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3254         if (!priv)
3255                 return NULL;
3256         priv->i2c = i2c;
3257         priv->config = cfg;
3258         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3259         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3260         priv->xtal = cfg->xtal;
3261         /* create dvb_frontend */
3262         switch (system) {
3263         case SYS_DVBS:
3264                 memcpy(&priv->frontend.ops,
3265                         &cxd2841er_dvbs_s2_ops,
3266                         sizeof(struct dvb_frontend_ops));
3267                 type = "S/S2";
3268                 break;
3269         case SYS_DVBT:
3270                 memcpy(&priv->frontend.ops,
3271                         &cxd2841er_dvbt_t2_ops,
3272                         sizeof(struct dvb_frontend_ops));
3273                 type = "T/T2";
3274                 break;
3275         case SYS_ISDBT:
3276                 memcpy(&priv->frontend.ops,
3277                                 &cxd2841er_isdbt_ops,
3278                                 sizeof(struct dvb_frontend_ops));
3279                 type = "ISDBT";
3280                 break;
3281         case SYS_DVBC_ANNEX_A:
3282                 memcpy(&priv->frontend.ops,
3283                         &cxd2841er_dvbc_ops,
3284                         sizeof(struct dvb_frontend_ops));
3285                 type = "C/C2";
3286                 break;
3287         default:
3288                 kfree(priv);
3289                 return NULL;
3290         }
3291         priv->frontend.demodulator_priv = priv;
3292         dev_info(&priv->i2c->dev,
3293                 "%s(): attaching CXD2841ER DVB-%s frontend\n",
3294                 __func__, type);
3295         dev_info(&priv->i2c->dev,
3296                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3297                 __func__, priv->i2c,
3298                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3299         chip_id = cxd2841er_chip_id(priv);
3300         if (chip_id != CXD2841ER_CHIP_ID && chip_id != CXD2854ER_CHIP_ID) {
3301                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3302                         __func__, chip_id);
3303                 priv->frontend.demodulator_priv = NULL;
3304                 kfree(priv);
3305                 return NULL;
3306         }
3307         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3308                 __func__, chip_id);
3309         return &priv->frontend;
3310 }
3311
3312 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3313                                         struct i2c_adapter *i2c)
3314 {
3315         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3316 }
3317 EXPORT_SYMBOL(cxd2841er_attach_s);
3318
3319 struct dvb_frontend *cxd2841er_attach_t(struct cxd2841er_config *cfg,
3320                                         struct i2c_adapter *i2c)
3321 {
3322         return cxd2841er_attach(cfg, i2c, SYS_DVBT);
3323 }
3324 EXPORT_SYMBOL(cxd2841er_attach_t);
3325
3326 struct dvb_frontend *cxd2841er_attach_i(struct cxd2841er_config *cfg,
3327                 struct i2c_adapter *i2c)
3328 {
3329         return cxd2841er_attach(cfg, i2c, SYS_ISDBT);
3330 }
3331 EXPORT_SYMBOL(cxd2841er_attach_i);
3332
3333 struct dvb_frontend *cxd2841er_attach_c(struct cxd2841er_config *cfg,
3334                                         struct i2c_adapter *i2c)
3335 {
3336         return cxd2841er_attach(cfg, i2c, SYS_DVBC_ANNEX_A);
3337 }
3338 EXPORT_SYMBOL(cxd2841er_attach_c);
3339
3340 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3341         .delsys = { SYS_DVBS, SYS_DVBS2 },
3342         .info = {
3343                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3344                 .frequency_min  = 500000,
3345                 .frequency_max  = 2500000,
3346                 .frequency_stepsize     = 0,
3347                 .symbol_rate_min = 1000000,
3348                 .symbol_rate_max = 45000000,
3349                 .symbol_rate_tolerance = 500,
3350                 .caps = FE_CAN_INVERSION_AUTO |
3351                         FE_CAN_FEC_AUTO |
3352                         FE_CAN_QPSK,
3353         },
3354         .init = cxd2841er_init_s,
3355         .sleep = cxd2841er_sleep_s,
3356         .release = cxd2841er_release,
3357         .set_frontend = cxd2841er_set_frontend_s,
3358         .get_frontend = cxd2841er_get_frontend,
3359         .read_status = cxd2841er_read_status_s,
3360         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3361         .get_frontend_algo = cxd2841er_get_algo,
3362         .set_tone = cxd2841er_set_tone,
3363         .diseqc_send_burst = cxd2841er_send_burst,
3364         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3365         .tune = cxd2841er_tune_s
3366 };
3367
3368 static struct  dvb_frontend_ops cxd2841er_dvbt_t2_ops = {
3369         .delsys = { SYS_DVBT, SYS_DVBT2 },
3370         .info = {
3371                 .name   = "Sony CXD2841ER DVB-T/T2 demodulator",
3372                 .caps = FE_CAN_FEC_1_2 |
3373                         FE_CAN_FEC_2_3 |
3374                         FE_CAN_FEC_3_4 |
3375                         FE_CAN_FEC_5_6 |
3376                         FE_CAN_FEC_7_8 |
3377                         FE_CAN_FEC_AUTO |
3378                         FE_CAN_QPSK |
3379                         FE_CAN_QAM_16 |
3380                         FE_CAN_QAM_32 |
3381                         FE_CAN_QAM_64 |
3382                         FE_CAN_QAM_128 |
3383                         FE_CAN_QAM_256 |
3384                         FE_CAN_QAM_AUTO |
3385                         FE_CAN_TRANSMISSION_MODE_AUTO |
3386                         FE_CAN_GUARD_INTERVAL_AUTO |
3387                         FE_CAN_HIERARCHY_AUTO |
3388                         FE_CAN_MUTE_TS |
3389                         FE_CAN_2G_MODULATION,
3390                 .frequency_min = 42000000,
3391                 .frequency_max = 1002000000
3392         },
3393         .init = cxd2841er_init_tc,
3394         .sleep = cxd2841er_sleep_tc,
3395         .release = cxd2841er_release,
3396         .set_frontend = cxd2841er_set_frontend_tc,
3397         .get_frontend = cxd2841er_get_frontend,
3398         .read_status = cxd2841er_read_status_tc,
3399         .tune = cxd2841er_tune_tc,
3400         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3401         .get_frontend_algo = cxd2841er_get_algo
3402 };
3403
3404 static struct  dvb_frontend_ops cxd2841er_isdbt_ops = {
3405         .delsys = { SYS_ISDBT },
3406         .info = {
3407                 .name   = "Sony CXD2854ER ISDBT demodulator",
3408                 .caps = FE_CAN_FEC_1_2 |
3409                         FE_CAN_FEC_2_3 |
3410                         FE_CAN_FEC_3_4 |
3411                         FE_CAN_FEC_5_6 |
3412                         FE_CAN_FEC_7_8 |
3413                         FE_CAN_FEC_AUTO |
3414                         FE_CAN_QPSK |
3415                         FE_CAN_QAM_16 |
3416                         FE_CAN_QAM_32 |
3417                         FE_CAN_QAM_64 |
3418                         FE_CAN_QAM_128 |
3419                         FE_CAN_QAM_256 |
3420                         FE_CAN_QAM_AUTO |
3421                         FE_CAN_TRANSMISSION_MODE_AUTO |
3422                         FE_CAN_GUARD_INTERVAL_AUTO |
3423                         FE_CAN_HIERARCHY_AUTO |
3424                         FE_CAN_MUTE_TS |
3425                         FE_CAN_2G_MODULATION,
3426                 .frequency_min = 42000000,
3427                 .frequency_max = 1002000000
3428         },
3429         .init = cxd2841er_init_tc,
3430         .sleep = cxd2841er_sleep_tc,
3431         .release = cxd2841er_release,
3432         .set_frontend = cxd2841er_set_frontend_tc,
3433         .get_frontend = cxd2841er_get_frontend,
3434         .read_status = cxd2841er_read_status_tc,
3435         .tune = cxd2841er_tune_tc,
3436         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3437         .get_frontend_algo = cxd2841er_get_algo
3438 };
3439
3440 static struct  dvb_frontend_ops cxd2841er_dvbc_ops = {
3441         .delsys = { SYS_DVBC_ANNEX_A },
3442         .info = {
3443                 .name   = "Sony CXD2841ER DVB-C demodulator",
3444                 .caps = FE_CAN_FEC_1_2 |
3445                         FE_CAN_FEC_2_3 |
3446                         FE_CAN_FEC_3_4 |
3447                         FE_CAN_FEC_5_6 |
3448                         FE_CAN_FEC_7_8 |
3449                         FE_CAN_FEC_AUTO |
3450                         FE_CAN_QAM_16 |
3451                         FE_CAN_QAM_32 |
3452                         FE_CAN_QAM_64 |
3453                         FE_CAN_QAM_128 |
3454                         FE_CAN_QAM_256 |
3455                         FE_CAN_QAM_AUTO |
3456                         FE_CAN_INVERSION_AUTO,
3457                 .frequency_min = 42000000,
3458                 .frequency_max = 1002000000
3459         },
3460         .init = cxd2841er_init_tc,
3461         .sleep = cxd2841er_sleep_tc,
3462         .release = cxd2841er_release,
3463         .set_frontend = cxd2841er_set_frontend_tc,
3464         .get_frontend = cxd2841er_get_frontend,
3465         .read_status = cxd2841er_read_status_tc,
3466         .tune = cxd2841er_tune_tc,
3467         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3468         .get_frontend_algo = cxd2841er_get_algo,
3469 };
3470
3471 MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3472 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
3473 MODULE_LICENSE("GPL");