2 * Linux-DVB Driver for DiBcom's DiB0090 base-band RF Tuner.
4 * Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 * This code is more or less generated from another driver, please
23 * excuse some codingstyle oddities.
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/kernel.h>
30 #include <linux/slab.h>
31 #include <linux/i2c.h>
32 #include <linux/mutex.h>
34 #include "dvb_frontend.h"
37 #include "dibx000_common.h"
40 module_param(debug, int, 0644);
41 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
43 #define dprintk(fmt, arg...) do { \
45 printk(KERN_DEBUG pr_fmt("%s: " fmt), \
49 #define CONFIG_SYS_DVBT
50 #define CONFIG_SYS_ISDBT
51 #define CONFIG_BAND_CBAND
52 #define CONFIG_BAND_VHF
53 #define CONFIG_BAND_UHF
54 #define CONFIG_DIB0090_USE_PWM_AGC
56 #define EN_LNA0 0x8000
57 #define EN_LNA1 0x4000
58 #define EN_LNA2 0x2000
59 #define EN_LNA3 0x1000
60 #define EN_MIX0 0x0800
61 #define EN_MIX1 0x0400
62 #define EN_MIX2 0x0200
63 #define EN_MIX3 0x0100
64 #define EN_IQADC 0x0040
69 #define EN_BIAS 0x0001
71 #define EN_IQANA 0x0002
72 #define EN_DIGCLK 0x0080 /* not in the 0x24 reg, only in 0x1b */
73 #define EN_CRYSTAL 0x0002
81 /* Calibration defines */
85 #define CAPTRIM_CAL 0x8
87 #define KROSUS_PLL_LOCKED 0x800
90 /* Use those defines to identify SOC version */
92 #define SOC_7090_P1G_11R1 0x82
93 #define SOC_7090_P1G_21R1 0x8a
94 #define SOC_8090_P1G_11R1 0x86
95 #define SOC_8090_P1G_21R1 0x8e
97 /* else use thos ones to check */
104 #define MP001 0x1 /* Single 9090/8096 */
105 #define MP005 0x4 /* Single Sband */
106 #define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
107 #define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
109 #define pgm_read_word(w) (*w)
111 struct dc_calibration;
113 struct dib0090_tuning {
114 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
125 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
132 struct dib0090_identity {
139 struct dib0090_state {
140 struct i2c_adapter *i2c;
141 struct dvb_frontend *fe;
142 const struct dib0090_config *config;
145 enum frontend_tune_state tune_state;
149 s16 wbd_target; /* in dB */
151 s16 rf_gain_limit; /* take-over-point: where to split between bb and rf gain */
152 s16 current_gain; /* keeps the currently programmed gain */
153 u8 agc_step; /* new binary search */
155 u16 gain[2]; /* for channel monitoring */
160 /* for the software AGC ramps */
165 /* for the captrim/dc-offset search */
173 const struct dc_calibration *dc;
176 const struct dib0090_tuning *current_tune_table_index;
177 const struct dib0090_pll *current_pll_table_index;
182 struct dib0090_identity identity;
192 u8 wbd_calibration_gain;
193 const struct dib0090_wbd_slope *current_wbd_table;
196 /* for the I2C transfer */
197 struct i2c_msg msg[2];
198 u8 i2c_write_buffer[3];
199 u8 i2c_read_buffer[2];
200 struct mutex i2c_buffer_lock;
203 struct dib0090_fw_state {
204 struct i2c_adapter *i2c;
205 struct dvb_frontend *fe;
206 struct dib0090_identity identity;
207 const struct dib0090_config *config;
209 /* for the I2C transfer */
211 u8 i2c_write_buffer[2];
212 u8 i2c_read_buffer[2];
213 struct mutex i2c_buffer_lock;
216 static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
220 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
221 dprintk("could not acquire lock\n");
225 state->i2c_write_buffer[0] = reg;
227 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
228 state->msg[0].addr = state->config->i2c_address;
229 state->msg[0].flags = 0;
230 state->msg[0].buf = state->i2c_write_buffer;
231 state->msg[0].len = 1;
232 state->msg[1].addr = state->config->i2c_address;
233 state->msg[1].flags = I2C_M_RD;
234 state->msg[1].buf = state->i2c_read_buffer;
235 state->msg[1].len = 2;
237 if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
238 pr_warn("DiB0090 I2C read failed\n");
241 ret = (state->i2c_read_buffer[0] << 8)
242 | state->i2c_read_buffer[1];
244 mutex_unlock(&state->i2c_buffer_lock);
248 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
252 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
253 dprintk("could not acquire lock\n");
257 state->i2c_write_buffer[0] = reg & 0xff;
258 state->i2c_write_buffer[1] = val >> 8;
259 state->i2c_write_buffer[2] = val & 0xff;
261 memset(state->msg, 0, sizeof(struct i2c_msg));
262 state->msg[0].addr = state->config->i2c_address;
263 state->msg[0].flags = 0;
264 state->msg[0].buf = state->i2c_write_buffer;
265 state->msg[0].len = 3;
267 if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
268 pr_warn("DiB0090 I2C write failed\n");
273 mutex_unlock(&state->i2c_buffer_lock);
277 static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
281 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
282 dprintk("could not acquire lock\n");
286 state->i2c_write_buffer[0] = reg;
288 memset(&state->msg, 0, sizeof(struct i2c_msg));
289 state->msg.addr = reg;
290 state->msg.flags = I2C_M_RD;
291 state->msg.buf = state->i2c_read_buffer;
293 if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {
294 pr_warn("DiB0090 I2C read failed\n");
297 ret = (state->i2c_read_buffer[0] << 8)
298 | state->i2c_read_buffer[1];
300 mutex_unlock(&state->i2c_buffer_lock);
304 static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
308 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
309 dprintk("could not acquire lock\n");
313 state->i2c_write_buffer[0] = val >> 8;
314 state->i2c_write_buffer[1] = val & 0xff;
316 memset(&state->msg, 0, sizeof(struct i2c_msg));
317 state->msg.addr = reg;
318 state->msg.flags = 0;
319 state->msg.buf = state->i2c_write_buffer;
321 if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {
322 pr_warn("DiB0090 I2C write failed\n");
327 mutex_unlock(&state->i2c_buffer_lock);
331 #define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0)
332 #define ADC_TARGET -220
336 static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c)
339 dib0090_write_reg(state, r++, *b++);
343 static int dib0090_identify(struct dvb_frontend *fe)
345 struct dib0090_state *state = fe->tuner_priv;
347 struct dib0090_identity *identity = &state->identity;
349 v = dib0090_read_reg(state, 0x1a);
352 identity->in_soc = 0;
354 dprintk("Tuner identification (Version = 0x%04x)\n", v);
356 /* without PLL lock info */
357 v &= ~KROSUS_PLL_LOCKED;
359 identity->version = v & 0xff;
360 identity->product = (v >> 8) & 0xf;
362 if (identity->product != KROSUS)
363 goto identification_error;
365 if ((identity->version & 0x3) == SOC) {
366 identity->in_soc = 1;
367 switch (identity->version) {
368 case SOC_8090_P1G_11R1:
369 dprintk("SOC 8090 P1-G11R1 Has been detected\n");
372 case SOC_8090_P1G_21R1:
373 dprintk("SOC 8090 P1-G21R1 Has been detected\n");
376 case SOC_7090_P1G_11R1:
377 dprintk("SOC 7090 P1-G11R1 Has been detected\n");
380 case SOC_7090_P1G_21R1:
381 dprintk("SOC 7090 P1-G21R1 Has been detected\n");
385 goto identification_error;
388 switch ((identity->version >> 5) & 0x7) {
390 dprintk("MP001 : 9090/8096\n");
393 dprintk("MP005 : Single Sband\n");
396 dprintk("MP008 : diversity VHF-UHF-LBAND\n");
399 dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND\n");
402 goto identification_error;
405 switch (identity->version & 0x1f) {
407 dprintk("P1G_21R2 detected\n");
411 dprintk("P1G detected\n");
415 dprintk("P1D/E/F detected\n");
418 dprintk("P1C detected\n");
421 dprintk("P1-A/B detected: driver is deactivated - not available\n");
422 goto identification_error;
425 goto identification_error;
431 identification_error:
435 static int dib0090_fw_identify(struct dvb_frontend *fe)
437 struct dib0090_fw_state *state = fe->tuner_priv;
438 struct dib0090_identity *identity = &state->identity;
440 u16 v = dib0090_fw_read_reg(state, 0x1a);
442 identity->in_soc = 0;
444 dprintk("FE: Tuner identification (Version = 0x%04x)\n", v);
446 /* without PLL lock info */
447 v &= ~KROSUS_PLL_LOCKED;
449 identity->version = v & 0xff;
450 identity->product = (v >> 8) & 0xf;
452 if (identity->product != KROSUS)
453 goto identification_error;
455 if ((identity->version & 0x3) == SOC) {
456 identity->in_soc = 1;
457 switch (identity->version) {
458 case SOC_8090_P1G_11R1:
459 dprintk("SOC 8090 P1-G11R1 Has been detected\n");
462 case SOC_8090_P1G_21R1:
463 dprintk("SOC 8090 P1-G21R1 Has been detected\n");
466 case SOC_7090_P1G_11R1:
467 dprintk("SOC 7090 P1-G11R1 Has been detected\n");
470 case SOC_7090_P1G_21R1:
471 dprintk("SOC 7090 P1-G21R1 Has been detected\n");
475 goto identification_error;
478 switch ((identity->version >> 5) & 0x7) {
480 dprintk("MP001 : 9090/8096\n");
483 dprintk("MP005 : Single Sband\n");
486 dprintk("MP008 : diversity VHF-UHF-LBAND\n");
489 dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND\n");
492 goto identification_error;
495 switch (identity->version & 0x1f) {
497 dprintk("P1G_21R2 detected\n");
501 dprintk("P1G detected\n");
505 dprintk("P1D/E/F detected\n");
508 dprintk("P1C detected\n");
511 dprintk("P1-A/B detected: driver is deactivated - not available\n");
512 goto identification_error;
515 goto identification_error;
521 identification_error:
525 static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
527 struct dib0090_state *state = fe->tuner_priv;
531 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
535 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
536 /* adcClkOutRatio=8->7, release reset */
537 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
538 if (cfg->clkoutdrive != 0)
539 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
540 | (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
542 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
543 | (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
545 /* Read Pll current config * */
546 PllCfg = dib0090_read_reg(state, 0x21);
548 /** Reconfigure PLL if current setting is different from default setting **/
549 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
550 && !cfg->io.pll_bypass) {
552 /* Set Bypass mode */
554 dib0090_write_reg(state, 0x21, PllCfg);
557 PllCfg &= ~(1 << 13);
558 dib0090_write_reg(state, 0x21, PllCfg);
560 /*** Set new Pll configuration in bypass and reset state ***/
561 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
562 dib0090_write_reg(state, 0x21, PllCfg);
564 /* Remove Reset Pll */
566 dib0090_write_reg(state, 0x21, PllCfg);
568 /*** Wait for PLL lock ***/
571 v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
577 dprintk("Pll: Unable to lock Pll\n");
581 /* Finally Remove Bypass mode */
582 PllCfg &= ~(1 << 15);
583 dib0090_write_reg(state, 0x21, PllCfg);
586 if (cfg->io.pll_bypass) {
587 PllCfg |= (cfg->io.pll_bypass << 15);
588 dib0090_write_reg(state, 0x21, PllCfg);
592 static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
594 struct dib0090_fw_state *state = fe->tuner_priv;
599 dprintk("fw reset digital\n");
602 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
603 dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
605 dib0090_fw_write_reg(state, 0x20,
606 ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) | cfg->ls_cfg_pad_drv);
608 v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
609 if (cfg->clkoutdrive != 0)
610 v |= cfg->clkoutdrive << 5;
615 dib0090_fw_write_reg(state, 0x23, v);
617 /* Read Pll current config * */
618 PllCfg = dib0090_fw_read_reg(state, 0x21);
620 /** Reconfigure PLL if current setting is different from default setting **/
621 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
623 /* Set Bypass mode */
625 dib0090_fw_write_reg(state, 0x21, PllCfg);
628 PllCfg &= ~(1 << 13);
629 dib0090_fw_write_reg(state, 0x21, PllCfg);
631 /*** Set new Pll configuration in bypass and reset state ***/
632 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
633 dib0090_fw_write_reg(state, 0x21, PllCfg);
635 /* Remove Reset Pll */
637 dib0090_fw_write_reg(state, 0x21, PllCfg);
639 /*** Wait for PLL lock ***/
642 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
648 dprintk("Pll: Unable to lock Pll\n");
652 /* Finally Remove Bypass mode */
653 PllCfg &= ~(1 << 15);
654 dib0090_fw_write_reg(state, 0x21, PllCfg);
657 if (cfg->io.pll_bypass) {
658 PllCfg |= (cfg->io.pll_bypass << 15);
659 dib0090_fw_write_reg(state, 0x21, PllCfg);
662 return dib0090_fw_identify(fe);
665 static int dib0090_wakeup(struct dvb_frontend *fe)
667 struct dib0090_state *state = fe->tuner_priv;
668 if (state->config->sleep)
669 state->config->sleep(fe, 0);
671 /* enable dataTX in case we have been restarted in the wrong moment */
672 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
676 static int dib0090_sleep(struct dvb_frontend *fe)
678 struct dib0090_state *state = fe->tuner_priv;
679 if (state->config->sleep)
680 state->config->sleep(fe, 1);
684 void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
686 struct dib0090_state *state = fe->tuner_priv;
688 dib0090_write_reg(state, 0x04, 0);
690 dib0090_write_reg(state, 0x04, 1);
693 EXPORT_SYMBOL(dib0090_dcc_freq);
695 static const u16 bb_ramp_pwm_normal_socs[] = {
696 550, /* max BB gain in 10th of dB */
697 (1<<9) | 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
699 (4 << 9) | 0, /* BB_RAMP3 = 26dB */
700 (0 << 9) | 208, /* BB_RAMP4 */
701 (4 << 9) | 208, /* BB_RAMP5 = 29dB */
702 (0 << 9) | 440, /* BB_RAMP6 */
705 static const u16 rf_ramp_pwm_cband_7090p[] = {
706 280, /* max RF gain in 10th of dB */
707 18, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
708 504, /* ramp_max = maximum X used on the ramp */
709 (29 << 10) | 364, /* RF_RAMP5, LNA 1 = 8dB */
710 (0 << 10) | 504, /* RF_RAMP6, LNA 1 */
711 (60 << 10) | 228, /* RF_RAMP7, LNA 2 = 7.7dB */
712 (0 << 10) | 364, /* RF_RAMP8, LNA 2 */
713 (34 << 10) | 109, /* GAIN_4_1, LNA 3 = 6.8dB */
714 (0 << 10) | 228, /* GAIN_4_2, LNA 3 */
715 (37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
716 (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
719 static const u16 rf_ramp_pwm_cband_7090e_sensitivity[] = {
720 186, /* max RF gain in 10th of dB */
721 40, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
722 746, /* ramp_max = maximum X used on the ramp */
723 (10 << 10) | 345, /* RF_RAMP5, LNA 1 = 10dB */
724 (0 << 10) | 746, /* RF_RAMP6, LNA 1 */
725 (0 << 10) | 0, /* RF_RAMP7, LNA 2 = 0 dB */
726 (0 << 10) | 0, /* RF_RAMP8, LNA 2 */
727 (28 << 10) | 200, /* GAIN_4_1, LNA 3 = 6.8dB */ /* 3.61 dB */
728 (0 << 10) | 345, /* GAIN_4_2, LNA 3 */
729 (20 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */ /* 4.96 dB */
730 (0 << 10) | 200, /* RF_RAMP4, LNA 4 */
733 static const u16 rf_ramp_pwm_cband_7090e_aci[] = {
734 86, /* max RF gain in 10th of dB */
735 40, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
736 345, /* ramp_max = maximum X used on the ramp */
737 (0 << 10) | 0, /* RF_RAMP5, LNA 1 = 8dB */ /* 7.47 dB */
738 (0 << 10) | 0, /* RF_RAMP6, LNA 1 */
739 (0 << 10) | 0, /* RF_RAMP7, LNA 2 = 0 dB */
740 (0 << 10) | 0, /* RF_RAMP8, LNA 2 */
741 (28 << 10) | 200, /* GAIN_4_1, LNA 3 = 6.8dB */ /* 3.61 dB */
742 (0 << 10) | 345, /* GAIN_4_2, LNA 3 */
743 (20 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */ /* 4.96 dB */
744 (0 << 10) | 200, /* RF_RAMP4, LNA 4 */
747 static const u16 rf_ramp_pwm_cband_8090[] = {
748 345, /* max RF gain in 10th of dB */
749 29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
750 1000, /* ramp_max = maximum X used on the ramp */
751 (35 << 10) | 772, /* RF_RAMP3, LNA 1 = 8dB */
752 (0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
753 (58 << 10) | 496, /* RF_RAMP5, LNA 2 = 9.5dB */
754 (0 << 10) | 772, /* RF_RAMP6, LNA 2 */
755 (27 << 10) | 200, /* RF_RAMP7, LNA 3 = 10.5dB */
756 (0 << 10) | 496, /* RF_RAMP8, LNA 3 */
757 (40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
758 (0 << 10) | 200, /* GAIN_4_2, LNA 4 */
761 static const u16 rf_ramp_pwm_uhf_7090[] = {
762 407, /* max RF gain in 10th of dB */
763 13, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
764 529, /* ramp_max = maximum X used on the ramp */
765 (23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
766 (0 << 10) | 176, /* RF_RAMP4, LNA 1 */
767 (63 << 10) | 400, /* RF_RAMP5, LNA 2 = 8dB */
768 (0 << 10) | 529, /* RF_RAMP6, LNA 2 */
769 (48 << 10) | 316, /* RF_RAMP7, LNA 3 = 6.8dB */
770 (0 << 10) | 400, /* RF_RAMP8, LNA 3 */
771 (29 << 10) | 176, /* GAIN_4_1, LNA 4 = 11.5dB */
772 (0 << 10) | 316, /* GAIN_4_2, LNA 4 */
775 static const u16 rf_ramp_pwm_uhf_8090[] = {
776 388, /* max RF gain in 10th of dB */
777 26, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
778 1008, /* ramp_max = maximum X used on the ramp */
779 (11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
780 (0 << 10) | 369, /* RF_RAMP4, LNA 1 */
781 (41 << 10) | 809, /* RF_RAMP5, LNA 2 = 8dB */
782 (0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
783 (27 << 10) | 659, /* RF_RAMP7, LNA 3 = 6dB */
784 (0 << 10) | 809, /* RF_RAMP8, LNA 3 */
785 (14 << 10) | 369, /* GAIN_4_1, LNA 4 = 11.5dB */
786 (0 << 10) | 659, /* GAIN_4_2, LNA 4 */
789 /* GENERAL PWM ramp definition for all other Krosus */
790 static const u16 bb_ramp_pwm_normal[] = {
791 500, /* max BB gain in 10th of dB */
792 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
794 (2 << 9) | 0, /* BB_RAMP3 = 21dB */
795 (0 << 9) | 168, /* BB_RAMP4 */
796 (2 << 9) | 168, /* BB_RAMP5 = 29dB */
797 (0 << 9) | 400, /* BB_RAMP6 */
801 /* Currently unused */
802 static const u16 bb_ramp_pwm_boost[] = {
803 550, /* max BB gain in 10th of dB */
804 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
806 (2 << 9) | 0, /* BB_RAMP3 = 26dB */
807 (0 << 9) | 208, /* BB_RAMP4 */
808 (2 << 9) | 208, /* BB_RAMP5 = 29dB */
809 (0 << 9) | 440, /* BB_RAMP6 */
813 static const u16 rf_ramp_pwm_cband[] = {
814 314, /* max RF gain in 10th of dB */
815 33, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
816 1023, /* ramp_max = maximum X used on the ramp */
817 (8 << 10) | 743, /* RF_RAMP3, LNA 1 = 0dB */
818 (0 << 10) | 1023, /* RF_RAMP4, LNA 1 */
819 (15 << 10) | 469, /* RF_RAMP5, LNA 2 = 0dB */
820 (0 << 10) | 742, /* RF_RAMP6, LNA 2 */
821 (9 << 10) | 234, /* RF_RAMP7, LNA 3 = 0dB */
822 (0 << 10) | 468, /* RF_RAMP8, LNA 3 */
823 (9 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
824 (0 << 10) | 233, /* GAIN_4_2, LNA 4 */
827 static const u16 rf_ramp_pwm_vhf[] = {
828 398, /* max RF gain in 10th of dB */
829 24, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
830 954, /* ramp_max = maximum X used on the ramp */
831 (7 << 10) | 0, /* RF_RAMP3, LNA 1 = 13.2dB */
832 (0 << 10) | 290, /* RF_RAMP4, LNA 1 */
833 (16 << 10) | 699, /* RF_RAMP5, LNA 2 = 10.5dB */
834 (0 << 10) | 954, /* RF_RAMP6, LNA 2 */
835 (17 << 10) | 580, /* RF_RAMP7, LNA 3 = 5dB */
836 (0 << 10) | 699, /* RF_RAMP8, LNA 3 */
837 (7 << 10) | 290, /* GAIN_4_1, LNA 4 = 12.5dB */
838 (0 << 10) | 580, /* GAIN_4_2, LNA 4 */
841 static const u16 rf_ramp_pwm_uhf[] = {
842 398, /* max RF gain in 10th of dB */
843 24, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
844 954, /* ramp_max = maximum X used on the ramp */
845 (7 << 10) | 0, /* RF_RAMP3, LNA 1 = 13.2dB */
846 (0 << 10) | 290, /* RF_RAMP4, LNA 1 */
847 (16 << 10) | 699, /* RF_RAMP5, LNA 2 = 10.5dB */
848 (0 << 10) | 954, /* RF_RAMP6, LNA 2 */
849 (17 << 10) | 580, /* RF_RAMP7, LNA 3 = 5dB */
850 (0 << 10) | 699, /* RF_RAMP8, LNA 3 */
851 (7 << 10) | 290, /* GAIN_4_1, LNA 4 = 12.5dB */
852 (0 << 10) | 580, /* GAIN_4_2, LNA 4 */
856 /* Currently unused */
857 static const u16 rf_ramp_pwm_sband[] = {
858 253, /* max RF gain in 10th of dB */
859 38, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
861 (4 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.1dB */
862 (0 << 10) | 508, /* RF_RAMP4, LNA 1 */
863 (9 << 10) | 508, /* RF_RAMP5, LNA 2 = 11.2dB */
864 (0 << 10) | 961, /* RF_RAMP6, LNA 2 */
865 (0 << 10) | 0, /* RF_RAMP7, LNA 3 = 0dB */
866 (0 << 10) | 0, /* RF_RAMP8, LNA 3 */
867 (0 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
868 (0 << 10) | 0, /* GAIN_4_2, LNA 4 */
876 static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
881 for (i = 0; i < num; i++) {
882 if (val > slopes[i].range)
883 rest = slopes[i].range;
886 ret += (rest * slopes[i].slope) / slopes[i].range;
892 static const struct slope dib0090_wbd_slopes[3] = {
893 {66, 120}, /* -64,-52: offset - 65 */
894 {600, 170}, /* -52,-35: 65 - 665 */
895 {170, 250}, /* -45,-10: 665 - 835 */
898 static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd)
901 if (wbd < state->wbd_offset)
904 wbd -= state->wbd_offset;
905 /* -64dB is the floor */
906 return -640 + (s16) slopes_to_scale(dib0090_wbd_slopes, ARRAY_SIZE(dib0090_wbd_slopes), wbd);
909 static void dib0090_wbd_target(struct dib0090_state *state, u32 rf)
913 /* TODO : DAB digital N+/-1 interferer perfs : offset = 10 */
915 if (state->current_band == BAND_VHF)
917 #ifndef FIRMWARE_FIREFLY
918 if (state->current_band == BAND_VHF)
919 offset = state->config->wbd_vhf_offset;
920 if (state->current_band == BAND_CBAND)
921 offset = state->config->wbd_cband_offset;
924 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset);
925 dprintk("wbd-target: %d dB\n", (u32) state->wbd_target);
928 static const int gain_reg_addr[4] = {
929 0x08, 0x0a, 0x0f, 0x01
932 static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force)
935 u16 i, v, gain_reg[4] = { 0 }, gain;
938 if (top_delta < -511)
944 top_delta *= (1 << WBD_ALPHA);
945 gain_delta *= (1 << GAIN_ALPHA);
948 if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit)) /* overflow */
949 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
951 state->rf_gain_limit += top_delta;
953 if (state->rf_gain_limit < 0) /*underflow */
954 state->rf_gain_limit = 0;
956 /* use gain as a temporary variable and correct current_gain */
957 gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA;
958 if (gain_delta >= ((s16) gain - state->current_gain)) /* overflow */
959 state->current_gain = gain;
961 state->current_gain += gain_delta;
962 /* cannot be less than 0 (only if gain_delta is less than 0 we can have current_gain < 0) */
963 if (state->current_gain < 0)
964 state->current_gain = 0;
966 /* now split total gain to rf and bb gain */
967 gain = state->current_gain >> GAIN_ALPHA;
969 /* requested gain is bigger than rf gain limit - ACI/WBD adjustment */
970 if (gain > (state->rf_gain_limit >> WBD_ALPHA)) {
971 rf = state->rf_gain_limit >> WBD_ALPHA;
973 if (bb > state->bb_ramp[0])
974 bb = state->bb_ramp[0];
975 } else { /* high signal level -> all gains put on RF */
984 /* Start with RF gains */
985 g = state->rf_ramp + 1; /* point on RF LNA1 max gain */
987 for (i = 0; i < 7; i++) { /* Go over all amplifiers => 5RF amps + 2 BB amps = 7 amps */
988 if (g[0] == 0 || ref < (g[1] - g[0])) /* if total gain of the current amp is null or this amp is not concerned because it starts to work from an higher gain value */
989 v = 0; /* force the gain to write for the current amp to be null */
990 else if (ref >= g[1]) /* Gain to set is higher than the high working point of this amp */
991 v = g[2]; /* force this amp to be full gain */
992 else /* compute the value to set to this amp because we are somewhere in his range */
993 v = ((ref - (g[1] - g[0])) * g[2]) / g[0];
995 if (i == 0) /* LNA 1 reg mapping */
997 else if (i == 1) /* LNA 2 reg mapping */
998 gain_reg[0] |= v << 7;
999 else if (i == 2) /* LNA 3 reg mapping */
1001 else if (i == 3) /* LNA 4 reg mapping */
1002 gain_reg[1] |= v << 7;
1003 else if (i == 4) /* CBAND LNA reg mapping */
1004 gain_reg[2] = v | state->rf_lt_def;
1005 else if (i == 5) /* BB gain 1 reg mapping */
1006 gain_reg[3] = v << 3;
1007 else if (i == 6) /* BB gain 2 reg mapping */
1008 gain_reg[3] |= v << 8;
1010 g += 3; /* go to next gain bloc */
1012 /* When RF is finished, start with BB */
1014 g = state->bb_ramp + 1; /* point on BB gain 1 max gain */
1018 gain_reg[3] |= state->bb_1_def;
1019 gain_reg[3] |= ((bb % 10) * 100) / 125;
1022 dprintk("GA CALC: DB: %3d(rf) + %3d(bb) = %3d gain_reg[0]=%04x gain_reg[1]=%04x gain_reg[2]=%04x gain_reg[0]=%04x\n", rf, bb, rf + bb,
1023 gain_reg[0], gain_reg[1], gain_reg[2], gain_reg[3]);
1026 /* Write the amplifier regs */
1027 for (i = 0; i < 4; i++) {
1029 if (force || state->gain_reg[i] != v) {
1030 state->gain_reg[i] = v;
1031 dib0090_write_reg(state, gain_reg_addr[i], v);
1036 static void dib0090_set_boost(struct dib0090_state *state, int onoff)
1038 state->bb_1_def &= 0xdfff;
1039 state->bb_1_def |= onoff << 13;
1042 static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg)
1044 state->rf_ramp = cfg;
1047 static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg)
1049 state->rf_ramp = cfg;
1051 dib0090_write_reg(state, 0x2a, 0xffff);
1053 dprintk("total RF gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x2a));
1055 dib0090_write_regs(state, 0x2c, cfg + 3, 6);
1056 dib0090_write_regs(state, 0x3e, cfg + 9, 2);
1059 static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg)
1061 state->bb_ramp = cfg;
1062 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
1065 static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg)
1067 state->bb_ramp = cfg;
1069 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
1071 dib0090_write_reg(state, 0x33, 0xffff);
1072 dprintk("total BB gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x33));
1073 dib0090_write_regs(state, 0x35, cfg + 3, 4);
1076 void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
1078 struct dib0090_state *state = fe->tuner_priv;
1079 u16 *bb_ramp = (u16 *)&bb_ramp_pwm_normal; /* default baseband config */
1080 u16 *rf_ramp = NULL;
1081 u8 en_pwm_rf_mux = 1;
1084 if (state->config->use_pwm_agc) {
1085 if (state->current_band == BAND_CBAND) {
1086 if (state->identity.in_soc) {
1087 bb_ramp = (u16 *)&bb_ramp_pwm_normal_socs;
1088 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1089 rf_ramp = (u16 *)&rf_ramp_pwm_cband_8090;
1090 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) {
1091 if (state->config->is_dib7090e) {
1092 if (state->rf_ramp == NULL)
1093 rf_ramp = (u16 *)&rf_ramp_pwm_cband_7090e_sensitivity;
1095 rf_ramp = (u16 *)state->rf_ramp;
1097 rf_ramp = (u16 *)&rf_ramp_pwm_cband_7090p;
1100 rf_ramp = (u16 *)&rf_ramp_pwm_cband;
1103 if (state->current_band == BAND_VHF) {
1104 if (state->identity.in_soc) {
1105 bb_ramp = (u16 *)&bb_ramp_pwm_normal_socs;
1106 /* rf_ramp = &rf_ramp_pwm_vhf_socs; */ /* TODO */
1108 rf_ramp = (u16 *)&rf_ramp_pwm_vhf;
1109 } else if (state->current_band == BAND_UHF) {
1110 if (state->identity.in_soc) {
1111 bb_ramp = (u16 *)&bb_ramp_pwm_normal_socs;
1112 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1113 rf_ramp = (u16 *)&rf_ramp_pwm_uhf_8090;
1114 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
1115 rf_ramp = (u16 *)&rf_ramp_pwm_uhf_7090;
1117 rf_ramp = (u16 *)&rf_ramp_pwm_uhf;
1120 dib0090_set_rframp_pwm(state, rf_ramp);
1121 dib0090_set_bbramp_pwm(state, bb_ramp);
1123 /* activate the ramp generator using PWM control */
1125 dprintk("ramp RF gain = %d BAND = %s version = %d\n",
1127 (state->current_band == BAND_CBAND) ? "CBAND" : "NOT CBAND",
1128 state->identity.version & 0x1f);
1130 if (rf_ramp && ((state->rf_ramp && state->rf_ramp[0] == 0) ||
1131 (state->current_band == BAND_CBAND &&
1132 (state->identity.version & 0x1f) <= P1D_E_F))) {
1133 dprintk("DE-Engage mux for direct gain reg control\n");
1136 dprintk("Engage mux for PWM control\n");
1138 dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11));
1140 /* Set fast servo cutoff to start AGC; 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast*/
1141 if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
1142 dib0090_write_reg(state, 0x04, 3);
1144 dib0090_write_reg(state, 0x04, 1);
1145 dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */
1148 EXPORT_SYMBOL(dib0090_pwm_gain_reset);
1150 void dib0090_set_dc_servo(struct dvb_frontend *fe, u8 DC_servo_cutoff)
1152 struct dib0090_state *state = fe->tuner_priv;
1153 if (DC_servo_cutoff < 4)
1154 dib0090_write_reg(state, 0x04, DC_servo_cutoff);
1156 EXPORT_SYMBOL(dib0090_set_dc_servo);
1158 static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
1160 u16 adc_val = dib0090_read_reg(state, 0x1d);
1161 if (state->identity.in_soc)
1166 int dib0090_gain_control(struct dvb_frontend *fe)
1168 struct dib0090_state *state = fe->tuner_priv;
1169 enum frontend_tune_state *tune_state = &state->tune_state;
1173 u8 apply_gain_immediatly = 1;
1174 s16 wbd_error = 0, adc_error = 0;
1176 if (*tune_state == CT_AGC_START) {
1177 state->agc_freeze = 0;
1178 dib0090_write_reg(state, 0x04, 0x0);
1180 #ifdef CONFIG_BAND_SBAND
1181 if (state->current_band == BAND_SBAND) {
1182 dib0090_set_rframp(state, rf_ramp_sband);
1183 dib0090_set_bbramp(state, bb_ramp_boost);
1186 #ifdef CONFIG_BAND_VHF
1187 if (state->current_band == BAND_VHF && !state->identity.p1g) {
1188 dib0090_set_rframp(state, rf_ramp_pwm_vhf);
1189 dib0090_set_bbramp(state, bb_ramp_pwm_normal);
1192 #ifdef CONFIG_BAND_CBAND
1193 if (state->current_band == BAND_CBAND && !state->identity.p1g) {
1194 dib0090_set_rframp(state, rf_ramp_pwm_cband);
1195 dib0090_set_bbramp(state, bb_ramp_pwm_normal);
1198 if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) {
1199 dib0090_set_rframp(state, rf_ramp_pwm_cband_7090p);
1200 dib0090_set_bbramp(state, bb_ramp_pwm_normal_socs);
1202 dib0090_set_rframp(state, rf_ramp_pwm_uhf);
1203 dib0090_set_bbramp(state, bb_ramp_pwm_normal);
1206 dib0090_write_reg(state, 0x32, 0);
1207 dib0090_write_reg(state, 0x39, 0);
1209 dib0090_wbd_target(state, state->current_rf);
1211 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
1212 state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA;
1214 *tune_state = CT_AGC_STEP_0;
1215 } else if (!state->agc_freeze) {
1216 s16 wbd = 0, i, cnt;
1219 wbd_val = dib0090_get_slow_adc_val(state);
1221 if (*tune_state == CT_AGC_STEP_0)
1226 for (i = 0; i < cnt; i++) {
1227 wbd_val = dib0090_get_slow_adc_val(state);
1228 wbd += dib0090_wbd_to_db(state, wbd_val);
1231 wbd_error = state->wbd_target - wbd;
1233 if (*tune_state == CT_AGC_STEP_0) {
1234 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {
1235 #ifdef CONFIG_BAND_CBAND
1236 /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
1237 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
1238 if (state->current_band == BAND_CBAND && ltg2) {
1240 state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */
1244 state->agc_step = 0;
1245 *tune_state = CT_AGC_STEP_1;
1248 /* calc the adc power */
1249 adc = state->config->get_adc_power(fe);
1250 adc = (adc * ((s32) 355774) + (((s32) 1) << 20)) >> 21; /* included in [0:-700] */
1252 adc_error = (s16) (((s32) ADC_TARGET) - adc);
1253 #ifdef CONFIG_STANDARD_DAB
1254 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
1257 #ifdef CONFIG_STANDARD_DVBT
1258 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
1259 (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
1262 #ifdef CONFIG_SYS_ISDBT
1263 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
1266 ((state->fe->dtv_property_cache.layer[0].modulation ==
1268 || (state->fe->dtv_property_cache.
1269 layer[0].modulation == QAM_16)))
1271 ((state->fe->dtv_property_cache.layer[1].segment_count >
1274 ((state->fe->dtv_property_cache.layer[1].modulation ==
1276 || (state->fe->dtv_property_cache.
1277 layer[1].modulation == QAM_16)))
1279 ((state->fe->dtv_property_cache.layer[2].segment_count >
1282 ((state->fe->dtv_property_cache.layer[2].modulation ==
1284 || (state->fe->dtv_property_cache.
1285 layer[2].modulation == QAM_16)))
1291 if (*tune_state == CT_AGC_STEP_1) { /* quickly go to the correct range of the ADC power */
1292 if (ABS(adc_error) < 50 || state->agc_step++ > 5) {
1294 #ifdef CONFIG_STANDARD_DAB
1295 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) {
1296 dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */
1297 dib0090_write_reg(state, 0x04, 0x0);
1301 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32));
1302 dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */
1305 *tune_state = CT_AGC_STOP;
1308 /* everything higher than or equal to CT_AGC_STOP means tracking */
1309 ret = 100; /* 10ms interval */
1310 apply_gain_immediatly = 0;
1315 ("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
1316 (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
1317 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
1322 if (!state->agc_freeze)
1323 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
1327 EXPORT_SYMBOL(dib0090_gain_control);
1329 void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
1331 struct dib0090_state *state = fe->tuner_priv;
1333 *rf = state->gain[0];
1335 *bb = state->gain[1];
1337 *rf_gain_limit = state->rf_gain_limit;
1339 *rflt = (state->rf_lt_def >> 10) & 0x7;
1342 EXPORT_SYMBOL(dib0090_get_current_gain);
1344 u16 dib0090_get_wbd_target(struct dvb_frontend *fe)
1346 struct dib0090_state *state = fe->tuner_priv;
1347 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
1348 s32 current_temp = state->temperature;
1349 s32 wbd_thot, wbd_tcold;
1350 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1352 while (f_MHz > wbd->max_freq)
1355 dprintk("using wbd-table-entry with max freq %d\n", wbd->max_freq);
1357 if (current_temp < 0)
1359 if (current_temp > 128)
1362 state->wbdmux &= ~(7 << 13);
1363 if (wbd->wbd_gain != 0)
1364 state->wbdmux |= (wbd->wbd_gain << 13);
1366 state->wbdmux |= (4 << 13);
1368 dib0090_write_reg(state, 0x10, state->wbdmux);
1370 wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
1371 wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
1373 wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
1375 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);
1376 dprintk("wbd-target: %d dB\n", (u32) state->wbd_target);
1377 dprintk("wbd offset applied is %d\n", wbd_tcold);
1379 return state->wbd_offset + wbd_tcold;
1381 EXPORT_SYMBOL(dib0090_get_wbd_target);
1383 u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
1385 struct dib0090_state *state = fe->tuner_priv;
1386 return state->wbd_offset;
1388 EXPORT_SYMBOL(dib0090_get_wbd_offset);
1390 int dib0090_set_switch(struct dvb_frontend *fe, u8 sw1, u8 sw2, u8 sw3)
1392 struct dib0090_state *state = fe->tuner_priv;
1394 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8)
1395 | ((sw3 & 1) << 2) | ((sw2 & 1) << 1) | (sw1 & 1));
1399 EXPORT_SYMBOL(dib0090_set_switch);
1401 int dib0090_set_vga(struct dvb_frontend *fe, u8 onoff)
1403 struct dib0090_state *state = fe->tuner_priv;
1405 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff)
1406 | ((onoff & 1) << 15));
1409 EXPORT_SYMBOL(dib0090_set_vga);
1411 int dib0090_update_rframp_7090(struct dvb_frontend *fe, u8 cfg_sensitivity)
1413 struct dib0090_state *state = fe->tuner_priv;
1415 if ((!state->identity.p1g) || (!state->identity.in_soc)
1416 || ((state->identity.version != SOC_7090_P1G_21R1)
1417 && (state->identity.version != SOC_7090_P1G_11R1))) {
1418 dprintk("%s() function can only be used for dib7090P\n", __func__);
1422 if (cfg_sensitivity)
1423 state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_sensitivity;
1425 state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_aci;
1426 dib0090_pwm_gain_reset(fe);
1430 EXPORT_SYMBOL(dib0090_update_rframp_7090);
1432 static const u16 dib0090_defaults[] = {
1472 EN_UHF | EN_CRYSTAL,
1480 static const u16 dib0090_p1g_additionnal_defaults[] = {
1495 static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)
1499 l = pgm_read_word(n++);
1501 r = pgm_read_word(n++);
1503 dib0090_write_reg(state, r, pgm_read_word(n++));
1506 l = pgm_read_word(n++);
1510 #define CAP_VALUE_MIN (u8) 9
1511 #define CAP_VALUE_MAX (u8) 40
1512 #define HR_MIN (u8) 25
1513 #define HR_MAX (u8) 40
1514 #define POLY_MIN (u8) 0
1515 #define POLY_MAX (u8) 8
1517 static void dib0090_set_EFUSE(struct dib0090_state *state)
1523 e2 = dib0090_read_reg(state, 0x26);
1524 e4 = dib0090_read_reg(state, 0x28);
1526 if ((state->identity.version == P1D_E_F) ||
1527 (state->identity.version == P1G) || (e2 == 0xffff)) {
1529 dib0090_write_reg(state, 0x22, 0x10);
1530 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;
1532 if ((cal < 670) || (cal == 1023))
1534 n = 165 - ((cal * 10)>>6) ;
1535 e2 = e4 = (3<<12) | (34<<6) | (n);
1539 e2 &= e4; /* Remove the redundancy */
1543 n = (e2 >> 12) & 0xf;
1544 h = (e2 >> 6) & 0x3f;
1546 if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
1550 if ((h >= HR_MAX) || (h <= HR_MIN))
1552 if ((n >= POLY_MAX) || (n <= POLY_MIN))
1555 dib0090_write_reg(state, 0x13, (h << 10));
1556 e2 = (n << 11) | ((h >> 2)<<6) | c;
1557 dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */
1561 static int dib0090_reset(struct dvb_frontend *fe)
1563 struct dib0090_state *state = fe->tuner_priv;
1565 dib0090_reset_digital(fe, state->config);
1566 if (dib0090_identify(fe) < 0)
1569 #ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
1570 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */
1574 if (!state->identity.in_soc) {
1575 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
1576 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1578 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1581 dib0090_set_default_config(state, dib0090_defaults);
1583 if (state->identity.in_soc)
1584 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
1586 if (state->identity.p1g)
1587 dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
1589 /* Update the efuse : Only available for KROSUS > P1C and SOC as well*/
1590 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc))
1591 dib0090_set_EFUSE(state);
1593 /* Congigure in function of the crystal */
1594 if (state->config->force_crystal_mode != 0)
1595 dib0090_write_reg(state, 0x14,
1596 state->config->force_crystal_mode & 3);
1597 else if (state->config->io.clock_khz >= 24000)
1598 dib0090_write_reg(state, 0x14, 1);
1600 dib0090_write_reg(state, 0x14, 2);
1601 dprintk("Pll lock : %d\n", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
1603 state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
1608 #define steps(u) (((u) > 15) ? ((u)-16) : (u))
1609 #define INTERN_WAIT 10
1610 static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1612 int ret = INTERN_WAIT * 10;
1614 switch (*tune_state) {
1615 case CT_TUNER_STEP_2:
1616 /* Turns to positive */
1617 dib0090_write_reg(state, 0x1f, 0x7);
1618 *tune_state = CT_TUNER_STEP_3;
1621 case CT_TUNER_STEP_3:
1622 state->adc_diff = dib0090_read_reg(state, 0x1d);
1624 /* Turns to negative */
1625 dib0090_write_reg(state, 0x1f, 0x4);
1626 *tune_state = CT_TUNER_STEP_4;
1629 case CT_TUNER_STEP_4:
1630 state->adc_diff -= dib0090_read_reg(state, 0x1d);
1631 *tune_state = CT_TUNER_STEP_5;
1642 struct dc_calibration {
1650 static const struct dc_calibration dc_table[] = {
1651 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1652 {0x06, 5, 1, (1 << 13) | (0 << 8) | (26 << 3), 1},
1653 {0x07, 11, 1, (1 << 13) | (0 << 8) | (26 << 3), 0},
1654 /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
1655 {0x06, 0, 0, (1 << 13) | (29 << 8) | (26 << 3), 1},
1656 {0x06, 10, 0, (1 << 13) | (29 << 8) | (26 << 3), 0},
1660 static const struct dc_calibration dc_p1g_table[] = {
1661 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1662 /* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
1663 {0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
1664 {0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
1665 /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
1666 {0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
1667 {0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
1671 static void dib0090_set_trim(struct dib0090_state *state)
1675 if (state->dc->addr == 0x07)
1680 *val &= ~(0x1f << state->dc->offset);
1681 *val |= state->step << state->dc->offset;
1683 dib0090_write_reg(state, state->dc->addr, *val);
1686 static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1691 switch (*tune_state) {
1692 case CT_TUNER_START:
1693 dprintk("Start DC offset calibration");
1695 /* force vcm2 = 0.8V */
1697 state->bb7 = 0x040d;
1699 /* the LNA AND LO are off */
1700 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
1701 dib0090_write_reg(state, 0x24, reg);
1703 state->wbdmux = dib0090_read_reg(state, 0x10);
1704 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);
1705 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
1707 state->dc = dc_table;
1709 if (state->identity.p1g)
1710 state->dc = dc_p1g_table;
1713 case CT_TUNER_STEP_0:
1714 dprintk("Start/continue DC calibration for %s path\n",
1715 (state->dc->i == 1) ? "I" : "Q");
1716 dib0090_write_reg(state, 0x01, state->dc->bb1);
1717 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
1720 state->min_adc_diff = 1023;
1721 *tune_state = CT_TUNER_STEP_1;
1725 case CT_TUNER_STEP_1:
1726 dib0090_set_trim(state);
1727 *tune_state = CT_TUNER_STEP_2;
1730 case CT_TUNER_STEP_2:
1731 case CT_TUNER_STEP_3:
1732 case CT_TUNER_STEP_4:
1733 ret = dib0090_get_offset(state, tune_state);
1736 case CT_TUNER_STEP_5: /* found an offset */
1737 dprintk("adc_diff = %d, current step= %d\n", (u32) state->adc_diff, state->step);
1738 if (state->step == 0 && state->adc_diff < 0) {
1739 state->min_adc_diff = -1023;
1740 dprintk("Change of sign of the minimum adc diff\n");
1743 dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d\n", state->adc_diff, state->min_adc_diff, state->step);
1745 /* first turn for this frequency */
1746 if (state->step == 0) {
1747 if (state->dc->pga && state->adc_diff < 0)
1749 if (state->dc->pga == 0 && state->adc_diff > 0)
1753 /* Look for a change of Sign in the Adc_diff.min_adc_diff is used to STORE the setp N-1 */
1754 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
1755 /* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
1757 state->min_adc_diff = state->adc_diff;
1758 *tune_state = CT_TUNER_STEP_1;
1760 /* the minimum was what we have seen in the step before */
1761 if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) {
1762 dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step\n", state->adc_diff, state->min_adc_diff);
1766 dib0090_set_trim(state);
1767 dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd\n", state->dc->addr, state->adc_diff, state->step);
1770 if (state->dc->addr == 0) /* done */
1771 *tune_state = CT_TUNER_STEP_6;
1773 *tune_state = CT_TUNER_STEP_0;
1778 case CT_TUNER_STEP_6:
1779 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
1780 dib0090_write_reg(state, 0x1f, 0x7);
1781 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
1782 state->calibrate &= ~DC_CAL;
1789 static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1792 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1794 switch (*tune_state) {
1795 case CT_TUNER_START:
1796 while (state->current_rf / 1000 > wbd->max_freq)
1798 if (wbd->wbd_gain != 0)
1799 wbd_gain = wbd->wbd_gain;
1802 #if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
1803 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))
1808 if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */
1809 *tune_state = CT_TUNER_START;
1810 state->calibrate &= ~WBD_CAL;
1814 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));
1816 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));
1817 *tune_state = CT_TUNER_STEP_0;
1818 state->wbd_calibration_gain = wbd_gain;
1819 return 90; /* wait for the WBDMUX to switch and for the ADC to sample */
1821 case CT_TUNER_STEP_0:
1822 state->wbd_offset = dib0090_get_slow_adc_val(state);
1823 dprintk("WBD calibration offset = %d\n", state->wbd_offset);
1824 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
1825 state->calibrate &= ~WBD_CAL;
1834 static void dib0090_set_bandwidth(struct dib0090_state *state)
1838 if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000)
1840 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000)
1842 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000)
1847 state->bb_1_def &= 0x3fff;
1848 state->bb_1_def |= tmp;
1850 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
1852 dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
1853 dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
1854 if (state->identity.in_soc) {
1855 dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
1857 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
1858 dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
1862 static const struct dib0090_pll dib0090_pll_table[] = {
1863 #ifdef CONFIG_BAND_CBAND
1864 {56000, 0, 9, 48, 6},
1865 {70000, 1, 9, 48, 6},
1866 {87000, 0, 8, 32, 4},
1867 {105000, 1, 8, 32, 4},
1868 {115000, 0, 7, 24, 6},
1869 {140000, 1, 7, 24, 6},
1870 {170000, 0, 6, 16, 4},
1872 #ifdef CONFIG_BAND_VHF
1873 {200000, 1, 6, 16, 4},
1874 {230000, 0, 5, 12, 6},
1875 {280000, 1, 5, 12, 6},
1876 {340000, 0, 4, 8, 4},
1877 {380000, 1, 4, 8, 4},
1878 {450000, 0, 3, 6, 6},
1880 #ifdef CONFIG_BAND_UHF
1881 {580000, 1, 3, 6, 6},
1882 {700000, 0, 2, 4, 4},
1883 {860000, 1, 2, 4, 4},
1885 #ifdef CONFIG_BAND_LBAND
1886 {1800000, 1, 0, 2, 4},
1888 #ifdef CONFIG_BAND_SBAND
1889 {2900000, 0, 14, 1, 4},
1893 static const struct dib0090_tuning dib0090_tuning_table_fm_vhf_on_cband[] = {
1895 #ifdef CONFIG_BAND_CBAND
1896 {184000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1897 {227000, 4, 3, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1898 {380000, 4, 7, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1900 #ifdef CONFIG_BAND_UHF
1901 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1902 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1903 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1904 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1905 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1906 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1908 #ifdef CONFIG_BAND_LBAND
1909 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1910 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1911 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1913 #ifdef CONFIG_BAND_SBAND
1914 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1915 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1919 static const struct dib0090_tuning dib0090_tuning_table[] = {
1921 #ifdef CONFIG_BAND_CBAND
1922 {170000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1924 #ifdef CONFIG_BAND_VHF
1925 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1926 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1927 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1929 #ifdef CONFIG_BAND_UHF
1930 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1931 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1932 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1933 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1934 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1935 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1937 #ifdef CONFIG_BAND_LBAND
1938 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1939 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1940 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1942 #ifdef CONFIG_BAND_SBAND
1943 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1944 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1948 static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
1949 #ifdef CONFIG_BAND_CBAND
1950 {170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
1952 #ifdef CONFIG_BAND_VHF
1953 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1954 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1955 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1957 #ifdef CONFIG_BAND_UHF
1958 {510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1959 {540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1960 {600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1961 {630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1962 {680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1963 {720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1964 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1966 #ifdef CONFIG_BAND_LBAND
1967 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1968 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1969 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1971 #ifdef CONFIG_BAND_SBAND
1972 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1973 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1977 static const struct dib0090_pll dib0090_p1g_pll_table[] = {
1978 #ifdef CONFIG_BAND_CBAND
1979 {57000, 0, 11, 48, 6},
1980 {70000, 1, 11, 48, 6},
1981 {86000, 0, 10, 32, 4},
1982 {105000, 1, 10, 32, 4},
1983 {115000, 0, 9, 24, 6},
1984 {140000, 1, 9, 24, 6},
1985 {170000, 0, 8, 16, 4},
1987 #ifdef CONFIG_BAND_VHF
1988 {200000, 1, 8, 16, 4},
1989 {230000, 0, 7, 12, 6},
1990 {280000, 1, 7, 12, 6},
1991 {340000, 0, 6, 8, 4},
1992 {380000, 1, 6, 8, 4},
1993 {455000, 0, 5, 6, 6},
1995 #ifdef CONFIG_BAND_UHF
1996 {580000, 1, 5, 6, 6},
1997 {680000, 0, 4, 4, 4},
1998 {860000, 1, 4, 4, 4},
2000 #ifdef CONFIG_BAND_LBAND
2001 {1800000, 1, 2, 2, 4},
2003 #ifdef CONFIG_BAND_SBAND
2004 {2900000, 0, 1, 1, 6},
2008 static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
2009 #ifdef CONFIG_BAND_CBAND
2010 {184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
2011 {227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
2012 {380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
2014 #ifdef CONFIG_BAND_UHF
2015 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2016 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2017 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2018 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2019 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2020 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2022 #ifdef CONFIG_BAND_LBAND
2023 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2024 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2025 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2027 #ifdef CONFIG_BAND_SBAND
2028 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
2029 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
2033 static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
2034 #ifdef CONFIG_BAND_CBAND
2035 {300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2036 {380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2037 {570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2038 {858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2042 static const struct dib0090_tuning dib0090_tuning_table_cband_7090e_sensitivity[] = {
2043 #ifdef CONFIG_BAND_CBAND
2044 { 300000, 0 , 3, 0x8105, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2045 { 380000, 0 , 10, 0x810F, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2046 { 600000, 0 , 10, 0x815E, 0x280, 0x2d12, 0xb84e, EN_CAB },
2047 { 660000, 0 , 5, 0x85E3, 0x280, 0x2d12, 0xb84e, EN_CAB },
2048 { 720000, 0 , 5, 0x852E, 0x280, 0x2d12, 0xb84e, EN_CAB },
2049 { 860000, 0 , 4, 0x85E5, 0x280, 0x2d12, 0xb84e, EN_CAB },
2053 int dib0090_update_tuning_table_7090(struct dvb_frontend *fe,
2056 struct dib0090_state *state = fe->tuner_priv;
2057 const struct dib0090_tuning *tune =
2058 dib0090_tuning_table_cband_7090e_sensitivity;
2059 const struct dib0090_tuning dib0090_tuning_table_cband_7090e_aci[] = {
2060 { 300000, 0 , 3, 0x8165, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2061 { 650000, 0 , 4, 0x815B, 0x280, 0x2d12, 0xb84e, EN_CAB },
2062 { 860000, 0 , 5, 0x84EF, 0x280, 0x2d12, 0xb84e, EN_CAB },
2065 if ((!state->identity.p1g) || (!state->identity.in_soc)
2066 || ((state->identity.version != SOC_7090_P1G_21R1)
2067 && (state->identity.version != SOC_7090_P1G_11R1))) {
2068 dprintk("%s() function can only be used for dib7090\n", __func__);
2072 if (cfg_sensitivity)
2073 tune = dib0090_tuning_table_cband_7090e_sensitivity;
2075 tune = dib0090_tuning_table_cband_7090e_aci;
2077 while (state->rf_request > tune->max_freq)
2080 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000)
2081 | (tune->lna_bias & 0x7fff));
2082 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f)
2083 | ((tune->lna_tune << 6) & 0x07c0));
2086 EXPORT_SYMBOL(dib0090_update_tuning_table_7090);
2088 static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
2096 u8 force_soft_search = 0;
2098 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
2099 force_soft_search = 1;
2101 if (*tune_state == CT_TUNER_START) {
2102 dprintk("Start Captrim search : %s\n",
2103 (force_soft_search == 1) ? "FORCE SOFT SEARCH" : "AUTO");
2104 dib0090_write_reg(state, 0x10, 0x2B1);
2105 dib0090_write_reg(state, 0x1e, 0x0032);
2107 if (!state->tuner_is_tuned) {
2108 /* prepare a complete captrim */
2109 if (!state->identity.p1g || force_soft_search)
2110 state->step = state->captrim = state->fcaptrim = 64;
2112 state->current_rf = state->rf_request;
2113 } else { /* we are already tuned to this frequency - the configuration is correct */
2114 if (!state->identity.p1g || force_soft_search) {
2115 /* do a minimal captrim even if the frequency has not changed */
2117 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
2120 state->adc_diff = 3000;
2121 *tune_state = CT_TUNER_STEP_0;
2123 } else if (*tune_state == CT_TUNER_STEP_0) {
2124 if (state->identity.p1g && !force_soft_search) {
2127 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
2128 dib0090_read_reg(state, 0x40);
2132 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
2134 if (state->identity.in_soc)
2137 *tune_state = CT_TUNER_STEP_1;
2139 } else if (*tune_state == CT_TUNER_STEP_1) {
2140 if (state->identity.p1g && !force_soft_search) {
2141 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
2142 dib0090_read_reg(state, 0x40);
2144 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
2145 dprintk("***Final Captrim= 0x%x\n", state->fcaptrim);
2146 *tune_state = CT_TUNER_STEP_3;
2149 /* MERGE for all krosus before P1G */
2150 adc = dib0090_get_slow_adc_val(state);
2151 dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV\n", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024);
2153 if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */
2158 if (adc >= adc_target) {
2162 adc = adc_target - adc;
2166 if (adc < state->adc_diff) {
2167 dprintk("CAPTRIM=%d is closer to target (%d/%d)\n", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
2168 state->adc_diff = adc;
2169 state->fcaptrim = state->captrim;
2172 state->captrim += step_sign * state->step;
2173 if (state->step >= 1)
2174 *tune_state = CT_TUNER_STEP_0;
2176 *tune_state = CT_TUNER_STEP_2;
2180 } else if (*tune_state == CT_TUNER_STEP_2) { /* this step is only used by krosus < P1G */
2181 /*write the final cptrim config */
2182 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
2184 *tune_state = CT_TUNER_STEP_3;
2186 } else if (*tune_state == CT_TUNER_STEP_3) {
2187 state->calibrate &= ~CAPTRIM_CAL;
2188 *tune_state = CT_TUNER_STEP_0;
2194 static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state)
2199 switch (*tune_state) {
2200 case CT_TUNER_START:
2201 state->wbdmux = dib0090_read_reg(state, 0x10);
2202 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));
2204 state->bias = dib0090_read_reg(state, 0x13);
2205 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));
2207 *tune_state = CT_TUNER_STEP_0;
2208 /* wait for the WBDMUX to switch and for the ADC to sample */
2211 case CT_TUNER_STEP_0:
2212 state->adc_diff = dib0090_get_slow_adc_val(state);
2213 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));
2214 *tune_state = CT_TUNER_STEP_1;
2217 case CT_TUNER_STEP_1:
2218 val = dib0090_get_slow_adc_val(state);
2219 state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;
2221 dprintk("temperature: %d C\n", state->temperature - 30);
2223 *tune_state = CT_TUNER_STEP_2;
2226 case CT_TUNER_STEP_2:
2227 dib0090_write_reg(state, 0x13, state->bias);
2228 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
2230 *tune_state = CT_TUNER_START;
2231 state->calibrate &= ~TEMP_CAL;
2232 if (state->config->analog_output == 0)
2233 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2244 #define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
2245 static int dib0090_tune(struct dvb_frontend *fe)
2247 struct dib0090_state *state = fe->tuner_priv;
2248 const struct dib0090_tuning *tune = state->current_tune_table_index;
2249 const struct dib0090_pll *pll = state->current_pll_table_index;
2250 enum frontend_tune_state *tune_state = &state->tune_state;
2252 u16 lo5, lo6, Den, tmp;
2253 u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
2254 int ret = 10; /* 1ms is the default delay most of the time */
2257 /************************* VCO ***************************/
2258 /* Default values for FG */
2259 /* from these are needed : */
2260 /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */
2262 /* in any case we first need to do a calibration if needed */
2263 if (*tune_state == CT_TUNER_START) {
2264 /* deactivate DataTX before some calibrations */
2265 if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
2266 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
2268 /* Activate DataTX in case a calibration has been done before */
2269 if (state->config->analog_output == 0)
2270 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2273 if (state->calibrate & DC_CAL)
2274 return dib0090_dc_offset_calibration(state, tune_state);
2275 else if (state->calibrate & WBD_CAL) {
2276 if (state->current_rf == 0)
2277 state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
2278 return dib0090_wbd_calibration(state, tune_state);
2279 } else if (state->calibrate & TEMP_CAL)
2280 return dib0090_get_temperature(state, tune_state);
2281 else if (state->calibrate & CAPTRIM_CAL)
2282 return dib0090_captrim_search(state, tune_state);
2284 if (*tune_state == CT_TUNER_START) {
2285 /* if soc and AGC pwm control, disengage mux to be able to R/W access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, otherwise, SOC SERPAR error when accessing to 0x01 */
2286 if (state->config->use_pwm_agc && state->identity.in_soc) {
2287 tmp = dib0090_read_reg(state, 0x39);
2288 if ((tmp >> 10) & 0x1)
2289 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));
2292 state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
2294 state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
2295 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->
2296 freq_offset_khz_vhf);
2298 /* in ISDB-T 1seg we shift tuning frequency */
2299 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1
2300 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {
2301 const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;
2302 u8 found_offset = 0;
2303 u32 margin_khz = 100;
2305 if (LUT_offset != NULL) {
2306 while (LUT_offset->RF_freq != 0xffff) {
2307 if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))
2308 && (state->rf_request < (LUT_offset->RF_freq + margin_khz)))
2309 && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {
2310 state->rf_request += LUT_offset->offset_khz;
2318 if (found_offset == 0)
2319 state->rf_request += 400;
2321 if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) {
2322 state->tuner_is_tuned = 0;
2323 state->current_rf = 0;
2324 state->current_standard = 0;
2326 tune = dib0090_tuning_table;
2327 if (state->identity.p1g)
2328 tune = dib0090_p1g_tuning_table;
2330 tmp = (state->identity.version >> 5) & 0x7;
2332 if (state->identity.in_soc) {
2333 if (state->config->force_cband_input) { /* Use the CBAND input for all band */
2334 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
2335 || state->current_band & BAND_UHF) {
2336 state->current_band = BAND_CBAND;
2337 if (state->config->is_dib7090e)
2338 tune = dib0090_tuning_table_cband_7090e_sensitivity;
2340 tune = dib0090_tuning_table_cband_7090;
2342 } else { /* Use the CBAND input for all band under UHF */
2343 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
2344 state->current_band = BAND_CBAND;
2345 if (state->config->is_dib7090e)
2346 tune = dib0090_tuning_table_cband_7090e_sensitivity;
2348 tune = dib0090_tuning_table_cband_7090;
2352 if (tmp == 0x4 || tmp == 0x7) {
2353 /* CBAND tuner version for VHF */
2354 if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) {
2355 state->current_band = BAND_CBAND; /* Force CBAND */
2357 tune = dib0090_tuning_table_fm_vhf_on_cband;
2358 if (state->identity.p1g)
2359 tune = dib0090_p1g_tuning_table_fm_vhf_on_cband;
2363 pll = dib0090_pll_table;
2364 if (state->identity.p1g)
2365 pll = dib0090_p1g_pll_table;
2367 /* Look for the interval */
2368 while (state->rf_request > tune->max_freq)
2370 while (state->rf_request > pll->max_freq)
2373 state->current_tune_table_index = tune;
2374 state->current_pll_table_index = pll;
2376 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
2378 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
2380 FREF = state->config->io.clock_khz;
2381 if (state->config->fref_clock_ratio != 0)
2382 FREF /= state->config->fref_clock_ratio;
2384 FBDiv = (VCOF_kHz / pll->topresc / FREF);
2385 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
2389 else if (Rest < 2 * LPF)
2391 else if (Rest > (FREF - LPF)) {
2394 } else if (Rest > (FREF - 2 * LPF))
2395 Rest = FREF - 2 * LPF;
2396 Rest = (Rest * 6528) / (FREF / 10);
2399 /* external loop filter, otherwise:
2400 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
2411 else if (state->config->analog_output)
2417 if (state->identity.p1g) { /* Bias is done automatically in P1G */
2418 if (state->identity.in_soc) {
2419 if (state->identity.version == SOC_8090_P1G_11R1)
2427 lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
2429 if (!state->config->io.pll_int_loop_filt) {
2430 if (state->identity.in_soc)
2432 else if (state->identity.p1g || (Rest == 0))
2437 lo6 = (state->config->io.pll_int_loop_filt << 3);
2442 if (state->config->analog_output)
2443 lo6 |= (1 << 2) | 2;
2445 if (state->identity.in_soc)
2446 lo6 |= (1 << 2) | 2;
2448 lo6 |= (1 << 2) | 2;
2452 dib0090_write_reg(state, 0x15, (u16) FBDiv);
2453 if (state->config->fref_clock_ratio != 0)
2454 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
2456 dib0090_write_reg(state, 0x16, (Den << 8) | 1);
2457 dib0090_write_reg(state, 0x17, (u16) Rest);
2458 dib0090_write_reg(state, 0x19, lo5);
2459 dib0090_write_reg(state, 0x1c, lo6);
2461 lo6 = tune->tuner_enable;
2462 if (state->config->analog_output)
2463 lo6 = (lo6 & 0xff9f) | 0x2;
2465 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
2469 state->current_rf = state->rf_request;
2470 state->current_standard = state->fe->dtv_property_cache.delivery_system;
2473 state->calibrate = CAPTRIM_CAL; /* captrim serach now */
2476 else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
2477 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
2479 while (state->current_rf / 1000 > wbd->max_freq)
2482 dib0090_write_reg(state, 0x1e, 0x07ff);
2483 dprintk("Final Captrim: %d\n", (u32) state->fcaptrim);
2484 dprintk("HFDIV code: %d\n", (u32) pll->hfdiv_code);
2485 dprintk("VCO = %d\n", (u32) pll->vco_band);
2486 dprintk("VCOF in kHz: %d ((%d*%d) << 1))\n", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
2487 dprintk("REFDIV: %d, FREF: %d\n", (u32) 1, (u32) state->config->io.clock_khz);
2488 dprintk("FBDIV: %d, Rest: %d\n", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
2489 dprintk("Num: %d, Den: %d, SD: %d\n", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
2490 (u32) dib0090_read_reg(state, 0x1c) & 0x3);
2492 #define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
2496 if (wbd->wbd_gain != 0)
2499 state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
2500 dib0090_write_reg(state, 0x10, state->wbdmux);
2502 if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {
2503 dprintk("P1G : The cable band is selected and lna_tune = %d\n", tune->lna_tune);
2504 dib0090_write_reg(state, 0x09, tune->lna_bias);
2505 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
2507 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
2509 dib0090_write_reg(state, 0x0c, tune->v2i);
2510 dib0090_write_reg(state, 0x0d, tune->mix);
2511 dib0090_write_reg(state, 0x0e, tune->load);
2512 *tune_state = CT_TUNER_STEP_1;
2514 } else if (*tune_state == CT_TUNER_STEP_1) {
2515 /* initialize the lt gain register */
2516 state->rf_lt_def = 0x7c00;
2518 dib0090_set_bandwidth(state);
2519 state->tuner_is_tuned = 1;
2521 state->calibrate |= WBD_CAL;
2522 state->calibrate |= TEMP_CAL;
2523 *tune_state = CT_TUNER_STOP;
2525 ret = FE_CALLBACK_TIME_NEVER;
2529 static void dib0090_release(struct dvb_frontend *fe)
2531 kfree(fe->tuner_priv);
2532 fe->tuner_priv = NULL;
2535 enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
2537 struct dib0090_state *state = fe->tuner_priv;
2539 return state->tune_state;
2542 EXPORT_SYMBOL(dib0090_get_tune_state);
2544 int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
2546 struct dib0090_state *state = fe->tuner_priv;
2548 state->tune_state = tune_state;
2552 EXPORT_SYMBOL(dib0090_set_tune_state);
2554 static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
2556 struct dib0090_state *state = fe->tuner_priv;
2558 *frequency = 1000 * state->current_rf;
2562 static int dib0090_set_params(struct dvb_frontend *fe)
2564 struct dib0090_state *state = fe->tuner_priv;
2567 state->tune_state = CT_TUNER_START;
2570 ret = dib0090_tune(fe);
2571 if (ret == FE_CALLBACK_TIME_NEVER)
2575 * Despite dib0090_tune returns time at a 0.1 ms range,
2576 * the actual sleep time depends on CONFIG_HZ. The worse case
2577 * is when CONFIG_HZ=100. In such case, the minimum granularity
2578 * is 10ms. On some real field tests, the tuner sometimes don't
2579 * lock when this timer is lower than 10ms. So, enforce a 10ms
2580 * granularity and use usleep_range() instead of msleep().
2582 ret = 10 * (ret + 99)/100;
2583 usleep_range(ret * 1000, (ret + 1) * 1000);
2584 } while (state->tune_state != CT_TUNER_STOP);
2589 static const struct dvb_tuner_ops dib0090_ops = {
2591 .name = "DiBcom DiB0090",
2592 .frequency_min = 45000000,
2593 .frequency_max = 860000000,
2594 .frequency_step = 1000,
2596 .release = dib0090_release,
2598 .init = dib0090_wakeup,
2599 .sleep = dib0090_sleep,
2600 .set_params = dib0090_set_params,
2601 .get_frequency = dib0090_get_frequency,
2604 static const struct dvb_tuner_ops dib0090_fw_ops = {
2606 .name = "DiBcom DiB0090",
2607 .frequency_min = 45000000,
2608 .frequency_max = 860000000,
2609 .frequency_step = 1000,
2611 .release = dib0090_release,
2616 .get_frequency = NULL,
2619 static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
2620 {470, 0, 250, 0, 100, 4},
2621 {860, 51, 866, 21, 375, 4},
2622 {1700, 0, 800, 0, 850, 4},
2623 {2900, 0, 250, 0, 100, 6},
2624 {0xFFFF, 0, 0, 0, 0, 0},
2627 struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
2629 struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
2633 st->config = config;
2636 mutex_init(&st->i2c_buffer_lock);
2637 fe->tuner_priv = st;
2639 if (config->wbd == NULL)
2640 st->current_wbd_table = dib0090_wbd_table_default;
2642 st->current_wbd_table = config->wbd;
2644 if (dib0090_reset(fe) != 0)
2647 pr_info("DiB0090: successfully identified\n");
2648 memcpy(&fe->ops.tuner_ops, &dib0090_ops, sizeof(struct dvb_tuner_ops));
2653 fe->tuner_priv = NULL;
2657 EXPORT_SYMBOL(dib0090_register);
2659 struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
2661 struct dib0090_fw_state *st = kzalloc(sizeof(struct dib0090_fw_state), GFP_KERNEL);
2665 st->config = config;
2668 mutex_init(&st->i2c_buffer_lock);
2669 fe->tuner_priv = st;
2671 if (dib0090_fw_reset_digital(fe, st->config) != 0)
2674 dprintk("DiB0090 FW: successfully identified\n");
2675 memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
2680 fe->tuner_priv = NULL;
2683 EXPORT_SYMBOL(dib0090_fw_register);
2685 MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>");
2686 MODULE_AUTHOR("Olivier Grenie <olivier.grenie@parrot.com>");
2687 MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
2688 MODULE_LICENSE("GPL");