2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
8 * Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 this list of conditions and the following disclaimer in the documentation
12 and/or other materials provided with the distribution.
13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14 nor the names of its contributors may be used to endorse or promote
15 products derived from this software without specific prior written
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE.
30 DRXJ specific implementation of DRX driver
31 authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
33 The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was
34 written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
36 This program is free software; you can redistribute it and/or modify
37 it under the terms of the GNU General Public License as published by
38 the Free Software Foundation; either version 2 of the License, or
39 (at your option) any later version.
41 This program is distributed in the hope that it will be useful,
42 but WITHOUT ANY WARRANTY; without even the implied warranty of
43 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 GNU General Public License for more details.
47 You should have received a copy of the GNU General Public License
48 along with this program; if not, write to the Free Software
49 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
52 /*-----------------------------------------------------------------------------
54 ----------------------------------------------------------------------------*/
56 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
58 #include <linux/module.h>
59 #include <linux/init.h>
60 #include <linux/string.h>
61 #include <linux/slab.h>
62 #include <asm/div64.h>
64 #include "dvb_frontend.h"
70 /*============================================================================*/
71 /*=== DEFINES ================================================================*/
72 /*============================================================================*/
74 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
77 * \brief Maximum u32 value.
80 #define MAX_U32 ((u32) (0xFFFFFFFFL))
83 /* Customer configurable hardware settings, etc */
84 #ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
85 #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
88 #ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
89 #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
92 #ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
93 #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
96 #ifndef OOB_CRX_DRIVE_STRENGTH
97 #define OOB_CRX_DRIVE_STRENGTH 0x02
100 #ifndef OOB_DRX_DRIVE_STRENGTH
101 #define OOB_DRX_DRIVE_STRENGTH 0x02
103 /**** START DJCOMBO patches to DRXJ registermap constants *********************/
104 /**** registermap 200706071303 from drxj **************************************/
105 #define ATV_TOP_CR_AMP_TH_FM 0x0
106 #define ATV_TOP_CR_AMP_TH_L 0xA
107 #define ATV_TOP_CR_AMP_TH_LP 0xA
108 #define ATV_TOP_CR_AMP_TH_BG 0x8
109 #define ATV_TOP_CR_AMP_TH_DK 0x8
110 #define ATV_TOP_CR_AMP_TH_I 0x8
111 #define ATV_TOP_CR_CONT_CR_D_MN 0x18
112 #define ATV_TOP_CR_CONT_CR_D_FM 0x0
113 #define ATV_TOP_CR_CONT_CR_D_L 0x20
114 #define ATV_TOP_CR_CONT_CR_D_LP 0x20
115 #define ATV_TOP_CR_CONT_CR_D_BG 0x18
116 #define ATV_TOP_CR_CONT_CR_D_DK 0x18
117 #define ATV_TOP_CR_CONT_CR_D_I 0x18
118 #define ATV_TOP_CR_CONT_CR_I_MN 0x80
119 #define ATV_TOP_CR_CONT_CR_I_FM 0x0
120 #define ATV_TOP_CR_CONT_CR_I_L 0x80
121 #define ATV_TOP_CR_CONT_CR_I_LP 0x80
122 #define ATV_TOP_CR_CONT_CR_I_BG 0x80
123 #define ATV_TOP_CR_CONT_CR_I_DK 0x80
124 #define ATV_TOP_CR_CONT_CR_I_I 0x80
125 #define ATV_TOP_CR_CONT_CR_P_MN 0x4
126 #define ATV_TOP_CR_CONT_CR_P_FM 0x0
127 #define ATV_TOP_CR_CONT_CR_P_L 0x4
128 #define ATV_TOP_CR_CONT_CR_P_LP 0x4
129 #define ATV_TOP_CR_CONT_CR_P_BG 0x4
130 #define ATV_TOP_CR_CONT_CR_P_DK 0x4
131 #define ATV_TOP_CR_CONT_CR_P_I 0x4
132 #define ATV_TOP_CR_OVM_TH_MN 0xA0
133 #define ATV_TOP_CR_OVM_TH_FM 0x0
134 #define ATV_TOP_CR_OVM_TH_L 0xA0
135 #define ATV_TOP_CR_OVM_TH_LP 0xA0
136 #define ATV_TOP_CR_OVM_TH_BG 0xA0
137 #define ATV_TOP_CR_OVM_TH_DK 0xA0
138 #define ATV_TOP_CR_OVM_TH_I 0xA0
139 #define ATV_TOP_EQU0_EQU_C0_FM 0x0
140 #define ATV_TOP_EQU0_EQU_C0_L 0x3
141 #define ATV_TOP_EQU0_EQU_C0_LP 0x3
142 #define ATV_TOP_EQU0_EQU_C0_BG 0x7
143 #define ATV_TOP_EQU0_EQU_C0_DK 0x0
144 #define ATV_TOP_EQU0_EQU_C0_I 0x3
145 #define ATV_TOP_EQU1_EQU_C1_FM 0x0
146 #define ATV_TOP_EQU1_EQU_C1_L 0x1F6
147 #define ATV_TOP_EQU1_EQU_C1_LP 0x1F6
148 #define ATV_TOP_EQU1_EQU_C1_BG 0x197
149 #define ATV_TOP_EQU1_EQU_C1_DK 0x198
150 #define ATV_TOP_EQU1_EQU_C1_I 0x1F6
151 #define ATV_TOP_EQU2_EQU_C2_FM 0x0
152 #define ATV_TOP_EQU2_EQU_C2_L 0x28
153 #define ATV_TOP_EQU2_EQU_C2_LP 0x28
154 #define ATV_TOP_EQU2_EQU_C2_BG 0xC5
155 #define ATV_TOP_EQU2_EQU_C2_DK 0xB0
156 #define ATV_TOP_EQU2_EQU_C2_I 0x28
157 #define ATV_TOP_EQU3_EQU_C3_FM 0x0
158 #define ATV_TOP_EQU3_EQU_C3_L 0x192
159 #define ATV_TOP_EQU3_EQU_C3_LP 0x192
160 #define ATV_TOP_EQU3_EQU_C3_BG 0x12E
161 #define ATV_TOP_EQU3_EQU_C3_DK 0x18E
162 #define ATV_TOP_EQU3_EQU_C3_I 0x192
163 #define ATV_TOP_STD_MODE_MN 0x0
164 #define ATV_TOP_STD_MODE_FM 0x1
165 #define ATV_TOP_STD_MODE_L 0x0
166 #define ATV_TOP_STD_MODE_LP 0x0
167 #define ATV_TOP_STD_MODE_BG 0x0
168 #define ATV_TOP_STD_MODE_DK 0x0
169 #define ATV_TOP_STD_MODE_I 0x0
170 #define ATV_TOP_STD_VID_POL_MN 0x0
171 #define ATV_TOP_STD_VID_POL_FM 0x0
172 #define ATV_TOP_STD_VID_POL_L 0x2
173 #define ATV_TOP_STD_VID_POL_LP 0x2
174 #define ATV_TOP_STD_VID_POL_BG 0x0
175 #define ATV_TOP_STD_VID_POL_DK 0x0
176 #define ATV_TOP_STD_VID_POL_I 0x0
177 #define ATV_TOP_VID_AMP_MN 0x380
178 #define ATV_TOP_VID_AMP_FM 0x0
179 #define ATV_TOP_VID_AMP_L 0xF50
180 #define ATV_TOP_VID_AMP_LP 0xF50
181 #define ATV_TOP_VID_AMP_BG 0x380
182 #define ATV_TOP_VID_AMP_DK 0x394
183 #define ATV_TOP_VID_AMP_I 0x3D8
184 #define IQM_CF_OUT_ENA_OFDM__M 0x4
185 #define IQM_FS_ADJ_SEL_B_QAM 0x1
186 #define IQM_FS_ADJ_SEL_B_OFF 0x0
187 #define IQM_FS_ADJ_SEL_B_VSB 0x2
188 #define IQM_RC_ADJ_SEL_B_OFF 0x0
189 #define IQM_RC_ADJ_SEL_B_QAM 0x1
190 #define IQM_RC_ADJ_SEL_B_VSB 0x2
191 /**** END DJCOMBO patches to DRXJ registermap *********************************/
193 #include "drx_driver_version.h"
195 /* #define DRX_DEBUG */
200 /*-----------------------------------------------------------------------------
202 ----------------------------------------------------------------------------*/
204 /*-----------------------------------------------------------------------------
206 ----------------------------------------------------------------------------*/
207 #ifndef DRXJ_WAKE_UP_KEY
208 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
212 * \def DRXJ_DEF_I2C_ADDR
213 * \brief Default I2C address of a demodulator instance.
215 #define DRXJ_DEF_I2C_ADDR (0x52)
218 * \def DRXJ_DEF_DEMOD_DEV_ID
219 * \brief Default device identifier of a demodultor instance.
221 #define DRXJ_DEF_DEMOD_DEV_ID (1)
224 * \def DRXJ_SCAN_TIMEOUT
225 * \brief Timeout value for waiting on demod lock during channel scan (millisec).
227 #define DRXJ_SCAN_TIMEOUT 1000
231 * \brief HI timing delay for I2C timing (in nano seconds)
233 * Used to compute HI_CFG_DIV
235 #define HI_I2C_DELAY 42
238 * \def HI_I2C_BRIDGE_DELAY
239 * \brief HI timing delay for I2C timing (in nano seconds)
241 * Used to compute HI_CFG_BDL
243 #define HI_I2C_BRIDGE_DELAY 750
246 * \brief Time Window for MER and SER Measurement in Units of Segment duration.
248 #define VSB_TOP_MEASUREMENT_PERIOD 64
249 #define SYMBOLS_PER_SEGMENT 832
252 * \brief bit rate and segment rate constants used for SER and BER.
254 /* values taken from the QAM microcode */
255 #define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
256 #define DRXJ_QAM_SL_SIG_POWER_QPSK 32768
257 #define DRXJ_QAM_SL_SIG_POWER_QAM8 24576
258 #define DRXJ_QAM_SL_SIG_POWER_QAM16 40960
259 #define DRXJ_QAM_SL_SIG_POWER_QAM32 20480
260 #define DRXJ_QAM_SL_SIG_POWER_QAM64 43008
261 #define DRXJ_QAM_SL_SIG_POWER_QAM128 20992
262 #define DRXJ_QAM_SL_SIG_POWER_QAM256 43520
264 * \brief Min supported symbolrates.
266 #ifndef DRXJ_QAM_SYMBOLRATE_MIN
267 #define DRXJ_QAM_SYMBOLRATE_MIN (520000)
271 * \brief Max supported symbolrates.
273 #ifndef DRXJ_QAM_SYMBOLRATE_MAX
274 #define DRXJ_QAM_SYMBOLRATE_MAX (7233000)
278 * \def DRXJ_QAM_MAX_WAITTIME
279 * \brief Maximal wait time for QAM auto constellation in ms
281 #ifndef DRXJ_QAM_MAX_WAITTIME
282 #define DRXJ_QAM_MAX_WAITTIME 900
285 #ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
286 #define DRXJ_QAM_FEC_LOCK_WAITTIME 150
289 #ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
290 #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
294 * \def SCU status and results
297 #define DRX_SCU_READY 0
298 #define DRXJ_MAX_WAITTIME 100 /* ms */
299 #define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */
300 #define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */
303 * \def DRX_AUD_MAX_DEVIATION
304 * \brief Needed for calculation of prescale feature in AUD
306 #ifndef DRXJ_AUD_MAX_FM_DEVIATION
307 #define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */
311 * \brief Needed for calculation of NICAM prescale feature in AUD
313 #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
314 #define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */
318 * \brief Needed for calculation of NICAM prescale feature in AUD
320 #ifndef DRXJ_AUD_MAX_WAITTIME
321 #define DRXJ_AUD_MAX_WAITTIME 250 /* ms */
324 /* ATV config changed flags */
325 #define DRXJ_ATV_CHANGED_COEF (0x00000001UL)
326 #define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL)
327 #define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL)
328 #define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL)
329 #define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL)
332 #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
333 #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
336 * MICROCODE RELATED DEFINES
339 /* Magic word for checking correct Endianness of microcode data */
340 #define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L'))
342 /* CRC flag in ucode header, flags field. */
343 #define DRX_UCODE_CRC_FLAG (0x0001)
346 * Maximum size of buffer used to verify the microcode.
347 * Must be an even number
349 #define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
351 #if DRX_UCODE_MAX_BUF_SIZE & 1
352 #error DRX_UCODE_MAX_BUF_SIZE must be an even number
359 #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
360 (mode == DRX_POWER_MODE_10) || \
361 (mode == DRX_POWER_MODE_11) || \
362 (mode == DRX_POWER_MODE_12) || \
363 (mode == DRX_POWER_MODE_13) || \
364 (mode == DRX_POWER_MODE_14) || \
365 (mode == DRX_POWER_MODE_15) || \
366 (mode == DRX_POWER_MODE_16) || \
367 (mode == DRX_POWER_DOWN))
369 /* Pin safe mode macro */
370 #define DRXJ_PIN_SAFE_MODE 0x0000
371 /*============================================================================*/
372 /*=== GLOBAL VARIABLEs =======================================================*/
373 /*============================================================================*/
378 * \brief Temporary register definitions.
379 * (register definitions that are not yet available in register master)
382 /******************************************************************************/
383 /* Audio block 0x103 is write only. To avoid shadowing in driver accessing */
384 /* RAM adresses directly. This must be READ ONLY to avoid problems. */
385 /* Writing to the interface adresses is more than only writing the RAM */
387 /******************************************************************************/
389 * \brief RAM location of MODUS registers
391 #define AUD_DEM_RAM_MODUS_HI__A 0x10204A3
392 #define AUD_DEM_RAM_MODUS_HI__M 0xF000
394 #define AUD_DEM_RAM_MODUS_LO__A 0x10204A4
395 #define AUD_DEM_RAM_MODUS_LO__M 0x0FFF
398 * \brief RAM location of I2S config registers
400 #define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1
401 #define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2
404 * \brief RAM location of DCO config registers
406 #define AUD_DEM_RAM_DCO_B_HI__A 0x1020461
407 #define AUD_DEM_RAM_DCO_B_LO__A 0x1020462
408 #define AUD_DEM_RAM_DCO_A_HI__A 0x1020463
409 #define AUD_DEM_RAM_DCO_A_LO__A 0x1020464
412 * \brief RAM location of Threshold registers
414 #define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A
415 #define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB
416 #define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6
419 * \brief RAM location of Carrier Threshold registers
421 #define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF
422 #define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0
425 * \brief FM Matrix register fix
427 #ifdef AUD_DEM_WR_FM_MATRIX__A
428 #undef AUD_DEM_WR_FM_MATRIX__A
430 #define AUD_DEM_WR_FM_MATRIX__A 0x105006F
432 /*============================================================================*/
434 * \brief Defines required for audio
436 #define AUD_VOLUME_ZERO_DB 115
437 #define AUD_VOLUME_DB_MIN -60
438 #define AUD_VOLUME_DB_MAX 12
439 #define AUD_CARRIER_STRENGTH_QP_0DB 0x4000
440 #define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421
441 #define AUD_MAX_AVC_REF_LEVEL 15
442 #define AUD_I2S_FREQUENCY_MAX 48000UL
443 #define AUD_I2S_FREQUENCY_MIN 12000UL
444 #define AUD_RDS_ARRAY_SIZE 18
447 * \brief Needed for calculation of prescale feature in AUD
449 #ifndef DRX_AUD_MAX_FM_DEVIATION
450 #define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */
454 * \brief Needed for calculation of NICAM prescale feature in AUD
456 #ifndef DRX_AUD_MAX_NICAM_PRESCALE
457 #define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */
460 /*============================================================================*/
461 /* Values for I2S Master/Slave pin configurations */
462 #define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004
463 #define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008
464 #define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004
465 #define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000
467 #define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003
468 #define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008
469 #define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003
470 #define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008
472 #define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004
473 #define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008
474 #define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004
475 #define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000
477 /*============================================================================*/
478 /*=== REGISTER ACCESS MACROS =================================================*/
479 /*============================================================================*/
482 * This macro is used to create byte arrays for block writes.
483 * Block writes speed up I2C traffic between host and demod.
484 * The macro takes care of the required byte order in a 16 bits word.
485 * x -> lowbyte(x), highbyte(x)
487 #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
488 ((u8)((((u16)x)>>8)&0xFF))
490 * This macro is used to convert byte array to 16 bit register value for block read.
491 * Block read speed up I2C traffic between host and demod.
492 * The macro takes care of the required byte order in a 16 bits word.
494 #define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
496 /*============================================================================*/
497 /*=== MISC DEFINES ===========================================================*/
498 /*============================================================================*/
500 /*============================================================================*/
501 /*=== HI COMMAND RELATED DEFINES =============================================*/
502 /*============================================================================*/
505 * \brief General maximum number of retries for ucode command interfaces
507 #define DRXJ_MAX_RETRIES (100)
509 /*============================================================================*/
510 /*=== STANDARD RELATED MACROS ================================================*/
511 /*============================================================================*/
513 #define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
514 (std == DRX_STANDARD_PAL_SECAM_DK) || \
515 (std == DRX_STANDARD_PAL_SECAM_I) || \
516 (std == DRX_STANDARD_PAL_SECAM_L) || \
517 (std == DRX_STANDARD_PAL_SECAM_LP) || \
518 (std == DRX_STANDARD_NTSC) || \
519 (std == DRX_STANDARD_FM))
521 #define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
522 (std == DRX_STANDARD_ITU_B) || \
523 (std == DRX_STANDARD_ITU_C) || \
524 (std == DRX_STANDARD_ITU_D))
526 /*-----------------------------------------------------------------------------
528 ----------------------------------------------------------------------------*/
530 * DRXJ DAP structures
533 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
536 u8 *data, u32 flags);
539 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
542 u16 wdata, u16 *rdata);
544 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
546 u16 *data, u32 flags);
548 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
550 u32 *data, u32 flags);
552 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
555 u8 *data, u32 flags);
557 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
559 u16 data, u32 flags);
561 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
563 u32 data, u32 flags);
565 static struct drxj_data drxj_data_g = {
566 false, /* has_lna : true if LNA (aka PGA) present */
567 false, /* has_oob : true if OOB supported */
568 false, /* has_ntsc: true if NTSC supported */
569 false, /* has_btsc: true if BTSC supported */
570 false, /* has_smatx: true if SMA_TX pin is available */
571 false, /* has_smarx: true if SMA_RX pin is available */
572 false, /* has_gpio : true if GPIO pin is available */
573 false, /* has_irqn : true if IRQN pin is available */
574 0, /* mfx A1/A2/A... */
577 false, /* tuner mirrors RF signal */
578 /* standard/channel settings */
579 DRX_STANDARD_UNKNOWN, /* current standard */
580 DRX_CONSTELLATION_AUTO, /* constellation */
581 0, /* frequency in KHz */
582 DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */
583 DRX_MIRROR_NO, /* mirror */
585 /* signal quality information: */
586 /* default values taken from the QAM Programming guide */
587 /* fec_bits_desired should not be less than 4000000 */
588 4000000, /* fec_bits_desired */
590 4, /* qam_vd_prescale */
591 0xFFFF, /* qamVDPeriod */
592 204 * 8, /* fec_rs_plen annex A */
593 1, /* fec_rs_prescale */
594 FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */
595 true, /* reset_pkt_err_acc */
596 0, /* pkt_err_acc_start */
598 /* HI configuration */
599 0, /* hi_cfg_timing_div */
600 0, /* hi_cfg_bridge_delay */
601 0, /* hi_cfg_wake_up_key */
603 0, /* HICfgTimeout */
604 /* UIO configuration */
605 DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */
606 DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */
607 DRX_UIO_MODE_DISABLE, /* uioASELMode */
608 DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */
610 0UL, /* iqm_fs_rate_ofs */
611 false, /* pos_image */
613 0UL, /* iqm_rc_rate_ofs */
614 /* AUD information */
615 /* false, * flagSetAUDdone */
616 /* false, * detectedRDS */
617 /* true, * flagASDRequest */
618 /* false, * flagHDevClear */
619 /* false, * flagHDevSet */
620 /* (u16) 0xFFF, * rdsLastCount */
622 /* ATV configuration */
623 0UL, /* flags cfg changes */
624 /* shadow of ATV_TOP_EQU0__A */
626 ATV_TOP_EQU0_EQU_C0_FM,
627 ATV_TOP_EQU0_EQU_C0_L,
628 ATV_TOP_EQU0_EQU_C0_LP,
629 ATV_TOP_EQU0_EQU_C0_BG,
630 ATV_TOP_EQU0_EQU_C0_DK,
631 ATV_TOP_EQU0_EQU_C0_I},
632 /* shadow of ATV_TOP_EQU1__A */
634 ATV_TOP_EQU1_EQU_C1_FM,
635 ATV_TOP_EQU1_EQU_C1_L,
636 ATV_TOP_EQU1_EQU_C1_LP,
637 ATV_TOP_EQU1_EQU_C1_BG,
638 ATV_TOP_EQU1_EQU_C1_DK,
639 ATV_TOP_EQU1_EQU_C1_I},
640 /* shadow of ATV_TOP_EQU2__A */
642 ATV_TOP_EQU2_EQU_C2_FM,
643 ATV_TOP_EQU2_EQU_C2_L,
644 ATV_TOP_EQU2_EQU_C2_LP,
645 ATV_TOP_EQU2_EQU_C2_BG,
646 ATV_TOP_EQU2_EQU_C2_DK,
647 ATV_TOP_EQU2_EQU_C2_I},
648 /* shadow of ATV_TOP_EQU3__A */
650 ATV_TOP_EQU3_EQU_C3_FM,
651 ATV_TOP_EQU3_EQU_C3_L,
652 ATV_TOP_EQU3_EQU_C3_LP,
653 ATV_TOP_EQU3_EQU_C3_BG,
654 ATV_TOP_EQU3_EQU_C3_DK,
655 ATV_TOP_EQU3_EQU_C3_I},
656 false, /* flag: true=bypass */
657 ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */
658 ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */
659 true, /* flag CVBS ouput enable */
660 false, /* flag SIF ouput enable */
661 DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */
662 { /* qam_rf_agc_cfg */
663 DRX_STANDARD_ITU_B, /* standard */
664 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
665 0, /* output_level */
666 0, /* min_output_level */
667 0xFFFF, /* max_output_level */
672 { /* qam_if_agc_cfg */
673 DRX_STANDARD_ITU_B, /* standard */
674 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
675 0, /* output_level */
676 0, /* min_output_level */
677 0xFFFF, /* max_output_level */
679 0x0000, /* top (don't care) */
680 0x0000 /* c.o.c. (don't care) */
682 { /* vsb_rf_agc_cfg */
683 DRX_STANDARD_8VSB, /* standard */
684 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
685 0, /* output_level */
686 0, /* min_output_level */
687 0xFFFF, /* max_output_level */
689 0x0000, /* top (don't care) */
690 0x0000 /* c.o.c. (don't care) */
692 { /* vsb_if_agc_cfg */
693 DRX_STANDARD_8VSB, /* standard */
694 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
695 0, /* output_level */
696 0, /* min_output_level */
697 0xFFFF, /* max_output_level */
699 0x0000, /* top (don't care) */
700 0x0000 /* c.o.c. (don't care) */
704 { /* qam_pre_saw_cfg */
705 DRX_STANDARD_ITU_B, /* standard */
707 false /* use_pre_saw */
709 { /* vsb_pre_saw_cfg */
710 DRX_STANDARD_8VSB, /* standard */
712 false /* use_pre_saw */
715 /* Version information */
718 "01234567890", /* human readable version microcode */
719 "01234567890" /* human readable version device specific code */
722 { /* struct drx_version for microcode */
730 { /* struct drx_version for device specific code */
740 { /* struct drx_version_list for microcode */
741 (struct drx_version *) (NULL),
742 (struct drx_version_list *) (NULL)
744 { /* struct drx_version_list for device specific code */
745 (struct drx_version *) (NULL),
746 (struct drx_version_list *) (NULL)
750 false, /* smart_ant_inverted */
751 /* Tracking filter setting for OOB */
761 false, /* oob_power_on */
762 0, /* mpeg_ts_static_bitrate */
763 false, /* disable_te_ihandling */
764 false, /* bit_reverse_mpeg_outout */
765 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */
766 DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */
768 /* Pre SAW & Agc configuration for ATV */
770 DRX_STANDARD_NTSC, /* standard */
772 true /* use_pre_saw */
775 DRX_STANDARD_NTSC, /* standard */
776 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
777 0, /* output_level */
778 0, /* min_output_level (d.c.) */
779 0, /* max_output_level (d.c.) */
782 4000 /* cut-off current */
785 DRX_STANDARD_NTSC, /* standard */
786 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
787 0, /* output_level */
788 0, /* min_output_level (d.c.) */
789 0, /* max_output_level (d.c.) */
792 0 /* c.o.c. (d.c.) */
794 140, /* ATV PGA config */
795 0, /* curr_symbol_rate */
797 false, /* pdr_safe_mode */
798 SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */
799 SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */
800 SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */
801 SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */
804 DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */
806 false /* aud_data, only first member */
811 * \var drxj_default_addr_g
812 * \brief Default I2C address and device identifier.
814 static struct i2c_device_addr drxj_default_addr_g = {
815 DRXJ_DEF_I2C_ADDR, /* i2c address */
816 DRXJ_DEF_DEMOD_DEV_ID /* device id */
820 * \var drxj_default_comm_attr_g
821 * \brief Default common attributes of a drxj demodulator instance.
823 static struct drx_common_attr drxj_default_comm_attr_g = {
824 NULL, /* ucode file */
825 true, /* ucode verify switch */
826 {0}, /* version record */
828 44000, /* IF in kHz in case no tuner instance is used */
829 (151875 - 0), /* system clock frequency in kHz */
830 0, /* oscillator frequency kHz */
831 0, /* oscillator deviation in ppm, signed */
832 false, /* If true mirror frequency spectrum */
834 /* MPEG output configuration */
835 true, /* If true, enable MPEG ouput */
836 false, /* If true, insert RS byte */
837 false, /* If true, parallel out otherwise serial */
838 false, /* If true, invert DATA signals */
839 false, /* If true, invert ERR signal */
840 false, /* If true, invert STR signals */
841 false, /* If true, invert VAL signals */
842 false, /* If true, invert CLK signals */
843 true, /* If true, static MPEG clockrate will
844 be used, otherwise clockrate will
845 adapt to the bitrate of the TS */
846 19392658UL, /* Maximum bitrate in b/s in case
847 static clockrate is selected */
848 DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */
850 /* Initilisations below can be omitted, they require no user input and
851 are initialy 0, NULL or false. The compiler will initialize them to these
852 values when omitted. */
853 false, /* is_opened */
856 NULL, /* no scan params yet */
857 0, /* current scan index */
858 0, /* next scan frequency */
859 false, /* scan ready flag */
860 0, /* max channels to scan */
861 0, /* nr of channels scanned */
862 NULL, /* default scan function */
863 NULL, /* default context pointer */
864 0, /* millisec to wait for demod lock */
865 DRXJ_DEMOD_LOCK, /* desired lock */
868 /* Power management */
872 1, /* nr of I2C port to wich tuner is */
873 0L, /* minimum RF input frequency, in kHz */
874 0L, /* maximum RF input frequency, in kHz */
875 false, /* Rf Agc Polarity */
876 false, /* If Agc Polarity */
877 false, /* tuner slow mode */
879 { /* current channel (all 0) */
880 0UL /* channel.frequency */
882 DRX_STANDARD_UNKNOWN, /* current standard */
883 DRX_STANDARD_UNKNOWN, /* previous standard */
884 DRX_STANDARD_UNKNOWN, /* di_cache_standard */
885 false, /* use_bootloader */
886 0UL, /* capabilities */
891 * \var drxj_default_demod_g
892 * \brief Default drxj demodulator instance.
894 static struct drx_demod_instance drxj_default_demod_g = {
895 &drxj_default_addr_g, /* i2c address & device id */
896 &drxj_default_comm_attr_g, /* demod common attributes */
897 &drxj_data_g /* demod device specific attributes */
901 * \brief Default audio data structure for DRK demodulator instance.
903 * This structure is DRXK specific.
906 static struct drx_aud_data drxj_default_aud_data_g = {
907 false, /* audio_is_active */
908 DRX_AUD_STANDARD_AUTO, /* audio_standard */
912 false, /* output_enable */
913 48000, /* frequency */
914 DRX_I2S_MODE_MASTER, /* mode */
915 DRX_I2S_WORDLENGTH_32, /* word_length */
916 DRX_I2S_POLARITY_RIGHT, /* polarity */
917 DRX_I2S_FORMAT_WS_WITH_DATA /* format */
923 DRX_AUD_AVC_OFF, /* avc_mode */
924 0, /* avc_ref_level */
925 DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */
926 DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */
927 0, /* strength_left */
928 0 /* strength_right */
930 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */
942 DRX_NO_CARRIER_NOISE, /* opt */
949 DRX_NO_CARRIER_MUTE, /* opt */
957 DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */
958 DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */
959 DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */
961 DRX_AUD_DEVIATION_NORMAL, /* deviation */
962 DRX_AUD_AVSYNC_OFF, /* av_sync */
966 DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */
967 DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */
969 DRX_AUD_FM_DEEMPH_75US, /* deemph */
970 DRX_BTSC_STEREO, /* btsc_detect */
971 0, /* rds_data_counter */
972 false /* rds_data_present */
975 /*-----------------------------------------------------------------------------
977 ----------------------------------------------------------------------------*/
996 /*============================================================================*/
997 /*=== MICROCODE RELATED STRUCTURES ===========================================*/
998 /*============================================================================*/
1001 * struct drxu_code_block_hdr - Structure of the microcode block headers
1003 * @addr: Destination address of the data in this block
1004 * @size: Size of the block data following this header counted in
1006 * @CRC: CRC value of the data block, only valid if CRC flag is
1009 struct drxu_code_block_hdr {
1016 /*-----------------------------------------------------------------------------
1018 ----------------------------------------------------------------------------*/
1019 /* Some prototypes */
1021 hi_command(struct i2c_device_addr *dev_addr,
1022 const struct drxj_hi_cmd *cmd, u16 *result);
1025 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat);
1028 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
1030 static int power_down_aud(struct drx_demod_instance *demod);
1033 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
1036 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain);
1038 /*============================================================================*/
1039 /*============================================================================*/
1040 /*== HELPER FUNCTIONS ==*/
1041 /*============================================================================*/
1042 /*============================================================================*/
1045 /*============================================================================*/
1048 * \fn u32 frac28(u32 N, u32 D)
1049 * \brief Compute: (1<<28)*N/D
1052 * \return (1<<28)*N/D
1053 * This function is used to avoid floating-point calculations as they may
1054 * not be present on the target platform.
1056 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1057 * fraction used for setting the Frequency Shifter registers.
1058 * N and D can hold numbers up to width: 28-bits.
1059 * The 4 bits integer part and the 28 bits fractional part are calculated.
1061 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1063 * N: 0...(1<<28)-1 = 268435454
1067 static u32 frac28(u32 N, u32 D)
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */
1074 Q1 = N / D; /* integer part, only the 4 least significant bits
1075 will be visible in the result */
1077 /* division using radix 16, 7 nibbles in the result */
1078 for (i = 0; i < 7; i++) {
1079 Q1 = (Q1 << 4) | R0 / D;
1090 * \fn u32 log1_times100( u32 x)
1091 * \brief Compute: 100*log10(x)
1093 * \return 100*log10(x)
1096 * = 100*(log2(x)/log2(10)))
1097 * = (100*(2^15)*log2(x))/((2^15)*log2(10))
1098 * = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2
1099 * = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2
1100 * = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2
1102 * where y = 2^k and 1<= (x/y) < 2
1105 static u32 log1_times100(u32 x)
1107 static const u8 scale = 15;
1108 static const u8 index_width = 5;
1110 log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n ))
1111 0 <= n < ((1<<INDEXWIDTH)+1)
1114 static const u32 log2lut[] = {
1116 290941, /* 290941.300628 */
1117 573196, /* 573196.476418 */
1118 847269, /* 847269.179851 */
1119 1113620, /* 1113620.489452 */
1120 1372674, /* 1372673.576986 */
1121 1624818, /* 1624817.752104 */
1122 1870412, /* 1870411.981536 */
1123 2109788, /* 2109787.962654 */
1124 2343253, /* 2343252.817465 */
1125 2571091, /* 2571091.461923 */
1126 2793569, /* 2793568.696416 */
1127 3010931, /* 3010931.055901 */
1128 3223408, /* 3223408.452106 */
1129 3431216, /* 3431215.635215 */
1130 3634553, /* 3634553.498355 */
1131 3833610, /* 3833610.244726 */
1132 4028562, /* 4028562.434393 */
1133 4219576, /* 4219575.925308 */
1134 4406807, /* 4406806.721144 */
1135 4590402, /* 4590401.736809 */
1136 4770499, /* 4770499.491025 */
1137 4947231, /* 4947230.734179 */
1138 5120719, /* 5120719.018555 */
1139 5291081, /* 5291081.217197 */
1140 5458428, /* 5458427.996830 */
1141 5622864, /* 5622864.249668 */
1142 5784489, /* 5784489.488298 */
1143 5943398, /* 5943398.207380 */
1144 6099680, /* 6099680.215452 */
1145 6253421, /* 6253420.939751 */
1146 6404702, /* 6404701.706649 */
1147 6553600, /* 6553600.000000 */
1159 /* Scale x (normalize) */
1160 /* computing y in log(x/y) = log(x) - log(y) */
1161 if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
1162 for (k = scale; k > 0; k--) {
1163 if (x & (((u32) 1) << scale))
1168 for (k = scale; k < 31; k++) {
1169 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
1175 Now x has binary point between bit[scale] and bit[scale-1]
1176 and 1.0 <= x < 2.0 */
1178 /* correction for division: log(x) = log(x/y)+log(y) */
1179 y = k * ((((u32) 1) << scale) * 200);
1181 /* remove integer part */
1182 x &= ((((u32) 1) << scale) - 1);
1184 i = (u8) (x >> (scale - index_width));
1185 /* compute delta (x-a) */
1186 d = x & ((((u32) 1) << (scale - index_width)) - 1);
1187 /* compute log, multiplication ( d* (.. )) must be within range ! */
1189 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
1190 /* Conver to log10() */
1191 y /= 108853; /* (log2(10) << scale) */
1202 * \fn u32 frac_times1e6( u16 N, u32 D)
1203 * \brief Compute: (N/D) * 1000000.
1204 * \param N nominator 16-bits.
1205 * \param D denominator 32-bits.
1207 * \retval ((N/D) * 1000000), 32 bits
1211 static u32 frac_times1e6(u32 N, u32 D)
1217 frac = (N * 1000000) / D
1218 To let it fit in a 32 bits computation:
1219 frac = (N * (1000000 >> 4)) / (D >> 4)
1220 This would result in a problem in case D < 16 (div by 0).
1221 So we do it more elaborate as shown below.
1223 frac = (((u32) N) * (1000000 >> 4)) / D;
1225 remainder = (((u32) N) * (1000000 >> 4)) % D;
1227 frac += remainder / D;
1228 remainder = remainder % D;
1229 if ((remainder * 2) > D)
1235 /*============================================================================*/
1239 * \brief Values for NICAM prescaler gain. Computed from dB to integer
1240 * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20).
1244 /* Currently, unused as we lack support for analog TV */
1245 static const u16 nicam_presc_table_val[43] = {
1246 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4,
1247 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16,
1248 18, 20, 23, 25, 28, 32, 36, 40, 45,
1249 51, 57, 64, 71, 80, 90, 101, 113, 127
1253 /*============================================================================*/
1254 /*== END HELPER FUNCTIONS ==*/
1255 /*============================================================================*/
1257 /*============================================================================*/
1258 /*============================================================================*/
1259 /*== DRXJ DAP FUNCTIONS ==*/
1260 /*============================================================================*/
1261 /*============================================================================*/
1264 This layer takes care of some device specific register access protocols:
1265 -conversion to short address format
1266 -access to audio block
1267 This layer is placed between the drx_dap_fasi and the rest of the drxj
1268 specific implementation. This layer can use address map knowledge whereas
1269 dap_fasi may not use memory map knowledge.
1271 * For audio currently only 16 bits read and write register access is
1272 supported. More is not needed. RMW and 32 or 8 bit access on audio
1273 registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast
1274 single/multi master) will be ignored.
1276 TODO: check ignoring single/multimaster is ok for AUD access ?
1279 #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
1280 #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */
1281 /*============================================================================*/
1284 * \fn bool is_handled_by_aud_tr_if( u32 addr )
1285 * \brief Check if this address is handled by the audio token ring interface.
1288 * \retval true Yes, handled by audio token ring interface
1289 * \retval false No, not handled by audio token ring interface
1293 bool is_handled_by_aud_tr_if(u32 addr)
1295 bool retval = false;
1297 if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
1298 (DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
1299 (DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
1306 /*============================================================================*/
1308 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
1311 struct i2c_device_addr *r_dev_addr,
1312 u16 r_count, u8 *r_data)
1314 struct drx39xxj_state *state;
1315 struct i2c_msg msg[2];
1316 unsigned int num_msgs;
1318 if (w_dev_addr == NULL) {
1320 state = r_dev_addr->user_data;
1321 msg[0].addr = r_dev_addr->i2c_addr >> 1;
1322 msg[0].flags = I2C_M_RD;
1323 msg[0].buf = r_data;
1324 msg[0].len = r_count;
1326 } else if (r_dev_addr == NULL) {
1328 state = w_dev_addr->user_data;
1329 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1332 msg[0].len = w_count;
1335 /* Both write and read */
1336 state = w_dev_addr->user_data;
1337 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1340 msg[0].len = w_count;
1341 msg[1].addr = r_dev_addr->i2c_addr >> 1;
1342 msg[1].flags = I2C_M_RD;
1343 msg[1].buf = r_data;
1344 msg[1].len = r_count;
1348 if (state->i2c == NULL) {
1349 pr_err("i2c was zero, aborting\n");
1352 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
1353 pr_warn("drx3933: I2C write/read failed\n");
1358 if (w_dev_addr == NULL || r_dev_addr == NULL)
1361 state = w_dev_addr->user_data;
1363 if (state->i2c == NULL)
1366 msg[0].addr = w_dev_addr->i2c_addr;
1369 msg[0].len = w_count;
1370 msg[1].addr = r_dev_addr->i2c_addr;
1371 msg[1].flags = I2C_M_RD;
1372 msg[1].buf = r_data;
1373 msg[1].len = r_count;
1376 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1377 w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
1379 if (i2c_transfer(state->i2c, msg, 2) != 2) {
1380 pr_warn("drx3933: I2C write/read failed\n");
1387 /*============================================================================*/
1389 /******************************
1391 * int drxdap_fasi_read_block (
1392 * struct i2c_device_addr *dev_addr, -- address of I2C device
1393 * u32 addr, -- address of chip register/memory
1394 * u16 datasize, -- number of bytes to read
1395 * u8 *data, -- data to receive
1396 * u32 flags) -- special device flags
1398 * Read block data from chip address. Because the chip is word oriented,
1399 * the number of bytes to read must be even.
1401 * Make sure that the buffer to receive the data is large enough.
1403 * Although this function expects an even number of bytes, it is still byte
1404 * oriented, and the data read back is NOT translated to the endianness of
1405 * the target platform.
1408 * - 0 if reading was successful
1409 * in that case: data read is in *data.
1410 * - -EIO if anything went wrong
1412 ******************************/
1414 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
1417 u8 *data, u32 flags)
1422 u16 overhead_size = 0;
1424 /* Check parameters ******************************************************* */
1425 if (dev_addr == NULL)
1428 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1429 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1431 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1432 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1433 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1434 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1435 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
1439 /* ReadModifyWrite & mode flag bits are not allowed */
1440 flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
1441 #if DRXDAP_SINGLE_MASTER
1442 flags |= DRXDAP_FASI_SINGLE_MASTER;
1445 /* Read block from I2C **************************************************** */
1447 u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
1448 datasize : DRXDAP_MAX_RCHUNKSIZE);
1452 addr &= ~DRXDAP_FASI_FLAGS;
1455 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1456 /* short format address preferred but long format otherwise */
1457 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1459 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1460 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1461 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1462 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1463 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1465 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1468 #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
1469 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1471 (u8) (((addr >> 16) & 0x0F) |
1472 ((addr >> 18) & 0xF0));
1474 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1478 #if DRXDAP_SINGLE_MASTER
1480 * In single master mode, split the read and write actions.
1481 * No special action is needed for write chunks here.
1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1488 /* In multi master mode, do everything in one RW action */
1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
1493 addr += (todo >> 1);
1495 } while (datasize && rc == 0);
1501 /******************************
1503 * int drxdap_fasi_read_reg16 (
1504 * struct i2c_device_addr *dev_addr, -- address of I2C device
1505 * u32 addr, -- address of chip register/memory
1506 * u16 *data, -- data to receive
1507 * u32 flags) -- special device flags
1509 * Read one 16-bit register or memory location. The data received back is
1510 * converted back to the target platform's endianness.
1513 * - 0 if reading was successful
1514 * in that case: read data is at *data
1515 * - -EIO if anything went wrong
1517 ******************************/
1519 static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
1521 u16 *data, u32 flags)
1523 u8 buf[sizeof(*data)];
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1530 *data = buf[0] + (((u16) buf[1]) << 8);
1534 /******************************
1536 * int drxdap_fasi_read_reg32 (
1537 * struct i2c_device_addr *dev_addr, -- address of I2C device
1538 * u32 addr, -- address of chip register/memory
1539 * u32 *data, -- data to receive
1540 * u32 flags) -- special device flags
1542 * Read one 32-bit register or memory location. The data received back is
1543 * converted back to the target platform's endianness.
1546 * - 0 if reading was successful
1547 * in that case: read data is at *data
1548 * - -EIO if anything went wrong
1550 ******************************/
1552 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
1554 u32 *data, u32 flags)
1556 u8 buf[sizeof(*data)];
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1563 *data = (((u32) buf[0]) << 0) +
1564 (((u32) buf[1]) << 8) +
1565 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1569 /******************************
1571 * int drxdap_fasi_write_block (
1572 * struct i2c_device_addr *dev_addr, -- address of I2C device
1573 * u32 addr, -- address of chip register/memory
1574 * u16 datasize, -- number of bytes to read
1575 * u8 *data, -- data to receive
1576 * u32 flags) -- special device flags
1578 * Write block data to chip address. Because the chip is word oriented,
1579 * the number of bytes to write must be even.
1581 * Although this function expects an even number of bytes, it is still byte
1582 * oriented, and the data being written is NOT translated from the endianness of
1583 * the target platform.
1586 * - 0 if writing was successful
1587 * - -EIO if anything went wrong
1589 ******************************/
1591 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
1594 u8 *data, u32 flags)
1596 u8 buf[DRXDAP_MAX_WCHUNKSIZE];
1599 u16 overhead_size = 0;
1602 /* Check parameters ******************************************************* */
1603 if (dev_addr == NULL)
1606 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1607 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1609 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1610 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1611 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1612 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1613 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
1616 flags &= DRXDAP_FASI_FLAGS;
1617 flags &= ~DRXDAP_FASI_MODEFLAGS;
1618 #if DRXDAP_SINGLE_MASTER
1619 flags |= DRXDAP_FASI_SINGLE_MASTER;
1622 /* Write block to I2C ***************************************************** */
1623 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
1628 /* Buffer device address */
1629 addr &= ~DRXDAP_FASI_FLAGS;
1631 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1632 /* short format address preferred but long format otherwise */
1633 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1635 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
1636 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1637 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1638 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1639 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1641 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1644 #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
1645 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1647 (u8) (((addr >> 16) & 0x0F) |
1648 ((addr >> 18) & 0xF0));
1650 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1655 In single master mode block_size can be 0. In such a case this I2C
1656 sequense will be visible: (1) write address {i2c addr,
1657 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
1658 (3) write address (4) write data etc...
1659 Address must be rewriten because HI is reset after data transport and
1662 todo = (block_size < datasize ? block_size : datasize);
1664 u16 overhead_size_i2c_addr = 0;
1665 u16 data_block_size = 0;
1667 overhead_size_i2c_addr =
1668 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
1670 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
1672 /* write device address */
1673 st = drxbsp_i2c_write_read(dev_addr,
1676 (struct i2c_device_addr *)(NULL),
1679 if ((st != 0) && (first_err == 0)) {
1680 /* at the end, return the first error encountered */
1686 datasize ? data_block_size : datasize);
1688 memcpy(&buf[bufx], data, todo);
1689 /* write (address if can do and) data */
1690 st = drxbsp_i2c_write_read(dev_addr,
1691 (u16) (bufx + todo),
1693 (struct i2c_device_addr *)(NULL),
1696 if ((st != 0) && (first_err == 0)) {
1697 /* at the end, return the first error encountered */
1702 addr += (todo >> 1);
1708 /******************************
1710 * int drxdap_fasi_write_reg16 (
1711 * struct i2c_device_addr *dev_addr, -- address of I2C device
1712 * u32 addr, -- address of chip register/memory
1713 * u16 data, -- data to send
1714 * u32 flags) -- special device flags
1716 * Write one 16-bit register or memory location. The data being written is
1717 * converted from the target platform's endianness to little endian.
1720 * - 0 if writing was successful
1721 * - -EIO if anything went wrong
1723 ******************************/
1725 static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
1727 u16 data, u32 flags)
1729 u8 buf[sizeof(data)];
1731 buf[0] = (u8) ((data >> 0) & 0xFF);
1732 buf[1] = (u8) ((data >> 8) & 0xFF);
1734 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1737 /******************************
1739 * int drxdap_fasi_read_modify_write_reg16 (
1740 * struct i2c_device_addr *dev_addr, -- address of I2C device
1741 * u32 waddr, -- address of chip register/memory
1742 * u32 raddr, -- chip address to read back from
1743 * u16 wdata, -- data to send
1744 * u16 *rdata) -- data to receive back
1746 * Write 16-bit data, then read back the original contents of that location.
1747 * Requires long addressing format to be allowed.
1749 * Before sending data, the data is converted to little endian. The
1750 * data received back is converted back to the target platform's endianness.
1752 * WARNING: This function is only guaranteed to work if there is one
1753 * master on the I2C bus.
1756 * - 0 if reading was successful
1757 * in that case: read back data is at *rdata
1758 * - -EIO if anything went wrong
1760 ******************************/
1762 static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1765 u16 wdata, u16 *rdata)
1769 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1773 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
1775 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
1781 /******************************
1783 * int drxdap_fasi_write_reg32 (
1784 * struct i2c_device_addr *dev_addr, -- address of I2C device
1785 * u32 addr, -- address of chip register/memory
1786 * u32 data, -- data to send
1787 * u32 flags) -- special device flags
1789 * Write one 32-bit register or memory location. The data being written is
1790 * converted from the target platform's endianness to little endian.
1793 * - 0 if writing was successful
1794 * - -EIO if anything went wrong
1796 ******************************/
1798 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
1800 u32 data, u32 flags)
1802 u8 buf[sizeof(data)];
1804 buf[0] = (u8) ((data >> 0) & 0xFF);
1805 buf[1] = (u8) ((data >> 8) & 0xFF);
1806 buf[2] = (u8) ((data >> 16) & 0xFF);
1807 buf[3] = (u8) ((data >> 24) & 0xFF);
1809 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1812 /*============================================================================*/
1815 * \fn int drxj_dap_rm_write_reg16short
1816 * \brief Read modify write 16 bits audio register using short format only.
1818 * \param waddr Address to write to
1819 * \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A)
1820 * \param wdata Data to write
1821 * \param rdata Buffer for data to read
1824 * \retval -EIO Timeout, I2C error, illegal bank
1826 * 16 bits register read modify write access using short addressing format only.
1827 * Requires knowledge of the registermap, thus device dependent.
1828 * Using DAP FASI directly to avoid endless recursion of RMWs to audio registers.
1832 /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
1833 See comments drxj_dap_read_modify_write_reg16 */
1834 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
1835 static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr,
1838 u16 wdata, u16 *rdata)
1846 rc = drxdap_fasi_write_reg16(dev_addr,
1847 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1848 SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
1851 /* Write new data: triggers RMW */
1852 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
1857 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
1861 /* Reset RMW flag */
1862 rc = drxdap_fasi_write_reg16(dev_addr,
1863 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1871 /*============================================================================*/
1873 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1876 u16 wdata, u16 *rdata)
1878 /* TODO: correct short/long addressing format decision,
1879 now long format has higher prio then short because short also
1880 needs virt bnks (not impl yet) for certain audio registers */
1881 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1882 return drxdap_fasi_read_modify_write_reg16(dev_addr,
1884 raddr, wdata, rdata);
1886 return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata);
1891 /*============================================================================*/
1894 * \fn int drxj_dap_read_aud_reg16
1895 * \brief Read 16 bits audio register
1901 * \retval -EIO Timeout, I2C error, illegal bank
1903 * 16 bits register read access via audio token ring interface.
1906 static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr,
1907 u32 addr, u16 *data)
1909 u32 start_timer = 0;
1910 u32 current_timer = 0;
1911 u32 delta_timer = 0;
1915 /* No read possible for bank 3, return with error */
1916 if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
1919 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
1921 /* Force reset write bit */
1922 addr &= (~write_bit);
1925 start_timer = jiffies_to_msecs(jiffies);
1927 /* RMW to aud TR IF until request is granted or timeout */
1928 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1930 SIO_HI_RA_RAM_S0_RMWBUF__A,
1931 0x0000, &tr_status);
1936 current_timer = jiffies_to_msecs(jiffies);
1937 delta_timer = current_timer - start_timer;
1938 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1943 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
1944 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
1945 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
1946 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
1947 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */
1949 /* Wait for read ready status or timeout */
1951 start_timer = jiffies_to_msecs(jiffies);
1953 while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) !=
1954 AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
1955 stat = drxj_dap_read_reg16(dev_addr,
1957 &tr_status, 0x0000);
1961 current_timer = jiffies_to_msecs(jiffies);
1962 delta_timer = current_timer - start_timer;
1963 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1967 } /* while ( ... ) */
1972 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1973 AUD_TOP_TR_RD_REG__A,
1974 SIO_HI_RA_RAM_S0_RMWBUF__A,
1979 /*============================================================================*/
1981 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
1983 u16 *data, u32 flags)
1988 if ((dev_addr == NULL) || (data == NULL))
1991 if (is_handled_by_aud_tr_if(addr))
1992 stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
1994 stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
1998 /*============================================================================*/
2001 * \fn int drxj_dap_write_aud_reg16
2002 * \brief Write 16 bits audio register
2008 * \retval -EIO Timeout, I2C error, illegal bank
2010 * 16 bits register write access via audio token ring interface.
2013 static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr,
2018 /* No write possible for bank 2, return with error */
2019 if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
2022 u32 start_timer = 0;
2023 u32 current_timer = 0;
2024 u32 delta_timer = 0;
2026 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
2028 /* Force write bit */
2030 start_timer = jiffies_to_msecs(jiffies);
2032 /* RMW to aud TR IF until request is granted or timeout */
2033 stat = drxj_dap_read_modify_write_reg16(dev_addr,
2035 SIO_HI_RA_RAM_S0_RMWBUF__A,
2040 current_timer = jiffies_to_msecs(jiffies);
2041 delta_timer = current_timer - start_timer;
2042 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
2047 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
2048 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
2049 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
2050 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
2052 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */
2057 /*============================================================================*/
2059 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
2061 u16 data, u32 flags)
2066 if (dev_addr == NULL)
2069 if (is_handled_by_aud_tr_if(addr))
2070 stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
2072 stat = drxdap_fasi_write_reg16(dev_addr,
2078 /*============================================================================*/
2080 /* Free data ram in SIO HI */
2081 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2082 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2084 #define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2085 #define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2086 #define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2087 #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2090 * \fn int drxj_dap_atomic_read_write_block()
2091 * \brief Basic access routine for atomic read or write access
2092 * \param dev_addr pointer to i2c dev address
2093 * \param addr destination/source address
2094 * \param datasize size of data buffer in bytes
2095 * \param data pointer to data buffer
2098 * \retval -EIO Timeout, I2C error, illegal bank
2102 int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr,
2105 u8 *data, bool read_flag)
2107 struct drxj_hi_cmd hi_cmd;
2113 /* Parameter check */
2114 if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
2117 /* Set up HI parameters to read or write n bytes */
2118 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
2120 (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) +
2121 DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START));
2123 (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
2124 hi_cmd.param3 = (u16) ((datasize / 2) - 1);
2126 hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
2128 hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
2129 hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
2130 DRXDAP_FASI_ADDR2BANK(addr));
2131 hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
2134 /* write data to buffer */
2135 for (i = 0; i < (datasize / 2); i++) {
2137 word = ((u16) data[2 * i]);
2138 word += (((u16) data[(2 * i) + 1]) << 8);
2139 drxj_dap_write_reg16(dev_addr,
2140 (DRXJ_HI_ATOMIC_BUF_START + i),
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy);
2147 pr_err("error %d\n", rc);
2152 /* read data from buffer */
2153 for (i = 0; i < (datasize / 2); i++) {
2154 drxj_dap_read_reg16(dev_addr,
2155 (DRXJ_HI_ATOMIC_BUF_START + i),
2157 data[2 * i] = (u8) (word & 0xFF);
2158 data[(2 * i) + 1] = (u8) (word >> 8);
2169 /*============================================================================*/
2172 * \fn int drxj_dap_atomic_read_reg32()
2173 * \brief Atomic read of 32 bits words
2176 int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr,
2178 u32 *data, u32 flags)
2180 u8 buf[sizeof(*data)] = { 0 };
2187 rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
2188 sizeof(*data), buf, true);
2193 word = (u32) buf[3];
2195 word |= (u32) buf[2];
2197 word |= (u32) buf[1];
2199 word |= (u32) buf[0];
2206 /*============================================================================*/
2208 /*============================================================================*/
2209 /*== END DRXJ DAP FUNCTIONS ==*/
2210 /*============================================================================*/
2212 /*============================================================================*/
2213 /*============================================================================*/
2214 /*== HOST INTERFACE FUNCTIONS ==*/
2215 /*============================================================================*/
2216 /*============================================================================*/
2219 * \fn int hi_cfg_command()
2220 * \brief Configure HI with settings stored in the demod structure.
2221 * \param demod Demodulator.
2224 * This routine was created because to much orthogonal settings have
2225 * been put into one HI API function (configure). Especially the I2C bridge
2226 * enable/disable should not need re-configuration of the HI.
2229 static int hi_cfg_command(const struct drx_demod_instance *demod)
2231 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2232 struct drxj_hi_cmd hi_cmd;
2236 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2238 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
2239 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
2240 hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2241 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2242 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2243 hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2244 hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2246 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2248 pr_err("error %d\n", rc);
2252 /* Reset power down flag (set one call only) */
2253 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2262 * \fn int hi_command()
2263 * \brief Configure HI with settings stored in the demod structure.
2264 * \param dev_addr I2C address.
2265 * \param cmd HI command.
2266 * \param result HI command result.
2269 * Sends command to HI
2273 hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result)
2277 bool powerdown_cmd = false;
2280 /* Write parameters */
2283 case SIO_HI_RA_RAM_CMD_CONFIG:
2284 case SIO_HI_RA_RAM_CMD_ATOMIC_COPY:
2285 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2287 pr_err("error %d\n", rc);
2290 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2292 pr_err("error %d\n", rc);
2295 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2297 pr_err("error %d\n", rc);
2300 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2302 pr_err("error %d\n", rc);
2306 case SIO_HI_RA_RAM_CMD_BRDCTRL:
2307 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2309 pr_err("error %d\n", rc);
2312 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2314 pr_err("error %d\n", rc);
2318 case SIO_HI_RA_RAM_CMD_NULL:
2328 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2330 pr_err("error %d\n", rc);
2334 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
2337 /* Detect power down to ommit reading result */
2338 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
2340 param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
2341 == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2342 if (!powerdown_cmd) {
2343 /* Wait until command rdy */
2346 if (nr_retries > DRXJ_MAX_RETRIES) {
2347 pr_err("timeout\n");
2351 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
2353 pr_err("error %d\n", rc);
2356 } while (wait_cmd != 0);
2359 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
2361 pr_err("error %d\n", rc);
2366 /* if ( powerdown_cmd == true ) */
2373 * \fn int init_hi( const struct drx_demod_instance *demod )
2374 * \brief Initialise and configurate HI.
2375 * \param demod pointer to demod data.
2376 * \return int Return status.
2377 * \retval 0 Success.
2378 * \retval -EIO Failure.
2380 * Needs to know Psys (System Clock period) and Posc (Osc Clock period)
2381 * Need to store configuration in driver because of the way I2C
2382 * bridging is controlled.
2385 static int init_hi(const struct drx_demod_instance *demod)
2387 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2388 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2389 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2392 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2393 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2394 dev_addr = demod->my_i2c_dev_addr;
2396 /* PATCH for bug 5003, HI ucode v3.1.0 */
2397 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
2399 pr_err("error %d\n", rc);
2403 /* Timing div, 250ns/Psys */
2404 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2405 ext_attr->hi_cfg_timing_div =
2406 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
2408 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
2409 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
2410 /* Bridge delay, uses oscilator clock */
2411 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2412 /* SDA brdige delay */
2413 ext_attr->hi_cfg_bridge_delay =
2414 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
2417 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
2418 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
2419 /* SCL bridge delay, same as SDA for now */
2420 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
2421 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
2422 /* Wakeup key, setting the read flag (as suggest in the documentation) does
2423 not always result into a working solution (barebones worked VI2C failed).
2424 Not setting the bit works in all cases . */
2425 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
2426 /* port/bridge/power down ctrl */
2427 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
2428 /* transit mode time out delay and watch dog divider */
2429 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
2431 rc = hi_cfg_command(demod);
2433 pr_err("error %d\n", rc);
2443 /*============================================================================*/
2444 /*== END HOST INTERFACE FUNCTIONS ==*/
2445 /*============================================================================*/
2447 /*============================================================================*/
2448 /*============================================================================*/
2449 /*== AUXILIARY FUNCTIONS ==*/
2450 /*============================================================================*/
2451 /*============================================================================*/
2454 * \fn int get_device_capabilities()
2455 * \brief Get and store device capabilities.
2456 * \param demod Pointer to demodulator instance.
2459 * \retval -EIO Failure
2461 * Depending on pulldowns on MDx pins the following internals are set:
2462 * * common_attr->osc_clock_freq
2463 * * ext_attr->has_lna
2464 * * ext_attr->has_ntsc
2465 * * ext_attr->has_btsc
2466 * * ext_attr->has_oob
2469 static int get_device_capabilities(struct drx_demod_instance *demod)
2471 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2472 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
2473 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2474 u16 sio_pdr_ohw_cfg = 0;
2475 u32 sio_top_jtagid_lo = 0;
2479 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2480 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2481 dev_addr = demod->my_i2c_dev_addr;
2483 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2485 pr_err("error %d\n", rc);
2488 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
2490 pr_err("error %d\n", rc);
2493 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2495 pr_err("error %d\n", rc);
2499 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
2501 /* ignore (bypass ?) */
2505 common_attr->osc_clock_freq = 27000;
2509 common_attr->osc_clock_freq = 20250;
2513 common_attr->osc_clock_freq = 4000;
2520 Determine device capabilities
2521 Based on pinning v47
2523 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
2525 pr_err("error %d\n", rc);
2528 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
2530 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
2532 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2534 pr_err("error %d\n", rc);
2537 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
2539 pr_err("error %d\n", rc);
2542 bid = (bid >> 10) & 0xf;
2543 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2545 pr_err("error %d\n", rc);
2549 ext_attr->has_lna = true;
2550 ext_attr->has_ntsc = false;
2551 ext_attr->has_btsc = false;
2552 ext_attr->has_oob = false;
2553 ext_attr->has_smatx = true;
2554 ext_attr->has_smarx = false;
2555 ext_attr->has_gpio = false;
2556 ext_attr->has_irqn = false;
2559 ext_attr->has_lna = false;
2560 ext_attr->has_ntsc = false;
2561 ext_attr->has_btsc = false;
2562 ext_attr->has_oob = false;
2563 ext_attr->has_smatx = true;
2564 ext_attr->has_smarx = false;
2565 ext_attr->has_gpio = false;
2566 ext_attr->has_irqn = false;
2569 ext_attr->has_lna = true;
2570 ext_attr->has_ntsc = true;
2571 ext_attr->has_btsc = false;
2572 ext_attr->has_oob = false;
2573 ext_attr->has_smatx = true;
2574 ext_attr->has_smarx = true;
2575 ext_attr->has_gpio = true;
2576 ext_attr->has_irqn = false;
2579 ext_attr->has_lna = false;
2580 ext_attr->has_ntsc = true;
2581 ext_attr->has_btsc = false;
2582 ext_attr->has_oob = false;
2583 ext_attr->has_smatx = true;
2584 ext_attr->has_smarx = true;
2585 ext_attr->has_gpio = true;
2586 ext_attr->has_irqn = false;
2589 ext_attr->has_lna = true;
2590 ext_attr->has_ntsc = true;
2591 ext_attr->has_btsc = true;
2592 ext_attr->has_oob = false;
2593 ext_attr->has_smatx = true;
2594 ext_attr->has_smarx = true;
2595 ext_attr->has_gpio = true;
2596 ext_attr->has_irqn = false;
2599 ext_attr->has_lna = false;
2600 ext_attr->has_ntsc = true;
2601 ext_attr->has_btsc = true;
2602 ext_attr->has_oob = false;
2603 ext_attr->has_smatx = true;
2604 ext_attr->has_smarx = true;
2605 ext_attr->has_gpio = true;
2606 ext_attr->has_irqn = false;
2609 ext_attr->has_lna = true;
2610 ext_attr->has_ntsc = false;
2611 ext_attr->has_btsc = false;
2612 ext_attr->has_oob = true;
2613 ext_attr->has_smatx = true;
2614 ext_attr->has_smarx = true;
2615 ext_attr->has_gpio = true;
2616 ext_attr->has_irqn = true;
2619 ext_attr->has_lna = false;
2620 ext_attr->has_ntsc = true;
2621 ext_attr->has_btsc = true;
2622 ext_attr->has_oob = true;
2623 ext_attr->has_smatx = true;
2624 ext_attr->has_smarx = true;
2625 ext_attr->has_gpio = true;
2626 ext_attr->has_irqn = true;
2629 ext_attr->has_lna = true;
2630 ext_attr->has_ntsc = true;
2631 ext_attr->has_btsc = true;
2632 ext_attr->has_oob = true;
2633 ext_attr->has_smatx = true;
2634 ext_attr->has_smarx = true;
2635 ext_attr->has_gpio = true;
2636 ext_attr->has_irqn = true;
2639 ext_attr->has_lna = false;
2640 ext_attr->has_ntsc = true;
2641 ext_attr->has_btsc = true;
2642 ext_attr->has_oob = true;
2643 ext_attr->has_smatx = true;
2644 ext_attr->has_smarx = true;
2645 ext_attr->has_gpio = true;
2646 ext_attr->has_irqn = true;
2649 /* Unknown device variant */
2660 * \fn int power_up_device()
2661 * \brief Power up device.
2662 * \param demod Pointer to demodulator instance.
2665 * \retval -EIO Failure, I2C or max retries reached
2669 #ifndef DRXJ_MAX_RETRIES_POWERUP
2670 #define DRXJ_MAX_RETRIES_POWERUP 10
2673 static int power_up_device(struct drx_demod_instance *demod)
2675 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2677 u16 retry_count = 0;
2678 struct i2c_device_addr wake_up_addr;
2680 dev_addr = demod->my_i2c_dev_addr;
2681 wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;
2682 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
2683 wake_up_addr.user_data = dev_addr->user_data;
2685 * I2C access may fail in this case: no ack
2686 * dummy write must be used to wake uop device, dummy read must be used to
2687 * reset HI state machine (avoiding actual writes)
2691 drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
2692 (struct i2c_device_addr *)(NULL), 0,
2696 } while ((drxbsp_i2c_write_read
2697 ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,
2699 != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));
2701 /* Need some recovery time .... */
2704 if (retry_count == DRXJ_MAX_RETRIES_POWERUP)
2710 /*----------------------------------------------------------------------------*/
2711 /* MPEG Output Configuration Functions - begin */
2712 /*----------------------------------------------------------------------------*/
2714 * \fn int ctrl_set_cfg_mpeg_output()
2715 * \brief Set MPEG output configuration of the device.
2716 * \param devmod Pointer to demodulator instance.
2717 * \param cfg_data Pointer to mpeg output configuaration.
2720 * Configure MPEG output parameters.
2724 ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
2726 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2727 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2728 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2730 u16 fec_oc_reg_mode = 0;
2731 u16 fec_oc_reg_ipr_mode = 0;
2732 u16 fec_oc_reg_ipr_invert = 0;
2733 u32 max_bit_rate = 0;
2736 u16 sio_pdr_md_cfg = 0;
2737 /* data mask for the output data byte */
2738 u16 invert_data_mask =
2739 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2740 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2741 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2742 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2744 /* check arguments */
2745 if ((demod == NULL) || (cfg_data == NULL))
2748 dev_addr = demod->my_i2c_dev_addr;
2749 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2750 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2752 if (cfg_data->enable_mpeg_output == true) {
2753 /* quick and dirty patch to set MPEG incase current std is not
2755 switch (ext_attr->standard) {
2756 case DRX_STANDARD_8VSB:
2757 case DRX_STANDARD_ITU_A:
2758 case DRX_STANDARD_ITU_B:
2759 case DRX_STANDARD_ITU_C:
2765 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
2767 pr_err("error %d\n", rc);
2770 switch (ext_attr->standard) {
2771 case DRX_STANDARD_8VSB:
2772 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
2774 pr_err("error %d\n", rc);
2776 } /* 2048 bytes fifo ram */
2777 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
2779 pr_err("error %d\n", rc);
2782 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
2784 pr_err("error %d\n", rc);
2787 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
2789 pr_err("error %d\n", rc);
2792 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
2794 pr_err("error %d\n", rc);
2797 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
2799 pr_err("error %d\n", rc);
2802 /* Low Water Mark for synchronization */
2803 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
2805 pr_err("error %d\n", rc);
2808 /* High Water Mark for synchronization */
2809 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
2811 pr_err("error %d\n", rc);
2815 case DRX_STANDARD_ITU_A:
2816 case DRX_STANDARD_ITU_C:
2817 switch (ext_attr->constellation) {
2818 case DRX_CONSTELLATION_QAM256:
2821 case DRX_CONSTELLATION_QAM128:
2824 case DRX_CONSTELLATION_QAM64:
2827 case DRX_CONSTELLATION_QAM32:
2830 case DRX_CONSTELLATION_QAM16:
2835 } /* ext_attr->constellation */
2836 /* max_bit_rate = symbol_rate * nr_bits * coef */
2837 /* coef = 188/204 */
2839 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2840 /* pass through as b/c Annex A/c need following settings */
2842 case DRX_STANDARD_ITU_B:
2843 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2845 pr_err("error %d\n", rc);
2848 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2850 pr_err("error %d\n", rc);
2853 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
2855 pr_err("error %d\n", rc);
2858 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
2860 pr_err("error %d\n", rc);
2863 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
2865 pr_err("error %d\n", rc);
2868 if (cfg_data->static_clk == true) {
2869 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
2871 pr_err("error %d\n", rc);
2875 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
2877 pr_err("error %d\n", rc);
2881 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
2883 pr_err("error %d\n", rc);
2886 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
2888 pr_err("error %d\n", rc);
2894 } /* swtich (standard) */
2896 /* Check insertion of the Reed-Solomon parity bytes */
2897 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
2899 pr_err("error %d\n", rc);
2902 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
2904 pr_err("error %d\n", rc);
2907 if (cfg_data->insert_rs_byte == true) {
2908 /* enable parity symbol forward */
2909 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2910 /* MVAL disable during parity bytes */
2911 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2912 switch (ext_attr->standard) {
2913 case DRX_STANDARD_8VSB:
2914 rcn_rate = 0x004854D3;
2916 case DRX_STANDARD_ITU_B:
2917 fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M;
2918 switch (ext_attr->constellation) {
2919 case DRX_CONSTELLATION_QAM256:
2920 rcn_rate = 0x008945E7;
2922 case DRX_CONSTELLATION_QAM64:
2923 rcn_rate = 0x005F64D4;
2929 case DRX_STANDARD_ITU_A:
2930 case DRX_STANDARD_ITU_C:
2931 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
2935 (u32) (common_attr->sys_clock_freq / 8))) /
2940 } /* ext_attr->standard */
2941 } else { /* insert_rs_byte == false */
2943 /* disable parity symbol forward */
2944 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2945 /* MVAL enable during parity bytes */
2946 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2947 switch (ext_attr->standard) {
2948 case DRX_STANDARD_8VSB:
2949 rcn_rate = 0x0041605C;
2951 case DRX_STANDARD_ITU_B:
2952 fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M);
2953 switch (ext_attr->constellation) {
2954 case DRX_CONSTELLATION_QAM256:
2955 rcn_rate = 0x0082D6A0;
2957 case DRX_CONSTELLATION_QAM64:
2958 rcn_rate = 0x005AEC1A;
2964 case DRX_STANDARD_ITU_A:
2965 case DRX_STANDARD_ITU_C:
2966 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
2970 (u32) (common_attr->sys_clock_freq / 8))) /
2975 } /* ext_attr->standard */
2978 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */
2979 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2980 } else { /* MPEG data output is serial -> set ipr_mode[0] */
2981 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2984 /* Control slective inversion of output bits */
2985 if (cfg_data->invert_data == true)
2986 fec_oc_reg_ipr_invert |= invert_data_mask;
2988 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2990 if (cfg_data->invert_err == true)
2991 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2993 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2995 if (cfg_data->invert_str == true)
2996 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2998 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
3000 if (cfg_data->invert_val == true)
3001 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
3003 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
3005 if (cfg_data->invert_clk == true)
3006 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
3008 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
3011 if (cfg_data->static_clk == true) { /* Static mode */
3014 u16 fec_oc_dto_burst_len = 0;
3015 u16 fec_oc_dto_period = 0;
3017 fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE;
3019 switch (ext_attr->standard) {
3020 case DRX_STANDARD_8VSB:
3021 fec_oc_dto_period = 4;
3022 if (cfg_data->insert_rs_byte == true)
3023 fec_oc_dto_burst_len = 208;
3025 case DRX_STANDARD_ITU_A:
3027 u32 symbol_rate_th = 6400000;
3028 if (cfg_data->insert_rs_byte == true) {
3029 fec_oc_dto_burst_len = 204;
3030 symbol_rate_th = 5900000;
3032 if (ext_attr->curr_symbol_rate >=
3034 fec_oc_dto_period = 0;
3036 fec_oc_dto_period = 1;
3040 case DRX_STANDARD_ITU_B:
3041 fec_oc_dto_period = 1;
3042 if (cfg_data->insert_rs_byte == true)
3043 fec_oc_dto_burst_len = 128;
3045 case DRX_STANDARD_ITU_C:
3046 fec_oc_dto_period = 1;
3047 if (cfg_data->insert_rs_byte == true)
3048 fec_oc_dto_burst_len = 204;
3054 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
3057 frac28(bit_rate, common_attr->sys_clock_freq * 1000);
3059 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
3061 pr_err("error %d\n", rc);
3064 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
3066 pr_err("error %d\n", rc);
3069 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
3071 pr_err("error %d\n", rc);
3074 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
3076 pr_err("error %d\n", rc);
3079 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
3081 pr_err("error %d\n", rc);
3084 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
3085 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
3086 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
3088 pr_err("error %d\n", rc);
3091 } else { /* Dynamic mode */
3093 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
3095 pr_err("error %d\n", rc);
3098 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
3100 pr_err("error %d\n", rc);
3105 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
3107 pr_err("error %d\n", rc);
3111 /* Write appropriate registers with requested configuration */
3112 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
3114 pr_err("error %d\n", rc);
3117 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
3119 pr_err("error %d\n", rc);
3122 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
3124 pr_err("error %d\n", rc);
3128 /* enabling for both parallel and serial now */
3129 /* Write magic word to enable pdr reg write */
3130 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3132 pr_err("error %d\n", rc);
3135 /* Set MPEG TS pads to outputmode */
3136 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
3138 pr_err("error %d\n", rc);
3141 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
3143 pr_err("error %d\n", rc);
3146 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
3148 pr_err("error %d\n", rc);
3151 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
3153 pr_err("error %d\n", rc);
3157 MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
3158 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
3159 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3161 pr_err("error %d\n", rc);
3164 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */
3166 MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
3167 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
3168 SIO_PDR_MD0_CFG_MODE__B;
3169 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3171 pr_err("error %d\n", rc);
3174 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
3176 pr_err("error %d\n", rc);
3179 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
3181 pr_err("error %d\n", rc);
3184 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
3186 pr_err("error %d\n", rc);
3189 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
3191 pr_err("error %d\n", rc);
3194 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
3196 pr_err("error %d\n", rc);
3199 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
3201 pr_err("error %d\n", rc);
3204 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
3206 pr_err("error %d\n", rc);
3209 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */
3210 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3212 pr_err("error %d\n", rc);
3215 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3217 pr_err("error %d\n", rc);
3220 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3222 pr_err("error %d\n", rc);
3225 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3227 pr_err("error %d\n", rc);
3230 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3232 pr_err("error %d\n", rc);
3235 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3237 pr_err("error %d\n", rc);
3240 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3242 pr_err("error %d\n", rc);
3246 /* Enable Monitor Bus output over MPEG pads and ctl input */
3247 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3249 pr_err("error %d\n", rc);
3252 /* Write nomagic word to enable pdr reg write */
3253 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3255 pr_err("error %d\n", rc);
3259 /* Write magic word to enable pdr reg write */
3260 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3262 pr_err("error %d\n", rc);
3265 /* Set MPEG TS pads to inputmode */
3266 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
3268 pr_err("error %d\n", rc);
3271 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
3273 pr_err("error %d\n", rc);
3276 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
3278 pr_err("error %d\n", rc);
3281 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
3283 pr_err("error %d\n", rc);
3286 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
3288 pr_err("error %d\n", rc);
3291 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3293 pr_err("error %d\n", rc);
3296 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3298 pr_err("error %d\n", rc);
3301 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3303 pr_err("error %d\n", rc);
3306 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3308 pr_err("error %d\n", rc);
3311 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3313 pr_err("error %d\n", rc);
3316 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3318 pr_err("error %d\n", rc);
3321 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3323 pr_err("error %d\n", rc);
3326 /* Enable Monitor Bus output over MPEG pads and ctl input */
3327 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3329 pr_err("error %d\n", rc);
3332 /* Write nomagic word to enable pdr reg write */
3333 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3335 pr_err("error %d\n", rc);
3340 /* save values for restore after re-acquire */
3341 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
3348 /*----------------------------------------------------------------------------*/
3351 /*----------------------------------------------------------------------------*/
3352 /* MPEG Output Configuration Functions - end */
3353 /*----------------------------------------------------------------------------*/
3355 /*----------------------------------------------------------------------------*/
3356 /* miscellaneous configurations - begin */
3357 /*----------------------------------------------------------------------------*/
3360 * \fn int set_mpegtei_handling()
3361 * \brief Activate MPEG TEI handling settings.
3362 * \param devmod Pointer to demodulator instance.
3365 * This routine should be called during a set channel of QAM/VSB
3368 static int set_mpegtei_handling(struct drx_demod_instance *demod)
3370 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3371 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3373 u16 fec_oc_dpr_mode = 0;
3374 u16 fec_oc_snc_mode = 0;
3375 u16 fec_oc_ems_mode = 0;
3377 dev_addr = demod->my_i2c_dev_addr;
3378 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3380 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
3382 pr_err("error %d\n", rc);
3385 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
3387 pr_err("error %d\n", rc);
3390 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
3392 pr_err("error %d\n", rc);
3396 /* reset to default, allow TEI bit to be changed */
3397 fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);
3398 fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |
3399 FEC_OC_SNC_MODE_CORR_DISABLE__M));
3400 fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
3402 if (ext_attr->disable_te_ihandling) {
3403 /* do not change TEI bit */
3404 fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
3405 fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
3406 ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));
3407 fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));
3410 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
3412 pr_err("error %d\n", rc);
3415 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
3417 pr_err("error %d\n", rc);
3420 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
3422 pr_err("error %d\n", rc);
3431 /*----------------------------------------------------------------------------*/
3433 * \fn int bit_reverse_mpeg_output()
3434 * \brief Set MPEG output bit-endian settings.
3435 * \param devmod Pointer to demodulator instance.
3438 * This routine should be called during a set channel of QAM/VSB
3441 static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)
3443 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3444 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3446 u16 fec_oc_ipr_mode = 0;
3448 dev_addr = demod->my_i2c_dev_addr;
3449 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3451 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
3453 pr_err("error %d\n", rc);
3457 /* reset to default (normal bit order) */
3458 fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
3460 if (ext_attr->bit_reverse_mpeg_outout)
3461 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
3463 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
3465 pr_err("error %d\n", rc);
3474 /*----------------------------------------------------------------------------*/
3476 * \fn int set_mpeg_start_width()
3477 * \brief Set MPEG start width.
3478 * \param devmod Pointer to demodulator instance.
3481 * This routine should be called during a set channel of QAM/VSB
3484 static int set_mpeg_start_width(struct drx_demod_instance *demod)
3486 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3487 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3488 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
3490 u16 fec_oc_comm_mb = 0;
3492 dev_addr = demod->my_i2c_dev_addr;
3493 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3494 common_attr = demod->my_common_attr;
3496 if ((common_attr->mpeg_cfg.static_clk == true)
3497 && (common_attr->mpeg_cfg.enable_parallel == false)) {
3498 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
3500 pr_err("error %d\n", rc);
3503 fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;
3504 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
3505 fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;
3506 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
3508 pr_err("error %d\n", rc);
3518 /*----------------------------------------------------------------------------*/
3519 /* miscellaneous configurations - end */
3520 /*----------------------------------------------------------------------------*/
3522 /*----------------------------------------------------------------------------*/
3523 /* UIO Configuration Functions - begin */
3524 /*----------------------------------------------------------------------------*/
3526 * \fn int ctrl_set_uio_cfg()
3527 * \brief Configure modus oprandi UIO.
3528 * \param demod Pointer to demodulator instance.
3529 * \param uio_cfg Pointer to a configuration setting for a certain UIO.
3532 static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
3534 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3537 if ((uio_cfg == NULL) || (demod == NULL))
3540 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3542 /* Write magic word to enable pdr reg write */
3543 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3545 pr_err("error %d\n", rc);
3548 switch (uio_cfg->uio) {
3549 /*====================================================================*/
3551 /* DRX_UIO1: SMA_TX UIO-1 */
3552 if (!ext_attr->has_smatx)
3554 switch (uio_cfg->mode) {
3555 case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */
3556 case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */
3557 case DRX_UIO_MODE_READWRITE:
3558 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3560 case DRX_UIO_MODE_DISABLE:
3561 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3562 /* pad configuration register is set 0 - input mode */
3563 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3565 pr_err("error %d\n", rc);
3571 } /* switch ( uio_cfg->mode ) */
3573 /*====================================================================*/
3575 /* DRX_UIO2: SMA_RX UIO-2 */
3576 if (!ext_attr->has_smarx)
3578 switch (uio_cfg->mode) {
3579 case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
3580 case DRX_UIO_MODE_READWRITE:
3581 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3583 case DRX_UIO_MODE_DISABLE:
3584 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3585 /* pad configuration register is set 0 - input mode */
3586 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3588 pr_err("error %d\n", rc);
3595 } /* switch ( uio_cfg->mode ) */
3597 /*====================================================================*/
3599 /* DRX_UIO3: GPIO UIO-3 */
3600 if (!ext_attr->has_gpio)
3602 switch (uio_cfg->mode) {
3603 case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
3604 case DRX_UIO_MODE_READWRITE:
3605 ext_attr->uio_gpio_mode = uio_cfg->mode;
3607 case DRX_UIO_MODE_DISABLE:
3608 ext_attr->uio_gpio_mode = uio_cfg->mode;
3609 /* pad configuration register is set 0 - input mode */
3610 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3612 pr_err("error %d\n", rc);
3619 } /* switch ( uio_cfg->mode ) */
3621 /*====================================================================*/
3623 /* DRX_UIO4: IRQN UIO-4 */
3624 if (!ext_attr->has_irqn)
3626 switch (uio_cfg->mode) {
3627 case DRX_UIO_MODE_READWRITE:
3628 ext_attr->uio_irqn_mode = uio_cfg->mode;
3630 case DRX_UIO_MODE_DISABLE:
3631 /* pad configuration register is set 0 - input mode */
3632 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3634 pr_err("error %d\n", rc);
3637 ext_attr->uio_irqn_mode = uio_cfg->mode;
3639 case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
3643 } /* switch ( uio_cfg->mode ) */
3645 /*====================================================================*/
3648 } /* switch ( uio_cfg->uio ) */
3650 /* Write magic word to disable pdr reg write */
3651 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3653 pr_err("error %d\n", rc);
3663 * \fn int ctrl_uio_write()
3664 * \brief Write to a UIO.
3665 * \param demod Pointer to demodulator instance.
3666 * \param uio_data Pointer to data container for a certain UIO.
3670 ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
3672 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3674 u16 pin_cfg_value = 0;
3677 if ((uio_data == NULL) || (demod == NULL))
3680 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3682 /* Write magic word to enable pdr reg write */
3683 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3685 pr_err("error %d\n", rc);
3688 switch (uio_data->uio) {
3689 /*====================================================================*/
3691 /* DRX_UIO1: SMA_TX UIO-1 */
3692 if (!ext_attr->has_smatx)
3694 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
3695 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
3699 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3700 pin_cfg_value |= 0x0113;
3701 /* io_pad_cfg_mode output mode is drive always */
3702 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3704 /* write to io pad configuration register - output mode */
3705 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3707 pr_err("error %d\n", rc);
3711 /* use corresponding bit in io data output registar */
3712 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3714 pr_err("error %d\n", rc);
3717 if (!uio_data->value)
3718 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
3720 value |= 0x8000; /* write one to 15th bit - 1st UIO */
3722 /* write back to io data output register */
3723 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3725 pr_err("error %d\n", rc);
3729 /*======================================================================*/
3731 /* DRX_UIO2: SMA_RX UIO-2 */
3732 if (!ext_attr->has_smarx)
3734 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
3738 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3739 pin_cfg_value |= 0x0113;
3740 /* io_pad_cfg_mode output mode is drive always */
3741 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3743 /* write to io pad configuration register - output mode */
3744 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3746 pr_err("error %d\n", rc);
3750 /* use corresponding bit in io data output registar */
3751 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3753 pr_err("error %d\n", rc);
3756 if (!uio_data->value)
3757 value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */
3759 value |= 0x4000; /* write one to 14th bit - 2nd UIO */
3761 /* write back to io data output register */
3762 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3764 pr_err("error %d\n", rc);
3768 /*====================================================================*/
3770 /* DRX_UIO3: ASEL UIO-3 */
3771 if (!ext_attr->has_gpio)
3773 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
3777 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3778 pin_cfg_value |= 0x0113;
3779 /* io_pad_cfg_mode output mode is drive always */
3780 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3782 /* write to io pad configuration register - output mode */
3783 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3785 pr_err("error %d\n", rc);
3789 /* use corresponding bit in io data output registar */
3790 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3792 pr_err("error %d\n", rc);
3795 if (!uio_data->value)
3796 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
3798 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
3800 /* write back to io data output register */
3801 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3803 pr_err("error %d\n", rc);
3807 /*=====================================================================*/
3809 /* DRX_UIO4: IRQN UIO-4 */
3810 if (!ext_attr->has_irqn)
3813 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
3817 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3818 pin_cfg_value |= 0x0113;
3819 /* io_pad_cfg_mode output mode is drive always */
3820 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3822 /* write to io pad configuration register - output mode */
3823 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3825 pr_err("error %d\n", rc);
3829 /* use corresponding bit in io data output registar */
3830 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3832 pr_err("error %d\n", rc);
3835 if (uio_data->value == false)
3836 value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */
3838 value |= 0x1000; /* write one to 12th bit - 4th UIO */
3840 /* write back to io data output register */
3841 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3843 pr_err("error %d\n", rc);
3847 /*=====================================================================*/
3850 } /* switch ( uio_data->uio ) */
3852 /* Write magic word to disable pdr reg write */
3853 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3855 pr_err("error %d\n", rc);
3864 /*---------------------------------------------------------------------------*/
3865 /* UIO Configuration Functions - end */
3866 /*---------------------------------------------------------------------------*/
3868 /*----------------------------------------------------------------------------*/
3869 /* I2C Bridge Functions - begin */
3870 /*----------------------------------------------------------------------------*/
3872 * \fn int ctrl_i2c_bridge()
3873 * \brief Open or close the I2C switch to tuner.
3874 * \param demod Pointer to demodulator instance.
3875 * \param bridge_closed Pointer to bool indication if bridge is closed not.
3880 ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed)
3882 struct drxj_hi_cmd hi_cmd;
3885 /* check arguments */
3886 if (bridge_closed == NULL)
3889 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
3890 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
3892 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
3894 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
3896 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
3899 /*----------------------------------------------------------------------------*/
3900 /* I2C Bridge Functions - end */
3901 /*----------------------------------------------------------------------------*/
3903 /*----------------------------------------------------------------------------*/
3904 /* Smart antenna Functions - begin */
3905 /*----------------------------------------------------------------------------*/
3907 * \fn int smart_ant_init()
3908 * \brief Initialize Smart Antenna.
3909 * \param pointer to struct drx_demod_instance.
3913 static int smart_ant_init(struct drx_demod_instance *demod)
3915 struct drxj_data *ext_attr = NULL;
3916 struct i2c_device_addr *dev_addr = NULL;
3917 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };
3921 dev_addr = demod->my_i2c_dev_addr;
3922 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3924 /* Write magic word to enable pdr reg write */
3925 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3927 pr_err("error %d\n", rc);
3930 /* init smart antenna */
3931 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3933 pr_err("error %d\n", rc);
3936 if (ext_attr->smart_ant_inverted) {
3937 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3939 pr_err("error %d\n", rc);
3943 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3945 pr_err("error %d\n", rc);
3950 /* config SMA_TX pin to smart antenna mode */
3951 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
3953 pr_err("error %d\n", rc);
3956 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3958 pr_err("error %d\n", rc);
3961 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3963 pr_err("error %d\n", rc);
3967 /* Write magic word to disable pdr reg write */
3968 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3970 pr_err("error %d\n", rc);
3979 static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
3983 unsigned long timeout;
3989 /* Wait until SCU command interface is ready to receive command */
3990 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
3992 pr_err("error %d\n", rc);
3995 if (cur_cmd != DRX_SCU_READY)
3998 switch (cmd->parameter_len) {
4000 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
4002 pr_err("error %d\n", rc);
4006 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4008 pr_err("error %d\n", rc);
4012 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4014 pr_err("error %d\n", rc);
4018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4020 pr_err("error %d\n", rc);
4024 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4026 pr_err("error %d\n", rc);
4033 /* this number of parameters is not supported */
4036 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4038 pr_err("error %d\n", rc);
4042 /* Wait until SCU has processed command */
4043 timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME);
4044 while (time_is_after_jiffies(timeout)) {
4045 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
4047 pr_err("error %d\n", rc);
4050 if (cur_cmd == DRX_SCU_READY)
4052 usleep_range(1000, 2000);
4055 if (cur_cmd != DRX_SCU_READY)
4059 if ((cmd->result_len > 0) && (cmd->result != NULL)) {
4062 switch (cmd->result_len) {
4064 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4066 pr_err("error %d\n", rc);
4070 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4072 pr_err("error %d\n", rc);
4076 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4078 pr_err("error %d\n", rc);
4082 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4084 pr_err("error %d\n", rc);
4091 /* this number of parameters is not supported */
4095 /* Check if an error was reported by SCU */
4096 err = cmd->result[0];
4098 /* check a few fixed error codes */
4099 if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD)
4100 || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD)
4101 || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR)
4102 || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE)
4106 /* here it is assumed that negative means error, and positive no error */
4120 * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock()
4121 * \brief Basic access routine for SCU atomic read or write access
4122 * \param dev_addr pointer to i2c dev address
4123 * \param addr destination/source address
4124 * \param datasize size of data buffer in bytes
4125 * \param data pointer to data buffer
4128 * \retval -EIO Timeout, I2C error, illegal bank
4131 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4133 int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */
4134 u8 *data, bool read_flag)
4136 struct drxjscu_cmd scu_cmd;
4138 u16 set_param_parameters[18];
4141 /* Parameter check */
4142 if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
4145 set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
4146 if (read_flag) { /* read */
4147 set_param_parameters[0] = ((~(0x0080)) & datasize);
4148 scu_cmd.parameter_len = 2;
4149 scu_cmd.result_len = datasize / 2 + 2;
4153 set_param_parameters[0] = 0x0080 | datasize;
4154 for (i = 0; i < (datasize / 2); i++) {
4155 set_param_parameters[i + 2] =
4156 (data[2 * i] | (data[(2 * i) + 1] << 8));
4158 scu_cmd.parameter_len = datasize / 2 + 2;
4159 scu_cmd.result_len = 1;
4163 SCU_RAM_COMMAND_STANDARD_TOP |
4164 SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
4165 scu_cmd.result = cmd_result;
4166 scu_cmd.parameter = set_param_parameters;
4167 rc = scu_command(dev_addr, &scu_cmd);
4169 pr_err("error %d\n", rc);
4175 /* read data from buffer */
4176 for (i = 0; i < (datasize / 2); i++) {
4177 data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
4178 data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
4189 /*============================================================================*/
4192 * \fn int DRXJ_DAP_AtomicReadReg16()
4193 * \brief Atomic read of 16 bits words
4196 int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr,
4198 u16 *data, u32 flags)
4207 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4211 word = (u16) (buf[0] + (buf[1] << 8));
4218 /*============================================================================*/
4220 * \fn int drxj_dap_scu_atomic_write_reg16()
4221 * \brief Atomic read of 16 bits words
4224 int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr,
4226 u16 data, u32 flags)
4231 buf[0] = (u8) (data & 0xff);
4232 buf[1] = (u8) ((data >> 8) & 0xff);
4234 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
4239 /* -------------------------------------------------------------------------- */
4241 * \brief Measure result of ADC synchronisation
4242 * \param demod demod instance
4243 * \param count (returned) count
4246 * \retval -EIO Failure: I2C error
4249 static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)
4251 struct i2c_device_addr *dev_addr = NULL;
4255 dev_addr = demod->my_i2c_dev_addr;
4257 /* Start measurement */
4258 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
4260 pr_err("error %d\n", rc);
4263 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
4265 pr_err("error %d\n", rc);
4269 /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */
4273 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4275 pr_err("error %d\n", rc);
4279 *count = *count + 1;
4280 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4282 pr_err("error %d\n", rc);
4286 *count = *count + 1;
4287 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4289 pr_err("error %d\n", rc);
4293 *count = *count + 1;
4301 * \brief Synchronize analog and digital clock domains
4302 * \param demod demod instance
4305 * \retval -EIO Failure: I2C error or failure to synchronize
4307 * An IQM reset will also reset the results of this synchronization.
4308 * After an IQM reset this routine needs to be called again.
4312 static int adc_synchronization(struct drx_demod_instance *demod)
4314 struct i2c_device_addr *dev_addr = NULL;
4318 dev_addr = demod->my_i2c_dev_addr;
4320 rc = adc_sync_measurement(demod, &count);
4322 pr_err("error %d\n", rc);
4327 /* Try sampling on a different edge */
4330 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
4332 pr_err("error %d\n", rc);
4336 clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M;
4337 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
4339 pr_err("error %d\n", rc);
4343 rc = adc_sync_measurement(demod, &count);
4345 pr_err("error %d\n", rc);
4350 /* TODO: implement fallback scenarios */
4359 /*============================================================================*/
4360 /*== END AUXILIARY FUNCTIONS ==*/
4361 /*============================================================================*/
4363 /*============================================================================*/
4364 /*============================================================================*/
4365 /*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
4366 /*============================================================================*/
4367 /*============================================================================*/
4369 * \fn int init_agc ()
4370 * \brief Initialize AGC for all standards.
4371 * \param demod instance of demodulator.
4372 * \param channel pointer to channel data.
4375 static int init_agc(struct drx_demod_instance *demod)
4377 struct i2c_device_addr *dev_addr = NULL;
4378 struct drx_common_attr *common_attr = NULL;
4379 struct drxj_data *ext_attr = NULL;
4380 struct drxj_cfg_agc *p_agc_rf_settings = NULL;
4381 struct drxj_cfg_agc *p_agc_if_settings = NULL;
4383 u16 ingain_tgt_max = 0;
4385 u16 sns_sum_max = 0;
4386 u16 clp_sum_max = 0;
4388 u16 ki_innergain_min = 0;
4391 u16 if_iaccu_hi_tgt_min = 0;
4393 u16 agc_ki_dgain = 0;
4395 u16 clp_ctrl_mode = 0;
4399 dev_addr = demod->my_i2c_dev_addr;
4400 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4401 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4403 switch (ext_attr->standard) {
4404 case DRX_STANDARD_8VSB:
4406 clp_dir_to = (u16) (-9);
4408 sns_dir_to = (u16) (-9);
4409 ki_innergain_min = (u16) (-32768);
4412 if_iaccu_hi_tgt_min = 2047;
4414 ingain_tgt_max = 16383;
4416 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4418 pr_err("error %d\n", rc);
4421 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4423 pr_err("error %d\n", rc);
4426 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4428 pr_err("error %d\n", rc);
4431 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4433 pr_err("error %d\n", rc);
4436 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4438 pr_err("error %d\n", rc);
4441 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4443 pr_err("error %d\n", rc);
4446 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4448 pr_err("error %d\n", rc);
4451 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4453 pr_err("error %d\n", rc);
4456 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4458 pr_err("error %d\n", rc);
4461 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4463 pr_err("error %d\n", rc);
4466 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
4468 pr_err("error %d\n", rc);
4471 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
4473 pr_err("error %d\n", rc);
4476 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
4478 pr_err("error %d\n", rc);
4481 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
4482 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
4484 #ifndef DRXJ_VSB_ONLY
4485 case DRX_STANDARD_ITU_A:
4486 case DRX_STANDARD_ITU_C:
4487 case DRX_STANDARD_ITU_B:
4488 ingain_tgt_max = 5119;
4490 clp_dir_to = (u16) (-5);
4492 sns_dir_to = (u16) (-3);
4493 ki_innergain_min = 0;
4495 if_iaccu_hi_tgt_min = 2047;
4499 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4501 pr_err("error %d\n", rc);
4504 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4506 pr_err("error %d\n", rc);
4509 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4511 pr_err("error %d\n", rc);
4514 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4516 pr_err("error %d\n", rc);
4519 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4521 pr_err("error %d\n", rc);
4524 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4526 pr_err("error %d\n", rc);
4529 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4531 pr_err("error %d\n", rc);
4534 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4536 pr_err("error %d\n", rc);
4539 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4541 pr_err("error %d\n", rc);
4544 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4546 pr_err("error %d\n", rc);
4549 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
4550 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
4551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4553 pr_err("error %d\n", rc);
4557 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
4559 pr_err("error %d\n", rc);
4563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
4565 pr_err("error %d\n", rc);
4574 /* for new AGC interface */
4575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4577 pr_err("error %d\n", rc);
4580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4582 pr_err("error %d\n", rc);
4584 } /* Gain fed from inner to outer AGC */
4585 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
4587 pr_err("error %d\n", rc);
4590 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
4592 pr_err("error %d\n", rc);
4595 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
4597 pr_err("error %d\n", rc);
4599 } /* set to p_agc_settings->top before */
4600 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
4602 pr_err("error %d\n", rc);
4605 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
4607 pr_err("error %d\n", rc);
4610 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
4612 pr_err("error %d\n", rc);
4615 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
4617 pr_err("error %d\n", rc);
4620 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
4622 pr_err("error %d\n", rc);
4625 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
4627 pr_err("error %d\n", rc);
4630 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
4632 pr_err("error %d\n", rc);
4635 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
4637 pr_err("error %d\n", rc);
4640 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
4642 pr_err("error %d\n", rc);
4645 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
4647 pr_err("error %d\n", rc);
4650 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
4652 pr_err("error %d\n", rc);
4655 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
4657 pr_err("error %d\n", rc);
4660 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
4662 pr_err("error %d\n", rc);
4665 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
4667 pr_err("error %d\n", rc);
4670 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
4672 pr_err("error %d\n", rc);
4675 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
4677 pr_err("error %d\n", rc);
4680 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
4682 pr_err("error %d\n", rc);
4685 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
4687 pr_err("error %d\n", rc);
4690 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
4692 pr_err("error %d\n", rc);
4695 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
4697 pr_err("error %d\n", rc);
4700 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
4702 pr_err("error %d\n", rc);
4706 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
4707 if (common_attr->tuner_rf_agc_pol == true)
4708 agc_rf = 0x87ff - agc_rf;
4711 if (common_attr->tuner_if_agc_pol == true)
4712 agc_rf = 0x87ff - agc_rf;
4714 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
4716 pr_err("error %d\n", rc);
4719 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
4721 pr_err("error %d\n", rc);
4725 /* Set/restore Ki DGAIN factor */
4726 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4728 pr_err("error %d\n", rc);
4731 data &= ~SCU_RAM_AGC_KI_DGAIN__M;
4732 data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
4733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4735 pr_err("error %d\n", rc);
4745 * \fn int set_frequency ()
4746 * \brief Set frequency shift.
4747 * \param demod instance of demodulator.
4748 * \param channel pointer to channel data.
4749 * \param tuner_freq_offset residual frequency from tuner.
4753 set_frequency(struct drx_demod_instance *demod,
4754 struct drx_channel *channel, s32 tuner_freq_offset)
4756 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
4757 struct drxj_data *ext_attr = demod->my_ext_attr;
4759 s32 sampling_frequency = 0;
4760 s32 frequency_shift = 0;
4761 s32 if_freq_actual = 0;
4762 s32 rf_freq_residual = -1 * tuner_freq_offset;
4764 s32 intermediate_freq = 0;
4765 u32 iqm_fs_rate_ofs = 0;
4766 bool adc_flip = true;
4767 bool select_pos_image = false;
4770 bool image_to_select = true;
4771 s32 fm_frequency_shift = 0;
4773 rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false;
4774 tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true;
4776 Program frequency shifter
4777 No need to account for mirroring on RF
4779 switch (ext_attr->standard) {
4780 case DRX_STANDARD_ITU_A:
4781 case DRX_STANDARD_ITU_C:
4782 case DRX_STANDARD_PAL_SECAM_LP:
4783 case DRX_STANDARD_8VSB:
4784 select_pos_image = true;
4786 case DRX_STANDARD_FM:
4787 /* After IQM FS sound carrier must appear at 4 Mhz in spect.
4788 Sound carrier is already 3Mhz above centre frequency due
4789 to tuner setting so now add an extra shift of 1MHz... */
4790 fm_frequency_shift = 1000;
4792 case DRX_STANDARD_ITU_B:
4793 case DRX_STANDARD_NTSC:
4794 case DRX_STANDARD_PAL_SECAM_BG:
4795 case DRX_STANDARD_PAL_SECAM_DK:
4796 case DRX_STANDARD_PAL_SECAM_I:
4797 case DRX_STANDARD_PAL_SECAM_L:
4798 select_pos_image = false;
4803 intermediate_freq = demod->my_common_attr->intermediate_freq;
4804 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
4806 if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift;
4808 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
4809 if (if_freq_actual > sampling_frequency / 2) {
4811 adc_freq = sampling_frequency - if_freq_actual;
4814 /* adc doesn't mirror */
4815 adc_freq = if_freq_actual;
4819 frequency_shift = adc_freq;
4821 (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image);
4822 iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency);
4824 if (image_to_select)
4825 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
4827 /* Program frequency shifter with tuner offset compensation */
4828 /* frequency_shift += tuner_freq_offset; TODO */
4829 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
4831 pr_err("error %d\n", rc);
4834 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
4835 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
4843 * \fn int get_acc_pkt_err()
4844 * \brief Retrieve signal strength for VSB and QAM.
4845 * \param demod Pointer to demod instance
4846 * \param packet_err Pointer to packet error
4848 * \retval 0 sig_strength contains valid data.
4849 * \retval -EINVAL sig_strength is NULL.
4850 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4852 #ifdef DRXJ_SIGNAL_ACCUM_ERR
4853 static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err)
4857 static u16 last_pkt_err;
4859 struct drxj_data *ext_attr = NULL;
4860 struct i2c_device_addr *dev_addr = NULL;
4862 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4863 dev_addr = demod->my_i2c_dev_addr;
4865 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4867 pr_err("error %d\n", rc);
4870 if (ext_attr->reset_pkt_err_acc) {
4871 last_pkt_err = data;
4873 ext_attr->reset_pkt_err_acc = false;
4876 if (data < last_pkt_err) {
4877 pkt_err += 0xffff - last_pkt_err;
4880 pkt_err += (data - last_pkt_err);
4882 *packet_err = pkt_err;
4883 last_pkt_err = data;
4892 /*============================================================================*/
4895 * \fn int set_agc_rf ()
4896 * \brief Configure RF AGC
4897 * \param demod instance of demodulator.
4898 * \param agc_settings AGC configuration structure
4902 set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
4904 struct i2c_device_addr *dev_addr = NULL;
4905 struct drxj_data *ext_attr = NULL;
4906 struct drxj_cfg_agc *p_agc_settings = NULL;
4907 struct drx_common_attr *common_attr = NULL;
4909 drx_write_reg16func_t scu_wr16 = NULL;
4910 drx_read_reg16func_t scu_rr16 = NULL;
4912 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4913 dev_addr = demod->my_i2c_dev_addr;
4914 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4917 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
4918 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
4920 scu_rr16 = drxj_dap_read_reg16;
4921 scu_wr16 = drxj_dap_write_reg16;
4924 /* Configure AGC only if standard is currently active */
4925 if ((ext_attr->standard == agc_settings->standard) ||
4926 (DRXJ_ISQAMSTD(ext_attr->standard) &&
4927 DRXJ_ISQAMSTD(agc_settings->standard)) ||
4928 (DRXJ_ISATVSTD(ext_attr->standard) &&
4929 DRXJ_ISATVSTD(agc_settings->standard))) {
4932 switch (agc_settings->ctrl_mode) {
4933 case DRX_AGC_CTRL_AUTO:
4935 /* Enable RF AGC DAC */
4936 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4938 pr_err("error %d\n", rc);
4941 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
4942 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4944 pr_err("error %d\n", rc);
4948 /* Enable SCU RF AGC loop */
4949 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4951 pr_err("error %d\n", rc);
4954 data &= ~SCU_RAM_AGC_KI_RF__M;
4955 if (ext_attr->standard == DRX_STANDARD_8VSB)
4956 data |= (2 << SCU_RAM_AGC_KI_RF__B);
4957 else if (DRXJ_ISQAMSTD(ext_attr->standard))
4958 data |= (5 << SCU_RAM_AGC_KI_RF__B);
4960 data |= (4 << SCU_RAM_AGC_KI_RF__B);
4962 if (common_attr->tuner_rf_agc_pol)
4963 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
4965 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
4966 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4968 pr_err("error %d\n", rc);
4972 /* Set speed ( using complementary reduction value ) */
4973 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4975 pr_err("error %d\n", rc);
4978 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
4979 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4981 pr_err("error %d\n", rc);
4985 if (agc_settings->standard == DRX_STANDARD_8VSB)
4986 p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
4987 else if (DRXJ_ISQAMSTD(agc_settings->standard))
4988 p_agc_settings = &(ext_attr->qam_if_agc_cfg);
4989 else if (DRXJ_ISATVSTD(agc_settings->standard))
4990 p_agc_settings = &(ext_attr->atv_if_agc_cfg);
4994 /* Set TOP, only if IF-AGC is in AUTO mode */
4995 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
4996 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
4998 pr_err("error %d\n", rc);
5001 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
5003 pr_err("error %d\n", rc);
5008 /* Cut-Off current */
5009 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5011 pr_err("error %d\n", rc);
5015 case DRX_AGC_CTRL_USER:
5017 /* Enable RF AGC DAC */
5018 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5020 pr_err("error %d\n", rc);
5023 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
5024 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5026 pr_err("error %d\n", rc);
5030 /* Disable SCU RF AGC loop */
5031 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5033 pr_err("error %d\n", rc);
5036 data &= ~SCU_RAM_AGC_KI_RF__M;
5037 if (common_attr->tuner_rf_agc_pol)
5038 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
5040 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
5041 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5043 pr_err("error %d\n", rc);
5047 /* Write value to output pin */
5048 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5050 pr_err("error %d\n", rc);
5054 case DRX_AGC_CTRL_OFF:
5056 /* Disable RF AGC DAC */
5057 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5059 pr_err("error %d\n", rc);
5062 data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5063 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5065 pr_err("error %d\n", rc);
5069 /* Disable SCU RF AGC loop */
5070 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5072 pr_err("error %d\n", rc);
5075 data &= ~SCU_RAM_AGC_KI_RF__M;
5076 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5078 pr_err("error %d\n", rc);
5084 } /* switch ( agcsettings->ctrl_mode ) */
5087 /* Store rf agc settings */
5088 switch (agc_settings->standard) {
5089 case DRX_STANDARD_8VSB:
5090 ext_attr->vsb_rf_agc_cfg = *agc_settings;
5092 #ifndef DRXJ_VSB_ONLY
5093 case DRX_STANDARD_ITU_A:
5094 case DRX_STANDARD_ITU_B:
5095 case DRX_STANDARD_ITU_C:
5096 ext_attr->qam_rf_agc_cfg = *agc_settings;
5109 * \fn int set_agc_if ()
5110 * \brief Configure If AGC
5111 * \param demod instance of demodulator.
5112 * \param agc_settings AGC configuration structure
5116 set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
5118 struct i2c_device_addr *dev_addr = NULL;
5119 struct drxj_data *ext_attr = NULL;
5120 struct drxj_cfg_agc *p_agc_settings = NULL;
5121 struct drx_common_attr *common_attr = NULL;
5122 drx_write_reg16func_t scu_wr16 = NULL;
5123 drx_read_reg16func_t scu_rr16 = NULL;
5126 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5127 dev_addr = demod->my_i2c_dev_addr;
5128 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5131 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
5132 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
5134 scu_rr16 = drxj_dap_read_reg16;
5135 scu_wr16 = drxj_dap_write_reg16;
5138 /* Configure AGC only if standard is currently active */
5139 if ((ext_attr->standard == agc_settings->standard) ||
5140 (DRXJ_ISQAMSTD(ext_attr->standard) &&
5141 DRXJ_ISQAMSTD(agc_settings->standard)) ||
5142 (DRXJ_ISATVSTD(ext_attr->standard) &&
5143 DRXJ_ISATVSTD(agc_settings->standard))) {
5146 switch (agc_settings->ctrl_mode) {
5147 case DRX_AGC_CTRL_AUTO:
5148 /* Enable IF AGC DAC */
5149 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5151 pr_err("error %d\n", rc);
5154 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5155 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5157 pr_err("error %d\n", rc);
5161 /* Enable SCU IF AGC loop */
5162 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5164 pr_err("error %d\n", rc);
5167 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5168 data &= ~SCU_RAM_AGC_KI_IF__M;
5169 if (ext_attr->standard == DRX_STANDARD_8VSB)
5170 data |= (3 << SCU_RAM_AGC_KI_IF__B);
5171 else if (DRXJ_ISQAMSTD(ext_attr->standard))
5172 data |= (6 << SCU_RAM_AGC_KI_IF__B);
5174 data |= (5 << SCU_RAM_AGC_KI_IF__B);
5176 if (common_attr->tuner_if_agc_pol)
5177 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5179 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5180 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5182 pr_err("error %d\n", rc);
5186 /* Set speed (using complementary reduction value) */
5187 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5189 pr_err("error %d\n", rc);
5192 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
5193 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5195 pr_err("error %d\n", rc);
5199 if (agc_settings->standard == DRX_STANDARD_8VSB)
5200 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
5201 else if (DRXJ_ISQAMSTD(agc_settings->standard))
5202 p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
5203 else if (DRXJ_ISATVSTD(agc_settings->standard))
5204 p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
5209 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5210 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5212 pr_err("error %d\n", rc);
5215 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5217 pr_err("error %d\n", rc);
5221 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
5223 pr_err("error %d\n", rc);
5226 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
5228 pr_err("error %d\n", rc);
5234 case DRX_AGC_CTRL_USER:
5236 /* Enable IF AGC DAC */
5237 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5239 pr_err("error %d\n", rc);
5242 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5243 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5245 pr_err("error %d\n", rc);
5249 /* Disable SCU IF AGC loop */
5250 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5252 pr_err("error %d\n", rc);
5255 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5256 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5257 if (common_attr->tuner_if_agc_pol)
5258 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5260 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5261 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5263 pr_err("error %d\n", rc);
5267 /* Write value to output pin */
5268 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5270 pr_err("error %d\n", rc);
5275 case DRX_AGC_CTRL_OFF:
5277 /* Disable If AGC DAC */
5278 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5280 pr_err("error %d\n", rc);
5283 data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
5284 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5286 pr_err("error %d\n", rc);
5290 /* Disable SCU IF AGC loop */
5291 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5293 pr_err("error %d\n", rc);
5296 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5297 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5298 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5300 pr_err("error %d\n", rc);
5306 } /* switch ( agcsettings->ctrl_mode ) */
5308 /* always set the top to support configurations without if-loop */
5309 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5311 pr_err("error %d\n", rc);
5316 /* Store if agc settings */
5317 switch (agc_settings->standard) {
5318 case DRX_STANDARD_8VSB:
5319 ext_attr->vsb_if_agc_cfg = *agc_settings;
5321 #ifndef DRXJ_VSB_ONLY
5322 case DRX_STANDARD_ITU_A:
5323 case DRX_STANDARD_ITU_B:
5324 case DRX_STANDARD_ITU_C:
5325 ext_attr->qam_if_agc_cfg = *agc_settings;
5338 * \fn int set_iqm_af ()
5339 * \brief Configure IQM AF registers
5340 * \param demod instance of demodulator.
5344 static int set_iqm_af(struct drx_demod_instance *demod, bool active)
5347 struct i2c_device_addr *dev_addr = NULL;
5350 dev_addr = demod->my_i2c_dev_addr;
5353 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5355 pr_err("error %d\n", rc);
5359 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
5361 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5362 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5364 pr_err("error %d\n", rc);
5373 /*============================================================================*/
5374 /*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
5375 /*============================================================================*/
5377 /*============================================================================*/
5378 /*============================================================================*/
5379 /*== 8VSB DATAPATH FUNCTIONS ==*/
5380 /*============================================================================*/
5381 /*============================================================================*/
5384 * \fn int power_down_vsb ()
5385 * \brief Powr down QAM related blocks.
5386 * \param demod instance of demodulator.
5387 * \param channel pointer to channel data.
5390 static int power_down_vsb(struct drx_demod_instance *demod, bool primary)
5392 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
5393 struct drxjscu_cmd cmd_scu = { /* command */ 0,
5394 /* parameter_len */ 0,
5396 /* *parameter */ NULL,
5399 struct drx_cfg_mpeg_output cfg_mpeg_output;
5405 reset of FEC and VSB HW
5407 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
5408 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
5409 cmd_scu.parameter_len = 0;
5410 cmd_scu.result_len = 1;
5411 cmd_scu.parameter = NULL;
5412 cmd_scu.result = &cmd_result;
5413 rc = scu_command(dev_addr, &cmd_scu);
5415 pr_err("error %d\n", rc);
5419 /* stop all comm_exec */
5420 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5422 pr_err("error %d\n", rc);
5425 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5427 pr_err("error %d\n", rc);
5431 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
5433 pr_err("error %d\n", rc);
5436 rc = set_iqm_af(demod, false);
5438 pr_err("error %d\n", rc);
5442 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5444 pr_err("error %d\n", rc);
5447 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5449 pr_err("error %d\n", rc);
5452 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5454 pr_err("error %d\n", rc);
5457 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5459 pr_err("error %d\n", rc);
5462 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5464 pr_err("error %d\n", rc);
5469 cfg_mpeg_output.enable_mpeg_output = false;
5470 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
5472 pr_err("error %d\n", rc);
5482 * \fn int set_vsb_leak_n_gain ()
5483 * \brief Set ATSC demod.
5484 * \param demod instance of demodulator.
5487 static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)
5489 struct i2c_device_addr *dev_addr = NULL;
5492 const u8 vsb_ffe_leak_gain_ram0[] = {
5493 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */
5494 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */
5495 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */
5496 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */
5497 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */
5498 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */
5499 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */
5500 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */
5501 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */
5502 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */
5503 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */
5504 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */
5505 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */
5506 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */
5507 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */
5508 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */
5509 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */
5510 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */
5511 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */
5512 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */
5513 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */
5514 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */
5515 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */
5516 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */
5517 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */
5518 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */
5519 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */
5520 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */
5521 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */
5522 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */
5523 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */
5524 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */
5525 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */
5526 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */
5527 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */
5528 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */
5529 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */
5530 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */
5531 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */
5532 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */
5533 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */
5534 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */
5535 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */
5536 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */
5537 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */
5538 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */
5539 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */
5540 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */
5541 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */
5542 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */
5543 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */
5544 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */
5545 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */
5546 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */
5547 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */
5548 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */
5549 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */
5550 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */
5551 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */
5552 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */
5553 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */
5554 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */
5555 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */
5556 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */
5557 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */
5558 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */
5559 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */
5560 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */
5561 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */
5562 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */
5563 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */
5564 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */
5565 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */
5566 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */
5567 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */
5568 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */
5569 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */
5570 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */
5571 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */
5572 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */
5573 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */
5574 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */
5575 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */
5576 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */
5577 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */
5578 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */
5579 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */
5580 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */
5581 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */
5582 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */
5583 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */
5584 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */
5585 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */
5586 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */
5587 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */
5588 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */
5589 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */
5590 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */
5591 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */
5592 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */
5593 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */
5594 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */
5595 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */
5596 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */
5597 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */
5598 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */
5599 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */
5600 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */
5601 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */
5602 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */
5603 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */
5604 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */
5605 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */
5606 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */
5607 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */
5608 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */
5609 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */
5610 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */
5611 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */
5612 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */
5613 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */
5614 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */
5615 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */
5616 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */
5617 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */
5618 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */
5619 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */
5620 DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */
5623 const u8 vsb_ffe_leak_gain_ram1[] = {
5624 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */
5625 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */
5626 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */
5627 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */
5628 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */
5629 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */
5630 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */
5631 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */
5632 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */
5633 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */
5634 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */
5635 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */
5636 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */
5637 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */
5638 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */
5639 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */
5640 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */
5641 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */
5642 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */
5643 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */
5644 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */
5645 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */
5646 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */
5647 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */
5648 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */
5649 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */
5650 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */
5651 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */
5652 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */
5653 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */
5654 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */
5655 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */
5656 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */
5657 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */
5658 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */
5659 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */
5660 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */
5661 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */
5662 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */
5663 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */
5664 DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */
5665 DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */
5666 DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */
5667 DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */
5668 DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */
5669 DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */
5670 DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */
5671 DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */
5672 DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */
5673 DRXJ_16TO8(0x0000), /* DFETRAINGAIN */
5674 DRXJ_16TO8(0x2020), /* DFERCA1GAIN */
5675 DRXJ_16TO8(0x1010), /* DFERCA2GAIN */
5676 DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */
5677 DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */
5680 dev_addr = demod->my_i2c_dev_addr;
5681 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
5683 pr_err("error %d\n", rc);
5686 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
5688 pr_err("error %d\n", rc);
5699 * \brief Set 8VSB demod.
5700 * \param demod instance of demodulator.
5704 static int set_vsb(struct drx_demod_instance *demod)
5706 struct i2c_device_addr *dev_addr = NULL;
5708 struct drx_common_attr *common_attr = NULL;
5709 struct drxjscu_cmd cmd_scu;
5710 struct drxj_data *ext_attr = NULL;
5713 const u8 vsb_taps_re[] = {
5714 DRXJ_16TO8(-2), /* re0 */
5715 DRXJ_16TO8(4), /* re1 */
5716 DRXJ_16TO8(1), /* re2 */
5717 DRXJ_16TO8(-4), /* re3 */
5718 DRXJ_16TO8(1), /* re4 */
5719 DRXJ_16TO8(4), /* re5 */
5720 DRXJ_16TO8(-3), /* re6 */
5721 DRXJ_16TO8(-3), /* re7 */
5722 DRXJ_16TO8(6), /* re8 */
5723 DRXJ_16TO8(1), /* re9 */
5724 DRXJ_16TO8(-9), /* re10 */
5725 DRXJ_16TO8(3), /* re11 */
5726 DRXJ_16TO8(12), /* re12 */
5727 DRXJ_16TO8(-9), /* re13 */
5728 DRXJ_16TO8(-15), /* re14 */
5729 DRXJ_16TO8(17), /* re15 */
5730 DRXJ_16TO8(19), /* re16 */
5731 DRXJ_16TO8(-29), /* re17 */
5732 DRXJ_16TO8(-22), /* re18 */
5733 DRXJ_16TO8(45), /* re19 */
5734 DRXJ_16TO8(25), /* re20 */
5735 DRXJ_16TO8(-70), /* re21 */
5736 DRXJ_16TO8(-28), /* re22 */
5737 DRXJ_16TO8(111), /* re23 */
5738 DRXJ_16TO8(30), /* re24 */
5739 DRXJ_16TO8(-201), /* re25 */
5740 DRXJ_16TO8(-31), /* re26 */
5741 DRXJ_16TO8(629) /* re27 */
5744 dev_addr = demod->my_i2c_dev_addr;
5745 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5746 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5748 /* stop all comm_exec */
5749 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5751 pr_err("error %d\n", rc);
5754 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5756 pr_err("error %d\n", rc);
5759 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5761 pr_err("error %d\n", rc);
5764 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5766 pr_err("error %d\n", rc);
5769 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5771 pr_err("error %d\n", rc);
5774 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5776 pr_err("error %d\n", rc);
5779 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5781 pr_err("error %d\n", rc);
5785 /* reset demodulator */
5786 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
5787 | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
5788 cmd_scu.parameter_len = 0;
5789 cmd_scu.result_len = 1;
5790 cmd_scu.parameter = NULL;
5791 cmd_scu.result = &cmd_result;
5792 rc = scu_command(dev_addr, &cmd_scu);
5794 pr_err("error %d\n", rc);
5798 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
5800 pr_err("error %d\n", rc);
5803 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
5805 pr_err("error %d\n", rc);
5808 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
5810 pr_err("error %d\n", rc);
5813 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
5814 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
5816 pr_err("error %d\n", rc);
5819 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
5821 pr_err("error %d\n", rc);
5824 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
5826 pr_err("error %d\n", rc);
5830 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
5832 pr_err("error %d\n", rc);
5835 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
5837 pr_err("error %d\n", rc);
5840 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
5842 pr_err("error %d\n", rc);
5845 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
5847 pr_err("error %d\n", rc);
5850 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
5852 pr_err("error %d\n", rc);
5855 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
5857 pr_err("error %d\n", rc);
5860 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
5862 pr_err("error %d\n", rc);
5865 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
5867 pr_err("error %d\n", rc);
5870 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
5872 pr_err("error %d\n", rc);
5876 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5878 pr_err("error %d\n", rc);
5881 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5883 pr_err("error %d\n", rc);
5887 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
5889 pr_err("error %d\n", rc);
5891 } /* set higher threshold */
5892 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
5894 pr_err("error %d\n", rc);
5896 } /* burst detection on */
5897 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
5899 pr_err("error %d\n", rc);
5901 } /* drop thresholds by 1 dB */
5902 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
5904 pr_err("error %d\n", rc);
5906 } /* drop thresholds by 2 dB */
5907 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
5909 pr_err("error %d\n", rc);
5912 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
5914 pr_err("error %d\n", rc);
5918 /* Initialize the FEC Subsystem */
5919 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
5921 pr_err("error %d\n", rc);
5925 u16 fec_oc_snc_mode = 0;
5926 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
5928 pr_err("error %d\n", rc);
5931 /* output data even when not locked */
5932 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
5934 pr_err("error %d\n", rc);
5940 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
5942 pr_err("error %d\n", rc);
5945 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
5947 pr_err("error %d\n", rc);
5950 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
5952 pr_err("error %d\n", rc);
5955 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
5957 pr_err("error %d\n", rc);
5960 /* no transparent, no A&C framing; parity is set in mpegoutput */
5962 u16 fec_oc_reg_mode = 0;
5963 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
5965 pr_err("error %d\n", rc);
5968 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
5970 pr_err("error %d\n", rc);
5975 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
5977 pr_err("error %d\n", rc);
5979 } /* timeout counter for restarting */
5980 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
5982 pr_err("error %d\n", rc);
5985 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
5987 pr_err("error %d\n", rc);
5989 } /* bypass disabled */
5990 /* initialize RS packet error measurement parameters */
5991 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
5993 pr_err("error %d\n", rc);
5996 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
5998 pr_err("error %d\n", rc);
6002 /* init measurement period of MER/SER */
6003 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
6005 pr_err("error %d\n", rc);
6008 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6010 pr_err("error %d\n", rc);
6013 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6015 pr_err("error %d\n", rc);
6018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6020 pr_err("error %d\n", rc);
6024 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
6026 pr_err("error %d\n", rc);
6029 /* B-Input to ADC, PGA+filter in standby */
6030 if (!ext_attr->has_lna) {
6031 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
6033 pr_err("error %d\n", rc);
6038 /* turn on IQMAF. It has to be in front of setAgc**() */
6039 rc = set_iqm_af(demod, true);
6041 pr_err("error %d\n", rc);
6044 rc = adc_synchronization(demod);
6046 pr_err("error %d\n", rc);
6050 rc = init_agc(demod);
6052 pr_err("error %d\n", rc);
6055 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6057 pr_err("error %d\n", rc);
6060 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6062 pr_err("error %d\n", rc);
6066 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
6068 struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
6070 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
6071 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
6073 pr_err("error %d\n", rc);
6077 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6079 pr_err("error %d\n", rc);
6083 /* Mpeg output has to be in front of FEC active */
6084 rc = set_mpegtei_handling(demod);
6086 pr_err("error %d\n", rc);
6089 rc = bit_reverse_mpeg_output(demod);
6091 pr_err("error %d\n", rc);
6094 rc = set_mpeg_start_width(demod);
6096 pr_err("error %d\n", rc);
6100 /* TODO: move to set_standard after hardware reset value problem is solved */
6101 /* Configure initial MPEG output */
6102 struct drx_cfg_mpeg_output cfg_mpeg_output;
6104 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6105 cfg_mpeg_output.enable_mpeg_output = true;
6107 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6109 pr_err("error %d\n", rc);
6114 /* TBD: what parameters should be set */
6115 cmd_param = 0x00; /* Default mode AGC on, etc */
6116 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6117 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
6118 cmd_scu.parameter_len = 1;
6119 cmd_scu.result_len = 1;
6120 cmd_scu.parameter = &cmd_param;
6121 cmd_scu.result = &cmd_result;
6122 rc = scu_command(dev_addr, &cmd_scu);
6124 pr_err("error %d\n", rc);
6128 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
6130 pr_err("error %d\n", rc);
6133 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
6135 pr_err("error %d\n", rc);
6138 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
6140 pr_err("error %d\n", rc);
6143 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
6145 pr_err("error %d\n", rc);
6148 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
6150 pr_err("error %d\n", rc);
6153 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
6155 pr_err("error %d\n", rc);
6158 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
6160 pr_err("error %d\n", rc);
6163 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
6165 pr_err("error %d\n", rc);
6169 /* start demodulator */
6170 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6171 | SCU_RAM_COMMAND_CMD_DEMOD_START;
6172 cmd_scu.parameter_len = 0;
6173 cmd_scu.result_len = 1;
6174 cmd_scu.parameter = NULL;
6175 cmd_scu.result = &cmd_result;
6176 rc = scu_command(dev_addr, &cmd_scu);
6178 pr_err("error %d\n", rc);
6182 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
6184 pr_err("error %d\n", rc);
6187 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
6189 pr_err("error %d\n", rc);
6192 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
6194 pr_err("error %d\n", rc);
6204 * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs)
6205 * \brief Get the values of packet error in 8VSB mode
6206 * \return Error code
6208 static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr,
6209 u32 *pck_errs, u32 *pck_count)
6215 u16 packet_errors_mant = 0;
6216 u16 packet_errors_exp = 0;
6218 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6220 pr_err("error %d\n", rc);
6223 packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
6224 packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
6225 >> FEC_RS_NR_FAILURES_EXP__B;
6226 period = FEC_RS_MEASUREMENT_PERIOD;
6227 prescale = FEC_RS_MEASUREMENT_PRESCALE;
6228 /* packet error rate = (error packet number) per second */
6229 /* 77.3 us is time for per packet */
6230 if (period * prescale == 0) {
6231 pr_err("error: period and/or prescale is zero!\n");
6234 *pck_errs = packet_errors_mant * (1 << packet_errors_exp);
6235 *pck_count = period * prescale * 77;
6243 * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber)
6244 * \brief Get the values of ber in VSB mode
6245 * \return Error code
6247 static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr,
6254 u16 bit_errors_mant = 0;
6255 u16 bit_errors_exp = 0;
6257 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6259 pr_err("error %d\n", rc);
6262 period = FEC_RS_MEASUREMENT_PERIOD;
6263 prescale = FEC_RS_MEASUREMENT_PRESCALE;
6265 bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
6266 bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
6267 >> FEC_RS_NR_BIT_ERRORS_EXP__B;
6269 *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8);
6271 if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700)
6272 *ber = (*cnt) * 26570;
6274 if (period * prescale == 0) {
6275 pr_err("error: period and/or prescale is zero!\n");
6278 *ber = bit_errors_mant << ((bit_errors_exp > 2) ?
6279 (bit_errors_exp - 3) : bit_errors_exp);
6288 * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber)
6289 * \brief Get the values of ber in VSB mode
6290 * \return Error code
6292 static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr,
6298 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6300 pr_err("error %d\n", rc);
6304 *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT;
6310 * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6311 * \brief Get the values of MER
6312 * \return Error code
6314 static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6319 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
6321 pr_err("error %d\n", rc);
6325 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
6333 /*============================================================================*/
6334 /*== END 8VSB DATAPATH FUNCTIONS ==*/
6335 /*============================================================================*/
6337 /*============================================================================*/
6338 /*============================================================================*/
6339 /*== QAM DATAPATH FUNCTIONS ==*/
6340 /*============================================================================*/
6341 /*============================================================================*/
6344 * \fn int power_down_qam ()
6345 * \brief Powr down QAM related blocks.
6346 * \param demod instance of demodulator.
6347 * \param channel pointer to channel data.
6350 static int power_down_qam(struct drx_demod_instance *demod, bool primary)
6352 struct drxjscu_cmd cmd_scu = { /* command */ 0,
6353 /* parameter_len */ 0,
6355 /* *parameter */ NULL,
6359 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6360 struct drx_cfg_mpeg_output cfg_mpeg_output;
6361 struct drx_common_attr *common_attr = demod->my_common_attr;
6366 resets IQM, QAM and FEC HW blocks
6368 /* stop all comm_exec */
6369 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
6371 pr_err("error %d\n", rc);
6374 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
6376 pr_err("error %d\n", rc);
6380 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
6381 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
6382 cmd_scu.parameter_len = 0;
6383 cmd_scu.result_len = 1;
6384 cmd_scu.parameter = NULL;
6385 cmd_scu.result = &cmd_result;
6386 rc = scu_command(dev_addr, &cmd_scu);
6388 pr_err("error %d\n", rc);
6393 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
6395 pr_err("error %d\n", rc);
6398 rc = set_iqm_af(demod, false);
6400 pr_err("error %d\n", rc);
6404 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
6406 pr_err("error %d\n", rc);
6409 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
6411 pr_err("error %d\n", rc);
6414 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
6416 pr_err("error %d\n", rc);
6419 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
6421 pr_err("error %d\n", rc);
6424 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
6426 pr_err("error %d\n", rc);
6431 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6432 cfg_mpeg_output.enable_mpeg_output = false;
6434 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6436 pr_err("error %d\n", rc);
6445 /*============================================================================*/
6448 * \fn int set_qam_measurement ()
6449 * \brief Setup of the QAM Measuremnt intervals for signal quality
6450 * \param demod instance of demod.
6451 * \param constellation current constellation.
6455 * Take into account that for certain settings the errorcounters can overflow.
6456 * The implementation does not check this.
6458 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6459 * constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired
6463 #ifndef DRXJ_VSB_ONLY
6465 set_qam_measurement(struct drx_demod_instance *demod,
6466 enum drx_modulation constellation, u32 symbol_rate)
6468 struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */
6469 struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */
6471 u32 fec_bits_desired = 0; /* BER accounting period */
6472 u16 fec_rs_plen = 0; /* defines RS BER measurement period */
6473 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
6474 u32 fec_rs_period = 0; /* Value for corresponding I2C register */
6475 u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */
6476 u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */
6477 u32 qam_vd_period = 0; /* Value for corresponding I2C register */
6478 u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */
6479 u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */
6480 u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
6482 dev_addr = demod->my_i2c_dev_addr;
6483 ext_attr = (struct drxj_data *) demod->my_ext_attr;
6485 fec_bits_desired = ext_attr->fec_bits_desired;
6486 fec_rs_prescale = ext_attr->fec_rs_prescale;
6488 switch (constellation) {
6489 case DRX_CONSTELLATION_QAM16:
6490 fec_bits_desired = 4 * symbol_rate;
6492 case DRX_CONSTELLATION_QAM32:
6493 fec_bits_desired = 5 * symbol_rate;
6495 case DRX_CONSTELLATION_QAM64:
6496 fec_bits_desired = 6 * symbol_rate;
6498 case DRX_CONSTELLATION_QAM128:
6499 fec_bits_desired = 7 * symbol_rate;
6501 case DRX_CONSTELLATION_QAM256:
6502 fec_bits_desired = 8 * symbol_rate;
6508 /* Parameters for Reed-Solomon Decoder */
6509 /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */
6510 /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */
6511 /* result is within 32 bit arithmetic -> */
6512 /* no need for mult or frac functions */
6514 /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
6515 switch (ext_attr->standard) {
6516 case DRX_STANDARD_ITU_A:
6517 case DRX_STANDARD_ITU_C:
6518 fec_rs_plen = 204 * 8;
6520 case DRX_STANDARD_ITU_B:
6521 fec_rs_plen = 128 * 7;
6527 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */
6528 fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */
6529 if (fec_rs_bit_cnt == 0) {
6530 pr_err("error: fec_rs_bit_cnt is zero!\n");
6533 fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */
6534 if (ext_attr->standard != DRX_STANDARD_ITU_B)
6535 fec_oc_snc_fail_period = fec_rs_period;
6537 /* limit to max 16 bit value (I2C register width) if needed */
6538 if (fec_rs_period > 0xFFFF)
6539 fec_rs_period = 0xFFFF;
6541 /* write corresponding registers */
6542 switch (ext_attr->standard) {
6543 case DRX_STANDARD_ITU_A:
6544 case DRX_STANDARD_ITU_C:
6546 case DRX_STANDARD_ITU_B:
6547 switch (constellation) {
6548 case DRX_CONSTELLATION_QAM64:
6549 fec_rs_period = 31581;
6550 fec_oc_snc_fail_period = 17932;
6552 case DRX_CONSTELLATION_QAM256:
6553 fec_rs_period = 45446;
6554 fec_oc_snc_fail_period = 25805;
6564 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
6566 pr_err("error %d\n", rc);
6569 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
6571 pr_err("error %d\n", rc);
6574 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
6576 pr_err("error %d\n", rc);
6579 ext_attr->fec_rs_period = (u16) fec_rs_period;
6580 ext_attr->fec_rs_prescale = fec_rs_prescale;
6581 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6583 pr_err("error %d\n", rc);
6586 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6588 pr_err("error %d\n", rc);
6591 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6593 pr_err("error %d\n", rc);
6597 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
6598 /* Parameters for Viterbi Decoder */
6599 /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */
6600 /* (qamvd_prescale*plen*(qam_constellation+1))) */
6601 /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */
6602 /* result is within 32 bit arithmetic -> */
6603 /* no need for mult or frac functions */
6605 /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */
6606 fec_vd_plen = ext_attr->fec_vd_plen;
6607 qam_vd_prescale = ext_attr->qam_vd_prescale;
6608 qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */
6610 switch (constellation) {
6611 case DRX_CONSTELLATION_QAM64:
6612 /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */
6614 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1)
6615 * (QAM_TOP_CONSTELLATION_QAM64 + 1);
6617 case DRX_CONSTELLATION_QAM256:
6618 /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */
6620 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1)
6621 * (QAM_TOP_CONSTELLATION_QAM256 + 1);
6626 if (qam_vd_period == 0) {
6627 pr_err("error: qam_vd_period is zero!\n");
6630 qam_vd_period = fec_bits_desired / qam_vd_period;
6631 /* limit to max 16 bit value (I2C register width) if needed */
6632 if (qam_vd_period > 0xFFFF)
6633 qam_vd_period = 0xFFFF;
6635 /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */
6636 qam_vd_bit_cnt *= qam_vd_period;
6638 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
6640 pr_err("error %d\n", rc);
6643 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
6645 pr_err("error %d\n", rc);
6648 ext_attr->qam_vd_period = (u16) qam_vd_period;
6649 ext_attr->qam_vd_prescale = qam_vd_prescale;
6657 /*============================================================================*/
6660 * \fn int set_qam16 ()
6661 * \brief QAM16 specific setup
6662 * \param demod instance of demod.
6665 static int set_qam16(struct drx_demod_instance *demod)
6667 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6669 const u8 qam_dq_qual_fun[] = {
6670 DRXJ_16TO8(2), /* fun0 */
6671 DRXJ_16TO8(2), /* fun1 */
6672 DRXJ_16TO8(2), /* fun2 */
6673 DRXJ_16TO8(2), /* fun3 */
6674 DRXJ_16TO8(3), /* fun4 */
6675 DRXJ_16TO8(3), /* fun5 */
6677 const u8 qam_eq_cma_rad[] = {
6678 DRXJ_16TO8(13517), /* RAD0 */
6679 DRXJ_16TO8(13517), /* RAD1 */
6680 DRXJ_16TO8(13517), /* RAD2 */
6681 DRXJ_16TO8(13517), /* RAD3 */
6682 DRXJ_16TO8(13517), /* RAD4 */
6683 DRXJ_16TO8(13517), /* RAD5 */
6686 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6688 pr_err("error %d\n", rc);
6691 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6693 pr_err("error %d\n", rc);
6697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
6699 pr_err("error %d\n", rc);
6702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6704 pr_err("error %d\n", rc);
6707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
6709 pr_err("error %d\n", rc);
6712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
6714 pr_err("error %d\n", rc);
6717 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
6719 pr_err("error %d\n", rc);
6722 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
6724 pr_err("error %d\n", rc);
6728 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6730 pr_err("error %d\n", rc);
6733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6735 pr_err("error %d\n", rc);
6738 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6740 pr_err("error %d\n", rc);
6744 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
6746 pr_err("error %d\n", rc);
6749 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
6751 pr_err("error %d\n", rc);
6754 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
6756 pr_err("error %d\n", rc);
6759 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
6761 pr_err("error %d\n", rc);
6764 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6766 pr_err("error %d\n", rc);
6769 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6771 pr_err("error %d\n", rc);
6774 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6776 pr_err("error %d\n", rc);
6780 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
6782 pr_err("error %d\n", rc);
6785 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
6787 pr_err("error %d\n", rc);
6790 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
6792 pr_err("error %d\n", rc);
6795 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
6797 pr_err("error %d\n", rc);
6800 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
6802 pr_err("error %d\n", rc);
6805 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
6807 pr_err("error %d\n", rc);
6810 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
6812 pr_err("error %d\n", rc);
6815 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
6817 pr_err("error %d\n", rc);
6820 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
6822 pr_err("error %d\n", rc);
6825 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
6827 pr_err("error %d\n", rc);
6830 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
6832 pr_err("error %d\n", rc);
6835 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
6837 pr_err("error %d\n", rc);
6840 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
6842 pr_err("error %d\n", rc);
6845 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
6847 pr_err("error %d\n", rc);
6850 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
6852 pr_err("error %d\n", rc);
6855 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
6857 pr_err("error %d\n", rc);
6860 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
6862 pr_err("error %d\n", rc);
6865 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
6867 pr_err("error %d\n", rc);
6870 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
6872 pr_err("error %d\n", rc);
6875 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
6877 pr_err("error %d\n", rc);
6881 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
6883 pr_err("error %d\n", rc);
6892 /*============================================================================*/
6895 * \fn int set_qam32 ()
6896 * \brief QAM32 specific setup
6897 * \param demod instance of demod.
6900 static int set_qam32(struct drx_demod_instance *demod)
6902 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6904 const u8 qam_dq_qual_fun[] = {
6905 DRXJ_16TO8(3), /* fun0 */
6906 DRXJ_16TO8(3), /* fun1 */
6907 DRXJ_16TO8(3), /* fun2 */
6908 DRXJ_16TO8(3), /* fun3 */
6909 DRXJ_16TO8(4), /* fun4 */
6910 DRXJ_16TO8(4), /* fun5 */
6912 const u8 qam_eq_cma_rad[] = {
6913 DRXJ_16TO8(6707), /* RAD0 */
6914 DRXJ_16TO8(6707), /* RAD1 */
6915 DRXJ_16TO8(6707), /* RAD2 */
6916 DRXJ_16TO8(6707), /* RAD3 */
6917 DRXJ_16TO8(6707), /* RAD4 */
6918 DRXJ_16TO8(6707), /* RAD5 */
6921 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6923 pr_err("error %d\n", rc);
6926 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6928 pr_err("error %d\n", rc);
6932 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
6934 pr_err("error %d\n", rc);
6937 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6939 pr_err("error %d\n", rc);
6942 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
6944 pr_err("error %d\n", rc);
6947 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
6949 pr_err("error %d\n", rc);
6952 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
6954 pr_err("error %d\n", rc);
6957 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
6959 pr_err("error %d\n", rc);
6963 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6965 pr_err("error %d\n", rc);
6968 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6970 pr_err("error %d\n", rc);
6973 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6975 pr_err("error %d\n", rc);
6979 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
6981 pr_err("error %d\n", rc);
6984 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
6986 pr_err("error %d\n", rc);
6989 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
6991 pr_err("error %d\n", rc);
6994 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
6996 pr_err("error %d\n", rc);
6999 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
7001 pr_err("error %d\n", rc);
7004 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7006 pr_err("error %d\n", rc);
7009 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7011 pr_err("error %d\n", rc);
7015 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7017 pr_err("error %d\n", rc);
7020 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7022 pr_err("error %d\n", rc);
7025 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7027 pr_err("error %d\n", rc);
7030 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
7032 pr_err("error %d\n", rc);
7035 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7037 pr_err("error %d\n", rc);
7040 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7042 pr_err("error %d\n", rc);
7045 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
7047 pr_err("error %d\n", rc);
7050 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
7052 pr_err("error %d\n", rc);
7055 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7057 pr_err("error %d\n", rc);
7060 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7062 pr_err("error %d\n", rc);
7065 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7067 pr_err("error %d\n", rc);
7070 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7072 pr_err("error %d\n", rc);
7075 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7077 pr_err("error %d\n", rc);
7080 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7082 pr_err("error %d\n", rc);
7085 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7087 pr_err("error %d\n", rc);
7090 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7092 pr_err("error %d\n", rc);
7095 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
7097 pr_err("error %d\n", rc);
7100 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7102 pr_err("error %d\n", rc);
7105 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7107 pr_err("error %d\n", rc);
7110 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
7112 pr_err("error %d\n", rc);
7116 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
7118 pr_err("error %d\n", rc);
7127 /*============================================================================*/
7130 * \fn int set_qam64 ()
7131 * \brief QAM64 specific setup
7132 * \param demod instance of demod.
7135 static int set_qam64(struct drx_demod_instance *demod)
7137 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7139 const u8 qam_dq_qual_fun[] = { /* this is hw reset value. no necessary to re-write */
7140 DRXJ_16TO8(4), /* fun0 */
7141 DRXJ_16TO8(4), /* fun1 */
7142 DRXJ_16TO8(4), /* fun2 */
7143 DRXJ_16TO8(4), /* fun3 */
7144 DRXJ_16TO8(6), /* fun4 */
7145 DRXJ_16TO8(6), /* fun5 */
7147 const u8 qam_eq_cma_rad[] = {
7148 DRXJ_16TO8(13336), /* RAD0 */
7149 DRXJ_16TO8(12618), /* RAD1 */
7150 DRXJ_16TO8(11988), /* RAD2 */
7151 DRXJ_16TO8(13809), /* RAD3 */
7152 DRXJ_16TO8(13809), /* RAD4 */
7153 DRXJ_16TO8(15609), /* RAD5 */
7156 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7158 pr_err("error %d\n", rc);
7161 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7163 pr_err("error %d\n", rc);
7167 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
7169 pr_err("error %d\n", rc);
7172 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7174 pr_err("error %d\n", rc);
7177 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7179 pr_err("error %d\n", rc);
7182 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
7184 pr_err("error %d\n", rc);
7187 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7189 pr_err("error %d\n", rc);
7192 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
7194 pr_err("error %d\n", rc);
7198 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7200 pr_err("error %d\n", rc);
7203 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7205 pr_err("error %d\n", rc);
7208 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7210 pr_err("error %d\n", rc);
7214 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
7216 pr_err("error %d\n", rc);
7219 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
7221 pr_err("error %d\n", rc);
7224 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
7226 pr_err("error %d\n", rc);
7229 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
7231 pr_err("error %d\n", rc);
7234 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7236 pr_err("error %d\n", rc);
7239 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7241 pr_err("error %d\n", rc);
7244 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7246 pr_err("error %d\n", rc);
7250 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7252 pr_err("error %d\n", rc);
7255 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7257 pr_err("error %d\n", rc);
7260 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7262 pr_err("error %d\n", rc);
7265 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
7267 pr_err("error %d\n", rc);
7270 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7272 pr_err("error %d\n", rc);
7275 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7277 pr_err("error %d\n", rc);
7280 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
7282 pr_err("error %d\n", rc);
7285 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7287 pr_err("error %d\n", rc);
7290 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7292 pr_err("error %d\n", rc);
7295 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7297 pr_err("error %d\n", rc);
7300 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7302 pr_err("error %d\n", rc);
7305 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7307 pr_err("error %d\n", rc);
7310 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7312 pr_err("error %d\n", rc);
7315 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7317 pr_err("error %d\n", rc);
7320 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7322 pr_err("error %d\n", rc);
7325 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7327 pr_err("error %d\n", rc);
7330 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
7332 pr_err("error %d\n", rc);
7335 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7337 pr_err("error %d\n", rc);
7340 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7342 pr_err("error %d\n", rc);
7345 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
7347 pr_err("error %d\n", rc);
7351 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
7353 pr_err("error %d\n", rc);
7362 /*============================================================================*/
7365 * \fn int set_qam128 ()
7366 * \brief QAM128 specific setup
7367 * \param demod: instance of demod.
7370 static int set_qam128(struct drx_demod_instance *demod)
7372 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7374 const u8 qam_dq_qual_fun[] = {
7375 DRXJ_16TO8(6), /* fun0 */
7376 DRXJ_16TO8(6), /* fun1 */
7377 DRXJ_16TO8(6), /* fun2 */
7378 DRXJ_16TO8(6), /* fun3 */
7379 DRXJ_16TO8(9), /* fun4 */
7380 DRXJ_16TO8(9), /* fun5 */
7382 const u8 qam_eq_cma_rad[] = {
7383 DRXJ_16TO8(6164), /* RAD0 */
7384 DRXJ_16TO8(6598), /* RAD1 */
7385 DRXJ_16TO8(6394), /* RAD2 */
7386 DRXJ_16TO8(6409), /* RAD3 */
7387 DRXJ_16TO8(6656), /* RAD4 */
7388 DRXJ_16TO8(7238), /* RAD5 */
7391 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7393 pr_err("error %d\n", rc);
7396 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7398 pr_err("error %d\n", rc);
7402 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7404 pr_err("error %d\n", rc);
7407 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7409 pr_err("error %d\n", rc);
7412 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7414 pr_err("error %d\n", rc);
7417 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
7419 pr_err("error %d\n", rc);
7422 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7424 pr_err("error %d\n", rc);
7427 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
7429 pr_err("error %d\n", rc);
7433 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7435 pr_err("error %d\n", rc);
7438 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7440 pr_err("error %d\n", rc);
7443 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7445 pr_err("error %d\n", rc);
7449 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7451 pr_err("error %d\n", rc);
7454 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
7456 pr_err("error %d\n", rc);
7459 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
7461 pr_err("error %d\n", rc);
7464 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
7466 pr_err("error %d\n", rc);
7469 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7471 pr_err("error %d\n", rc);
7474 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
7476 pr_err("error %d\n", rc);
7479 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7481 pr_err("error %d\n", rc);
7485 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7487 pr_err("error %d\n", rc);
7490 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7492 pr_err("error %d\n", rc);
7495 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7497 pr_err("error %d\n", rc);
7500 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
7502 pr_err("error %d\n", rc);
7505 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7507 pr_err("error %d\n", rc);
7510 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7512 pr_err("error %d\n", rc);
7515 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
7517 pr_err("error %d\n", rc);
7520 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7522 pr_err("error %d\n", rc);
7525 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7527 pr_err("error %d\n", rc);
7530 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7532 pr_err("error %d\n", rc);
7535 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7537 pr_err("error %d\n", rc);
7540 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7542 pr_err("error %d\n", rc);
7545 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7547 pr_err("error %d\n", rc);
7550 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7552 pr_err("error %d\n", rc);
7555 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7557 pr_err("error %d\n", rc);
7560 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7562 pr_err("error %d\n", rc);
7565 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
7567 pr_err("error %d\n", rc);
7570 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7572 pr_err("error %d\n", rc);
7575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7577 pr_err("error %d\n", rc);
7580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7582 pr_err("error %d\n", rc);
7586 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
7588 pr_err("error %d\n", rc);
7597 /*============================================================================*/
7600 * \fn int set_qam256 ()
7601 * \brief QAM256 specific setup
7602 * \param demod: instance of demod.
7605 static int set_qam256(struct drx_demod_instance *demod)
7607 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7609 const u8 qam_dq_qual_fun[] = {
7610 DRXJ_16TO8(8), /* fun0 */
7611 DRXJ_16TO8(8), /* fun1 */
7612 DRXJ_16TO8(8), /* fun2 */
7613 DRXJ_16TO8(8), /* fun3 */
7614 DRXJ_16TO8(12), /* fun4 */
7615 DRXJ_16TO8(12), /* fun5 */
7617 const u8 qam_eq_cma_rad[] = {
7618 DRXJ_16TO8(12345), /* RAD0 */
7619 DRXJ_16TO8(12345), /* RAD1 */
7620 DRXJ_16TO8(13626), /* RAD2 */
7621 DRXJ_16TO8(12931), /* RAD3 */
7622 DRXJ_16TO8(14719), /* RAD4 */
7623 DRXJ_16TO8(15356), /* RAD5 */
7626 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7628 pr_err("error %d\n", rc);
7631 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7633 pr_err("error %d\n", rc);
7637 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7639 pr_err("error %d\n", rc);
7642 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7644 pr_err("error %d\n", rc);
7647 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7649 pr_err("error %d\n", rc);
7652 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
7654 pr_err("error %d\n", rc);
7657 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7659 pr_err("error %d\n", rc);
7662 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
7664 pr_err("error %d\n", rc);
7668 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7670 pr_err("error %d\n", rc);
7673 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
7675 pr_err("error %d\n", rc);
7678 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7680 pr_err("error %d\n", rc);
7684 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7686 pr_err("error %d\n", rc);
7689 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
7691 pr_err("error %d\n", rc);
7694 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
7696 pr_err("error %d\n", rc);
7699 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
7701 pr_err("error %d\n", rc);
7704 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
7706 pr_err("error %d\n", rc);
7709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
7711 pr_err("error %d\n", rc);
7714 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7716 pr_err("error %d\n", rc);
7720 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7722 pr_err("error %d\n", rc);
7725 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7727 pr_err("error %d\n", rc);
7730 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7732 pr_err("error %d\n", rc);
7735 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
7737 pr_err("error %d\n", rc);
7740 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7742 pr_err("error %d\n", rc);
7745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7747 pr_err("error %d\n", rc);
7750 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
7752 pr_err("error %d\n", rc);
7755 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7757 pr_err("error %d\n", rc);
7760 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7762 pr_err("error %d\n", rc);
7765 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7767 pr_err("error %d\n", rc);
7770 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7772 pr_err("error %d\n", rc);
7775 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7777 pr_err("error %d\n", rc);
7780 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7782 pr_err("error %d\n", rc);
7785 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7787 pr_err("error %d\n", rc);
7790 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7792 pr_err("error %d\n", rc);
7795 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7797 pr_err("error %d\n", rc);
7800 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
7802 pr_err("error %d\n", rc);
7805 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7807 pr_err("error %d\n", rc);
7810 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7812 pr_err("error %d\n", rc);
7815 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7817 pr_err("error %d\n", rc);
7821 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
7823 pr_err("error %d\n", rc);
7832 /*============================================================================*/
7833 #define QAM_SET_OP_ALL 0x1
7834 #define QAM_SET_OP_CONSTELLATION 0x2
7835 #define QAM_SET_OP_SPECTRUM 0X4
7838 * \fn int set_qam ()
7839 * \brief Set QAM demod.
7840 * \param demod: instance of demod.
7841 * \param channel: pointer to channel data.
7845 set_qam(struct drx_demod_instance *demod,
7846 struct drx_channel *channel, s32 tuner_freq_offset, u32 op)
7848 struct i2c_device_addr *dev_addr = NULL;
7849 struct drxj_data *ext_attr = NULL;
7850 struct drx_common_attr *common_attr = NULL;
7852 u32 adc_frequency = 0;
7853 u32 iqm_rc_rate = 0;
7855 u16 lc_symbol_freq = 0;
7856 u16 iqm_rc_stretch = 0;
7857 u16 set_env_parameters = 0;
7858 u16 set_param_parameters[2] = { 0 };
7859 struct drxjscu_cmd cmd_scu = { /* command */ 0,
7860 /* parameter_len */ 0,
7862 /* parameter */ NULL,
7865 const u8 qam_a_taps[] = {
7866 DRXJ_16TO8(-1), /* re0 */
7867 DRXJ_16TO8(1), /* re1 */
7868 DRXJ_16TO8(1), /* re2 */
7869 DRXJ_16TO8(-1), /* re3 */
7870 DRXJ_16TO8(-1), /* re4 */
7871 DRXJ_16TO8(2), /* re5 */
7872 DRXJ_16TO8(1), /* re6 */
7873 DRXJ_16TO8(-2), /* re7 */
7874 DRXJ_16TO8(0), /* re8 */
7875 DRXJ_16TO8(3), /* re9 */
7876 DRXJ_16TO8(-1), /* re10 */
7877 DRXJ_16TO8(-3), /* re11 */
7878 DRXJ_16TO8(4), /* re12 */
7879 DRXJ_16TO8(1), /* re13 */
7880 DRXJ_16TO8(-8), /* re14 */
7881 DRXJ_16TO8(4), /* re15 */
7882 DRXJ_16TO8(13), /* re16 */
7883 DRXJ_16TO8(-13), /* re17 */
7884 DRXJ_16TO8(-19), /* re18 */
7885 DRXJ_16TO8(28), /* re19 */
7886 DRXJ_16TO8(25), /* re20 */
7887 DRXJ_16TO8(-53), /* re21 */
7888 DRXJ_16TO8(-31), /* re22 */
7889 DRXJ_16TO8(96), /* re23 */
7890 DRXJ_16TO8(37), /* re24 */
7891 DRXJ_16TO8(-190), /* re25 */
7892 DRXJ_16TO8(-40), /* re26 */
7893 DRXJ_16TO8(619) /* re27 */
7895 const u8 qam_b64_taps[] = {
7896 DRXJ_16TO8(0), /* re0 */
7897 DRXJ_16TO8(-2), /* re1 */
7898 DRXJ_16TO8(1), /* re2 */
7899 DRXJ_16TO8(2), /* re3 */
7900 DRXJ_16TO8(-2), /* re4 */
7901 DRXJ_16TO8(0), /* re5 */
7902 DRXJ_16TO8(4), /* re6 */
7903 DRXJ_16TO8(-2), /* re7 */
7904 DRXJ_16TO8(-4), /* re8 */
7905 DRXJ_16TO8(4), /* re9 */
7906 DRXJ_16TO8(3), /* re10 */
7907 DRXJ_16TO8(-6), /* re11 */
7908 DRXJ_16TO8(0), /* re12 */
7909 DRXJ_16TO8(6), /* re13 */
7910 DRXJ_16TO8(-5), /* re14 */
7911 DRXJ_16TO8(-3), /* re15 */
7912 DRXJ_16TO8(11), /* re16 */
7913 DRXJ_16TO8(-4), /* re17 */
7914 DRXJ_16TO8(-19), /* re18 */
7915 DRXJ_16TO8(19), /* re19 */
7916 DRXJ_16TO8(28), /* re20 */
7917 DRXJ_16TO8(-45), /* re21 */
7918 DRXJ_16TO8(-36), /* re22 */
7919 DRXJ_16TO8(90), /* re23 */
7920 DRXJ_16TO8(42), /* re24 */
7921 DRXJ_16TO8(-185), /* re25 */
7922 DRXJ_16TO8(-46), /* re26 */
7923 DRXJ_16TO8(614) /* re27 */
7925 const u8 qam_b256_taps[] = {
7926 DRXJ_16TO8(-2), /* re0 */
7927 DRXJ_16TO8(4), /* re1 */
7928 DRXJ_16TO8(1), /* re2 */
7929 DRXJ_16TO8(-4), /* re3 */
7930 DRXJ_16TO8(0), /* re4 */
7931 DRXJ_16TO8(4), /* re5 */
7932 DRXJ_16TO8(-2), /* re6 */
7933 DRXJ_16TO8(-4), /* re7 */
7934 DRXJ_16TO8(5), /* re8 */
7935 DRXJ_16TO8(2), /* re9 */
7936 DRXJ_16TO8(-8), /* re10 */
7937 DRXJ_16TO8(2), /* re11 */
7938 DRXJ_16TO8(11), /* re12 */
7939 DRXJ_16TO8(-8), /* re13 */
7940 DRXJ_16TO8(-15), /* re14 */
7941 DRXJ_16TO8(16), /* re15 */
7942 DRXJ_16TO8(19), /* re16 */
7943 DRXJ_16TO8(-27), /* re17 */
7944 DRXJ_16TO8(-22), /* re18 */
7945 DRXJ_16TO8(44), /* re19 */
7946 DRXJ_16TO8(26), /* re20 */
7947 DRXJ_16TO8(-69), /* re21 */
7948 DRXJ_16TO8(-28), /* re22 */
7949 DRXJ_16TO8(110), /* re23 */
7950 DRXJ_16TO8(31), /* re24 */
7951 DRXJ_16TO8(-201), /* re25 */
7952 DRXJ_16TO8(-32), /* re26 */
7953 DRXJ_16TO8(628) /* re27 */
7955 const u8 qam_c_taps[] = {
7956 DRXJ_16TO8(-3), /* re0 */
7957 DRXJ_16TO8(3), /* re1 */
7958 DRXJ_16TO8(2), /* re2 */
7959 DRXJ_16TO8(-4), /* re3 */
7960 DRXJ_16TO8(0), /* re4 */
7961 DRXJ_16TO8(4), /* re5 */
7962 DRXJ_16TO8(-1), /* re6 */
7963 DRXJ_16TO8(-4), /* re7 */
7964 DRXJ_16TO8(3), /* re8 */
7965 DRXJ_16TO8(3), /* re9 */
7966 DRXJ_16TO8(-5), /* re10 */
7967 DRXJ_16TO8(0), /* re11 */
7968 DRXJ_16TO8(9), /* re12 */
7969 DRXJ_16TO8(-4), /* re13 */
7970 DRXJ_16TO8(-12), /* re14 */
7971 DRXJ_16TO8(10), /* re15 */
7972 DRXJ_16TO8(16), /* re16 */
7973 DRXJ_16TO8(-21), /* re17 */
7974 DRXJ_16TO8(-20), /* re18 */
7975 DRXJ_16TO8(37), /* re19 */
7976 DRXJ_16TO8(25), /* re20 */
7977 DRXJ_16TO8(-62), /* re21 */
7978 DRXJ_16TO8(-28), /* re22 */
7979 DRXJ_16TO8(105), /* re23 */
7980 DRXJ_16TO8(31), /* re24 */
7981 DRXJ_16TO8(-197), /* re25 */
7982 DRXJ_16TO8(-33), /* re26 */
7983 DRXJ_16TO8(626) /* re27 */
7986 dev_addr = demod->my_i2c_dev_addr;
7987 ext_attr = (struct drxj_data *) demod->my_ext_attr;
7988 common_attr = (struct drx_common_attr *) demod->my_common_attr;
7990 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
7991 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
7992 switch (channel->constellation) {
7993 case DRX_CONSTELLATION_QAM256:
7994 iqm_rc_rate = 0x00AE3562;
7996 QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
7997 channel->symbolrate = 5360537;
7998 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256;
8000 case DRX_CONSTELLATION_QAM64:
8001 iqm_rc_rate = 0x00C05A0E;
8002 lc_symbol_freq = 409;
8003 channel->symbolrate = 5056941;
8004 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64;
8010 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
8011 if (channel->symbolrate == 0) {
8012 pr_err("error: channel symbolrate is zero!\n");
8016 (adc_frequency / channel->symbolrate) * (1 << 21) +
8018 ((adc_frequency % channel->symbolrate),
8019 channel->symbolrate) >> 7) - (1 << 23);
8022 (channel->symbolrate +
8023 (adc_frequency >> 13),
8024 adc_frequency) >> 16);
8025 if (lc_symbol_freq > 511)
8026 lc_symbol_freq = 511;
8028 iqm_rc_stretch = 21;
8031 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8032 set_env_parameters = QAM_TOP_ANNEX_A; /* annex */
8033 set_param_parameters[0] = channel->constellation; /* constellation */
8034 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
8035 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8036 set_env_parameters = QAM_TOP_ANNEX_B; /* annex */
8037 set_param_parameters[0] = channel->constellation; /* constellation */
8038 set_param_parameters[1] = channel->interleavemode; /* interleave mode */
8039 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8040 set_env_parameters = QAM_TOP_ANNEX_C; /* annex */
8041 set_param_parameters[0] = channel->constellation; /* constellation */
8042 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
8048 if (op & QAM_SET_OP_ALL) {
8050 STEP 1: reset demodulator
8051 resets IQM, QAM and FEC HW blocks
8052 resets SCU variables
8054 /* stop all comm_exec */
8055 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
8057 pr_err("error %d\n", rc);
8060 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
8062 pr_err("error %d\n", rc);
8065 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
8067 pr_err("error %d\n", rc);
8070 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
8072 pr_err("error %d\n", rc);
8075 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
8077 pr_err("error %d\n", rc);
8080 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
8082 pr_err("error %d\n", rc);
8085 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
8087 pr_err("error %d\n", rc);
8091 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8092 SCU_RAM_COMMAND_CMD_DEMOD_RESET;
8093 cmd_scu.parameter_len = 0;
8094 cmd_scu.result_len = 1;
8095 cmd_scu.parameter = NULL;
8096 cmd_scu.result = &cmd_result;
8097 rc = scu_command(dev_addr, &cmd_scu);
8099 pr_err("error %d\n", rc);
8104 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8106 STEP 2: configure demodulator
8108 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
8110 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8111 SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
8112 cmd_scu.parameter_len = 1;
8113 cmd_scu.result_len = 1;
8114 cmd_scu.parameter = &set_env_parameters;
8115 cmd_scu.result = &cmd_result;
8116 rc = scu_command(dev_addr, &cmd_scu);
8118 pr_err("error %d\n", rc);
8122 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8123 SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
8124 cmd_scu.parameter_len = 2;
8125 cmd_scu.result_len = 1;
8126 cmd_scu.parameter = set_param_parameters;
8127 cmd_scu.result = &cmd_result;
8128 rc = scu_command(dev_addr, &cmd_scu);
8130 pr_err("error %d\n", rc);
8133 /* set symbol rate */
8134 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
8136 pr_err("error %d\n", rc);
8139 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
8140 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8142 pr_err("error %d\n", rc);
8146 /* STEP 3: enable the system in a mode where the ADC provides valid signal
8147 setup constellation independent registers */
8148 /* from qam_cmd.py script (qam_driver_b) */
8149 /* TODO: remove re-writes of HW reset values */
8150 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) {
8151 rc = set_frequency(demod, channel, tuner_freq_offset);
8153 pr_err("error %d\n", rc);
8158 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8160 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
8162 pr_err("error %d\n", rc);
8165 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
8167 pr_err("error %d\n", rc);
8172 if (op & QAM_SET_OP_ALL) {
8173 if (!ext_attr->has_lna) {
8174 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
8176 pr_err("error %d\n", rc);
8180 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
8182 pr_err("error %d\n", rc);
8185 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
8187 pr_err("error %d\n", rc);
8190 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
8192 pr_err("error %d\n", rc);
8196 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
8198 pr_err("error %d\n", rc);
8200 } /* scu temporary shut down agc */
8202 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
8204 pr_err("error %d\n", rc);
8207 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
8209 pr_err("error %d\n", rc);
8212 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
8214 pr_err("error %d\n", rc);
8217 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
8219 pr_err("error %d\n", rc);
8222 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
8224 pr_err("error %d\n", rc);
8227 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
8229 pr_err("error %d\n", rc);
8232 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
8234 pr_err("error %d\n", rc);
8238 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
8240 pr_err("error %d\n", rc);
8243 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
8245 pr_err("error %d\n", rc);
8247 } /*! reset default val ! */
8249 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
8251 pr_err("error %d\n", rc);
8253 } /*! reset default val ! */
8254 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8255 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
8257 pr_err("error %d\n", rc);
8259 } /*! reset default val ! */
8260 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
8262 pr_err("error %d\n", rc);
8264 } /*! reset default val ! */
8265 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8267 pr_err("error %d\n", rc);
8269 } /*! reset default val ! */
8271 switch (channel->constellation) {
8272 case DRX_CONSTELLATION_QAM16:
8273 case DRX_CONSTELLATION_QAM64:
8274 case DRX_CONSTELLATION_QAM256:
8275 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8277 pr_err("error %d\n", rc);
8280 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
8282 pr_err("error %d\n", rc);
8285 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8287 pr_err("error %d\n", rc);
8289 } /*! reset default val ! */
8291 case DRX_CONSTELLATION_QAM32:
8292 case DRX_CONSTELLATION_QAM128:
8293 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8295 pr_err("error %d\n", rc);
8298 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
8300 pr_err("error %d\n", rc);
8303 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
8305 pr_err("error %d\n", rc);
8314 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
8316 pr_err("error %d\n", rc);
8318 } /*! reset default val ! */
8319 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
8321 pr_err("error %d\n", rc);
8324 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
8326 pr_err("error %d\n", rc);
8329 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
8331 pr_err("error %d\n", rc);
8334 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
8336 pr_err("error %d\n", rc);
8339 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
8341 pr_err("error %d\n", rc);
8344 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
8346 pr_err("error %d\n", rc);
8349 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
8351 pr_err("error %d\n", rc);
8354 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
8356 pr_err("error %d\n", rc);
8359 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
8361 pr_err("error %d\n", rc);
8364 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
8366 pr_err("error %d\n", rc);
8369 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
8371 pr_err("error %d\n", rc);
8374 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
8376 pr_err("error %d\n", rc);
8379 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
8381 pr_err("error %d\n", rc);
8384 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
8386 pr_err("error %d\n", rc);
8389 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
8391 pr_err("error %d\n", rc);
8394 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
8396 pr_err("error %d\n", rc);
8399 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
8401 pr_err("error %d\n", rc);
8404 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
8406 pr_err("error %d\n", rc);
8409 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
8411 pr_err("error %d\n", rc);
8415 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
8417 pr_err("error %d\n", rc);
8420 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
8422 pr_err("error %d\n", rc);
8425 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
8427 pr_err("error %d\n", rc);
8430 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
8432 pr_err("error %d\n", rc);
8435 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
8437 pr_err("error %d\n", rc);
8441 /* No more resets of the IQM, current standard correctly set =>
8442 now AGCs can be configured. */
8443 /* turn on IQMAF. It has to be in front of setAgc**() */
8444 rc = set_iqm_af(demod, true);
8446 pr_err("error %d\n", rc);
8449 rc = adc_synchronization(demod);
8451 pr_err("error %d\n", rc);
8455 rc = init_agc(demod);
8457 pr_err("error %d\n", rc);
8460 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8462 pr_err("error %d\n", rc);
8465 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8467 pr_err("error %d\n", rc);
8471 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
8473 struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 };
8475 qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
8476 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
8478 pr_err("error %d\n", rc);
8482 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8484 pr_err("error %d\n", rc);
8489 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8490 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8491 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8493 pr_err("error %d\n", rc);
8496 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8498 pr_err("error %d\n", rc);
8501 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8502 switch (channel->constellation) {
8503 case DRX_CONSTELLATION_QAM64:
8504 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8506 pr_err("error %d\n", rc);
8509 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8511 pr_err("error %d\n", rc);
8515 case DRX_CONSTELLATION_QAM256:
8516 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8518 pr_err("error %d\n", rc);
8521 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8523 pr_err("error %d\n", rc);
8530 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8531 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8533 pr_err("error %d\n", rc);
8536 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8538 pr_err("error %d\n", rc);
8543 /* SETP 4: constellation specific setup */
8544 switch (channel->constellation) {
8545 case DRX_CONSTELLATION_QAM16:
8546 rc = set_qam16(demod);
8548 pr_err("error %d\n", rc);
8552 case DRX_CONSTELLATION_QAM32:
8553 rc = set_qam32(demod);
8555 pr_err("error %d\n", rc);
8559 case DRX_CONSTELLATION_QAM64:
8560 rc = set_qam64(demod);
8562 pr_err("error %d\n", rc);
8566 case DRX_CONSTELLATION_QAM128:
8567 rc = set_qam128(demod);
8569 pr_err("error %d\n", rc);
8573 case DRX_CONSTELLATION_QAM256:
8574 rc = set_qam256(demod);
8576 pr_err("error %d\n", rc);
8585 if ((op & QAM_SET_OP_ALL)) {
8586 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
8588 pr_err("error %d\n", rc);
8592 /* Mpeg output has to be in front of FEC active */
8593 rc = set_mpegtei_handling(demod);
8595 pr_err("error %d\n", rc);
8598 rc = bit_reverse_mpeg_output(demod);
8600 pr_err("error %d\n", rc);
8603 rc = set_mpeg_start_width(demod);
8605 pr_err("error %d\n", rc);
8609 /* TODO: move to set_standard after hardware reset value problem is solved */
8610 /* Configure initial MPEG output */
8611 struct drx_cfg_mpeg_output cfg_mpeg_output;
8613 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
8614 cfg_mpeg_output.enable_mpeg_output = true;
8616 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
8618 pr_err("error %d\n", rc);
8624 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8626 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
8627 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8628 SCU_RAM_COMMAND_CMD_DEMOD_START;
8629 cmd_scu.parameter_len = 0;
8630 cmd_scu.result_len = 1;
8631 cmd_scu.parameter = NULL;
8632 cmd_scu.result = &cmd_result;
8633 rc = scu_command(dev_addr, &cmd_scu);
8635 pr_err("error %d\n", rc);
8640 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
8642 pr_err("error %d\n", rc);
8645 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
8647 pr_err("error %d\n", rc);
8650 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
8652 pr_err("error %d\n", rc);
8661 /*============================================================================*/
8662 static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod);
8664 static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)
8666 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8667 struct drxj_data *ext_attr = demod->my_ext_attr;
8669 u32 iqm_fs_rate_ofs = 0;
8670 u32 iqm_fs_rate_lo = 0;
8671 u16 qam_ctl_ena = 0;
8678 /* Silence the controlling of lc, equ, and the acquisition state machine */
8679 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
8681 pr_err("error %d\n", rc);
8684 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
8686 pr_err("error %d\n", rc);
8690 /* freeze the frequency control loop */
8691 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
8693 pr_err("error %d\n", rc);
8696 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
8698 pr_err("error %d\n", rc);
8702 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
8704 pr_err("error %d\n", rc);
8707 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
8709 pr_err("error %d\n", rc);
8712 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
8713 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
8714 iqm_fs_rate_ofs -= 2 * ofsofs;
8716 /* freeze dq/fq updating */
8717 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8719 pr_err("error %d\n", rc);
8722 data = (data & 0xfff9);
8723 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8725 pr_err("error %d\n", rc);
8728 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8730 pr_err("error %d\n", rc);
8734 /* lc_cp / _ci / _ca */
8735 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
8737 pr_err("error %d\n", rc);
8740 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
8742 pr_err("error %d\n", rc);
8745 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
8747 pr_err("error %d\n", rc);
8752 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
8754 pr_err("error %d\n", rc);
8757 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
8758 ext_attr->pos_image = (ext_attr->pos_image) ? false : true;
8760 /* freeze dq/fq updating */
8761 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8763 pr_err("error %d\n", rc);
8767 data = (data & 0xfff9);
8768 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8770 pr_err("error %d\n", rc);
8773 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8775 pr_err("error %d\n", rc);
8779 for (i = 0; i < 28; i++) {
8780 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8782 pr_err("error %d\n", rc);
8785 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8787 pr_err("error %d\n", rc);
8792 for (i = 0; i < 24; i++) {
8793 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8795 pr_err("error %d\n", rc);
8798 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8800 pr_err("error %d\n", rc);
8806 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8808 pr_err("error %d\n", rc);
8811 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8813 pr_err("error %d\n", rc);
8817 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
8819 pr_err("error %d\n", rc);
8824 while ((fsm_state != 4) && (i++ < 100)) {
8825 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
8827 pr_err("error %d\n", rc);
8831 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
8833 pr_err("error %d\n", rc);
8844 #define DEMOD_LOCKED 0x1
8845 #define SYNC_FLIPPED 0x2
8846 #define SPEC_MIRRORED 0x4
8848 * \fn int qam64auto ()
8849 * \brief auto do sync pattern switching and mirroring.
8850 * \param demod: instance of demod.
8851 * \param channel: pointer to channel data.
8852 * \param tuner_freq_offset: tuner frequency offset.
8853 * \param lock_status: pointer to lock status.
8857 qam64auto(struct drx_demod_instance *demod,
8858 struct drx_channel *channel,
8859 s32 tuner_freq_offset, enum drx_lock_status *lock_status)
8861 struct drxj_data *ext_attr = demod->my_ext_attr;
8862 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8863 struct drx39xxj_state *state = dev_addr->user_data;
8864 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
8866 u32 lck_state = NO_LOCK;
8868 u32 d_locked_time = 0;
8869 u32 timeout_ofs = 0;
8872 /* external attributes for storing acquired channel constellation */
8873 *lock_status = DRX_NOT_LOCKED;
8874 start_time = jiffies_to_msecs(jiffies);
8875 lck_state = NO_LOCK;
8877 rc = ctrl_lock_status(demod, lock_status);
8879 pr_err("error %d\n", rc);
8883 switch (lck_state) {
8885 if (*lock_status == DRXJ_DEMOD_LOCK) {
8886 rc = ctrl_get_qam_sig_quality(demod);
8888 pr_err("error %d\n", rc);
8891 if (p->cnr.stat[0].svalue > 20800) {
8892 lck_state = DEMOD_LOCKED;
8893 /* some delay to see if fec_lock possible TODO find the right value */
8894 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */
8895 d_locked_time = jiffies_to_msecs(jiffies);
8900 if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
8901 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8902 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8903 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8905 pr_err("error %d\n", rc);
8908 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8910 pr_err("error %d\n", rc);
8913 lck_state = SYNC_FLIPPED;
8918 if (*lock_status == DRXJ_DEMOD_LOCK) {
8919 if (channel->mirror == DRX_MIRROR_AUTO) {
8920 /* flip sync pattern back */
8921 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8923 pr_err("error %d\n", rc);
8926 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8928 pr_err("error %d\n", rc);
8932 ext_attr->mirror = DRX_MIRROR_YES;
8933 rc = qam_flip_spec(demod, channel);
8935 pr_err("error %d\n", rc);
8938 lck_state = SPEC_MIRRORED;
8939 /* reset timer TODO: still need 500ms? */
8940 start_time = d_locked_time =
8941 jiffies_to_msecs(jiffies);
8943 } else { /* no need to wait lock */
8946 jiffies_to_msecs(jiffies) -
8947 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8952 if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
8953 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8954 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8955 rc = ctrl_get_qam_sig_quality(demod);
8957 pr_err("error %d\n", rc);
8960 if (p->cnr.stat[0].svalue > 20800) {
8961 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8963 pr_err("error %d\n", rc);
8966 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8968 pr_err("error %d\n", rc);
8971 /* no need to wait lock */
8973 jiffies_to_msecs(jiffies) -
8974 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8983 ((*lock_status != DRX_LOCKED) &&
8984 (*lock_status != DRX_NEVER_LOCK) &&
8985 ((jiffies_to_msecs(jiffies) - start_time) <
8986 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
8988 /* Returning control to apllication ... */
8996 * \fn int qam256auto ()
8997 * \brief auto do sync pattern switching and mirroring.
8998 * \param demod: instance of demod.
8999 * \param channel: pointer to channel data.
9000 * \param tuner_freq_offset: tuner frequency offset.
9001 * \param lock_status: pointer to lock status.
9005 qam256auto(struct drx_demod_instance *demod,
9006 struct drx_channel *channel,
9007 s32 tuner_freq_offset, enum drx_lock_status *lock_status)
9009 struct drxj_data *ext_attr = demod->my_ext_attr;
9010 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9011 struct drx39xxj_state *state = dev_addr->user_data;
9012 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9014 u32 lck_state = NO_LOCK;
9016 u32 d_locked_time = 0;
9017 u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
9019 /* external attributes for storing acquired channel constellation */
9020 *lock_status = DRX_NOT_LOCKED;
9021 start_time = jiffies_to_msecs(jiffies);
9022 lck_state = NO_LOCK;
9024 rc = ctrl_lock_status(demod, lock_status);
9026 pr_err("error %d\n", rc);
9029 switch (lck_state) {
9031 if (*lock_status == DRXJ_DEMOD_LOCK) {
9032 rc = ctrl_get_qam_sig_quality(demod);
9034 pr_err("error %d\n", rc);
9037 if (p->cnr.stat[0].svalue > 26800) {
9038 lck_state = DEMOD_LOCKED;
9039 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */
9040 d_locked_time = jiffies_to_msecs(jiffies);
9045 if (*lock_status == DRXJ_DEMOD_LOCK) {
9046 if ((channel->mirror == DRX_MIRROR_AUTO) &&
9047 ((jiffies_to_msecs(jiffies) - d_locked_time) >
9048 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
9049 ext_attr->mirror = DRX_MIRROR_YES;
9050 rc = qam_flip_spec(demod, channel);
9052 pr_err("error %d\n", rc);
9055 lck_state = SPEC_MIRRORED;
9056 /* reset timer TODO: still need 300ms? */
9057 start_time = jiffies_to_msecs(jiffies);
9058 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
9069 ((*lock_status < DRX_LOCKED) &&
9070 (*lock_status != DRX_NEVER_LOCK) &&
9071 ((jiffies_to_msecs(jiffies) - start_time) <
9072 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)));
9080 * \fn int set_qam_channel ()
9081 * \brief Set QAM channel according to the requested constellation.
9082 * \param demod: instance of demod.
9083 * \param channel: pointer to channel data.
9087 set_qam_channel(struct drx_demod_instance *demod,
9088 struct drx_channel *channel, s32 tuner_freq_offset)
9090 struct drxj_data *ext_attr = NULL;
9092 enum drx_lock_status lock_status = DRX_NOT_LOCKED;
9093 bool auto_flag = false;
9095 /* external attributes for storing acquired channel constellation */
9096 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9098 /* set QAM channel constellation */
9099 switch (channel->constellation) {
9100 case DRX_CONSTELLATION_QAM16:
9101 case DRX_CONSTELLATION_QAM32:
9102 case DRX_CONSTELLATION_QAM128:
9104 case DRX_CONSTELLATION_QAM64:
9105 case DRX_CONSTELLATION_QAM256:
9106 if (ext_attr->standard != DRX_STANDARD_ITU_B)
9109 ext_attr->constellation = channel->constellation;
9110 if (channel->mirror == DRX_MIRROR_AUTO)
9111 ext_attr->mirror = DRX_MIRROR_NO;
9113 ext_attr->mirror = channel->mirror;
9115 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
9117 pr_err("error %d\n", rc);
9121 if (channel->constellation == DRX_CONSTELLATION_QAM64)
9122 rc = qam64auto(demod, channel, tuner_freq_offset,
9125 rc = qam256auto(demod, channel, tuner_freq_offset,
9128 pr_err("error %d\n", rc);
9132 case DRX_CONSTELLATION_AUTO: /* for channel scan */
9133 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9134 u16 qam_ctl_ena = 0;
9138 /* try to lock default QAM constellation: QAM256 */
9139 channel->constellation = DRX_CONSTELLATION_QAM256;
9140 ext_attr->constellation = DRX_CONSTELLATION_QAM256;
9141 if (channel->mirror == DRX_MIRROR_AUTO)
9142 ext_attr->mirror = DRX_MIRROR_NO;
9144 ext_attr->mirror = channel->mirror;
9145 rc = set_qam(demod, channel, tuner_freq_offset,
9148 pr_err("error %d\n", rc);
9151 rc = qam256auto(demod, channel, tuner_freq_offset,
9154 pr_err("error %d\n", rc);
9158 if (lock_status >= DRX_LOCKED) {
9159 channel->constellation = DRX_CONSTELLATION_AUTO;
9163 /* QAM254 not locked. Try QAM64 constellation */
9164 channel->constellation = DRX_CONSTELLATION_QAM64;
9165 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9166 if (channel->mirror == DRX_MIRROR_AUTO)
9167 ext_attr->mirror = DRX_MIRROR_NO;
9169 ext_attr->mirror = channel->mirror;
9171 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9172 SCU_RAM_QAM_CTL_ENA__A,
9175 pr_err("error %d\n", rc);
9178 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9179 SCU_RAM_QAM_CTL_ENA__A,
9180 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9182 pr_err("error %d\n", rc);
9185 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9186 SCU_RAM_QAM_FSM_STATE_TGT__A,
9189 pr_err("error %d\n", rc);
9191 } /* force to rate hunting */
9193 rc = set_qam(demod, channel, tuner_freq_offset,
9194 QAM_SET_OP_CONSTELLATION);
9196 pr_err("error %d\n", rc);
9199 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9200 SCU_RAM_QAM_CTL_ENA__A,
9203 pr_err("error %d\n", rc);
9207 rc = qam64auto(demod, channel, tuner_freq_offset,
9210 pr_err("error %d\n", rc);
9214 channel->constellation = DRX_CONSTELLATION_AUTO;
9215 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
9216 u16 qam_ctl_ena = 0;
9218 channel->constellation = DRX_CONSTELLATION_QAM64;
9219 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9222 if (channel->mirror == DRX_MIRROR_AUTO)
9223 ext_attr->mirror = DRX_MIRROR_NO;
9225 ext_attr->mirror = channel->mirror;
9226 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9227 SCU_RAM_QAM_CTL_ENA__A,
9230 pr_err("error %d\n", rc);
9233 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9234 SCU_RAM_QAM_CTL_ENA__A,
9235 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9237 pr_err("error %d\n", rc);
9240 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9241 SCU_RAM_QAM_FSM_STATE_TGT__A,
9244 pr_err("error %d\n", rc);
9246 } /* force to rate hunting */
9248 rc = set_qam(demod, channel, tuner_freq_offset,
9249 QAM_SET_OP_CONSTELLATION);
9251 pr_err("error %d\n", rc);
9254 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9255 SCU_RAM_QAM_CTL_ENA__A,
9258 pr_err("error %d\n", rc);
9261 rc = qam64auto(demod, channel, tuner_freq_offset,
9264 pr_err("error %d\n", rc);
9267 channel->constellation = DRX_CONSTELLATION_AUTO;
9278 /* restore starting value */
9280 channel->constellation = DRX_CONSTELLATION_AUTO;
9284 /*============================================================================*/
9287 * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr)
9288 * \brief Get RS error count in QAM mode (used for post RS BER calculation)
9289 * \return Error code
9291 * precondition: measurement period & measurement prescale must be set
9295 get_qamrs_err_count(struct i2c_device_addr *dev_addr,
9296 struct drxjrs_errors *rs_errors)
9299 u16 nr_bit_errors = 0,
9300 nr_symbol_errors = 0,
9301 nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0;
9303 /* check arguments */
9304 if (dev_addr == NULL)
9307 /* all reported errors are received in the */
9308 /* most recently finished measurment period */
9309 /* no of pre RS bit errors */
9310 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
9312 pr_err("error %d\n", rc);
9315 /* no of symbol errors */
9316 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
9318 pr_err("error %d\n", rc);
9321 /* no of packet errors */
9322 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
9324 pr_err("error %d\n", rc);
9327 /* no of failures to decode */
9328 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
9330 pr_err("error %d\n", rc);
9333 /* no of post RS bit erros */
9334 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
9336 pr_err("error %d\n", rc);
9340 /* These register values are fetched in non-atomic fashion */
9341 /* It is possible that the read values contain unrelated information */
9343 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
9344 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
9345 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
9346 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
9347 rs_errors->nr_snc_par_fail_count =
9348 nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M;
9355 /*============================================================================*/
9358 * \fn int get_sig_strength()
9359 * \brief Retrieve signal strength for VSB and QAM.
9360 * \param demod Pointer to demod instance
9361 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9363 * \retval 0 sig_strength contains valid data.
9364 * \retval -EINVAL sig_strength is NULL.
9365 * \retval -EIO Erroneous data, sig_strength contains invalid data.
9367 #define DRXJ_AGC_TOP 0x2800
9368 #define DRXJ_AGC_SNS 0x1600
9369 #define DRXJ_RFAGC_MAX 0x3fff
9370 #define DRXJ_RFAGC_MIN 0x800
9372 static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)
9374 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9383 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
9385 pr_err("error %d\n", rc);
9388 if_gain &= IQM_AF_AGC_IF__M;
9389 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
9391 pr_err("error %d\n", rc);
9394 rf_gain &= IQM_AF_AGC_RF__M;
9396 if_agc_sns = DRXJ_AGC_SNS;
9397 if_agc_top = DRXJ_AGC_TOP;
9398 rf_agc_max = DRXJ_RFAGC_MAX;
9399 rf_agc_min = DRXJ_RFAGC_MIN;
9401 if (if_gain > if_agc_top) {
9402 if (rf_gain > rf_agc_max)
9403 *sig_strength = 100;
9404 else if (rf_gain > rf_agc_min) {
9405 if (rf_agc_max == rf_agc_min) {
9406 pr_err("error: rf_agc_max == rf_agc_min\n");
9410 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
9414 } else if (if_gain > if_agc_sns) {
9415 if (if_agc_top == if_agc_sns) {
9416 pr_err("error: if_agc_top == if_agc_sns\n");
9420 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
9423 pr_err("error: if_agc_sns is zero!\n");
9426 *sig_strength = (20 * if_gain / if_agc_sns);
9429 if (*sig_strength <= 7)
9438 * \fn int ctrl_get_qam_sig_quality()
9439 * \brief Retrieve QAM signal quality from device.
9440 * \param devmod Pointer to demodulator instance.
9441 * \param sig_quality Pointer to signal quality data.
9443 * \retval 0 sig_quality contains valid data.
9444 * \retval -EINVAL sig_quality is NULL.
9445 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9447 * Pre-condition: Device must be started and in lock.
9450 ctrl_get_qam_sig_quality(struct drx_demod_instance *demod)
9452 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9453 struct drxj_data *ext_attr = demod->my_ext_attr;
9454 struct drx39xxj_state *state = dev_addr->user_data;
9455 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9456 struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 };
9457 enum drx_modulation constellation = ext_attr->constellation;
9460 u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */
9461 u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */
9462 u32 pkt_errs = 0; /* no of packet errors in RS */
9463 u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */
9464 u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */
9465 u16 fec_oc_period = 0; /* SNC sync failure measurement period */
9466 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
9467 u16 fec_rs_period = 0; /* Value for corresponding I2C register */
9468 /* calculation constants */
9469 u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */
9470 u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */
9471 /* intermediate results */
9472 u32 e = 0; /* exponent value used for QAM BER/SER */
9473 u32 m = 0; /* mantisa value used for QAM BER/SER */
9474 u32 ber_cnt = 0; /* BER count */
9475 /* signal quality info */
9476 u32 qam_sl_mer = 0; /* QAM MER */
9477 u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */
9478 u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */
9479 u32 qam_vd_ser = 0; /* ViterbiDecoder SER */
9480 u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
9481 u16 qam_vd_period = 0; /* Viterbi Measurement period */
9482 u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */
9484 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9486 /* read the physical registers */
9487 /* Get the RS error data */
9488 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
9490 pr_err("error %d\n", rc);
9493 /* get the register value needed for MER */
9494 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
9496 pr_err("error %d\n", rc);
9499 /* get the register value needed for post RS BER */
9500 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
9502 pr_err("error %d\n", rc);
9506 /* get constants needed for signal quality calculation */
9507 fec_rs_period = ext_attr->fec_rs_period;
9508 fec_rs_prescale = ext_attr->fec_rs_prescale;
9509 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
9510 qam_vd_period = ext_attr->qam_vd_period;
9511 qam_vd_prescale = ext_attr->qam_vd_prescale;
9512 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
9514 /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */
9515 switch (constellation) {
9516 case DRX_CONSTELLATION_QAM16:
9517 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2;
9519 case DRX_CONSTELLATION_QAM32:
9520 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2;
9522 case DRX_CONSTELLATION_QAM64:
9523 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2;
9525 case DRX_CONSTELLATION_QAM128:
9526 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2;
9528 case DRX_CONSTELLATION_QAM256:
9529 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2;
9535 /* ------------------------------ */
9536 /* MER Calculation */
9537 /* ------------------------------ */
9538 /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */
9540 /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */
9541 if (qam_sl_err_power == 0)
9544 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
9546 /* ----------------------------------------- */
9547 /* Pre Viterbi Symbol Error Rate Calculation */
9548 /* ----------------------------------------- */
9549 /* pre viterbi SER is good if it is below 0.025 */
9551 /* get the register value */
9552 /* no of quadrature symbol errors */
9553 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
9555 pr_err("error %d\n", rc);
9558 /* Extract the Exponent and the Mantisa */
9559 /* of number of quadrature symbol errors */
9560 e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >>
9561 QAM_VD_NR_QSYM_ERRORS_EXP__B;
9562 m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >>
9563 QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
9565 if ((m << e) >> 3 > 549752)
9566 qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9568 qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
9570 /* --------------------------------------- */
9571 /* pre and post RedSolomon BER Calculation */
9572 /* --------------------------------------- */
9573 /* pre RS BER is good if it is below 3.5e-4 */
9575 /* get the register values */
9576 pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors;
9577 pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count;
9579 /* Extract the Exponent and the Mantisa of the */
9580 /* pre Reed-Solomon bit error count */
9581 e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >>
9582 FEC_RS_NR_BIT_ERRORS_EXP__B;
9583 m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >>
9584 FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
9588 /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */
9589 if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0)
9590 qam_pre_rs_ber = 500000 * rs_bit_cnt >> e;
9592 qam_pre_rs_ber = ber_cnt;
9594 /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */
9595 /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */
9597 => c = (1000000*100*11.17)/1504 =
9598 post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) /
9599 (100 * FEC_OC_SNC_FAIL_PERIOD__A)
9600 *100 and /100 is for more precision.
9601 => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation
9603 Precision errors still possible.
9605 if (!fec_oc_period) {
9606 qam_post_rs_ber = 0xFFFFFFFF;
9608 e = post_bit_err_rs * 742686;
9609 m = fec_oc_period * 100;
9610 qam_post_rs_ber = e / m;
9613 /* fill signal quality data structure */
9614 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9615 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9616 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9617 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9618 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
9619 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
9621 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
9622 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9623 p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
9624 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9626 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
9627 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9630 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
9631 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9633 p->block_error.stat[0].uvalue += pkt_errs;
9635 #ifdef DRXJ_SIGNAL_ACCUM_ERR
9636 rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9638 pr_err("error %d\n", rc);
9645 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9646 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9647 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9648 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9649 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9650 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9655 #endif /* #ifndef DRXJ_VSB_ONLY */
9657 /*============================================================================*/
9658 /*== END QAM DATAPATH FUNCTIONS ==*/
9659 /*============================================================================*/
9661 /*============================================================================*/
9662 /*============================================================================*/
9663 /*== ATV DATAPATH FUNCTIONS ==*/
9664 /*============================================================================*/
9665 /*============================================================================*/
9668 Implementation notes.
9672 Four AGCs are used for NTSC:
9673 (1) RF (used to attenuate the input signal in case of to much power)
9674 (2) IF (used to attenuate the input signal in case of to much power)
9675 (3) Video AGC (used to amplify the output signal in case input to low)
9676 (4) SIF AGC (used to amplify the output signal in case input to low)
9678 Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed
9679 that the coupling between Video AGC and the RF and IF AGCs also works in
9680 favor of the SIF AGC.
9682 Three AGCs are used for FM:
9683 (1) RF (used to attenuate the input signal in case of to much power)
9684 (2) IF (used to attenuate the input signal in case of to much power)
9685 (3) SIF AGC (used to amplify the output signal in case input to low)
9687 The SIF AGC is now coupled to the RF/IF AGCs.
9688 The SIF AGC is needed for both SIF ouput and the internal SIF signal to
9691 RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
9692 the ATV block. The AGC control algorithms are all implemented in
9697 (Shadow settings will not be used for now, they will be implemented
9698 later on because of the schedule)
9700 Several HW/SCU "settings" can be used for ATV. The standard selection
9701 will reset most of these settings. To avoid that the end user apllication
9702 has to perform these settings each time the ATV or FM standards is
9703 selected the driver will shadow these settings. This enables the end user
9704 to perform the settings only once after a drx_open(). The driver must
9705 write the shadow settings to HW/SCU incase:
9706 ( setstandard FM/ATV) ||
9707 ( settings have changed && FM/ATV standard is active)
9708 The shadow settings will be stored in the device specific data container.
9709 A set of flags will be defined to flag changes in shadow settings.
9710 A routine will be implemented to write all changed shadow settings to
9713 The "settings" will consist of: AGC settings, filter settings etc.
9715 Disadvantage of use of shadow settings:
9716 Direct changes in HW/SCU registers will not be reflected in the
9717 shadow settings and these changes will be overwritten during a next
9718 update. This can happen during evaluation. This will not be a problem
9719 for normal customer usage.
9721 /* -------------------------------------------------------------------------- */
9724 * \fn int power_down_atv ()
9725 * \brief Power down ATV.
9726 * \param demod instance of demodulator
9727 * \param standard either NTSC or FM (sub strandard for ATV )
9730 * Stops and thus resets ATV and IQM block
9731 * SIF and CVBS ADC are powered down
9732 * Calls audio power down
9735 power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary)
9737 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9738 struct drxjscu_cmd cmd_scu = { /* command */ 0,
9739 /* parameter_len */ 0,
9741 /* *parameter */ NULL,
9749 /* Stop ATV SCU (will reset ATV and IQM hardware */
9750 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV |
9751 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9752 cmd_scu.parameter_len = 0;
9753 cmd_scu.result_len = 1;
9754 cmd_scu.parameter = NULL;
9755 cmd_scu.result = &cmd_result;
9756 rc = scu_command(dev_addr, &cmd_scu);
9758 pr_err("error %d\n", rc);
9761 /* Disable ATV outputs (ATV reset enables CVBS, undo this) */
9762 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
9764 pr_err("error %d\n", rc);
9768 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
9770 pr_err("error %d\n", rc);
9774 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
9776 pr_err("error %d\n", rc);
9779 rc = set_iqm_af(demod, false);
9781 pr_err("error %d\n", rc);
9785 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
9787 pr_err("error %d\n", rc);
9790 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
9792 pr_err("error %d\n", rc);
9795 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
9797 pr_err("error %d\n", rc);
9800 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
9802 pr_err("error %d\n", rc);
9805 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
9807 pr_err("error %d\n", rc);
9811 rc = power_down_aud(demod);
9813 pr_err("error %d\n", rc);
9822 /*============================================================================*/
9825 * \brief Power up AUD.
9826 * \param demod instance of demodulator
9830 static int power_down_aud(struct drx_demod_instance *demod)
9832 struct i2c_device_addr *dev_addr = NULL;
9833 struct drxj_data *ext_attr = NULL;
9836 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
9837 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9839 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
9841 pr_err("error %d\n", rc);
9845 ext_attr->aud_data.audio_is_active = false;
9853 * \fn int set_orx_nsu_aox()
9854 * \brief Configure OrxNsuAox for OOB
9855 * \param demod instance of demodulator.
9859 static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)
9861 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9865 /* Configure NSU_AOX */
9866 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9868 pr_err("error %d\n", rc);
9872 data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
9874 data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
9875 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
9877 pr_err("error %d\n", rc);
9887 * \fn int ctrl_set_oob()
9888 * \brief Set OOB channel to be used.
9889 * \param demod instance of demodulator
9890 * \param oob_param OOB parameters for channel setting.
9891 * \frequency should be in KHz
9894 * Accepts only. Returns error otherwise.
9895 * Demapper value is written after scu_command START
9896 * because START command causes COMM_EXEC transition
9897 * from 0 to 1 which causes all registers to be
9898 * overwritten with initial value
9902 /* Nyquist filter impulse response */
9903 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
9904 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
9905 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
9907 /* Coefficients for the nyquist fitler (total: 27 taps) */
9908 #define NYQFILTERLEN 27
9910 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
9913 s32 freq = 0; /* KHz */
9914 struct i2c_device_addr *dev_addr = NULL;
9915 struct drxj_data *ext_attr = NULL;
9917 bool mirror_freq_spect_oob = false;
9918 u16 trk_filter_value = 0;
9919 struct drxjscu_cmd scu_cmd;
9920 u16 set_param_parameters[3];
9921 u16 cmd_result[2] = { 0, 0 };
9922 s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {
9923 IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */
9924 IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */
9925 IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */
9926 IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */
9928 u8 mode_val[4] = { 2, 2, 0, 1 };
9929 u8 pfi_coeffs[4][6] = {
9930 {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
9931 {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
9932 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9933 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9937 dev_addr = demod->my_i2c_dev_addr;
9938 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9939 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
9941 /* Check parameters */
9942 if (oob_param == NULL) {
9943 /* power off oob module */
9944 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9945 | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9946 scu_cmd.parameter_len = 0;
9947 scu_cmd.result_len = 1;
9948 scu_cmd.result = cmd_result;
9949 rc = scu_command(dev_addr, &scu_cmd);
9951 pr_err("error %d\n", rc);
9954 rc = set_orx_nsu_aox(demod, false);
9956 pr_err("error %d\n", rc);
9959 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9961 pr_err("error %d\n", rc);
9965 ext_attr->oob_power_on = false;
9969 freq = oob_param->frequency;
9970 if ((freq < 70000) || (freq > 130000))
9972 freq = (freq - 50000) / 50;
9977 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
9979 index = (u16) ((freq - 400) / 200);
9980 remainder = (u16) ((freq - 400) % 200);
9982 trk_filtercfg[index] - (trk_filtercfg[index] -
9983 trk_filtercfg[index +
9984 1]) / 10 * remainder /
9991 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9993 pr_err("error %d\n", rc);
9996 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9997 | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9998 scu_cmd.parameter_len = 0;
9999 scu_cmd.result_len = 1;
10000 scu_cmd.result = cmd_result;
10001 rc = scu_command(dev_addr, &scu_cmd);
10003 pr_err("error %d\n", rc);
10009 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10010 | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
10011 scu_cmd.parameter_len = 0;
10012 scu_cmd.result_len = 1;
10013 scu_cmd.result = cmd_result;
10014 rc = scu_command(dev_addr, &scu_cmd);
10016 pr_err("error %d\n", rc);
10022 /* set frequency, spectrum inversion and data rate */
10023 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10024 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
10025 scu_cmd.parameter_len = 3;
10026 /* 1-data rate;2-frequency */
10027 switch (oob_param->standard) {
10028 case DRX_OOB_MODE_A:
10030 /* signal is transmitted inverted */
10031 ((oob_param->spectrum_inverted == true) &&
10032 /* and tuner is not mirroring the signal */
10033 (!mirror_freq_spect_oob)) |
10035 /* signal is transmitted noninverted */
10036 ((oob_param->spectrum_inverted == false) &&
10037 /* and tuner is mirroring the signal */
10038 (mirror_freq_spect_oob))
10040 set_param_parameters[0] =
10041 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
10043 set_param_parameters[0] =
10044 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
10046 case DRX_OOB_MODE_B_GRADE_A:
10048 /* signal is transmitted inverted */
10049 ((oob_param->spectrum_inverted == true) &&
10050 /* and tuner is not mirroring the signal */
10051 (!mirror_freq_spect_oob)) |
10053 /* signal is transmitted noninverted */
10054 ((oob_param->spectrum_inverted == false) &&
10055 /* and tuner is mirroring the signal */
10056 (mirror_freq_spect_oob))
10058 set_param_parameters[0] =
10059 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
10061 set_param_parameters[0] =
10062 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
10064 case DRX_OOB_MODE_B_GRADE_B:
10067 /* signal is transmitted inverted */
10068 ((oob_param->spectrum_inverted == true) &&
10069 /* and tuner is not mirroring the signal */
10070 (!mirror_freq_spect_oob)) |
10072 /* signal is transmitted noninverted */
10073 ((oob_param->spectrum_inverted == false) &&
10074 /* and tuner is mirroring the signal */
10075 (mirror_freq_spect_oob))
10077 set_param_parameters[0] =
10078 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
10080 set_param_parameters[0] =
10081 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
10084 set_param_parameters[1] = (u16) (freq & 0xFFFF);
10085 set_param_parameters[2] = trk_filter_value;
10086 scu_cmd.parameter = set_param_parameters;
10087 scu_cmd.result_len = 1;
10088 scu_cmd.result = cmd_result;
10089 mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];
10090 rc = scu_command(dev_addr, &scu_cmd);
10092 pr_err("error %d\n", rc);
10096 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
10098 pr_err("error %d\n", rc);
10100 } /* Write magic word to enable pdr reg write */
10101 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
10103 pr_err("error %d\n", rc);
10106 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
10108 pr_err("error %d\n", rc);
10111 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
10113 pr_err("error %d\n", rc);
10115 } /* Write magic word to disable pdr reg write */
10117 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
10119 pr_err("error %d\n", rc);
10122 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
10124 pr_err("error %d\n", rc);
10127 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
10129 pr_err("error %d\n", rc);
10134 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
10136 pr_err("error %d\n", rc);
10141 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10143 pr_err("error %d\n", rc);
10147 /* initialization for target mode */
10148 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
10150 pr_err("error %d\n", rc);
10153 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
10155 pr_err("error %d\n", rc);
10159 /* Reset bits for timing and freq. recovery */
10160 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
10162 pr_err("error %d\n", rc);
10165 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
10167 pr_err("error %d\n", rc);
10170 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
10172 pr_err("error %d\n", rc);
10175 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
10177 pr_err("error %d\n", rc);
10181 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
10182 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
10184 pr_err("error %d\n", rc);
10187 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10189 pr_err("error %d\n", rc);
10192 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
10194 pr_err("error %d\n", rc);
10197 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10199 pr_err("error %d\n", rc);
10202 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
10204 pr_err("error %d\n", rc);
10208 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
10209 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
10211 pr_err("error %d\n", rc);
10214 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10216 pr_err("error %d\n", rc);
10219 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
10221 pr_err("error %d\n", rc);
10224 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10226 pr_err("error %d\n", rc);
10229 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
10231 pr_err("error %d\n", rc);
10235 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
10236 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
10238 pr_err("error %d\n", rc);
10241 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10243 pr_err("error %d\n", rc);
10246 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
10248 pr_err("error %d\n", rc);
10251 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10253 pr_err("error %d\n", rc);
10256 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
10258 pr_err("error %d\n", rc);
10262 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
10263 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
10265 pr_err("error %d\n", rc);
10268 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10270 pr_err("error %d\n", rc);
10273 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
10275 pr_err("error %d\n", rc);
10278 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10280 pr_err("error %d\n", rc);
10283 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
10285 pr_err("error %d\n", rc);
10289 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */
10290 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
10292 pr_err("error %d\n", rc);
10295 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10297 pr_err("error %d\n", rc);
10300 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
10302 pr_err("error %d\n", rc);
10305 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10307 pr_err("error %d\n", rc);
10310 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
10312 pr_err("error %d\n", rc);
10316 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */
10317 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
10319 pr_err("error %d\n", rc);
10322 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10324 pr_err("error %d\n", rc);
10327 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
10329 pr_err("error %d\n", rc);
10332 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10334 pr_err("error %d\n", rc);
10337 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
10339 pr_err("error %d\n", rc);
10343 /* PRE-Filter coefficients (PFI) */
10344 rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
10346 pr_err("error %d\n", rc);
10349 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
10351 pr_err("error %d\n", rc);
10355 /* NYQUIST-Filter coefficients (NYQ) */
10356 for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {
10357 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
10359 pr_err("error %d\n", rc);
10362 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
10364 pr_err("error %d\n", rc);
10368 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
10370 pr_err("error %d\n", rc);
10373 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
10375 pr_err("error %d\n", rc);
10381 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10382 | SCU_RAM_COMMAND_CMD_DEMOD_START;
10383 scu_cmd.parameter_len = 0;
10384 scu_cmd.result_len = 1;
10385 scu_cmd.result = cmd_result;
10386 rc = scu_command(dev_addr, &scu_cmd);
10388 pr_err("error %d\n", rc);
10392 rc = set_orx_nsu_aox(demod, true);
10394 pr_err("error %d\n", rc);
10397 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10399 pr_err("error %d\n", rc);
10403 ext_attr->oob_power_on = true;
10410 /*============================================================================*/
10411 /*== END OOB DATAPATH FUNCTIONS ==*/
10412 /*============================================================================*/
10414 /*=============================================================================
10415 ===== MC command related functions ==========================================
10416 ===========================================================================*/
10418 /*=============================================================================
10419 ===== ctrl_set_channel() ==========================================================
10420 ===========================================================================*/
10422 * \fn int ctrl_set_channel()
10423 * \brief Select a new transmission channel.
10424 * \param demod instance of demod.
10425 * \param channel Pointer to channel data.
10428 * In case the tuner module is not used and in case of NTSC/FM the pogrammer
10429 * must tune the tuner to the centre frequency of the NTSC/FM channel.
10433 ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel)
10436 s32 tuner_freq_offset = 0;
10437 struct drxj_data *ext_attr = NULL;
10438 struct i2c_device_addr *dev_addr = NULL;
10439 enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10440 #ifndef DRXJ_VSB_ONLY
10441 u32 min_symbol_rate = 0;
10442 u32 max_symbol_rate = 0;
10443 int bandwidth_temp = 0;
10446 /*== check arguments ======================================================*/
10447 if ((demod == NULL) || (channel == NULL))
10450 dev_addr = demod->my_i2c_dev_addr;
10451 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10452 standard = ext_attr->standard;
10454 /* check valid standards */
10455 switch (standard) {
10456 case DRX_STANDARD_8VSB:
10457 #ifndef DRXJ_VSB_ONLY
10458 case DRX_STANDARD_ITU_A:
10459 case DRX_STANDARD_ITU_B:
10460 case DRX_STANDARD_ITU_C:
10461 #endif /* DRXJ_VSB_ONLY */
10463 case DRX_STANDARD_UNKNOWN:
10468 /* check bandwidth QAM annex B, NTSC and 8VSB */
10469 if ((standard == DRX_STANDARD_ITU_B) ||
10470 (standard == DRX_STANDARD_8VSB) ||
10471 (standard == DRX_STANDARD_NTSC)) {
10472 switch (channel->bandwidth) {
10473 case DRX_BANDWIDTH_6MHZ:
10474 case DRX_BANDWIDTH_UNKNOWN: /* fall through */
10475 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10477 case DRX_BANDWIDTH_8MHZ: /* fall through */
10478 case DRX_BANDWIDTH_7MHZ: /* fall through */
10484 /* For QAM annex A and annex C:
10485 -check symbolrate and constellation
10486 -derive bandwidth from symbolrate (input bandwidth is ignored)
10488 #ifndef DRXJ_VSB_ONLY
10489 if ((standard == DRX_STANDARD_ITU_A) ||
10490 (standard == DRX_STANDARD_ITU_C)) {
10491 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW };
10492 int bw_rolloff_factor = 0;
10494 bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113;
10495 min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN;
10496 max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX;
10497 /* config SMA_TX pin to SAW switch mode */
10498 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
10500 pr_err("error %d\n", rc);
10504 if (channel->symbolrate < min_symbol_rate ||
10505 channel->symbolrate > max_symbol_rate) {
10509 switch (channel->constellation) {
10510 case DRX_CONSTELLATION_QAM16: /* fall through */
10511 case DRX_CONSTELLATION_QAM32: /* fall through */
10512 case DRX_CONSTELLATION_QAM64: /* fall through */
10513 case DRX_CONSTELLATION_QAM128: /* fall through */
10514 case DRX_CONSTELLATION_QAM256:
10515 bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
10516 bandwidth = bandwidth_temp / 100;
10518 if ((bandwidth_temp % 100) >= 50)
10521 if (bandwidth <= 6100000) {
10522 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10523 } else if ((bandwidth > 6100000)
10524 && (bandwidth <= 7100000)) {
10525 channel->bandwidth = DRX_BANDWIDTH_7MHZ;
10526 } else if (bandwidth > 7100000) {
10527 channel->bandwidth = DRX_BANDWIDTH_8MHZ;
10535 /* For QAM annex B:
10536 -check constellation
10538 if (standard == DRX_STANDARD_ITU_B) {
10539 switch (channel->constellation) {
10540 case DRX_CONSTELLATION_AUTO:
10541 case DRX_CONSTELLATION_QAM256:
10542 case DRX_CONSTELLATION_QAM64:
10548 switch (channel->interleavemode) {
10549 case DRX_INTERLEAVEMODE_I128_J1:
10550 case DRX_INTERLEAVEMODE_I128_J1_V2:
10551 case DRX_INTERLEAVEMODE_I128_J2:
10552 case DRX_INTERLEAVEMODE_I64_J2:
10553 case DRX_INTERLEAVEMODE_I128_J3:
10554 case DRX_INTERLEAVEMODE_I32_J4:
10555 case DRX_INTERLEAVEMODE_I128_J4:
10556 case DRX_INTERLEAVEMODE_I16_J8:
10557 case DRX_INTERLEAVEMODE_I128_J5:
10558 case DRX_INTERLEAVEMODE_I8_J16:
10559 case DRX_INTERLEAVEMODE_I128_J6:
10560 case DRX_INTERLEAVEMODE_I128_J7:
10561 case DRX_INTERLEAVEMODE_I128_J8:
10562 case DRX_INTERLEAVEMODE_I12_J17:
10563 case DRX_INTERLEAVEMODE_I5_J4:
10564 case DRX_INTERLEAVEMODE_B52_M240:
10565 case DRX_INTERLEAVEMODE_B52_M720:
10566 case DRX_INTERLEAVEMODE_UNKNOWN:
10567 case DRX_INTERLEAVEMODE_AUTO:
10574 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
10575 /* SAW SW, user UIO is used for switchable SAW */
10576 struct drxuio_data uio1 = { DRX_UIO1, false };
10578 switch (channel->bandwidth) {
10579 case DRX_BANDWIDTH_8MHZ:
10582 case DRX_BANDWIDTH_7MHZ:
10583 uio1.value = false;
10585 case DRX_BANDWIDTH_6MHZ:
10586 uio1.value = false;
10588 case DRX_BANDWIDTH_UNKNOWN:
10593 rc = ctrl_uio_write(demod, &uio1);
10595 pr_err("error %d\n", rc);
10599 #endif /* DRXJ_VSB_ONLY */
10600 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
10602 pr_err("error %d\n", rc);
10606 tuner_freq_offset = 0;
10608 /*== Setup demod for specific standard ====================================*/
10609 switch (standard) {
10610 case DRX_STANDARD_8VSB:
10611 if (channel->mirror == DRX_MIRROR_AUTO)
10612 ext_attr->mirror = DRX_MIRROR_NO;
10614 ext_attr->mirror = channel->mirror;
10615 rc = set_vsb(demod);
10617 pr_err("error %d\n", rc);
10620 rc = set_frequency(demod, channel, tuner_freq_offset);
10622 pr_err("error %d\n", rc);
10626 #ifndef DRXJ_VSB_ONLY
10627 case DRX_STANDARD_ITU_A: /* fallthrough */
10628 case DRX_STANDARD_ITU_B: /* fallthrough */
10629 case DRX_STANDARD_ITU_C:
10630 rc = set_qam_channel(demod, channel, tuner_freq_offset);
10632 pr_err("error %d\n", rc);
10637 case DRX_STANDARD_UNKNOWN:
10642 /* flag the packet error counter reset */
10643 ext_attr->reset_pkt_err_acc = true;
10650 /*=============================================================================
10651 ===== SigQuality() ==========================================================
10652 ===========================================================================*/
10655 * \fn int ctrl_sig_quality()
10656 * \brief Retrieve signal quality form device.
10657 * \param devmod Pointer to demodulator instance.
10658 * \param sig_quality Pointer to signal quality data.
10660 * \retval 0 sig_quality contains valid data.
10661 * \retval -EINVAL sig_quality is NULL.
10662 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10666 ctrl_sig_quality(struct drx_demod_instance *demod,
10667 enum drx_lock_status lock_status)
10669 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
10670 struct drxj_data *ext_attr = demod->my_ext_attr;
10671 struct drx39xxj_state *state = dev_addr->user_data;
10672 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
10673 enum drx_standard standard = ext_attr->standard;
10675 u32 ber, cnt, err, pkt;
10676 u16 mer, strength = 0;
10678 rc = get_sig_strength(demod, &strength);
10680 pr_err("error getting signal strength %d\n", rc);
10681 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10683 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
10684 p->strength.stat[0].uvalue = 65535UL * strength/ 100;
10687 switch (standard) {
10688 case DRX_STANDARD_8VSB:
10689 #ifdef DRXJ_SIGNAL_ACCUM_ERR
10690 rc = get_acc_pkt_err(demod, &pkt);
10692 pr_err("error %d\n", rc);
10696 if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) {
10697 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10698 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10699 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10700 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10701 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10702 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10703 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10705 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
10707 pr_err("error %d getting UCB\n", rc);
10708 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10710 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
10711 p->block_error.stat[0].uvalue += err;
10712 p->block_count.stat[0].scale = FE_SCALE_COUNTER;
10713 p->block_count.stat[0].uvalue += pkt;
10716 /* PostViterbi is compute in steps of 10^(-6) */
10717 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
10719 pr_err("error %d getting pre-ber\n", rc);
10720 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10722 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10723 p->pre_bit_error.stat[0].uvalue += ber;
10724 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10725 p->pre_bit_count.stat[0].uvalue += cnt;
10728 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
10730 pr_err("error %d getting post-ber\n", rc);
10731 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10733 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10734 p->post_bit_error.stat[0].uvalue += ber;
10735 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10736 p->post_bit_count.stat[0].uvalue += cnt;
10738 rc = get_vsbmer(dev_addr, &mer);
10740 pr_err("error %d getting MER\n", rc);
10741 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10743 p->cnr.stat[0].svalue = mer * 100;
10744 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
10748 #ifndef DRXJ_VSB_ONLY
10749 case DRX_STANDARD_ITU_A:
10750 case DRX_STANDARD_ITU_B:
10751 case DRX_STANDARD_ITU_C:
10752 rc = ctrl_get_qam_sig_quality(demod);
10754 pr_err("error %d\n", rc);
10768 /*============================================================================*/
10771 * \fn int ctrl_lock_status()
10772 * \brief Retrieve lock status .
10773 * \param dev_addr Pointer to demodulator device address.
10774 * \param lock_stat Pointer to lock status structure.
10779 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat)
10781 enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10782 struct drxj_data *ext_attr = NULL;
10783 struct i2c_device_addr *dev_addr = NULL;
10784 struct drxjscu_cmd cmd_scu = { /* command */ 0,
10785 /* parameter_len */ 0,
10786 /* result_len */ 0,
10787 /* *parameter */ NULL,
10791 u16 cmd_result[2] = { 0, 0 };
10792 u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED;
10794 /* check arguments */
10795 if ((demod == NULL) || (lock_stat == NULL))
10798 dev_addr = demod->my_i2c_dev_addr;
10799 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10800 standard = ext_attr->standard;
10802 *lock_stat = DRX_NOT_LOCKED;
10804 /* define the SCU command code */
10805 switch (standard) {
10806 case DRX_STANDARD_8VSB:
10807 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
10808 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10811 #ifndef DRXJ_VSB_ONLY
10812 case DRX_STANDARD_ITU_A:
10813 case DRX_STANDARD_ITU_B:
10814 case DRX_STANDARD_ITU_C:
10815 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
10816 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10819 case DRX_STANDARD_UNKNOWN: /* fallthrough */
10824 /* define the SCU command parameters and execute the command */
10825 cmd_scu.parameter_len = 0;
10826 cmd_scu.result_len = 2;
10827 cmd_scu.parameter = NULL;
10828 cmd_scu.result = cmd_result;
10829 rc = scu_command(dev_addr, &cmd_scu);
10831 pr_err("error %d\n", rc);
10835 /* set the lock status */
10836 if (cmd_scu.result[1] < demod_lock) {
10837 /* 0x0000 NOT LOCKED */
10838 *lock_stat = DRX_NOT_LOCKED;
10839 } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) {
10840 *lock_stat = DRXJ_DEMOD_LOCK;
10841 } else if (cmd_scu.result[1] <
10842 SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
10843 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
10844 *lock_stat = DRX_LOCKED;
10846 /* 0xC000 NEVER LOCKED */
10847 /* (system will never be able to lock to the signal) */
10848 *lock_stat = DRX_NEVER_LOCK;
10856 /*============================================================================*/
10859 * \fn int ctrl_set_standard()
10860 * \brief Set modulation standard to be used.
10861 * \param standard Modulation standard.
10864 * Setup stuff for the desired demodulation standard.
10865 * Disable and power down the previous selected demodulation standard
10869 ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
10871 struct drxj_data *ext_attr = NULL;
10873 enum drx_standard prev_standard;
10875 /* check arguments */
10876 if ((standard == NULL) || (demod == NULL))
10879 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10880 prev_standard = ext_attr->standard;
10883 Stop and power down previous standard
10885 switch (prev_standard) {
10886 #ifndef DRXJ_VSB_ONLY
10887 case DRX_STANDARD_ITU_A: /* fallthrough */
10888 case DRX_STANDARD_ITU_B: /* fallthrough */
10889 case DRX_STANDARD_ITU_C:
10890 rc = power_down_qam(demod, false);
10892 pr_err("error %d\n", rc);
10897 case DRX_STANDARD_8VSB:
10898 rc = power_down_vsb(demod, false);
10900 pr_err("error %d\n", rc);
10904 case DRX_STANDARD_UNKNOWN:
10907 case DRX_STANDARD_AUTO: /* fallthrough */
10913 Initialize channel independent registers
10914 Power up new standard
10916 ext_attr->standard = *standard;
10918 switch (*standard) {
10919 #ifndef DRXJ_VSB_ONLY
10920 case DRX_STANDARD_ITU_A: /* fallthrough */
10921 case DRX_STANDARD_ITU_B: /* fallthrough */
10922 case DRX_STANDARD_ITU_C:
10925 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10927 pr_err("error %d\n", rc);
10933 case DRX_STANDARD_8VSB:
10934 rc = set_vsb_leak_n_gain(demod);
10936 pr_err("error %d\n", rc);
10941 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10948 /* Don't know what the standard is now ... try again */
10949 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10953 /*============================================================================*/
10955 static void drxj_reset_mode(struct drxj_data *ext_attr)
10957 /* Initialize default AFE configuration for QAM */
10958 if (ext_attr->has_lna) {
10959 /* IF AGC off, PGA active */
10960 #ifndef DRXJ_VSB_ONLY
10961 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10962 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10963 ext_attr->qam_pga_cfg = 140 + (11 * 13);
10965 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10966 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10967 ext_attr->vsb_pga_cfg = 140 + (11 * 13);
10969 /* IF AGC on, PGA not active */
10970 #ifndef DRXJ_VSB_ONLY
10971 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10972 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10973 ext_attr->qam_if_agc_cfg.min_output_level = 0;
10974 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
10975 ext_attr->qam_if_agc_cfg.speed = 3;
10976 ext_attr->qam_if_agc_cfg.top = 1297;
10977 ext_attr->qam_pga_cfg = 140;
10979 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10980 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10981 ext_attr->vsb_if_agc_cfg.min_output_level = 0;
10982 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
10983 ext_attr->vsb_if_agc_cfg.speed = 3;
10984 ext_attr->vsb_if_agc_cfg.top = 1024;
10985 ext_attr->vsb_pga_cfg = 140;
10987 /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */
10988 /* mc has not used them */
10989 #ifndef DRXJ_VSB_ONLY
10990 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
10991 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10992 ext_attr->qam_rf_agc_cfg.min_output_level = 0;
10993 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
10994 ext_attr->qam_rf_agc_cfg.speed = 3;
10995 ext_attr->qam_rf_agc_cfg.top = 9500;
10996 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
10997 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
10998 ext_attr->qam_pre_saw_cfg.reference = 0x07;
10999 ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
11001 /* Initialize default AFE configuration for VSB */
11002 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
11003 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11004 ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
11005 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
11006 ext_attr->vsb_rf_agc_cfg.speed = 3;
11007 ext_attr->vsb_rf_agc_cfg.top = 9500;
11008 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
11009 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
11010 ext_attr->vsb_pre_saw_cfg.reference = 0x07;
11011 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
11015 * \fn int ctrl_power_mode()
11016 * \brief Set the power mode of the device to the specified power mode
11017 * \param demod Pointer to demodulator instance.
11018 * \param mode Pointer to new power mode.
11020 * \retval 0 Success
11021 * \retval -EIO I2C error or other failure
11022 * \retval -EINVAL Invalid mode argument.
11027 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
11029 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
11030 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
11031 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL;
11033 u16 sio_cc_pwd_mode = 0;
11035 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11036 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11037 dev_addr = demod->my_i2c_dev_addr;
11039 /* Check arguments */
11043 /* If already in requested power mode, do nothing */
11044 if (common_attr->current_power_mode == *mode)
11049 case DRXJ_POWER_DOWN_MAIN_PATH:
11050 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
11052 case DRXJ_POWER_DOWN_CORE:
11053 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
11055 case DRXJ_POWER_DOWN_PLL:
11056 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
11058 case DRX_POWER_DOWN:
11059 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
11062 /* Unknow sleep mode */
11067 /* Check if device needs to be powered up */
11068 if ((common_attr->current_power_mode != DRX_POWER_UP)) {
11069 rc = power_up_device(demod);
11071 pr_err("error %d\n", rc);
11076 if ((*mode == DRX_POWER_UP)) {
11077 /* Restore analog & pin configuration */
11079 /* Initialize default AFE configuration for VSB */
11080 drxj_reset_mode(ext_attr);
11082 /* Power down to requested mode */
11083 /* Backup some register settings */
11084 /* Set pins with possible pull-ups connected to them in input mode */
11085 /* Analog power down */
11086 /* ADC power down */
11087 /* Power down device */
11088 /* stop all comm_exec */
11090 Stop and power down previous standard
11093 switch (ext_attr->standard) {
11094 case DRX_STANDARD_ITU_A:
11095 case DRX_STANDARD_ITU_B:
11096 case DRX_STANDARD_ITU_C:
11097 rc = power_down_qam(demod, true);
11099 pr_err("error %d\n", rc);
11103 case DRX_STANDARD_8VSB:
11104 rc = power_down_vsb(demod, true);
11106 pr_err("error %d\n", rc);
11110 case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */
11111 case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */
11112 case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */
11113 case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */
11114 case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */
11115 case DRX_STANDARD_NTSC: /* fallthrough */
11116 case DRX_STANDARD_FM:
11117 rc = power_down_atv(demod, ext_attr->standard, true);
11119 pr_err("error %d\n", rc);
11123 case DRX_STANDARD_UNKNOWN:
11126 case DRX_STANDARD_AUTO: /* fallthrough */
11130 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11133 if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) {
11134 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
11136 pr_err("error %d\n", rc);
11139 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11141 pr_err("error %d\n", rc);
11145 if ((*mode != DRX_POWER_UP)) {
11146 /* Initialize HI, wakeup key especially before put IC to sleep */
11147 rc = init_hi(demod);
11149 pr_err("error %d\n", rc);
11153 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
11154 rc = hi_cfg_command(demod);
11156 pr_err("error %d\n", rc);
11162 common_attr->current_power_mode = *mode;
11169 /*============================================================================*/
11170 /*== CTRL Set/Get Config related functions ===================================*/
11171 /*============================================================================*/
11174 * \fn int ctrl_set_cfg_pre_saw()
11175 * \brief Set Pre-saw reference.
11176 * \param demod demod instance
11181 * Dispatch handling to standard specific function.
11185 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw)
11187 struct i2c_device_addr *dev_addr = NULL;
11188 struct drxj_data *ext_attr = NULL;
11191 dev_addr = demod->my_i2c_dev_addr;
11192 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11194 /* check arguments */
11195 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
11200 /* Only if standard is currently active */
11201 if ((ext_attr->standard == pre_saw->standard) ||
11202 (DRXJ_ISQAMSTD(ext_attr->standard) &&
11203 DRXJ_ISQAMSTD(pre_saw->standard)) ||
11204 (DRXJ_ISATVSTD(ext_attr->standard) &&
11205 DRXJ_ISATVSTD(pre_saw->standard))) {
11206 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11208 pr_err("error %d\n", rc);
11213 /* Store pre-saw settings */
11214 switch (pre_saw->standard) {
11215 case DRX_STANDARD_8VSB:
11216 ext_attr->vsb_pre_saw_cfg = *pre_saw;
11218 #ifndef DRXJ_VSB_ONLY
11219 case DRX_STANDARD_ITU_A: /* fallthrough */
11220 case DRX_STANDARD_ITU_B: /* fallthrough */
11221 case DRX_STANDARD_ITU_C:
11222 ext_attr->qam_pre_saw_cfg = *pre_saw;
11234 /*============================================================================*/
11237 * \fn int ctrl_set_cfg_afe_gain()
11238 * \brief Set AFE Gain.
11239 * \param demod demod instance
11244 * Dispatch handling to standard specific function.
11248 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain)
11250 struct i2c_device_addr *dev_addr = NULL;
11251 struct drxj_data *ext_attr = NULL;
11255 /* check arguments */
11256 if (afe_gain == NULL)
11259 dev_addr = demod->my_i2c_dev_addr;
11260 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11262 switch (afe_gain->standard) {
11263 case DRX_STANDARD_8VSB: /* fallthrough */
11264 #ifndef DRXJ_VSB_ONLY
11265 case DRX_STANDARD_ITU_A: /* fallthrough */
11266 case DRX_STANDARD_ITU_B: /* fallthrough */
11267 case DRX_STANDARD_ITU_C:
11275 /* TODO PGA gain is also written by microcode (at least by QAM and VSB)
11276 So I (PJ) think interface requires choice between auto, user mode */
11278 if (afe_gain->gain >= 329)
11280 else if (afe_gain->gain <= 147)
11283 gain = (afe_gain->gain - 140 + 6) / 13;
11285 /* Only if standard is currently active */
11286 if (ext_attr->standard == afe_gain->standard) {
11287 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
11289 pr_err("error %d\n", rc);
11294 /* Store AFE Gain settings */
11295 switch (afe_gain->standard) {
11296 case DRX_STANDARD_8VSB:
11297 ext_attr->vsb_pga_cfg = gain * 13 + 140;
11299 #ifndef DRXJ_VSB_ONLY
11300 case DRX_STANDARD_ITU_A: /* fallthrough */
11301 case DRX_STANDARD_ITU_B: /* fallthrough */
11302 case DRX_STANDARD_ITU_C:
11303 ext_attr->qam_pga_cfg = gain * 13 + 140;
11315 /*============================================================================*/
11318 /*=============================================================================
11319 ===== EXPORTED FUNCTIONS ====================================================*/
11321 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11322 struct drxu_code_info *mc_info,
11323 enum drxu_code_action action);
11324 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state);
11328 * \brief Open the demod instance, configure device, configure drxdriver
11329 * \return Status_t Return status.
11331 * drxj_open() can be called with a NULL ucode image => no ucode upload.
11332 * This means that drxj_open() must NOT contain SCU commands or, in general,
11333 * rely on SCU or AUD ucode to be present.
11337 static int drxj_open(struct drx_demod_instance *demod)
11339 struct i2c_device_addr *dev_addr = NULL;
11340 struct drxj_data *ext_attr = NULL;
11341 struct drx_common_attr *common_attr = NULL;
11342 u32 driver_version = 0;
11343 struct drxu_code_info ucode_info;
11344 struct drx_cfg_mpeg_output cfg_mpeg_output;
11346 enum drx_power_mode power_mode = DRX_POWER_UP;
11348 if ((demod == NULL) ||
11349 (demod->my_common_attr == NULL) ||
11350 (demod->my_ext_attr == NULL) ||
11351 (demod->my_i2c_dev_addr == NULL) ||
11352 (demod->my_common_attr->is_opened)) {
11356 /* Check arguments */
11357 if (demod->my_ext_attr == NULL)
11360 dev_addr = demod->my_i2c_dev_addr;
11361 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11362 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11364 rc = ctrl_power_mode(demod, &power_mode);
11366 pr_err("error %d\n", rc);
11369 if (power_mode != DRX_POWER_UP) {
11371 pr_err("failed to powerup device\n");
11375 /* has to be in front of setIqmAf and setOrxNsuAox */
11376 rc = get_device_capabilities(demod);
11378 pr_err("error %d\n", rc);
11383 * Soft reset of sys- and osc-clockdomain
11385 * HACK: On windows, it writes a 0x07 here, instead of just 0x03.
11386 * As we didn't load the firmware here yet, we should do the same.
11387 * Btw, this is coherent with DRX-K, where we send reset codes
11388 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains.
11390 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
11392 pr_err("error %d\n", rc);
11395 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11397 pr_err("error %d\n", rc);
11402 /* TODO first make sure that everything keeps working before enabling this */
11403 /* PowerDownAnalogBlocks() */
11404 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
11406 pr_err("error %d\n", rc);
11410 rc = set_iqm_af(demod, false);
11412 pr_err("error %d\n", rc);
11415 rc = set_orx_nsu_aox(demod, false);
11417 pr_err("error %d\n", rc);
11421 rc = init_hi(demod);
11423 pr_err("error %d\n", rc);
11427 /* disable mpegoutput pins */
11428 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
11429 cfg_mpeg_output.enable_mpeg_output = false;
11431 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
11433 pr_err("error %d\n", rc);
11436 /* Stop AUD Inform SetAudio it will need to do all setting */
11437 rc = power_down_aud(demod);
11439 pr_err("error %d\n", rc);
11443 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
11445 pr_err("error %d\n", rc);
11449 /* Upload microcode */
11450 if (common_attr->microcode_file != NULL) {
11451 /* Dirty trick to use common ucode upload & verify,
11452 pretend device is already open */
11453 common_attr->is_opened = true;
11454 ucode_info.mc_file = common_attr->microcode_file;
11456 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
11457 pr_err("Should powerup before loading the firmware.");
11461 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
11463 pr_err("error %d while uploading the firmware\n", rc);
11466 if (common_attr->verify_microcode == true) {
11467 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
11469 pr_err("error %d while verifying the firmware\n",
11474 common_attr->is_opened = false;
11477 /* Run SCU for a little while to initialize microcode version numbers */
11478 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11480 pr_err("error %d\n", rc);
11484 /* Initialize scan timeout */
11485 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
11486 common_attr->scan_desired_lock = DRX_LOCKED;
11488 drxj_reset_mode(ext_attr);
11489 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11491 rc = smart_ant_init(demod);
11493 pr_err("error %d\n", rc);
11497 /* Stamp driver version number in SCU data RAM in BCD code
11498 Done to enable field application engineers to retrieve drxdriver version
11499 via I2C from SCU RAM
11501 driver_version = (VERSION_MAJOR / 100) % 10;
11502 driver_version <<= 4;
11503 driver_version += (VERSION_MAJOR / 10) % 10;
11504 driver_version <<= 4;
11505 driver_version += (VERSION_MAJOR % 10);
11506 driver_version <<= 4;
11507 driver_version += (VERSION_MINOR % 10);
11508 driver_version <<= 4;
11509 driver_version += (VERSION_PATCH / 1000) % 10;
11510 driver_version <<= 4;
11511 driver_version += (VERSION_PATCH / 100) % 10;
11512 driver_version <<= 4;
11513 driver_version += (VERSION_PATCH / 10) % 10;
11514 driver_version <<= 4;
11515 driver_version += (VERSION_PATCH % 10);
11516 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
11518 pr_err("error %d\n", rc);
11521 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
11523 pr_err("error %d\n", rc);
11527 rc = ctrl_set_oob(demod, NULL);
11529 pr_err("error %d\n", rc);
11533 /* refresh the audio data structure with default */
11534 ext_attr->aud_data = drxj_default_aud_data_g;
11536 demod->my_common_attr->is_opened = true;
11537 drxj_set_lna_state(demod, false);
11540 common_attr->is_opened = false;
11544 /*============================================================================*/
11547 * \brief Close the demod instance, power down the device
11548 * \return Status_t Return status.
11551 static int drxj_close(struct drx_demod_instance *demod)
11553 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11555 enum drx_power_mode power_mode = DRX_POWER_UP;
11557 if ((demod->my_common_attr == NULL) ||
11558 (demod->my_ext_attr == NULL) ||
11559 (demod->my_i2c_dev_addr == NULL) ||
11560 (!demod->my_common_attr->is_opened)) {
11565 rc = ctrl_power_mode(demod, &power_mode);
11567 pr_err("error %d\n", rc);
11571 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11573 pr_err("error %d\n", rc);
11576 power_mode = DRX_POWER_DOWN;
11577 rc = ctrl_power_mode(demod, &power_mode);
11579 pr_err("error %d\n", rc);
11583 DRX_ATTR_ISOPENED(demod) = false;
11587 DRX_ATTR_ISOPENED(demod) = false;
11593 * Microcode related functions
11597 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
11598 * @block_data: Pointer to microcode data.
11599 * @nr_words: Size of microcode block (number of 16 bits words).
11601 * returns The computed CRC residue.
11603 static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words)
11610 while (i < nr_words) {
11611 crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data));
11612 for (j = 0; j < 16; j++) {
11615 crc_word ^= 0x80050000UL;
11616 carry = crc_word & 0x80000000UL;
11619 block_data += (sizeof(u16));
11621 return (u16)(crc_word >> 16);
11625 * drx_check_firmware - checks if the loaded firmware is valid
11627 * @demod: demod structure
11628 * @mc_data: pointer to the start of the firmware
11629 * @size: firmware size
11631 static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data,
11634 struct drxu_code_block_hdr block_hdr;
11636 unsigned count = 2 * sizeof(u16);
11637 u32 mc_dev_type, mc_version, mc_base_version;
11638 u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16)));
11641 * Scan microcode blocks first for version info
11642 * and firmware check
11645 /* Clear version block */
11646 DRX_ATTR_MCRECORD(demod).aux_type = 0;
11647 DRX_ATTR_MCRECORD(demod).mc_dev_type = 0;
11648 DRX_ATTR_MCRECORD(demod).mc_version = 0;
11649 DRX_ATTR_MCRECORD(demod).mc_base_version = 0;
11651 for (i = 0; i < mc_nr_of_blks; i++) {
11652 if (count + 3 * sizeof(u16) + sizeof(u32) > size)
11655 /* Process block header */
11656 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
11657 count += sizeof(u32);
11658 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count));
11659 count += sizeof(u16);
11660 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count));
11661 count += sizeof(u16);
11662 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count));
11663 count += sizeof(u16);
11665 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11666 count, block_hdr.addr, block_hdr.size, block_hdr.flags,
11669 if (block_hdr.flags & 0x8) {
11670 u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
11673 if (block_hdr.addr + sizeof(u16) > size)
11676 auxtype = be16_to_cpu(*(__be16 *)(auxblk));
11678 /* Aux block. Check type */
11679 if (DRX_ISMCVERTYPE(auxtype)) {
11680 if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
11683 auxblk += sizeof(u16);
11684 mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk));
11685 auxblk += sizeof(u32);
11686 mc_version = be32_to_cpu(*(__be32 *)(auxblk));
11687 auxblk += sizeof(u32);
11688 mc_base_version = be32_to_cpu(*(__be32 *)(auxblk));
11690 DRX_ATTR_MCRECORD(demod).aux_type = auxtype;
11691 DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type;
11692 DRX_ATTR_MCRECORD(demod).mc_version = mc_version;
11693 DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version;
11695 pr_info("Firmware dev %x, ver %x, base ver %x\n",
11696 mc_dev_type, mc_version, mc_base_version);
11699 } else if (count + block_hdr.size * sizeof(u16) > size)
11702 count += block_hdr.size * sizeof(u16);
11706 pr_err("Firmware is truncated at pos %u/%u\n", count, size);
11711 * drx_ctrl_u_code - Handle microcode upload or verify.
11712 * @dev_addr: Address of device.
11713 * @mc_info: Pointer to information about microcode data.
11714 * @action: Either UCODE_UPLOAD or UCODE_VERIFY
11716 * This function returns:
11718 * - In case of UCODE_UPLOAD: code is successfully uploaded.
11719 * - In case of UCODE_VERIFY: image on device is equal to
11720 * image provided to this control function.
11722 * - In case of UCODE_UPLOAD: I2C error.
11723 * - In case of UCODE_VERIFY: I2C error or image on device
11724 * is not equal to image provided to this control function.
11726 * - Invalid arguments.
11727 * - Provided image is corrupt
11729 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11730 struct drxu_code_info *mc_info,
11731 enum drxu_code_action action)
11733 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11736 u16 mc_nr_of_blks = 0;
11737 u16 mc_magic_word = 0;
11738 const u8 *mc_data_init = NULL;
11739 u8 *mc_data = NULL;
11743 /* Check arguments */
11744 if (!mc_info || !mc_info->mc_file)
11747 mc_file = mc_info->mc_file;
11749 if (!demod->firmware) {
11750 const struct firmware *fw = NULL;
11752 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
11754 pr_err("Couldn't read firmware %s\n", mc_file);
11757 demod->firmware = fw;
11759 if (demod->firmware->size < 2 * sizeof(u16)) {
11761 pr_err("Firmware is too short!\n");
11765 pr_info("Firmware %s, size %zu\n",
11766 mc_file, demod->firmware->size);
11769 mc_data_init = demod->firmware->data;
11770 size = demod->firmware->size;
11772 mc_data = (void *)mc_data_init;
11774 mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data));
11775 mc_data += sizeof(u16);
11776 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data));
11777 mc_data += sizeof(u16);
11779 if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
11781 pr_err("Firmware magic word doesn't match\n");
11785 if (action == UCODE_UPLOAD) {
11786 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
11789 pr_info("Uploading firmware %s\n", mc_file);
11791 pr_info("Verifying if firmware upload was ok.\n");
11794 /* Process microcode blocks */
11795 for (i = 0; i < mc_nr_of_blks; i++) {
11796 struct drxu_code_block_hdr block_hdr;
11797 u16 mc_block_nr_bytes = 0;
11799 /* Process block header */
11800 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
11801 mc_data += sizeof(u32);
11802 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data));
11803 mc_data += sizeof(u16);
11804 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data));
11805 mc_data += sizeof(u16);
11806 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data));
11807 mc_data += sizeof(u16);
11809 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11810 (unsigned)(mc_data - mc_data_init), block_hdr.addr,
11811 block_hdr.size, block_hdr.flags, block_hdr.CRC);
11813 /* Check block header on:
11814 - data larger than 64Kb
11815 - if CRC enabled check CRC
11817 if ((block_hdr.size > 0x7FFF) ||
11818 (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
11819 (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size)))
11823 pr_err("firmware CRC is wrong\n");
11827 if (!block_hdr.size)
11830 mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
11832 /* Perform the desired action */
11834 case UCODE_UPLOAD: /* Upload microcode */
11835 if (drxdap_fasi_write_block(dev_addr,
11838 mc_data, 0x0000)) {
11840 pr_err("error writing firmware at pos %u\n",
11841 (unsigned)(mc_data - mc_data_init));
11845 case UCODE_VERIFY: { /* Verify uploaded microcode */
11847 u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE];
11848 u32 bytes_to_comp = 0;
11849 u32 bytes_left = mc_block_nr_bytes;
11850 u32 curr_addr = block_hdr.addr;
11851 u8 *curr_ptr = mc_data;
11853 while (bytes_left != 0) {
11854 if (bytes_left > DRX_UCODE_MAX_BUF_SIZE)
11855 bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE;
11857 bytes_to_comp = bytes_left;
11859 if (drxdap_fasi_read_block(dev_addr,
11861 (u16)bytes_to_comp,
11862 (u8 *)mc_data_buffer,
11864 pr_err("error reading firmware at pos %u\n",
11865 (unsigned)(mc_data - mc_data_init));
11869 result = memcmp(curr_ptr, mc_data_buffer,
11873 pr_err("error verifying firmware at pos %u\n",
11874 (unsigned)(mc_data - mc_data_init));
11878 curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2));
11879 curr_ptr =&(curr_ptr[bytes_to_comp]);
11880 bytes_left -=((u32) bytes_to_comp);
11889 mc_data += mc_block_nr_bytes;
11895 release_firmware(demod->firmware);
11896 demod->firmware = NULL;
11901 /* caller is expected to check if lna is supported before enabling */
11902 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)
11904 struct drxuio_cfg uio_cfg;
11905 struct drxuio_data uio_data;
11908 uio_cfg.uio = DRX_UIO1;
11909 uio_cfg.mode = DRX_UIO_MODE_READWRITE;
11910 /* Configure user-I/O #3: enable read/write */
11911 result = ctrl_set_uio_cfg(demod, &uio_cfg);
11913 pr_err("Failed to setup LNA GPIO!\n");
11917 uio_data.uio = DRX_UIO1;
11918 uio_data.value = state;
11919 result = ctrl_uio_write(demod, &uio_data);
11921 pr_err("Failed to %sable LNA!\n",
11922 state ? "en" : "dis");
11929 * The Linux DVB Driver for Micronas DRX39xx family (drx3933j)
11931 * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
11934 static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
11936 struct drx39xxj_state *state = fe->demodulator_priv;
11937 struct drx_demod_instance *demod = state->demod;
11939 enum drx_power_mode power_mode;
11942 power_mode = DRX_POWER_UP;
11944 power_mode = DRX_POWER_DOWN;
11946 result = ctrl_power_mode(demod, &power_mode);
11948 pr_err("Power state change failed\n");
11955 static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status)
11957 struct drx39xxj_state *state = fe->demodulator_priv;
11958 struct drx_demod_instance *demod = state->demod;
11960 enum drx_lock_status lock_status;
11964 result = ctrl_lock_status(demod, &lock_status);
11966 pr_err("drx39xxj: could not get lock status!\n");
11970 switch (lock_status) {
11971 case DRX_NEVER_LOCK:
11973 pr_err("drx says NEVER_LOCK\n");
11975 case DRX_NOT_LOCKED:
11978 case DRX_LOCK_STATE_1:
11979 case DRX_LOCK_STATE_2:
11980 case DRX_LOCK_STATE_3:
11981 case DRX_LOCK_STATE_4:
11982 case DRX_LOCK_STATE_5:
11983 case DRX_LOCK_STATE_6:
11984 case DRX_LOCK_STATE_7:
11985 case DRX_LOCK_STATE_8:
11986 case DRX_LOCK_STATE_9:
11987 *status = FE_HAS_SIGNAL
11988 | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
11991 *status = FE_HAS_SIGNAL
11993 | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
11996 pr_err("Lock state unknown %d\n", lock_status);
11998 ctrl_sig_quality(demod, lock_status);
12003 static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
12005 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12007 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12012 if (!p->pre_bit_count.stat[0].uvalue) {
12013 if (!p->pre_bit_error.stat[0].uvalue)
12018 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
12019 p->pre_bit_count.stat[0].uvalue);
12024 static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
12027 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12029 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12034 *strength = p->strength.stat[0].uvalue;
12038 static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
12040 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12043 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12048 tmp64 = p->cnr.stat[0].svalue;
12054 static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb)
12056 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12058 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12063 *ucb = p->block_error.stat[0].uvalue;
12067 static int drx39xxj_set_frontend(struct dvb_frontend *fe)
12072 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12073 struct drx39xxj_state *state = fe->demodulator_priv;
12074 struct drx_demod_instance *demod = state->demod;
12075 enum drx_standard standard = DRX_STANDARD_8VSB;
12076 struct drx_channel channel;
12078 static const struct drx_channel def_channel = {
12080 /* bandwidth */ DRX_BANDWIDTH_6MHZ,
12081 /* mirror */ DRX_MIRROR_NO,
12082 /* constellation */ DRX_CONSTELLATION_AUTO,
12083 /* hierarchy */ DRX_HIERARCHY_UNKNOWN,
12084 /* priority */ DRX_PRIORITY_UNKNOWN,
12085 /* coderate */ DRX_CODERATE_UNKNOWN,
12086 /* guard */ DRX_GUARD_UNKNOWN,
12087 /* fftmode */ DRX_FFTMODE_UNKNOWN,
12088 /* classification */ DRX_CLASSIFICATION_AUTO,
12089 /* symbolrate */ 5057000,
12090 /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
12091 /* ldpc */ DRX_LDPC_UNKNOWN,
12092 /* carrier */ DRX_CARRIER_UNKNOWN,
12093 /* frame mode */ DRX_FRAMEMODE_UNKNOWN
12095 u32 constellation = DRX_CONSTELLATION_AUTO;
12097 /* Bring the demod out of sleep */
12098 drx39xxj_set_powerstate(fe, 1);
12100 if (fe->ops.tuner_ops.set_params) {
12103 if (fe->ops.i2c_gate_ctrl)
12104 fe->ops.i2c_gate_ctrl(fe, 1);
12106 /* Set tuner to desired frequency and standard */
12107 fe->ops.tuner_ops.set_params(fe);
12109 /* Use the tuner's IF */
12110 if (fe->ops.tuner_ops.get_if_frequency) {
12111 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
12112 demod->my_common_attr->intermediate_freq = int_freq / 1000;
12115 if (fe->ops.i2c_gate_ctrl)
12116 fe->ops.i2c_gate_ctrl(fe, 0);
12119 switch (p->delivery_system) {
12121 standard = DRX_STANDARD_8VSB;
12123 case SYS_DVBC_ANNEX_B:
12124 standard = DRX_STANDARD_ITU_B;
12126 switch (p->modulation) {
12128 constellation = DRX_CONSTELLATION_QAM64;
12131 constellation = DRX_CONSTELLATION_QAM256;
12134 constellation = DRX_CONSTELLATION_AUTO;
12141 /* Set the standard (will be powered up if necessary */
12142 result = ctrl_set_standard(demod, &standard);
12144 pr_err("Failed to set standard! result=%02x\n",
12149 /* set channel parameters */
12150 channel = def_channel;
12151 channel.frequency = p->frequency / 1000;
12152 channel.bandwidth = DRX_BANDWIDTH_6MHZ;
12153 channel.constellation = constellation;
12155 /* program channel */
12156 result = ctrl_set_channel(demod, &channel);
12158 pr_err("Failed to set channel!\n");
12161 /* Just for giggles, let's shut off the LNA again.... */
12162 drxj_set_lna_state(demod, false);
12164 /* After set_frontend, except for strength, stats aren't available */
12165 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12170 static int drx39xxj_sleep(struct dvb_frontend *fe)
12172 /* power-down the demodulator */
12173 return drx39xxj_set_powerstate(fe, 0);
12176 static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
12178 struct drx39xxj_state *state = fe->demodulator_priv;
12179 struct drx_demod_instance *demod = state->demod;
12180 bool i2c_gate_state;
12184 pr_debug("i2c gate call: enable=%d state=%d\n", enable,
12185 state->i2c_gate_open);
12189 i2c_gate_state = true;
12191 i2c_gate_state = false;
12193 if (state->i2c_gate_open == enable) {
12194 /* We're already in the desired state */
12198 result = ctrl_i2c_bridge(demod, &i2c_gate_state);
12200 pr_err("drx39xxj: could not open i2c gate [%d]\n",
12204 state->i2c_gate_open = enable;
12209 static int drx39xxj_init(struct dvb_frontend *fe)
12211 struct drx39xxj_state *state = fe->demodulator_priv;
12212 struct drx_demod_instance *demod = state->demod;
12215 if (fe->exit == DVB_FE_DEVICE_RESUME) {
12216 /* so drxj_open() does what it needs to do */
12217 demod->my_common_attr->is_opened = false;
12218 rc = drxj_open(demod);
12220 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
12222 drx39xxj_set_powerstate(fe, 1);
12227 static int drx39xxj_set_lna(struct dvb_frontend *fe)
12229 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
12230 struct drx39xxj_state *state = fe->demodulator_priv;
12231 struct drx_demod_instance *demod = state->demod;
12232 struct drxj_data *ext_attr = demod->my_ext_attr;
12235 if (!ext_attr->has_lna) {
12236 pr_err("LNA is not supported on this device!\n");
12242 return drxj_set_lna_state(demod, c->lna);
12245 static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
12246 struct dvb_frontend_tune_settings *tune)
12248 tune->min_delay_ms = 1000;
12252 static void drx39xxj_release(struct dvb_frontend *fe)
12254 struct drx39xxj_state *state = fe->demodulator_priv;
12255 struct drx_demod_instance *demod = state->demod;
12257 /* if device is removed don't access it */
12258 if (fe->exit != DVB_FE_DEVICE_REMOVED)
12261 kfree(demod->my_ext_attr);
12262 kfree(demod->my_common_attr);
12263 kfree(demod->my_i2c_dev_addr);
12264 release_firmware(demod->firmware);
12269 static const struct dvb_frontend_ops drx39xxj_ops;
12271 struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
12273 struct drx39xxj_state *state = NULL;
12274 struct i2c_device_addr *demod_addr = NULL;
12275 struct drx_common_attr *demod_comm_attr = NULL;
12276 struct drxj_data *demod_ext_attr = NULL;
12277 struct drx_demod_instance *demod = NULL;
12278 struct dtv_frontend_properties *p;
12281 /* allocate memory for the internal state */
12282 state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
12286 demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL);
12290 demod_addr = kmemdup(&drxj_default_addr_g,
12291 sizeof(struct i2c_device_addr), GFP_KERNEL);
12292 if (demod_addr == NULL)
12295 demod_comm_attr = kmemdup(&drxj_default_comm_attr_g,
12296 sizeof(struct drx_common_attr), GFP_KERNEL);
12297 if (demod_comm_attr == NULL)
12300 demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data),
12302 if (demod_ext_attr == NULL)
12305 /* setup the state */
12307 state->demod = demod;
12309 /* setup the demod data */
12310 memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance));
12312 demod->my_i2c_dev_addr = demod_addr;
12313 demod->my_common_attr = demod_comm_attr;
12314 demod->my_i2c_dev_addr->user_data = state;
12315 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
12316 demod->my_common_attr->verify_microcode = true;
12317 demod->my_common_attr->intermediate_freq = 5000;
12318 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
12319 demod->my_ext_attr = demod_ext_attr;
12320 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
12323 result = drxj_open(demod);
12325 pr_err("DRX open failed! Aborting\n");
12329 /* create dvb_frontend */
12330 memcpy(&state->frontend.ops, &drx39xxj_ops,
12331 sizeof(struct dvb_frontend_ops));
12333 state->frontend.demodulator_priv = state;
12335 /* Initialize stats - needed for DVBv5 stats to work */
12336 p = &state->frontend.dtv_property_cache;
12337 p->strength.len = 1;
12338 p->pre_bit_count.len = 1;
12339 p->pre_bit_error.len = 1;
12340 p->post_bit_count.len = 1;
12341 p->post_bit_error.len = 1;
12342 p->block_count.len = 1;
12343 p->block_error.len = 1;
12346 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12347 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12348 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12349 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12350 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12351 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12352 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12353 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12355 return &state->frontend;
12358 kfree(demod_ext_attr);
12359 kfree(demod_comm_attr);
12366 EXPORT_SYMBOL(drx39xxj_attach);
12368 static const struct dvb_frontend_ops drx39xxj_ops = {
12369 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
12371 .name = "Micronas DRX39xxj family Frontend",
12372 .frequency_stepsize = 62500,
12373 .frequency_min = 51000000,
12374 .frequency_max = 858000000,
12375 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
12378 .init = drx39xxj_init,
12379 .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
12380 .sleep = drx39xxj_sleep,
12381 .set_frontend = drx39xxj_set_frontend,
12382 .get_tune_settings = drx39xxj_get_tune_settings,
12383 .read_status = drx39xxj_read_status,
12384 .read_ber = drx39xxj_read_ber,
12385 .read_signal_strength = drx39xxj_read_signal_strength,
12386 .read_snr = drx39xxj_read_snr,
12387 .read_ucblocks = drx39xxj_read_ucblocks,
12388 .release = drx39xxj_release,
12389 .set_lna = drx39xxj_set_lna,
12392 MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
12393 MODULE_AUTHOR("Devin Heitmueller");
12394 MODULE_LICENSE("GPL");
12395 MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE);