2 * drxk_hard: DRX-K DVB-C/T demodulator driver
4 * Copyright (C) 2010-2011 Digital Devices GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <linux/hardirq.h>
32 #include <asm/div64.h>
34 #include "dvb_frontend.h"
36 #include "drxk_hard.h"
38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39 static int PowerDownQAM(struct drxk_state *state);
40 static int SetDVBTStandard(struct drxk_state *state,
41 enum OperationMode oMode);
42 static int SetQAMStandard(struct drxk_state *state,
43 enum OperationMode oMode);
44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
46 static int SetDVBTStandard(struct drxk_state *state,
47 enum OperationMode oMode);
48 static int DVBTStart(struct drxk_state *state);
49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53 static int SwitchAntennaToQAM(struct drxk_state *state);
54 static int SwitchAntennaToDVBT(struct drxk_state *state);
56 static bool IsDVBT(struct drxk_state *state)
58 return state->m_OperationMode == OM_DVBT;
61 static bool IsQAM(struct drxk_state *state)
63 return state->m_OperationMode == OM_QAM_ITU_A ||
64 state->m_OperationMode == OM_QAM_ITU_B ||
65 state->m_OperationMode == OM_QAM_ITU_C;
70 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
71 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
73 #define DEFAULT_MER_83 165
74 #define DEFAULT_MER_93 250
76 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
77 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
80 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
81 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
84 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
85 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
87 #ifndef DRXK_KI_RAGC_ATV
88 #define DRXK_KI_RAGC_ATV 4
90 #ifndef DRXK_KI_IAGC_ATV
91 #define DRXK_KI_IAGC_ATV 6
93 #ifndef DRXK_KI_DAGC_ATV
94 #define DRXK_KI_DAGC_ATV 7
97 #ifndef DRXK_KI_RAGC_QAM
98 #define DRXK_KI_RAGC_QAM 3
100 #ifndef DRXK_KI_IAGC_QAM
101 #define DRXK_KI_IAGC_QAM 4
103 #ifndef DRXK_KI_DAGC_QAM
104 #define DRXK_KI_DAGC_QAM 7
106 #ifndef DRXK_KI_RAGC_DVBT
107 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
109 #ifndef DRXK_KI_IAGC_DVBT
110 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
112 #ifndef DRXK_KI_DAGC_DVBT
113 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
116 #ifndef DRXK_AGC_DAC_OFFSET
117 #define DRXK_AGC_DAC_OFFSET (0x800)
120 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
121 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
124 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
125 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
128 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
129 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
132 #ifndef DRXK_QAM_SYMBOLRATE_MAX
133 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
136 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
137 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
138 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
139 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
140 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
141 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
142 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
143 #define DRXK_BL_ROM_OFFSET_UCODE 0
145 #define DRXK_BLC_TIMEOUT 100
147 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
148 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
150 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
152 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
153 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
156 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
157 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
158 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
159 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
160 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
162 static unsigned int debug;
163 module_param(debug, int, 0644);
164 MODULE_PARM_DESC(debug, "enable debug messages");
166 #define dprintk(level, fmt, arg...) do { \
167 if (debug >= level) \
168 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
172 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
176 tmp64 = (u64) a * (u64) b;
182 static inline u32 Frac28a(u32 a, u32 c)
188 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
189 Q1 = a / c; /* integer part, only the 4 least significant bits
190 will be visible in the result */
192 /* division using radix 16, 7 nibbles in the result */
193 for (i = 0; i < 7; i++) {
194 Q1 = (Q1 << 4) | (R0 / c);
204 static u32 Log10Times100(u32 x)
206 static const u8 scale = 15;
207 static const u8 indexWidth = 5;
214 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
215 0 <= n < ((1<<INDEXWIDTH)+1)
218 static const u32 log2lut[] = {
220 290941, /* 290941.300628 */
221 573196, /* 573196.476418 */
222 847269, /* 847269.179851 */
223 1113620, /* 1113620.489452 */
224 1372674, /* 1372673.576986 */
225 1624818, /* 1624817.752104 */
226 1870412, /* 1870411.981536 */
227 2109788, /* 2109787.962654 */
228 2343253, /* 2343252.817465 */
229 2571091, /* 2571091.461923 */
230 2793569, /* 2793568.696416 */
231 3010931, /* 3010931.055901 */
232 3223408, /* 3223408.452106 */
233 3431216, /* 3431215.635215 */
234 3634553, /* 3634553.498355 */
235 3833610, /* 3833610.244726 */
236 4028562, /* 4028562.434393 */
237 4219576, /* 4219575.925308 */
238 4406807, /* 4406806.721144 */
239 4590402, /* 4590401.736809 */
240 4770499, /* 4770499.491025 */
241 4947231, /* 4947230.734179 */
242 5120719, /* 5120719.018555 */
243 5291081, /* 5291081.217197 */
244 5458428, /* 5458427.996830 */
245 5622864, /* 5622864.249668 */
246 5784489, /* 5784489.488298 */
247 5943398, /* 5943398.207380 */
248 6099680, /* 6099680.215452 */
249 6253421, /* 6253420.939751 */
250 6404702, /* 6404701.706649 */
251 6553600, /* 6553600.000000 */
258 /* Scale x (normalize) */
259 /* computing y in log(x/y) = log(x) - log(y) */
260 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
261 for (k = scale; k > 0; k--) {
262 if (x & (((u32) 1) << scale))
267 for (k = scale; k < 31; k++) {
268 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
274 Now x has binary point between bit[scale] and bit[scale-1]
275 and 1.0 <= x < 2.0 */
277 /* correction for divison: log(x) = log(x/y)+log(y) */
278 y = k * ((((u32) 1) << scale) * 200);
280 /* remove integer part */
281 x &= ((((u32) 1) << scale) - 1);
283 i = (u8) (x >> (scale - indexWidth));
284 /* compute delta (x - a) */
285 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
286 /* compute log, multiplication (d* (..)) must be within range ! */
288 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
289 /* Conver to log10() */
290 y /= 108853; /* (log2(10) << scale) */
298 /****************************************************************************/
299 /* I2C **********************************************************************/
300 /****************************************************************************/
302 static int drxk_i2c_lock(struct drxk_state *state)
304 i2c_lock_adapter(state->i2c);
305 state->drxk_i2c_exclusive_lock = true;
310 static void drxk_i2c_unlock(struct drxk_state *state)
312 if (!state->drxk_i2c_exclusive_lock)
315 i2c_unlock_adapter(state->i2c);
316 state->drxk_i2c_exclusive_lock = false;
319 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
322 if (state->drxk_i2c_exclusive_lock)
323 return __i2c_transfer(state->i2c, msgs, len);
325 return i2c_transfer(state->i2c, msgs, len);
328 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
330 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
331 .buf = val, .len = 1}
334 return drxk_i2c_transfer(state, msgs, 1);
337 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
340 struct i2c_msg msg = {
341 .addr = adr, .flags = 0, .buf = data, .len = len };
346 for (i = 0; i < len; i++)
347 printk(KERN_CONT " %02x", data[i]);
348 printk(KERN_CONT "\n");
350 status = drxk_i2c_transfer(state, &msg, 1);
351 if (status >= 0 && status != 1)
355 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
360 static int i2c_read(struct drxk_state *state,
361 u8 adr, u8 *msg, int len, u8 *answ, int alen)
364 struct i2c_msg msgs[2] = {
365 {.addr = adr, .flags = 0,
366 .buf = msg, .len = len},
367 {.addr = adr, .flags = I2C_M_RD,
368 .buf = answ, .len = alen}
371 status = drxk_i2c_transfer(state, msgs, 2);
374 printk(KERN_CONT ": ERROR!\n");
378 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
383 dprintk(2, ": read from");
384 for (i = 0; i < len; i++)
385 printk(KERN_CONT " %02x", msg[i]);
386 printk(KERN_CONT ", value = ");
387 for (i = 0; i < alen; i++)
388 printk(KERN_CONT " %02x", answ[i]);
389 printk(KERN_CONT "\n");
394 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
397 u8 adr = state->demod_address, mm1[4], mm2[2], len;
399 if (state->single_master)
402 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
403 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
404 mm1[1] = ((reg >> 16) & 0xFF);
405 mm1[2] = ((reg >> 24) & 0xFF) | flags;
406 mm1[3] = ((reg >> 7) & 0xFF);
409 mm1[0] = ((reg << 1) & 0xFF);
410 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
413 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
414 status = i2c_read(state, adr, mm1, len, mm2, 2);
418 *data = mm2[0] | (mm2[1] << 8);
423 static int read16(struct drxk_state *state, u32 reg, u16 *data)
425 return read16_flags(state, reg, data, 0);
428 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
431 u8 adr = state->demod_address, mm1[4], mm2[4], len;
433 if (state->single_master)
436 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
437 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
438 mm1[1] = ((reg >> 16) & 0xFF);
439 mm1[2] = ((reg >> 24) & 0xFF) | flags;
440 mm1[3] = ((reg >> 7) & 0xFF);
443 mm1[0] = ((reg << 1) & 0xFF);
444 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
447 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
448 status = i2c_read(state, adr, mm1, len, mm2, 4);
452 *data = mm2[0] | (mm2[1] << 8) |
453 (mm2[2] << 16) | (mm2[3] << 24);
458 static int read32(struct drxk_state *state, u32 reg, u32 *data)
460 return read32_flags(state, reg, data, 0);
463 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
465 u8 adr = state->demod_address, mm[6], len;
467 if (state->single_master)
469 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
470 mm[0] = (((reg << 1) & 0xFF) | 0x01);
471 mm[1] = ((reg >> 16) & 0xFF);
472 mm[2] = ((reg >> 24) & 0xFF) | flags;
473 mm[3] = ((reg >> 7) & 0xFF);
476 mm[0] = ((reg << 1) & 0xFF);
477 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
480 mm[len] = data & 0xff;
481 mm[len + 1] = (data >> 8) & 0xff;
483 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
484 return i2c_write(state, adr, mm, len + 2);
487 static int write16(struct drxk_state *state, u32 reg, u16 data)
489 return write16_flags(state, reg, data, 0);
492 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
494 u8 adr = state->demod_address, mm[8], len;
496 if (state->single_master)
498 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
499 mm[0] = (((reg << 1) & 0xFF) | 0x01);
500 mm[1] = ((reg >> 16) & 0xFF);
501 mm[2] = ((reg >> 24) & 0xFF) | flags;
502 mm[3] = ((reg >> 7) & 0xFF);
505 mm[0] = ((reg << 1) & 0xFF);
506 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
509 mm[len] = data & 0xff;
510 mm[len + 1] = (data >> 8) & 0xff;
511 mm[len + 2] = (data >> 16) & 0xff;
512 mm[len + 3] = (data >> 24) & 0xff;
513 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
515 return i2c_write(state, adr, mm, len + 4);
518 static int write32(struct drxk_state *state, u32 reg, u32 data)
520 return write32_flags(state, reg, data, 0);
523 static int write_block(struct drxk_state *state, u32 Address,
524 const int BlockSize, const u8 pBlock[])
526 int status = 0, BlkSize = BlockSize;
529 if (state->single_master)
532 while (BlkSize > 0) {
533 int Chunk = BlkSize > state->m_ChunkSize ?
534 state->m_ChunkSize : BlkSize;
535 u8 *AdrBuf = &state->Chunk[0];
538 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
539 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
540 AdrBuf[1] = ((Address >> 16) & 0xFF);
541 AdrBuf[2] = ((Address >> 24) & 0xFF);
542 AdrBuf[3] = ((Address >> 7) & 0xFF);
545 if (Chunk == state->m_ChunkSize)
548 AdrBuf[0] = ((Address << 1) & 0xFF);
549 AdrBuf[1] = (((Address >> 16) & 0x0F) |
550 ((Address >> 18) & 0xF0));
553 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
554 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
558 for (i = 0; i < Chunk; i++)
559 printk(KERN_CONT " %02x", pBlock[i]);
560 printk(KERN_CONT "\n");
562 status = i2c_write(state, state->demod_address,
563 &state->Chunk[0], Chunk + AdrLength);
565 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
570 Address += (Chunk >> 1);
576 #ifndef DRXK_MAX_RETRIES_POWERUP
577 #define DRXK_MAX_RETRIES_POWERUP 20
580 static int PowerUpDevice(struct drxk_state *state)
588 status = i2c_read1(state, state->demod_address, &data);
592 status = i2c_write(state, state->demod_address,
598 status = i2c_read1(state, state->demod_address,
600 } while (status < 0 &&
601 (retryCount < DRXK_MAX_RETRIES_POWERUP));
602 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
606 /* Make sure all clk domains are active */
607 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
610 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
613 /* Enable pll lock tests */
614 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
618 state->m_currentPowerMode = DRX_POWER_UP;
622 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
628 static int init_state(struct drxk_state *state)
631 * FIXME: most (all?) of the values bellow should be moved into
632 * struct drxk_config, as they are probably board-specific
634 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
635 u32 ulVSBIfAgcOutputLevel = 0;
636 u32 ulVSBIfAgcMinLevel = 0;
637 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
638 u32 ulVSBIfAgcSpeed = 3;
640 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
641 u32 ulVSBRfAgcOutputLevel = 0;
642 u32 ulVSBRfAgcMinLevel = 0;
643 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
644 u32 ulVSBRfAgcSpeed = 3;
645 u32 ulVSBRfAgcTop = 9500;
646 u32 ulVSBRfAgcCutOffCurrent = 4000;
648 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
649 u32 ulATVIfAgcOutputLevel = 0;
650 u32 ulATVIfAgcMinLevel = 0;
651 u32 ulATVIfAgcMaxLevel = 0;
652 u32 ulATVIfAgcSpeed = 3;
654 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
655 u32 ulATVRfAgcOutputLevel = 0;
656 u32 ulATVRfAgcMinLevel = 0;
657 u32 ulATVRfAgcMaxLevel = 0;
658 u32 ulATVRfAgcTop = 9500;
659 u32 ulATVRfAgcCutOffCurrent = 4000;
660 u32 ulATVRfAgcSpeed = 3;
662 u32 ulQual83 = DEFAULT_MER_83;
663 u32 ulQual93 = DEFAULT_MER_93;
665 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
666 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
668 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
669 /* io_pad_cfg_mode output mode is drive always */
670 /* io_pad_cfg_drive is set to power 2 (23 mA) */
671 u32 ulGPIOCfg = 0x0113;
672 u32 ulInvertTSClock = 0;
673 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
674 u32 ulDVBTBitrate = 50000000;
675 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
677 u32 ulInsertRSByte = 0;
684 state->m_hasLNA = false;
685 state->m_hasDVBT = false;
686 state->m_hasDVBC = false;
687 state->m_hasATV = false;
688 state->m_hasOOB = false;
689 state->m_hasAudio = false;
691 if (!state->m_ChunkSize)
692 state->m_ChunkSize = 124;
694 state->m_oscClockFreq = 0;
695 state->m_smartAntInverted = false;
696 state->m_bPDownOpenBridge = false;
698 /* real system clock frequency in kHz */
699 state->m_sysClockFreq = 151875;
700 /* Timing div, 250ns/Psys */
701 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
702 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
703 HI_I2C_DELAY) / 1000;
705 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
706 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
707 state->m_HICfgWakeUpKey = (state->demod_address << 1);
708 /* port/bridge/power down ctrl */
709 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
711 state->m_bPowerDown = (ulPowerDown != 0);
713 state->m_DRXK_A3_PATCH_CODE = false;
715 /* Init AGC and PGA parameters */
717 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
718 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
719 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
720 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
721 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
722 state->m_vsbPgaCfg = 140;
725 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
726 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
727 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
728 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
729 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
730 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
731 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
732 state->m_vsbPreSawCfg.reference = 0x07;
733 state->m_vsbPreSawCfg.usePreSaw = true;
735 state->m_Quality83percent = DEFAULT_MER_83;
736 state->m_Quality93percent = DEFAULT_MER_93;
737 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
738 state->m_Quality83percent = ulQual83;
739 state->m_Quality93percent = ulQual93;
743 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
744 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
745 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
746 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
747 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
750 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
751 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
752 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
753 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
754 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
755 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
756 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
757 state->m_atvPreSawCfg.reference = 0x04;
758 state->m_atvPreSawCfg.usePreSaw = true;
762 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
763 state->m_dvbtRfAgcCfg.outputLevel = 0;
764 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
765 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
766 state->m_dvbtRfAgcCfg.top = 0x2100;
767 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
768 state->m_dvbtRfAgcCfg.speed = 1;
772 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
773 state->m_dvbtIfAgcCfg.outputLevel = 0;
774 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
775 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
776 state->m_dvbtIfAgcCfg.top = 13424;
777 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
778 state->m_dvbtIfAgcCfg.speed = 3;
779 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
780 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
781 /* state->m_dvbtPgaCfg = 140; */
783 state->m_dvbtPreSawCfg.reference = 4;
784 state->m_dvbtPreSawCfg.usePreSaw = false;
787 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
788 state->m_qamRfAgcCfg.outputLevel = 0;
789 state->m_qamRfAgcCfg.minOutputLevel = 6023;
790 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
791 state->m_qamRfAgcCfg.top = 0x2380;
792 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
793 state->m_qamRfAgcCfg.speed = 3;
796 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
797 state->m_qamIfAgcCfg.outputLevel = 0;
798 state->m_qamIfAgcCfg.minOutputLevel = 0;
799 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
800 state->m_qamIfAgcCfg.top = 0x0511;
801 state->m_qamIfAgcCfg.cutOffCurrent = 0;
802 state->m_qamIfAgcCfg.speed = 3;
803 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
804 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
806 state->m_qamPgaCfg = 140;
807 state->m_qamPreSawCfg.reference = 4;
808 state->m_qamPreSawCfg.usePreSaw = false;
810 state->m_OperationMode = OM_NONE;
811 state->m_DrxkState = DRXK_UNINITIALIZED;
813 /* MPEG output configuration */
814 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
815 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
816 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
817 state->m_invertERR = false; /* If TRUE; invert ERR signal */
818 state->m_invertSTR = false; /* If TRUE; invert STR signals */
819 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
820 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
822 /* If TRUE; static MPEG clockrate will be used;
823 otherwise clockrate will adapt to the bitrate of the TS */
825 state->m_DVBTBitrate = ulDVBTBitrate;
826 state->m_DVBCBitrate = ulDVBCBitrate;
828 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
830 /* Maximum bitrate in b/s in case static clockrate is selected */
831 state->m_mpegTsStaticBitrate = 19392658;
832 state->m_disableTEIhandling = false;
835 state->m_insertRSByte = true;
837 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
838 if (ulMpegLockTimeOut < 10000)
839 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
840 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
841 if (ulDemodLockTimeOut < 10000)
842 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
845 state->m_Constellation = DRX_CONSTELLATION_AUTO;
846 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
847 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
848 state->m_fecRsPrescale = 1;
850 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
851 state->m_agcFastClipCtrlDelay = 0;
853 state->m_GPIOCfg = (ulGPIOCfg);
855 state->m_bPowerDown = false;
856 state->m_currentPowerMode = DRX_POWER_DOWN;
858 state->m_rfmirror = (ulRfMirror == 0);
859 state->m_IfAgcPol = false;
863 static int DRXX_Open(struct drxk_state *state)
871 /* stop lock indicator process */
872 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
875 /* Check device id */
876 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
879 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
882 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
885 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
888 status = write16(state, SIO_TOP_COMM_KEY__A, key);
891 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
895 static int GetDeviceCapabilities(struct drxk_state *state)
897 u16 sioPdrOhwCfg = 0;
898 u32 sioTopJtagidLo = 0;
900 const char *spin = "";
905 /* stop lock indicator process */
906 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
909 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
912 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
915 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
919 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
921 /* ignore (bypass ?) */
925 state->m_oscClockFreq = 27000;
929 state->m_oscClockFreq = 20250;
933 state->m_oscClockFreq = 20250;
936 printk(KERN_ERR "drxk: Clock Frequency is unknown\n");
940 Determine device capabilities
943 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
947 printk(KERN_INFO "drxk: status = 0x%08x\n", sioTopJtagidLo);
950 switch ((sioTopJtagidLo >> 29) & 0xF) {
952 state->m_deviceSpin = DRXK_SPIN_A1;
956 state->m_deviceSpin = DRXK_SPIN_A2;
960 state->m_deviceSpin = DRXK_SPIN_A3;
964 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
966 printk(KERN_ERR "drxk: Spin %d unknown\n",
967 (sioTopJtagidLo >> 29) & 0xF);
970 switch ((sioTopJtagidLo >> 12) & 0xFF) {
972 /* typeId = DRX3913K_TYPE_ID */
973 state->m_hasLNA = false;
974 state->m_hasOOB = false;
975 state->m_hasATV = false;
976 state->m_hasAudio = false;
977 state->m_hasDVBT = true;
978 state->m_hasDVBC = true;
979 state->m_hasSAWSW = true;
980 state->m_hasGPIO2 = false;
981 state->m_hasGPIO1 = false;
982 state->m_hasIRQN = false;
985 /* typeId = DRX3915K_TYPE_ID */
986 state->m_hasLNA = false;
987 state->m_hasOOB = false;
988 state->m_hasATV = true;
989 state->m_hasAudio = false;
990 state->m_hasDVBT = true;
991 state->m_hasDVBC = false;
992 state->m_hasSAWSW = true;
993 state->m_hasGPIO2 = true;
994 state->m_hasGPIO1 = true;
995 state->m_hasIRQN = false;
998 /* typeId = DRX3916K_TYPE_ID */
999 state->m_hasLNA = false;
1000 state->m_hasOOB = false;
1001 state->m_hasATV = true;
1002 state->m_hasAudio = false;
1003 state->m_hasDVBT = true;
1004 state->m_hasDVBC = false;
1005 state->m_hasSAWSW = true;
1006 state->m_hasGPIO2 = true;
1007 state->m_hasGPIO1 = true;
1008 state->m_hasIRQN = false;
1011 /* typeId = DRX3918K_TYPE_ID */
1012 state->m_hasLNA = false;
1013 state->m_hasOOB = false;
1014 state->m_hasATV = true;
1015 state->m_hasAudio = true;
1016 state->m_hasDVBT = true;
1017 state->m_hasDVBC = false;
1018 state->m_hasSAWSW = true;
1019 state->m_hasGPIO2 = true;
1020 state->m_hasGPIO1 = true;
1021 state->m_hasIRQN = false;
1024 /* typeId = DRX3921K_TYPE_ID */
1025 state->m_hasLNA = false;
1026 state->m_hasOOB = false;
1027 state->m_hasATV = true;
1028 state->m_hasAudio = true;
1029 state->m_hasDVBT = true;
1030 state->m_hasDVBC = true;
1031 state->m_hasSAWSW = true;
1032 state->m_hasGPIO2 = true;
1033 state->m_hasGPIO1 = true;
1034 state->m_hasIRQN = false;
1037 /* typeId = DRX3923K_TYPE_ID */
1038 state->m_hasLNA = false;
1039 state->m_hasOOB = false;
1040 state->m_hasATV = true;
1041 state->m_hasAudio = true;
1042 state->m_hasDVBT = true;
1043 state->m_hasDVBC = true;
1044 state->m_hasSAWSW = true;
1045 state->m_hasGPIO2 = true;
1046 state->m_hasGPIO1 = true;
1047 state->m_hasIRQN = false;
1050 /* typeId = DRX3925K_TYPE_ID */
1051 state->m_hasLNA = false;
1052 state->m_hasOOB = false;
1053 state->m_hasATV = true;
1054 state->m_hasAudio = true;
1055 state->m_hasDVBT = true;
1056 state->m_hasDVBC = true;
1057 state->m_hasSAWSW = true;
1058 state->m_hasGPIO2 = true;
1059 state->m_hasGPIO1 = true;
1060 state->m_hasIRQN = false;
1063 /* typeId = DRX3926K_TYPE_ID */
1064 state->m_hasLNA = false;
1065 state->m_hasOOB = false;
1066 state->m_hasATV = true;
1067 state->m_hasAudio = false;
1068 state->m_hasDVBT = true;
1069 state->m_hasDVBC = true;
1070 state->m_hasSAWSW = true;
1071 state->m_hasGPIO2 = true;
1072 state->m_hasGPIO1 = true;
1073 state->m_hasIRQN = false;
1076 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1077 ((sioTopJtagidLo >> 12) & 0xFF));
1083 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1084 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1085 state->m_oscClockFreq / 1000,
1086 state->m_oscClockFreq % 1000);
1090 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1096 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1104 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1107 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1111 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1112 ((state->m_HICfgCtrl) &
1113 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1114 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1115 if (powerdown_cmd == false) {
1116 /* Wait until command rdy */
1123 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1125 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1129 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1133 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1138 static int HI_CfgCommand(struct drxk_state *state)
1144 mutex_lock(&state->mutex);
1146 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1149 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1152 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1155 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1158 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1161 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1164 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1168 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1170 mutex_unlock(&state->mutex);
1172 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1176 static int InitHI(struct drxk_state *state)
1180 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1181 state->m_HICfgTimeout = 0x96FF;
1182 /* port/bridge/power down ctrl */
1183 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1185 return HI_CfgCommand(state);
1188 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1191 u16 sioPdrMclkCfg = 0;
1192 u16 sioPdrMdxCfg = 0;
1195 dprintk(1, ": mpeg %s, %s mode\n",
1196 mpegEnable ? "enable" : "disable",
1197 state->m_enableParallel ? "parallel" : "serial");
1199 /* stop lock indicator process */
1200 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1204 /* MPEG TS pad configuration */
1205 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1209 if (mpegEnable == false) {
1210 /* Set MPEG TS pads to inputmode */
1211 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1214 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1217 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1220 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1223 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1226 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1229 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1232 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1235 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1238 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1241 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1244 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1248 /* Enable MPEG output */
1250 ((state->m_TSDataStrength <<
1251 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1252 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1253 SIO_PDR_MCLK_CFG_DRIVE__B) |
1256 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1260 if (state->enable_merr_cfg)
1261 err_cfg = sioPdrMdxCfg;
1263 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1266 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1270 if (state->m_enableParallel == true) {
1271 /* paralel -> enable MD1 to MD7 */
1272 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1275 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1278 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1281 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1284 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1287 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1290 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1294 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1295 SIO_PDR_MD0_CFG_DRIVE__B)
1297 /* serial -> disable MD1 to MD7 */
1298 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1301 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1304 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1307 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1310 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1313 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1316 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1320 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1323 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1327 /* Enable MB output over MPEG pads and ctl input */
1328 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1331 /* Write nomagic word to enable pdr reg write */
1332 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1335 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1339 static int MPEGTSDisable(struct drxk_state *state)
1343 return MPEGTSConfigurePins(state, false);
1346 static int BLChainCmd(struct drxk_state *state,
1347 u16 romOffset, u16 nrOfElements, u32 timeOut)
1354 mutex_lock(&state->mutex);
1355 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1358 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1361 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1364 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1368 end = jiffies + msecs_to_jiffies(timeOut);
1371 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1374 } while ((blStatus == 0x1) &&
1375 ((time_is_after_jiffies(end))));
1377 if (blStatus == 0x1) {
1378 printk(KERN_ERR "drxk: SIO not ready\n");
1384 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1386 mutex_unlock(&state->mutex);
1391 static int DownloadMicrocode(struct drxk_state *state,
1392 const u8 pMCImage[], u32 Length)
1394 const u8 *pSrc = pMCImage;
1404 /* down the drain (we don't care about MAGIC_WORD) */
1406 /* For future reference */
1407 Drain = (pSrc[0] << 8) | pSrc[1];
1409 pSrc += sizeof(u16);
1410 offset += sizeof(u16);
1411 nBlocks = (pSrc[0] << 8) | pSrc[1];
1412 pSrc += sizeof(u16);
1413 offset += sizeof(u16);
1415 for (i = 0; i < nBlocks; i += 1) {
1416 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1417 (pSrc[2] << 8) | pSrc[3];
1418 pSrc += sizeof(u32);
1419 offset += sizeof(u32);
1421 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1422 pSrc += sizeof(u16);
1423 offset += sizeof(u16);
1426 /* For future reference */
1427 Flags = (pSrc[0] << 8) | pSrc[1];
1429 pSrc += sizeof(u16);
1430 offset += sizeof(u16);
1433 /* For future reference */
1434 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1436 pSrc += sizeof(u16);
1437 offset += sizeof(u16);
1439 if (offset + BlockSize > Length) {
1440 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1444 status = write_block(state, Address, BlockSize, pSrc);
1446 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1450 offset += BlockSize;
1455 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1459 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1460 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1465 if (enable == false) {
1466 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1467 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1470 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1471 if (status >= 0 && data == desiredStatus) {
1472 /* tokenring already has correct status */
1475 /* Disable/enable dvbt tokenring bridge */
1476 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1478 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1480 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1481 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1485 if (data != desiredStatus) {
1486 printk(KERN_ERR "drxk: SIO not ready\n");
1492 static int MPEGTSStop(struct drxk_state *state)
1495 u16 fecOcSncMode = 0;
1496 u16 fecOcIprMode = 0;
1500 /* Gracefull shutdown (byte boundaries) */
1501 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1504 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1505 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1509 /* Suppress MCLK during absence of data */
1510 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1513 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1514 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1518 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1523 static int scu_command(struct drxk_state *state,
1524 u16 cmd, u8 parameterLen,
1525 u16 *parameter, u8 resultLen, u16 *result)
1527 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1528 #error DRXK register mapping no longer compatible with this routine!
1531 int status = -EINVAL;
1540 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1541 ((resultLen > 0) && (result == NULL))) {
1542 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1546 mutex_lock(&state->mutex);
1548 /* assume that the command register is ready
1549 since it is checked afterwards */
1550 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1551 buffer[cnt++] = (parameter[ii] & 0xFF);
1552 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1554 buffer[cnt++] = (cmd & 0xFF);
1555 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1557 write_block(state, SCU_RAM_PARAM_0__A -
1558 (parameterLen - 1), cnt, buffer);
1559 /* Wait until SCU has processed command */
1560 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1563 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1566 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1567 if (curCmd != DRX_SCU_READY) {
1568 printk(KERN_ERR "drxk: SCU not ready\n");
1573 if ((resultLen > 0) && (result != NULL)) {
1577 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1578 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1583 /* Check if an error was reported by SCU */
1584 err = (s16)result[0];
1588 /* check for the known error codes */
1590 case SCU_RESULT_UNKCMD:
1591 p = "SCU_RESULT_UNKCMD";
1593 case SCU_RESULT_UNKSTD:
1594 p = "SCU_RESULT_UNKSTD";
1596 case SCU_RESULT_SIZE:
1597 p = "SCU_RESULT_SIZE";
1599 case SCU_RESULT_INVPAR:
1600 p = "SCU_RESULT_INVPAR";
1602 default: /* Other negative values are errors */
1603 sprintf(errname, "ERROR: %d\n", err);
1606 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1607 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1614 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1616 mutex_unlock(&state->mutex);
1620 static int SetIqmAf(struct drxk_state *state, bool active)
1628 status = read16(state, IQM_AF_STDBY__A, &data);
1633 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1634 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1635 | IQM_AF_STDBY_STDBY_PD_STANDBY
1636 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1637 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1639 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1640 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1641 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1642 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1643 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1646 status = write16(state, IQM_AF_STDBY__A, data);
1650 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1654 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1657 u16 sioCcPwdMode = 0;
1661 /* Check arguments */
1667 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1669 case DRXK_POWER_DOWN_OFDM:
1670 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1672 case DRXK_POWER_DOWN_CORE:
1673 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1675 case DRXK_POWER_DOWN_PLL:
1676 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1678 case DRX_POWER_DOWN:
1679 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1682 /* Unknow sleep mode */
1686 /* If already in requested power mode, do nothing */
1687 if (state->m_currentPowerMode == *mode)
1690 /* For next steps make sure to start from DRX_POWER_UP mode */
1691 if (state->m_currentPowerMode != DRX_POWER_UP) {
1692 status = PowerUpDevice(state);
1695 status = DVBTEnableOFDMTokenRing(state, true);
1700 if (*mode == DRX_POWER_UP) {
1701 /* Restore analog & pin configuartion */
1703 /* Power down to requested mode */
1704 /* Backup some register settings */
1705 /* Set pins with possible pull-ups connected
1706 to them in input mode */
1707 /* Analog power down */
1708 /* ADC power down */
1709 /* Power down device */
1710 /* stop all comm_exec */
1711 /* Stop and power down previous standard */
1712 switch (state->m_OperationMode) {
1714 status = MPEGTSStop(state);
1717 status = PowerDownDVBT(state, false);
1723 status = MPEGTSStop(state);
1726 status = PowerDownQAM(state);
1733 status = DVBTEnableOFDMTokenRing(state, false);
1736 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1739 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1743 if (*mode != DRXK_POWER_DOWN_OFDM) {
1744 state->m_HICfgCtrl |=
1745 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1746 status = HI_CfgCommand(state);
1751 state->m_currentPowerMode = *mode;
1755 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1760 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1762 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1769 status = read16(state, SCU_COMM_EXEC__A, &data);
1772 if (data == SCU_COMM_EXEC_ACTIVE) {
1773 /* Send OFDM stop command */
1774 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1777 /* Send OFDM reset command */
1778 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1783 /* Reset datapath for OFDM, processors first */
1784 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1787 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1790 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1795 status = SetIqmAf(state, false);
1799 /* powerdown to OFDM mode */
1801 status = CtrlPowerMode(state, &powerMode);
1807 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1811 static int SetOperationMode(struct drxk_state *state,
1812 enum OperationMode oMode)
1818 Stop and power down previous standard
1819 TODO investigate total power down instead of partial
1820 power down depending on "previous" standard.
1823 /* disable HW lock indicator */
1824 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1828 /* Device is already at the required mode */
1829 if (state->m_OperationMode == oMode)
1832 switch (state->m_OperationMode) {
1833 /* OM_NONE was added for start up */
1837 status = MPEGTSStop(state);
1840 status = PowerDownDVBT(state, true);
1843 state->m_OperationMode = OM_NONE;
1845 case OM_QAM_ITU_A: /* fallthrough */
1847 status = MPEGTSStop(state);
1850 status = PowerDownQAM(state);
1853 state->m_OperationMode = OM_NONE;
1862 Power up new standard
1866 dprintk(1, ": DVB-T\n");
1867 state->m_OperationMode = oMode;
1868 status = SetDVBTStandard(state, oMode);
1872 case OM_QAM_ITU_A: /* fallthrough */
1874 dprintk(1, ": DVB-C Annex %c\n",
1875 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1876 state->m_OperationMode = oMode;
1877 status = SetQAMStandard(state, oMode);
1887 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1891 static int Start(struct drxk_state *state, s32 offsetFreq,
1892 s32 IntermediateFrequency)
1894 int status = -EINVAL;
1897 s32 OffsetkHz = offsetFreq / 1000;
1900 if (state->m_DrxkState != DRXK_STOPPED &&
1901 state->m_DrxkState != DRXK_DTV_STARTED)
1904 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1906 if (IntermediateFrequency < 0) {
1907 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1908 IntermediateFrequency = -IntermediateFrequency;
1911 switch (state->m_OperationMode) {
1914 IFreqkHz = (IntermediateFrequency / 1000);
1915 status = SetQAM(state, IFreqkHz, OffsetkHz);
1918 state->m_DrxkState = DRXK_DTV_STARTED;
1921 IFreqkHz = (IntermediateFrequency / 1000);
1922 status = MPEGTSStop(state);
1925 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1928 status = DVBTStart(state);
1931 state->m_DrxkState = DRXK_DTV_STARTED;
1938 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1942 static int ShutDown(struct drxk_state *state)
1950 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus)
1952 int status = -EINVAL;
1956 if (pLockStatus == NULL)
1959 *pLockStatus = NOT_LOCKED;
1961 /* define the SCU command code */
1962 switch (state->m_OperationMode) {
1966 status = GetQAMLockStatus(state, pLockStatus);
1969 status = GetDVBTLockStatus(state, pLockStatus);
1976 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1980 static int MPEGTSStart(struct drxk_state *state)
1984 u16 fecOcSncMode = 0;
1986 /* Allow OC to sync again */
1987 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1990 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1991 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1994 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1997 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2001 static int MPEGTSDtoInit(struct drxk_state *state)
2007 /* Rate integration settings */
2008 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
2011 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
2014 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2017 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2020 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2023 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2026 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2029 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2033 /* Additional configuration */
2034 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2037 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2040 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2043 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2048 static int MPEGTSDtoSetup(struct drxk_state *state,
2049 enum OperationMode oMode)
2053 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2054 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2055 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2056 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2057 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2058 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2059 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2060 u16 fecOcTmdMode = 0;
2061 u16 fecOcTmdIntUpdRate = 0;
2063 bool staticCLK = false;
2067 /* Check insertion of the Reed-Solomon parity bytes */
2068 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2071 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2074 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2075 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2076 if (state->m_insertRSByte == true) {
2077 /* enable parity symbol forward */
2078 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2079 /* MVAL disable during parity bytes */
2080 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2081 /* TS burst length to 204 */
2082 fecOcDtoBurstLen = 204;
2085 /* Check serial or parrallel output */
2086 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2087 if (state->m_enableParallel == false) {
2088 /* MPEG data output is serial -> set ipr_mode[0] */
2089 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2094 maxBitRate = state->m_DVBTBitrate;
2096 fecOcRcnCtlRate = 0xC00000;
2097 staticCLK = state->m_DVBTStaticCLK;
2099 case OM_QAM_ITU_A: /* fallthrough */
2101 fecOcTmdMode = 0x0004;
2102 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2103 maxBitRate = state->m_DVBCBitrate;
2104 staticCLK = state->m_DVBCStaticCLK;
2108 } /* switch (standard) */
2112 /* Configure DTO's */
2116 /* Rational DTO for MCLK source (static MCLK rate),
2117 Dynamic DTO for optimal grouping
2118 (avoid intra-packet gaps),
2119 DTO offset enable to sync TS burst with MSTRT */
2120 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2121 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2122 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2123 FEC_OC_FCT_MODE_VIRT_ENA__M);
2125 /* Check user defined bitrate */
2126 bitRate = maxBitRate;
2127 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2128 bitRate = 75900000UL;
2130 /* Rational DTO period:
2131 dto_period = (Fsys / bitrate) - 2
2133 Result should be floored,
2134 to make sure >= requested bitrate
2136 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2138 if (fecOcDtoPeriod <= 2)
2141 fecOcDtoPeriod -= 2;
2142 fecOcTmdIntUpdRate = 8;
2144 /* (commonAttr->staticCLK == false) => dynamic mode */
2145 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2146 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2147 fecOcTmdIntUpdRate = 5;
2150 /* Write appropriate registers with requested configuration */
2151 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2154 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2157 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2160 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2163 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2166 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2170 /* Rate integration settings */
2171 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2174 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2177 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2180 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2184 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2186 u16 fecOcRegIprInvert = 0;
2188 /* Data mask for the output data byte */
2189 u16 InvertDataMask =
2190 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2191 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2192 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2193 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2197 /* Control selective inversion of output bits */
2198 fecOcRegIprInvert &= (~(InvertDataMask));
2199 if (state->m_invertDATA == true)
2200 fecOcRegIprInvert |= InvertDataMask;
2201 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2202 if (state->m_invertERR == true)
2203 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2204 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2205 if (state->m_invertSTR == true)
2206 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2207 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2208 if (state->m_invertVAL == true)
2209 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2210 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2211 if (state->m_invertCLK == true)
2212 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2214 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2217 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2219 static int SetAgcRf(struct drxk_state *state,
2220 struct SCfgAgc *pAgcCfg, bool isDTV)
2222 int status = -EINVAL;
2224 struct SCfgAgc *pIfAgcSettings;
2228 if (pAgcCfg == NULL)
2231 switch (pAgcCfg->ctrlMode) {
2232 case DRXK_AGC_CTRL_AUTO:
2233 /* Enable RF AGC DAC */
2234 status = read16(state, IQM_AF_STDBY__A, &data);
2237 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2238 status = write16(state, IQM_AF_STDBY__A, data);
2241 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2245 /* Enable SCU RF AGC loop */
2246 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2249 if (state->m_RfAgcPol)
2250 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2252 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2253 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2257 /* Set speed (using complementary reduction value) */
2258 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2262 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2263 data |= (~(pAgcCfg->speed <<
2264 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2265 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2267 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2272 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2273 else if (IsQAM(state))
2274 pIfAgcSettings = &state->m_qamIfAgcCfg;
2276 pIfAgcSettings = &state->m_atvIfAgcCfg;
2277 if (pIfAgcSettings == NULL) {
2282 /* Set TOP, only if IF-AGC is in AUTO mode */
2283 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2284 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2288 /* Cut-Off current */
2289 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2293 /* Max. output level */
2294 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2300 case DRXK_AGC_CTRL_USER:
2301 /* Enable RF AGC DAC */
2302 status = read16(state, IQM_AF_STDBY__A, &data);
2305 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2306 status = write16(state, IQM_AF_STDBY__A, data);
2310 /* Disable SCU RF AGC loop */
2311 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2314 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2315 if (state->m_RfAgcPol)
2316 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2318 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2319 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2323 /* SCU c.o.c. to 0, enabling full control range */
2324 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2328 /* Write value to output pin */
2329 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2334 case DRXK_AGC_CTRL_OFF:
2335 /* Disable RF AGC DAC */
2336 status = read16(state, IQM_AF_STDBY__A, &data);
2339 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2340 status = write16(state, IQM_AF_STDBY__A, data);
2344 /* Disable SCU RF AGC loop */
2345 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2348 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2349 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2360 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2364 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2366 static int SetAgcIf(struct drxk_state *state,
2367 struct SCfgAgc *pAgcCfg, bool isDTV)
2371 struct SCfgAgc *pRfAgcSettings;
2375 switch (pAgcCfg->ctrlMode) {
2376 case DRXK_AGC_CTRL_AUTO:
2378 /* Enable IF AGC DAC */
2379 status = read16(state, IQM_AF_STDBY__A, &data);
2382 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2383 status = write16(state, IQM_AF_STDBY__A, data);
2387 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2391 /* Enable SCU IF AGC loop */
2392 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2395 if (state->m_IfAgcPol)
2396 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2398 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2399 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2403 /* Set speed (using complementary reduction value) */
2404 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2407 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2408 data |= (~(pAgcCfg->speed <<
2409 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2410 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2412 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2417 pRfAgcSettings = &state->m_qamRfAgcCfg;
2419 pRfAgcSettings = &state->m_atvRfAgcCfg;
2420 if (pRfAgcSettings == NULL)
2423 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2428 case DRXK_AGC_CTRL_USER:
2430 /* Enable IF AGC DAC */
2431 status = read16(state, IQM_AF_STDBY__A, &data);
2434 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2435 status = write16(state, IQM_AF_STDBY__A, data);
2439 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2443 /* Disable SCU IF AGC loop */
2444 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2447 if (state->m_IfAgcPol)
2448 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2450 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2451 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2455 /* Write value to output pin */
2456 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2461 case DRXK_AGC_CTRL_OFF:
2463 /* Disable If AGC DAC */
2464 status = read16(state, IQM_AF_STDBY__A, &data);
2467 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2468 status = write16(state, IQM_AF_STDBY__A, data);
2472 /* Disable SCU IF AGC loop */
2473 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2476 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2477 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2481 } /* switch (agcSettingsIf->ctrlMode) */
2483 /* always set the top to support
2484 configurations without if-loop */
2485 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2488 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2492 static int GetQAMSignalToNoise(struct drxk_state *state,
2493 s32 *pSignalToNoise)
2496 u16 qamSlErrPower = 0; /* accum. error between
2497 raw and sliced symbols */
2498 u32 qamSlSigPower = 0; /* used for MER, depends of
2500 u32 qamSlMer = 0; /* QAM MER */
2504 /* MER calculation */
2506 /* get the register value needed for MER */
2507 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2509 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2513 switch (state->props.modulation) {
2515 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2518 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2521 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2524 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2528 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2532 if (qamSlErrPower > 0) {
2533 qamSlMer = Log10Times100(qamSlSigPower) -
2534 Log10Times100((u32) qamSlErrPower);
2536 *pSignalToNoise = qamSlMer;
2541 static int GetDVBTSignalToNoise(struct drxk_state *state,
2542 s32 *pSignalToNoise)
2546 u32 EqRegTdSqrErrI = 0;
2547 u32 EqRegTdSqrErrQ = 0;
2548 u16 EqRegTdSqrErrExp = 0;
2549 u16 EqRegTdTpsPwrOfs = 0;
2550 u16 EqRegTdReqSmbCnt = 0;
2557 u16 transmissionParams = 0;
2561 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2564 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2567 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2570 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data);
2573 /* Extend SQR_ERR_I operational range */
2574 EqRegTdSqrErrI = (u32) regData;
2575 if ((EqRegTdSqrErrExp > 11) &&
2576 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2577 EqRegTdSqrErrI += 0x00010000UL;
2579 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data);
2582 /* Extend SQR_ERR_Q operational range */
2583 EqRegTdSqrErrQ = (u32) regData;
2584 if ((EqRegTdSqrErrExp > 11) &&
2585 (EqRegTdSqrErrQ < 0x00000FFFUL))
2586 EqRegTdSqrErrQ += 0x00010000UL;
2588 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2592 /* Check input data for MER */
2594 /* MER calculation (in 0.1 dB) without math.h */
2595 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2597 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2598 /* No error at all, this must be the HW reset value
2599 * Apparently no first measurement yet
2603 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2605 if ((transmissionParams &
2606 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2607 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2612 /* IMER = 100 * log10 (x)
2613 where x = (EqRegTdTpsPwrOfs^2 *
2614 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2617 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2618 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2619 c = 100 * log10 (SqrErrIQ)
2622 /* log(x) x = 9bits * 9bits->18 bits */
2623 a = Log10Times100(EqRegTdTpsPwrOfs *
2625 /* log(x) x = 16bits * 7bits->23 bits */
2626 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2627 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2628 c = Log10Times100(SqrErrIQ);
2632 *pSignalToNoise = iMER;
2636 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2640 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2644 *pSignalToNoise = 0;
2645 switch (state->m_OperationMode) {
2647 return GetDVBTSignalToNoise(state, pSignalToNoise);
2650 return GetQAMSignalToNoise(state, pSignalToNoise);
2658 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2660 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2665 static s32 QE_SN[] = {
2671 108, /* 16-QAM 1/2 */
2672 131, /* 16-QAM 2/3 */
2673 146, /* 16-QAM 3/4 */
2674 156, /* 16-QAM 5/6 */
2675 160, /* 16-QAM 7/8 */
2676 165, /* 64-QAM 1/2 */
2677 187, /* 64-QAM 2/3 */
2678 202, /* 64-QAM 3/4 */
2679 216, /* 64-QAM 5/6 */
2680 225, /* 64-QAM 7/8 */
2686 s32 SignalToNoise = 0;
2687 u16 Constellation = 0;
2689 u32 SignalToNoiseRel;
2692 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2695 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2698 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2700 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2703 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2705 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2706 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2708 SignalToNoiseRel = SignalToNoise -
2709 QE_SN[Constellation * 5 + CodeRate];
2712 if (SignalToNoiseRel < -70)
2714 else if (SignalToNoiseRel < 30)
2715 *pQuality = ((SignalToNoiseRel + 70) *
2718 *pQuality = BERQuality;
2723 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2731 u32 SignalToNoise = 0;
2732 u32 BERQuality = 100;
2733 u32 SignalToNoiseRel = 0;
2735 status = GetQAMSignalToNoise(state, &SignalToNoise);
2739 switch (state->props.modulation) {
2741 SignalToNoiseRel = SignalToNoise - 200;
2744 SignalToNoiseRel = SignalToNoise - 230;
2745 break; /* Not in NorDig */
2747 SignalToNoiseRel = SignalToNoise - 260;
2750 SignalToNoiseRel = SignalToNoise - 290;
2754 SignalToNoiseRel = SignalToNoise - 320;
2758 if (SignalToNoiseRel < -70)
2760 else if (SignalToNoiseRel < 30)
2761 *pQuality = ((SignalToNoiseRel + 70) *
2764 *pQuality = BERQuality;
2770 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2774 switch (state->m_OperationMode) {
2776 return GetDVBTQuality(state, pQuality);
2778 return GetDVBCQuality(state, pQuality);
2787 /* Free data ram in SIO HI */
2788 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2789 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2791 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2792 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2793 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2794 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2796 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2797 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2798 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2800 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2802 int status = -EINVAL;
2806 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2808 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2811 if (state->no_i2c_bridge)
2814 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2817 if (bEnableBridge) {
2818 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2822 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2827 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2831 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2835 static int SetPreSaw(struct drxk_state *state,
2836 struct SCfgPreSaw *pPreSawCfg)
2838 int status = -EINVAL;
2842 if ((pPreSawCfg == NULL)
2843 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2846 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2849 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2853 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2854 u16 romOffset, u16 nrOfElements, u32 timeOut)
2857 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2858 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2864 mutex_lock(&state->mutex);
2865 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2868 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2871 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2874 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2877 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2880 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2884 end = jiffies + msecs_to_jiffies(timeOut);
2886 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2889 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2890 if (blStatus == 0x1) {
2891 printk(KERN_ERR "drxk: SIO not ready\n");
2897 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2899 mutex_unlock(&state->mutex);
2904 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2911 /* Start measurement */
2912 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2915 status = write16(state, IQM_AF_START_LOCK__A, 1);
2920 status = read16(state, IQM_AF_PHASE0__A, &data);
2924 *count = *count + 1;
2925 status = read16(state, IQM_AF_PHASE1__A, &data);
2929 *count = *count + 1;
2930 status = read16(state, IQM_AF_PHASE2__A, &data);
2934 *count = *count + 1;
2938 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2942 static int ADCSynchronization(struct drxk_state *state)
2949 status = ADCSyncMeasurement(state, &count);
2954 /* Try sampling on a diffrent edge */
2957 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2960 if ((clkNeg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2961 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2962 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2964 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2966 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2968 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2970 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2973 status = ADCSyncMeasurement(state, &count);
2982 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2986 static int SetFrequencyShifter(struct drxk_state *state,
2987 u16 intermediateFreqkHz,
2988 s32 tunerFreqOffset, bool isDTV)
2990 bool selectPosImage = false;
2991 u32 rfFreqResidual = tunerFreqOffset;
2992 u32 fmFrequencyShift = 0;
2993 bool tunerMirror = !state->m_bMirrorFreqSpect;
2998 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3005 Program frequency shifter
3006 No need to account for mirroring on RF
3009 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3010 (state->m_OperationMode == OM_QAM_ITU_C) ||
3011 (state->m_OperationMode == OM_DVBT))
3012 selectPosImage = true;
3014 selectPosImage = false;
3017 /* tuner doesn't mirror */
3018 ifFreqActual = intermediateFreqkHz +
3019 rfFreqResidual + fmFrequencyShift;
3022 ifFreqActual = intermediateFreqkHz -
3023 rfFreqResidual - fmFrequencyShift;
3024 if (ifFreqActual > samplingFrequency / 2) {
3026 adcFreq = samplingFrequency - ifFreqActual;
3029 /* adc doesn't mirror */
3030 adcFreq = ifFreqActual;
3034 frequencyShift = adcFreq;
3035 imageToSelect = state->m_rfmirror ^ tunerMirror ^
3036 adcFlip ^ selectPosImage;
3037 state->m_IqmFsRateOfs =
3038 Frac28a((frequencyShift), samplingFrequency);
3041 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3043 /* Program frequency shifter with tuner offset compensation */
3044 /* frequencyShift += tunerFreqOffset; TODO */
3045 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3046 state->m_IqmFsRateOfs);
3048 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3052 static int InitAGC(struct drxk_state *state, bool isDTV)
3055 u16 ingainTgtMin = 0;
3056 u16 ingainTgtMax = 0;
3064 u16 kiInnergainMin = 0;
3065 u16 ifIaccuHiTgt = 0;
3066 u16 ifIaccuHiTgtMin = 0;
3067 u16 ifIaccuHiTgtMax = 0;
3069 u16 fastClpCtrlDelay = 0;
3070 u16 clpCtrlMode = 0;
3075 /* Common settings */
3077 ifIaccuHiTgtMin = 2047;
3081 /* AGCInit() not available for DVBT; init done in microcode */
3082 if (!IsQAM(state)) {
3083 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3087 /* FIXME: Analog TV AGC require different settings */
3089 /* Standard specific settings */
3091 clpDirTo = (u16) -9;
3094 snsDirTo = (u16) -9;
3095 kiInnergainMin = (u16) -1030;
3096 ifIaccuHiTgtMax = 0x2380;
3097 ifIaccuHiTgt = 0x2380;
3098 ingainTgtMin = 0x0511;
3100 ingainTgtMax = 5119;
3101 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3103 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3107 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3110 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3113 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3116 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3119 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3122 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3125 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3128 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3131 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3134 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3137 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3140 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3144 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3147 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3150 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3154 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3157 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3160 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3164 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3167 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3170 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3173 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3176 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3179 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3182 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3185 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3188 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3191 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3194 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3197 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3200 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3203 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3206 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3209 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3212 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3215 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3218 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3222 /* Initialize inner-loop KI gain factors */
3223 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3228 data &= ~SCU_RAM_AGC_KI_RF__M;
3229 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3230 data &= ~SCU_RAM_AGC_KI_IF__M;
3231 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3233 status = write16(state, SCU_RAM_AGC_KI__A, data);
3236 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3240 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3245 if (packetErr == NULL)
3246 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3248 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3250 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3254 static int DVBTScCommand(struct drxk_state *state,
3255 u16 cmd, u16 subcmd,
3256 u16 param0, u16 param1, u16 param2,
3257 u16 param3, u16 param4)
3266 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3268 /* SC is not running */
3274 /* Wait until sc is ready to receive command */
3278 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3280 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3281 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3284 /* Write sub-command */
3286 /* All commands using sub-cmd */
3287 case OFDM_SC_RA_RAM_CMD_PROC_START:
3288 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3289 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3290 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3299 /* Write needed parameters and the command */
3301 /* All commands using 5 parameters */
3302 /* All commands using 4 parameters */
3303 /* All commands using 3 parameters */
3304 /* All commands using 2 parameters */
3305 case OFDM_SC_RA_RAM_CMD_PROC_START:
3306 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3307 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3308 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3309 /* All commands using 1 parameters */
3310 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3311 case OFDM_SC_RA_RAM_CMD_USER_IO:
3312 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3313 /* All commands using 0 parameters */
3314 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3315 case OFDM_SC_RA_RAM_CMD_NULL:
3317 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3320 /* Unknown command */
3326 /* Wait until sc is ready processing command */
3330 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3332 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3333 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3336 /* Check for illegal cmd */
3337 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3338 if (errCode == 0xFFFF) {
3339 /* illegal command */
3345 /* Retreive results parameters from SC */
3347 /* All commands yielding 5 results */
3348 /* All commands yielding 4 results */
3349 /* All commands yielding 3 results */
3350 /* All commands yielding 2 results */
3351 /* All commands yielding 1 result */
3352 case OFDM_SC_RA_RAM_CMD_USER_IO:
3353 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3354 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3355 /* All commands yielding 0 results */
3356 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3357 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3358 case OFDM_SC_RA_RAM_CMD_PROC_START:
3359 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3360 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3361 case OFDM_SC_RA_RAM_CMD_NULL:
3364 /* Unknown command */
3367 } /* switch (cmd->cmd) */
3370 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3374 static int PowerUpDVBT(struct drxk_state *state)
3376 enum DRXPowerMode powerMode = DRX_POWER_UP;
3380 status = CtrlPowerMode(state, &powerMode);
3382 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3386 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3391 if (*enabled == true)
3392 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3394 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3396 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3400 #define DEFAULT_FR_THRES_8K 4000
3401 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3407 if (*enabled == true) {
3408 /* write mask to 1 */
3409 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3410 DEFAULT_FR_THRES_8K);
3412 /* write mask to 0 */
3413 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3416 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3421 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3422 struct DRXKCfgDvbtEchoThres_t *echoThres)
3428 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3432 switch (echoThres->fftMode) {
3433 case DRX_FFTMODE_2K:
3434 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3435 data |= ((echoThres->threshold <<
3436 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3437 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3439 case DRX_FFTMODE_8K:
3440 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3441 data |= ((echoThres->threshold <<
3442 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3443 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3449 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3452 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3456 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3457 enum DRXKCfgDvbtSqiSpeed *speed)
3459 int status = -EINVAL;
3464 case DRXK_DVBT_SQI_SPEED_FAST:
3465 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3466 case DRXK_DVBT_SQI_SPEED_SLOW:
3471 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3475 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3479 /*============================================================================*/
3482 * \brief Activate DVBT specific presets
3483 * \param demod instance of demodulator.
3484 * \return DRXStatus_t.
3486 * Called in DVBTSetStandard
3489 static int DVBTActivatePresets(struct drxk_state *state)
3492 bool setincenable = false;
3493 bool setfrenable = true;
3495 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3496 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3499 status = DVBTCtrlSetIncEnable(state, &setincenable);
3502 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3505 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3508 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3511 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3514 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3518 /*============================================================================*/
3521 * \brief Initialize channelswitch-independent settings for DVBT.
3522 * \param demod instance of demodulator.
3523 * \return DRXStatus_t.
3525 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3526 * the DVB-T taps from the drxk_filters.h are used.
3528 static int SetDVBTStandard(struct drxk_state *state,
3529 enum OperationMode oMode)
3538 /* added antenna switch */
3539 SwitchAntennaToDVBT(state);
3540 /* send OFDM reset command */
3541 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3545 /* send OFDM setenv command */
3546 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3550 /* reset datapath for OFDM, processors first */
3551 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3554 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3557 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3562 /* synchronize on ofdstate->m_festart */
3563 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3566 /* window size for clipping ADC detection */
3567 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3570 /* window size for for sense pre-SAW detection */
3571 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3574 /* sense threshold for sense pre-SAW detection */
3575 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3578 status = SetIqmAf(state, true);
3582 status = write16(state, IQM_AF_AGC_RF__A, 0);
3586 /* Impulse noise cruncher setup */
3587 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3590 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3593 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3597 status = write16(state, IQM_RC_STRETCH__A, 16);
3600 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3603 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3606 status = write16(state, IQM_CF_SCALE__A, 1600);
3609 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3613 /* virtual clipping threshold for clipping ADC detection */
3614 status = write16(state, IQM_AF_CLP_TH__A, 448);
3617 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3621 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3625 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3628 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3631 /* enable power measurement interrupt */
3632 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3635 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3639 /* IQM will not be reset from here, sync ADC and update/init AGC */
3640 status = ADCSynchronization(state);
3643 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3647 /* Halt SCU to enable safe non-atomic accesses */
3648 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3652 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3655 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3659 /* Set Noise Estimation notch width and enable DC fix */
3660 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3663 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3664 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3668 /* Activate SCU to enable SCU commands */
3669 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3673 if (!state->m_DRXK_A3_ROM_CODE) {
3674 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3675 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3681 #ifdef COMPILE_FOR_NONRT
3682 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3685 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3691 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3696 #ifdef COMPILE_FOR_NONRT
3697 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3701 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3705 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3709 /* Setup MPEG bus */
3710 status = MPEGTSDtoSetup(state, OM_DVBT);
3713 /* Set DVBT Presets */
3714 status = DVBTActivatePresets(state);
3720 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3724 /*============================================================================*/
3726 * \brief Start dvbt demodulating for channel.
3727 * \param demod instance of demodulator.
3728 * \return DRXStatus_t.
3730 static int DVBTStart(struct drxk_state *state)
3734 /* DRXKOfdmScCmd_t scCmd; */
3737 /* Start correct processes to get in lock */
3738 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3739 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3740 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3744 status = MPEGTSStart(state);
3747 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3752 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3757 /*============================================================================*/
3760 * \brief Set up dvbt demodulator for channel.
3761 * \param demod instance of demodulator.
3762 * \return DRXStatus_t.
3763 * // original DVBTSetChannel()
3765 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3766 s32 tunerFreqOffset)
3769 u16 transmissionParams = 0;
3770 u16 operationMode = 0;
3771 u32 iqmRcRateOfs = 0;
3776 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3778 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3782 /* Halt SCU to enable safe non-atomic accesses */
3783 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3787 /* Stop processors */
3788 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3791 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3795 /* Mandatory fix, always stop CP, required to set spl offset back to
3796 hardware default (is set to 0 by ucode during pilot detection */
3797 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3801 /*== Write channel settings to device =====================================*/
3804 switch (state->props.transmission_mode) {
3805 case TRANSMISSION_MODE_AUTO:
3807 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3808 /* fall through , try first guess DRX_FFTMODE_8K */
3809 case TRANSMISSION_MODE_8K:
3810 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3812 case TRANSMISSION_MODE_2K:
3813 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3818 switch (state->props.guard_interval) {
3820 case GUARD_INTERVAL_AUTO:
3821 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3822 /* fall through , try first guess DRX_GUARD_1DIV4 */
3823 case GUARD_INTERVAL_1_4:
3824 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3826 case GUARD_INTERVAL_1_32:
3827 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3829 case GUARD_INTERVAL_1_16:
3830 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3832 case GUARD_INTERVAL_1_8:
3833 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3838 switch (state->props.hierarchy) {
3839 case HIERARCHY_AUTO:
3840 case HIERARCHY_NONE:
3842 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3843 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3844 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3847 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3850 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3853 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3859 switch (state->props.modulation) {
3862 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3863 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3865 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3868 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3871 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3875 /* No hierachical channels support in BDA */
3876 /* Priority (only for hierarchical channels) */
3877 switch (channel->priority) {
3878 case DRX_PRIORITY_LOW:
3879 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3880 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3881 OFDM_EC_SB_PRIOR_LO);
3883 case DRX_PRIORITY_HIGH:
3884 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3885 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3886 OFDM_EC_SB_PRIOR_HI));
3888 case DRX_PRIORITY_UNKNOWN: /* fall through */
3894 /* Set Priorty high */
3895 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3896 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3902 switch (state->props.code_rate_HP) {
3905 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3906 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3908 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3911 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3914 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3917 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3920 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3924 /* SAW filter selection: normaly not necesarry, but if wanted
3925 the application can select a SAW filter via the driver by using UIOs */
3926 /* First determine real bandwidth (Hz) */
3927 /* Also set delay for impulse noise cruncher */
3928 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3929 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3931 switch (state->props.bandwidth_hz) {
3933 state->props.bandwidth_hz = 8000000;
3936 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3937 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3940 /* cochannel protection for PAL 8 MHz */
3941 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3944 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3947 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3950 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3955 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3956 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3959 /* cochannel protection for PAL 7 MHz */
3960 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3966 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3969 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3974 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3975 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3978 /* cochannel protection for NTSC 6 MHz */
3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3985 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3988 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3997 if (iqmRcRateOfs == 0) {
3998 /* Now compute IQM_RC_RATE_OFS
3999 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4001 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4003 /* (SysFreq / BandWidth) * (2^28) */
4004 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4005 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4006 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4007 iqmRcRateOfs = Frac28a((u32)
4008 ((state->m_sysClockFreq *
4009 1000) / 3), bandwidth);
4010 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4011 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4012 iqmRcRateOfs += 0x80L;
4013 iqmRcRateOfs = iqmRcRateOfs >> 7;
4014 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4015 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4019 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4020 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4021 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4025 /* Bandwidth setting done */
4028 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4032 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4036 /*== Start SC, write channel settings to SC ===============================*/
4038 /* Activate SCU to enable SCU commands */
4039 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4043 /* Enable SC after setting all other parameters */
4044 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4047 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4052 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4056 /* Write SC parameter registers, set all AUTO flags in operation mode */
4057 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4058 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4059 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4060 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4061 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4062 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4063 0, transmissionParams, param1, 0, 0, 0);
4067 if (!state->m_DRXK_A3_ROM_CODE)
4068 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4071 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4077 /*============================================================================*/
4080 * \brief Retreive lock status .
4081 * \param demod Pointer to demodulator instance.
4082 * \param lockStat Pointer to lock status structure.
4083 * \return DRXStatus_t.
4086 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4089 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4090 OFDM_SC_RA_RAM_LOCK_FEC__M);
4091 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4092 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4094 u16 ScRaRamLock = 0;
4099 *pLockStatus = NOT_LOCKED;
4101 /* Check if SC is running */
4102 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4105 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4108 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4112 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4113 *pLockStatus = MPEG_LOCK;
4114 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4115 *pLockStatus = FEC_LOCK;
4116 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4117 *pLockStatus = DEMOD_LOCK;
4118 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4119 *pLockStatus = NEVER_LOCK;
4122 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4127 static int PowerUpQAM(struct drxk_state *state)
4129 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4133 status = CtrlPowerMode(state, &powerMode);
4135 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4141 /** Power Down QAM */
4142 static int PowerDownQAM(struct drxk_state *state)
4149 status = read16(state, SCU_COMM_EXEC__A, &data);
4152 if (data == SCU_COMM_EXEC_ACTIVE) {
4157 /* stop all comstate->m_exec */
4158 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4161 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4166 status = SetIqmAf(state, false);
4170 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4175 /*============================================================================*/
4178 * \brief Setup of the QAM Measurement intervals for signal quality
4179 * \param demod instance of demod.
4180 * \param modulation current modulation.
4181 * \return DRXStatus_t.
4184 * Take into account that for certain settings the errorcounters can overflow.
4185 * The implementation does not check this.
4188 static int SetQAMMeasurement(struct drxk_state *state,
4189 enum EDrxkConstellation modulation,
4192 u32 fecBitsDesired = 0; /* BER accounting period */
4193 u32 fecRsPeriodTotal = 0; /* Total period */
4194 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4195 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4201 /* fecBitsDesired = symbolRate [kHz] *
4207 switch (modulation) {
4208 case DRX_CONSTELLATION_QAM16:
4209 fecBitsDesired = 4 * symbolRate;
4211 case DRX_CONSTELLATION_QAM32:
4212 fecBitsDesired = 5 * symbolRate;
4214 case DRX_CONSTELLATION_QAM64:
4215 fecBitsDesired = 6 * symbolRate;
4217 case DRX_CONSTELLATION_QAM128:
4218 fecBitsDesired = 7 * symbolRate;
4220 case DRX_CONSTELLATION_QAM256:
4221 fecBitsDesired = 8 * symbolRate;
4229 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4230 fecBitsDesired *= 500; /* meas. period [ms] */
4232 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4233 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4234 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4236 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4237 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4238 if (fecRsPrescale == 0) {
4239 /* Divide by zero (though impossible) */
4245 ((u16) fecRsPeriodTotal +
4246 (fecRsPrescale >> 1)) / fecRsPrescale;
4248 /* write corresponding registers */
4249 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4252 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4255 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4258 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4262 static int SetQAM16(struct drxk_state *state)
4267 /* QAM Equalizer Setup */
4269 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4272 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4275 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4278 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4281 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4284 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4287 /* Decision Feedback Equalizer */
4288 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4291 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4294 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4297 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4300 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4303 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4307 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4310 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4313 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4317 /* QAM Slicer Settings */
4318 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4322 /* QAM Loop Controller Coeficients */
4323 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4326 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4329 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4332 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4335 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4338 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4341 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4344 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4348 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4351 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4354 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4357 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4360 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4363 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4366 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4369 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4372 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4375 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4378 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4381 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4386 /* QAM State Machine (FSM) Thresholds */
4388 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4391 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4394 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4397 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4400 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4403 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4407 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4410 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4413 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4418 /* QAM FSM Tracking Parameters */
4420 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4423 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4426 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4429 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4432 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4435 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4438 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4444 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4448 /*============================================================================*/
4451 * \brief QAM32 specific setup
4452 * \param demod instance of demod.
4453 * \return DRXStatus_t.
4455 static int SetQAM32(struct drxk_state *state)
4461 /* QAM Equalizer Setup */
4463 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4466 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4469 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4472 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4475 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4478 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4482 /* Decision Feedback Equalizer */
4483 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4486 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4489 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4492 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4495 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4498 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4502 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4505 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4508 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4512 /* QAM Slicer Settings */
4514 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4519 /* QAM Loop Controller Coeficients */
4521 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4524 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4527 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4530 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4533 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4536 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4539 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4542 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4546 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4549 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4552 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4555 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4558 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4561 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4564 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4567 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4570 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4573 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4576 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4579 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4584 /* QAM State Machine (FSM) Thresholds */
4586 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4589 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4592 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4595 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4598 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4601 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4605 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4608 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4611 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4616 /* QAM FSM Tracking Parameters */
4618 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4621 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4624 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4627 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4630 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4633 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4636 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4639 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4643 /*============================================================================*/
4646 * \brief QAM64 specific setup
4647 * \param demod instance of demod.
4648 * \return DRXStatus_t.
4650 static int SetQAM64(struct drxk_state *state)
4655 /* QAM Equalizer Setup */
4657 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4660 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4663 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4666 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4669 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4672 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4676 /* Decision Feedback Equalizer */
4677 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4680 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4683 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4686 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4689 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4692 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4696 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4699 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4702 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4706 /* QAM Slicer Settings */
4707 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4712 /* QAM Loop Controller Coeficients */
4714 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4717 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4720 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4723 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4726 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4729 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4732 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4735 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4739 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4742 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4745 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4748 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4751 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4754 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4757 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4760 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4763 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4766 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4769 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4772 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4777 /* QAM State Machine (FSM) Thresholds */
4779 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4782 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4785 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4788 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4791 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4794 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4798 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4801 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4804 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4809 /* QAM FSM Tracking Parameters */
4811 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4814 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4817 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4820 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4823 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4826 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4829 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4832 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4837 /*============================================================================*/
4840 * \brief QAM128 specific setup
4841 * \param demod: instance of demod.
4842 * \return DRXStatus_t.
4844 static int SetQAM128(struct drxk_state *state)
4849 /* QAM Equalizer Setup */
4851 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4854 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4857 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4860 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4863 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4866 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4870 /* Decision Feedback Equalizer */
4871 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4874 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4877 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4880 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4883 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4886 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4890 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4893 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4896 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4901 /* QAM Slicer Settings */
4903 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4908 /* QAM Loop Controller Coeficients */
4910 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4913 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4916 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4919 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4922 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4925 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4928 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4931 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4935 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4938 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4941 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4944 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4947 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4950 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4953 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4956 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4959 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4962 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4965 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4968 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4973 /* QAM State Machine (FSM) Thresholds */
4975 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4978 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4981 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4984 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4987 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4990 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4994 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4997 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5001 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5005 /* QAM FSM Tracking Parameters */
5007 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5010 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5013 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5016 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5019 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5022 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5025 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5028 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5033 /*============================================================================*/
5036 * \brief QAM256 specific setup
5037 * \param demod: instance of demod.
5038 * \return DRXStatus_t.
5040 static int SetQAM256(struct drxk_state *state)
5045 /* QAM Equalizer Setup */
5047 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5050 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5053 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5056 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5059 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5062 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5066 /* Decision Feedback Equalizer */
5067 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5070 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5073 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5076 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5079 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5082 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5086 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5089 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5092 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5096 /* QAM Slicer Settings */
5098 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5103 /* QAM Loop Controller Coeficients */
5105 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5108 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5111 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5114 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5117 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5120 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5123 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5126 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5130 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5133 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5136 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5139 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5142 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5145 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5148 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5151 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5154 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5157 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5160 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5163 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5168 /* QAM State Machine (FSM) Thresholds */
5170 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5173 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5176 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5179 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5182 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5185 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5189 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5192 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5195 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5200 /* QAM FSM Tracking Parameters */
5202 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5205 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5208 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5211 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5214 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5217 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5220 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5223 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5228 /*============================================================================*/
5230 * \brief Reset QAM block.
5231 * \param demod: instance of demod.
5232 * \param channel: pointer to channel data.
5233 * \return DRXStatus_t.
5235 static int QAMResetQAM(struct drxk_state *state)
5241 /* Stop QAM comstate->m_exec */
5242 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5246 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5249 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5253 /*============================================================================*/
5256 * \brief Set QAM symbolrate.
5257 * \param demod: instance of demod.
5258 * \param channel: pointer to channel data.
5259 * \return DRXStatus_t.
5261 static int QAMSetSymbolrate(struct drxk_state *state)
5263 u32 adcFrequency = 0;
5271 /* Select & calculate correct IQM rate */
5272 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5274 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5275 if (state->props.symbol_rate <= 1188750)
5277 else if (state->props.symbol_rate <= 2377500)
5279 else if (state->props.symbol_rate <= 4755000)
5281 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5286 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5288 symbFreq = state->props.symbol_rate * (1 << ratesel);
5289 if (symbFreq == 0) {
5290 /* Divide by zero */
5294 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5295 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5297 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5300 state->m_iqmRcRate = iqmRcRate;
5302 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5304 symbFreq = state->props.symbol_rate;
5305 if (adcFrequency == 0) {
5306 /* Divide by zero */
5310 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5311 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5313 if (lcSymbRate > 511)
5315 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5319 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5323 /*============================================================================*/
5326 * \brief Get QAM lock status.
5327 * \param demod: instance of demod.
5328 * \param channel: pointer to channel data.
5329 * \return DRXStatus_t.
5332 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5335 u16 Result[2] = { 0, 0 };
5338 *pLockStatus = NOT_LOCKED;
5339 status = scu_command(state,
5340 SCU_RAM_COMMAND_STANDARD_QAM |
5341 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5344 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5346 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5347 /* 0x0000 NOT LOCKED */
5348 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5349 /* 0x4000 DEMOD LOCKED */
5350 *pLockStatus = DEMOD_LOCK;
5351 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5352 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5353 *pLockStatus = MPEG_LOCK;
5355 /* 0xC000 NEVER LOCKED */
5356 /* (system will never be able to lock to the signal) */
5357 /* TODO: check this, intermediate & standard specific lock states are not
5358 taken into account here */
5359 *pLockStatus = NEVER_LOCK;
5364 #define QAM_MIRROR__M 0x03
5365 #define QAM_MIRROR_NORMAL 0x00
5366 #define QAM_MIRRORED 0x01
5367 #define QAM_MIRROR_AUTO_ON 0x02
5368 #define QAM_LOCKRANGE__M 0x10
5369 #define QAM_LOCKRANGE_NORMAL 0x10
5371 static int QAMDemodulatorCommand(struct drxk_state *state,
5372 int numberOfParameters)
5376 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5378 setParamParameters[0] = state->m_Constellation; /* modulation */
5379 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5381 if (numberOfParameters == 2) {
5382 u16 setEnvParameters[1] = { 0 };
5384 if (state->m_OperationMode == OM_QAM_ITU_C)
5385 setEnvParameters[0] = QAM_TOP_ANNEX_C;
5387 setEnvParameters[0] = QAM_TOP_ANNEX_A;
5389 status = scu_command(state,
5390 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5391 1, setEnvParameters, 1, &cmdResult);
5395 status = scu_command(state,
5396 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5397 numberOfParameters, setParamParameters,
5399 } else if (numberOfParameters == 4) {
5400 if (state->m_OperationMode == OM_QAM_ITU_C)
5401 setParamParameters[2] = QAM_TOP_ANNEX_C;
5403 setParamParameters[2] = QAM_TOP_ANNEX_A;
5405 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5406 /* Env parameters */
5407 /* check for LOCKRANGE Extented */
5408 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5410 status = scu_command(state,
5411 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5412 numberOfParameters, setParamParameters,
5415 printk(KERN_WARNING "drxk: Unknown QAM demodulator parameter "
5416 "count %d\n", numberOfParameters);
5422 printk(KERN_WARNING "drxk: Warning %d on %s\n",
5427 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5428 s32 tunerFreqOffset)
5432 int qamDemodParamCount = state->qam_demod_parameter_count;
5436 * STEP 1: reset demodulator
5437 * resets FEC DI and FEC RS
5439 * resets SCU variables
5441 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5444 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5447 status = QAMResetQAM(state);
5452 * STEP 2: configure demodulator
5453 * -set params; resets IQM,QAM,FEC HW; initializes some
5456 status = QAMSetSymbolrate(state);
5461 switch (state->props.modulation) {
5463 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5467 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5470 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5473 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5476 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5485 /* Use the 4-parameter if it's requested or we're probing for
5486 * the correct command. */
5487 if (state->qam_demod_parameter_count == 4
5488 || !state->qam_demod_parameter_count) {
5489 qamDemodParamCount = 4;
5490 status = QAMDemodulatorCommand(state, qamDemodParamCount);
5493 /* Use the 2-parameter command if it was requested or if we're
5494 * probing for the correct command and the 4-parameter command
5496 if (state->qam_demod_parameter_count == 2
5497 || (!state->qam_demod_parameter_count && status < 0)) {
5498 qamDemodParamCount = 2;
5499 status = QAMDemodulatorCommand(state, qamDemodParamCount);
5503 dprintk(1, "Could not set demodulator parameters. Make "
5504 "sure qam_demod_parameter_count (%d) is correct for "
5505 "your firmware (%s).\n",
5506 state->qam_demod_parameter_count,
5507 state->microcode_name);
5509 } else if (!state->qam_demod_parameter_count) {
5510 dprintk(1, "Auto-probing the correct QAM demodulator command "
5511 "parameters was successful - using %d parameters.\n",
5512 qamDemodParamCount);
5515 * One of our commands was successful. We don't need to
5516 * auto-probe anymore, now that we got the correct command.
5518 state->qam_demod_parameter_count = qamDemodParamCount;
5522 * STEP 3: enable the system in a mode where the ADC provides valid
5523 * signal setup modulation independent registers
5526 status = SetFrequency(channel, tunerFreqOffset));
5530 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5534 /* Setup BER measurement */
5535 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5539 /* Reset default values */
5540 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5543 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5547 /* Reset default LC values */
5548 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5551 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5554 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5557 status = write16(state, QAM_LC_MODE__A, 7);
5561 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5564 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5567 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5570 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5573 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5576 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5579 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5582 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5585 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5588 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5591 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5594 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5597 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5600 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5603 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5607 /* Mirroring, QAM-block starting point not inverted */
5608 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5612 /* Halt SCU to enable safe non-atomic accesses */
5613 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5617 /* STEP 4: modulation specific setup */
5618 switch (state->props.modulation) {
5620 status = SetQAM16(state);
5623 status = SetQAM32(state);
5627 status = SetQAM64(state);
5630 status = SetQAM128(state);
5633 status = SetQAM256(state);
5642 /* Activate SCU to enable SCU commands */
5643 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5647 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5648 /* extAttr->currentChannel.modulation = channel->modulation; */
5649 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5650 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5654 /* Start processes */
5655 status = MPEGTSStart(state);
5658 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5661 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5664 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5668 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5669 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5673 /* update global DRXK data container */
5674 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5678 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5682 static int SetQAMStandard(struct drxk_state *state,
5683 enum OperationMode oMode)
5686 #ifdef DRXK_QAM_TAPS
5687 #define DRXK_QAMA_TAPS_SELECT
5688 #include "drxk_filters.h"
5689 #undef DRXK_QAMA_TAPS_SELECT
5694 /* added antenna switch */
5695 SwitchAntennaToQAM(state);
5697 /* Ensure correct power-up mode */
5698 status = PowerUpQAM(state);
5701 /* Reset QAM block */
5702 status = QAMResetQAM(state);
5708 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5711 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5715 /* Upload IQM Channel Filter settings by
5716 boot loader from ROM table */
5719 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5722 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5725 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5733 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5736 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5739 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5743 status = write16(state, IQM_RC_STRETCH__A, 21);
5746 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5749 status = write16(state, IQM_AF_CLP_TH__A, 448);
5752 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5755 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5759 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5762 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5765 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5768 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5772 /* IQM Impulse Noise Processing Unit */
5773 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5776 status = write16(state, IQM_CF_DATATH__A, 1000);
5779 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5782 status = write16(state, IQM_CF_DET_LCT__A, 0);
5785 status = write16(state, IQM_CF_WND_LEN__A, 1);
5788 status = write16(state, IQM_CF_PKDTH__A, 1);
5791 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5795 /* turn on IQMAF. Must be done before setAgc**() */
5796 status = SetIqmAf(state, true);
5799 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5803 /* IQM will not be reset from here, sync ADC and update/init AGC */
5804 status = ADCSynchronization(state);
5808 /* Set the FSM step period */
5809 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5813 /* Halt SCU to enable safe non-atomic accesses */
5814 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5818 /* No more resets of the IQM, current standard correctly set =>
5819 now AGCs can be configured. */
5821 status = InitAGC(state, true);
5824 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5828 /* Configure AGC's */
5829 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5832 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5836 /* Activate SCU to enable SCU commands */
5837 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5840 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5844 static int WriteGPIO(struct drxk_state *state)
5850 /* stop lock indicator process */
5851 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5855 /* Write magic word to enable pdr reg write */
5856 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5860 if (state->m_hasSAWSW) {
5861 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5862 /* write to io pad configuration register - output mode */
5863 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5867 /* use corresponding bit in io data output registar */
5868 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5871 if ((state->m_GPIO & 0x0001) == 0)
5872 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5874 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5875 /* write back to io data output register */
5876 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5880 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5881 /* write to io pad configuration register - output mode */
5882 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg);
5886 /* use corresponding bit in io data output registar */
5887 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5890 if ((state->m_GPIO & 0x0002) == 0)
5891 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5893 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5894 /* write back to io data output register */
5895 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5899 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5900 /* write to io pad configuration register - output mode */
5901 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg);
5905 /* use corresponding bit in io data output registar */
5906 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5909 if ((state->m_GPIO & 0x0004) == 0)
5910 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5912 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5913 /* write back to io data output register */
5914 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5919 /* Write magic word to disable pdr reg write */
5920 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5923 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5927 static int SwitchAntennaToQAM(struct drxk_state *state)
5934 if (!state->antenna_gpio)
5937 gpio_state = state->m_GPIO & state->antenna_gpio;
5939 if (state->antenna_dvbt ^ gpio_state) {
5940 /* Antenna is on DVB-T mode. Switch */
5941 if (state->antenna_dvbt)
5942 state->m_GPIO &= ~state->antenna_gpio;
5944 state->m_GPIO |= state->antenna_gpio;
5945 status = WriteGPIO(state);
5948 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5952 static int SwitchAntennaToDVBT(struct drxk_state *state)
5959 if (!state->antenna_gpio)
5962 gpio_state = state->m_GPIO & state->antenna_gpio;
5964 if (!(state->antenna_dvbt ^ gpio_state)) {
5965 /* Antenna is on DVB-C mode. Switch */
5966 if (state->antenna_dvbt)
5967 state->m_GPIO |= state->antenna_gpio;
5969 state->m_GPIO &= ~state->antenna_gpio;
5970 status = WriteGPIO(state);
5973 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5978 static int PowerDownDevice(struct drxk_state *state)
5980 /* Power down to requested mode */
5981 /* Backup some register settings */
5982 /* Set pins with possible pull-ups connected to them in input mode */
5983 /* Analog power down */
5984 /* ADC power down */
5985 /* Power down device */
5989 if (state->m_bPDownOpenBridge) {
5990 /* Open I2C bridge before power down of DRXK */
5991 status = ConfigureI2CBridge(state, true);
5996 status = DVBTEnableOFDMTokenRing(state, false);
6000 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
6003 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6006 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6007 status = HI_CfgCommand(state);
6010 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6015 static int init_drxk(struct drxk_state *state)
6017 int status = 0, n = 0;
6018 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
6022 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
6023 drxk_i2c_lock(state);
6024 status = PowerUpDevice(state);
6027 status = DRXX_Open(state);
6030 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6031 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
6034 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6037 /* TODO is this needed, if yes how much delay in worst case scenario */
6039 state->m_DRXK_A3_PATCH_CODE = true;
6040 status = GetDeviceCapabilities(state);
6044 /* Bridge delay, uses oscilator clock */
6045 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6046 /* SDA brdige delay */
6047 state->m_HICfgBridgeDelay =
6048 (u16) ((state->m_oscClockFreq / 1000) *
6049 HI_I2C_BRIDGE_DELAY) / 1000;
6051 if (state->m_HICfgBridgeDelay >
6052 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6053 state->m_HICfgBridgeDelay =
6054 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6056 /* SCL bridge delay, same as SDA for now */
6057 state->m_HICfgBridgeDelay +=
6058 state->m_HICfgBridgeDelay <<
6059 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6061 status = InitHI(state);
6064 /* disable various processes */
6066 if (!(state->m_DRXK_A1_ROM_CODE)
6067 && !(state->m_DRXK_A2_ROM_CODE))
6070 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6075 /* disable MPEG port */
6076 status = MPEGTSDisable(state);
6080 /* Stop AUD and SCU */
6081 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6084 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6088 /* enable token-ring bus through OFDM block for possible ucode upload */
6089 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6093 /* include boot loader section */
6094 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6097 status = BLChainCmd(state, 0, 6, 100);
6102 status = DownloadMicrocode(state, state->fw->data,
6108 /* disable token-ring bus through OFDM block for possible ucode upload */
6109 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6113 /* Run SCU for a little while to initialize microcode version numbers */
6114 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6117 status = DRXX_Open(state);
6120 /* added for test */
6123 powerMode = DRXK_POWER_DOWN_OFDM;
6124 status = CtrlPowerMode(state, &powerMode);
6128 /* Stamp driver version number in SCU data RAM in BCD code
6129 Done to enable field application engineers to retreive drxdriver version
6130 via I2C from SCU RAM.
6131 Not using SCU command interface for SCU register access since no
6132 microcode may be present.
6135 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6136 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6137 ((DRXK_VERSION_MAJOR % 10) << 4) +
6138 (DRXK_VERSION_MINOR % 10);
6139 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6143 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6144 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6145 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6146 (DRXK_VERSION_PATCH % 10);
6147 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6151 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6152 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6153 DRXK_VERSION_PATCH);
6155 /* Dirty fix of default values for ROM/PATCH microcode
6156 Dirty because this fix makes it impossible to setup suitable values
6157 before calling DRX_Open. This solution requires changes to RF AGC speed
6158 to be done via the CTRL function after calling DRX_Open */
6160 /* m_dvbtRfAgcCfg.speed = 3; */
6162 /* Reset driver debug flags to 0 */
6163 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6168 NOTE: No more full FEC resets allowed afterwards!! */
6169 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6172 /* MPEGTS functions are still the same */
6173 status = MPEGTSDtoInit(state);
6176 status = MPEGTSStop(state);
6179 status = MPEGTSConfigurePolarity(state);
6182 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6185 /* added: configure GPIO */
6186 status = WriteGPIO(state);
6190 state->m_DrxkState = DRXK_STOPPED;
6192 if (state->m_bPowerDown) {
6193 status = PowerDownDevice(state);
6196 state->m_DrxkState = DRXK_POWERED_DOWN;
6198 state->m_DrxkState = DRXK_STOPPED;
6200 /* Initialize the supported delivery systems */
6202 if (state->m_hasDVBC) {
6203 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6204 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6205 strlcat(state->frontend.ops.info.name, " DVB-C",
6206 sizeof(state->frontend.ops.info.name));
6208 if (state->m_hasDVBT) {
6209 state->frontend.ops.delsys[n++] = SYS_DVBT;
6210 strlcat(state->frontend.ops.info.name, " DVB-T",
6211 sizeof(state->frontend.ops.info.name));
6213 drxk_i2c_unlock(state);
6217 state->m_DrxkState = DRXK_NO_DEV;
6218 drxk_i2c_unlock(state);
6219 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6225 static void load_firmware_cb(const struct firmware *fw,
6228 struct drxk_state *state = context;
6230 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6233 "drxk: Could not load firmware file %s.\n",
6234 state->microcode_name);
6236 "drxk: Copy %s to your hotplug directory!\n",
6237 state->microcode_name);
6238 state->microcode_name = NULL;
6241 * As firmware is now load asynchronous, it is not possible
6242 * anymore to fail at frontend attach. We might silently
6243 * return here, and hope that the driver won't crash.
6244 * We might also change all DVB callbacks to return -ENODEV
6245 * if the device is not initialized.
6246 * As the DRX-K devices have their own internal firmware,
6247 * let's just hope that it will match a firmware revision
6248 * compatible with this driver and proceed.
6256 static void drxk_release(struct dvb_frontend *fe)
6258 struct drxk_state *state = fe->demodulator_priv;
6262 release_firmware(state->fw);
6267 static int drxk_sleep(struct dvb_frontend *fe)
6269 struct drxk_state *state = fe->demodulator_priv;
6273 if (state->m_DrxkState == DRXK_NO_DEV)
6275 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6282 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6284 struct drxk_state *state = fe->demodulator_priv;
6286 dprintk(1, ": %s\n", enable ? "enable" : "disable");
6288 if (state->m_DrxkState == DRXK_NO_DEV)
6291 return ConfigureI2CBridge(state, enable ? true : false);
6294 static int drxk_set_parameters(struct dvb_frontend *fe)
6296 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6297 u32 delsys = p->delivery_system, old_delsys;
6298 struct drxk_state *state = fe->demodulator_priv;
6303 if (state->m_DrxkState == DRXK_NO_DEV)
6306 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6309 if (!fe->ops.tuner_ops.get_if_frequency) {
6311 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6315 if (fe->ops.i2c_gate_ctrl)
6316 fe->ops.i2c_gate_ctrl(fe, 1);
6317 if (fe->ops.tuner_ops.set_params)
6318 fe->ops.tuner_ops.set_params(fe);
6319 if (fe->ops.i2c_gate_ctrl)
6320 fe->ops.i2c_gate_ctrl(fe, 0);
6322 old_delsys = state->props.delivery_system;
6325 if (old_delsys != delsys) {
6328 case SYS_DVBC_ANNEX_A:
6329 case SYS_DVBC_ANNEX_C:
6330 if (!state->m_hasDVBC)
6332 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6333 if (state->m_itut_annex_c)
6334 SetOperationMode(state, OM_QAM_ITU_C);
6336 SetOperationMode(state, OM_QAM_ITU_A);
6339 if (!state->m_hasDVBT)
6341 SetOperationMode(state, OM_DVBT);
6348 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6349 Start(state, 0, IF);
6351 /* After set_frontend, stats aren't avaliable */
6352 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6353 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6354 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6355 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6356 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6357 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6358 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6359 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6361 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6366 static int get_strength(struct drxk_state *state, u64 *strength)
6369 struct SCfgAgc rfAgc, ifAgc;
6375 /* FIXME: those are part of the tuner presets */
6376 u16 tunerRfGain = 50; /* Default value on az6007 driver */
6377 u16 tunerIfGain = 40; /* Default value on az6007 driver */
6381 if (IsDVBT(state)) {
6382 rfAgc = state->m_dvbtRfAgcCfg;
6383 ifAgc = state->m_dvbtIfAgcCfg;
6384 } else if (IsQAM(state)) {
6385 rfAgc = state->m_qamRfAgcCfg;
6386 ifAgc = state->m_qamIfAgcCfg;
6388 rfAgc = state->m_atvRfAgcCfg;
6389 ifAgc = state->m_atvIfAgcCfg;
6392 if (rfAgc.ctrlMode == DRXK_AGC_CTRL_AUTO) {
6393 /* SCU outputLevel */
6394 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6399 read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6403 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6404 rfAgc.outputLevel = scu_lvl + scu_coc;
6406 rfAgc.outputLevel = 0xffff;
6408 /* Take RF gain into account */
6409 totalGain += tunerRfGain;
6411 /* clip output value */
6412 if (rfAgc.outputLevel < rfAgc.minOutputLevel)
6413 rfAgc.outputLevel = rfAgc.minOutputLevel;
6414 if (rfAgc.outputLevel > rfAgc.maxOutputLevel)
6415 rfAgc.outputLevel = rfAgc.maxOutputLevel;
6417 agcRange = (u32) (rfAgc.maxOutputLevel - rfAgc.minOutputLevel);
6420 ((u32)(tunerRfGain)) *
6421 ((u32)(rfAgc.outputLevel - rfAgc.minOutputLevel))
6426 if (ifAgc.ctrlMode == DRXK_AGC_CTRL_AUTO) {
6427 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6428 &ifAgc.outputLevel);
6432 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6437 /* Take IF gain into account */
6438 totalGain += (u32) tunerIfGain;
6440 /* clip output value */
6441 if (ifAgc.outputLevel < ifAgc.minOutputLevel)
6442 ifAgc.outputLevel = ifAgc.minOutputLevel;
6443 if (ifAgc.outputLevel > ifAgc.maxOutputLevel)
6444 ifAgc.outputLevel = ifAgc.maxOutputLevel;
6446 agcRange = (u32) (ifAgc.maxOutputLevel - ifAgc.minOutputLevel);
6449 ((u32)(tunerIfGain)) *
6450 ((u32)(ifAgc.outputLevel - ifAgc.minOutputLevel))
6456 * Convert to 0..65535 scale.
6457 * If it can't be measured (AGC is disabled), just show 100%.
6460 *strength = (65535UL * atten / totalGain / 100);
6467 static int drxk_get_stats(struct dvb_frontend *fe)
6469 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6470 struct drxk_state *state = fe->demodulator_priv;
6475 u32 post_bit_err_count;
6476 u32 post_bit_error_scale;
6477 u32 pre_bit_err_count;
6480 u32 pkt_error_count;
6483 if (state->m_DrxkState == DRXK_NO_DEV)
6485 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6489 state->fe_status = 0;
6490 GetLockStatus(state, &stat);
6491 if (stat == MPEG_LOCK)
6492 state->fe_status |= 0x1f;
6493 if (stat == FEC_LOCK)
6494 state->fe_status |= 0x0f;
6495 if (stat == DEMOD_LOCK)
6496 state->fe_status |= 0x07;
6499 * Estimate signal strength from AGC
6501 get_strength(state, &c->strength.stat[0].uvalue);
6502 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6505 if (stat >= DEMOD_LOCK) {
6506 GetSignalToNoise(state, &cnr);
6507 c->cnr.stat[0].svalue = cnr * 100;
6508 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6510 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6513 if (stat < FEC_LOCK) {
6514 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6515 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6516 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6517 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6518 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6519 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6525 /* BER measurement is valid if at least FEC lock is achieved */
6527 /* OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be written
6528 to set nr of symbols or bits over which
6529 to measure EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). */
6531 /* Read registers for post/preViterbi BER calculation */
6532 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6535 pre_bit_err_count = reg16;
6537 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6540 pre_bit_count = reg16;
6542 /* Number of bit-errors */
6543 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6546 post_bit_err_count = reg16;
6548 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6551 post_bit_error_scale = reg16;
6553 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6558 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6561 pkt_error_count = reg16;
6562 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6564 post_bit_err_count *= post_bit_error_scale;
6566 post_bit_count = pkt_count * 204 * 8;
6568 /* Store the results */
6569 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6570 c->block_error.stat[0].uvalue += pkt_error_count;
6571 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6572 c->block_count.stat[0].uvalue += pkt_count;
6574 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6575 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6576 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6577 c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6579 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6580 c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6581 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6582 c->post_bit_count.stat[0].uvalue += post_bit_count;
6589 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6591 struct drxk_state *state = fe->demodulator_priv;
6596 rc = drxk_get_stats(fe);
6600 *status = state->fe_status;
6605 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6608 struct drxk_state *state = fe->demodulator_priv;
6609 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6613 if (state->m_DrxkState == DRXK_NO_DEV)
6615 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6618 *strength = c->strength.stat[0].uvalue;
6622 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6624 struct drxk_state *state = fe->demodulator_priv;
6629 if (state->m_DrxkState == DRXK_NO_DEV)
6631 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6634 GetSignalToNoise(state, &snr2);
6636 /* No negative SNR, clip to zero */
6639 *snr = snr2 & 0xffff;
6643 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6645 struct drxk_state *state = fe->demodulator_priv;
6650 if (state->m_DrxkState == DRXK_NO_DEV)
6652 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6655 DVBTQAMGetAccPktErr(state, &err);
6656 *ucblocks = (u32) err;
6660 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6663 struct drxk_state *state = fe->demodulator_priv;
6664 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6668 if (state->m_DrxkState == DRXK_NO_DEV)
6670 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6673 switch (p->delivery_system) {
6674 case SYS_DVBC_ANNEX_A:
6675 case SYS_DVBC_ANNEX_C:
6677 sets->min_delay_ms = 3000;
6678 sets->max_drift = 0;
6679 sets->step_size = 0;
6686 static struct dvb_frontend_ops drxk_ops = {
6687 /* .delsys will be filled dynamically */
6690 .frequency_min = 47000000,
6691 .frequency_max = 865000000,
6693 .symbol_rate_min = 870000,
6694 .symbol_rate_max = 11700000,
6696 .frequency_stepsize = 166667,
6698 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6699 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6700 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6701 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6702 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6703 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6706 .release = drxk_release,
6707 .sleep = drxk_sleep,
6708 .i2c_gate_ctrl = drxk_gate_ctrl,
6710 .set_frontend = drxk_set_parameters,
6711 .get_tune_settings = drxk_get_tune_settings,
6713 .read_status = drxk_read_status,
6714 .read_signal_strength = drxk_read_signal_strength,
6715 .read_snr = drxk_read_snr,
6716 .read_ucblocks = drxk_read_ucblocks,
6719 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6720 struct i2c_adapter *i2c)
6722 struct dtv_frontend_properties *p;
6723 struct drxk_state *state = NULL;
6724 u8 adr = config->adr;
6728 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6733 state->demod_address = adr;
6734 state->single_master = config->single_master;
6735 state->microcode_name = config->microcode_name;
6736 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6737 state->no_i2c_bridge = config->no_i2c_bridge;
6738 state->antenna_gpio = config->antenna_gpio;
6739 state->antenna_dvbt = config->antenna_dvbt;
6740 state->m_ChunkSize = config->chunk_size;
6741 state->enable_merr_cfg = config->enable_merr_cfg;
6743 if (config->dynamic_clk) {
6744 state->m_DVBTStaticCLK = 0;
6745 state->m_DVBCStaticCLK = 0;
6747 state->m_DVBTStaticCLK = 1;
6748 state->m_DVBCStaticCLK = 1;
6752 if (config->mpeg_out_clk_strength)
6753 state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07;
6755 state->m_TSClockkStrength = 0x06;
6757 if (config->parallel_ts)
6758 state->m_enableParallel = true;
6760 state->m_enableParallel = false;
6762 /* NOTE: as more UIO bits will be used, add them to the mask */
6763 state->UIO_mask = config->antenna_gpio;
6765 /* Default gpio to DVB-C */
6766 if (!state->antenna_dvbt && state->antenna_gpio)
6767 state->m_GPIO |= state->antenna_gpio;
6769 state->m_GPIO &= ~state->antenna_gpio;
6771 mutex_init(&state->mutex);
6773 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6774 state->frontend.demodulator_priv = state;
6778 /* Load firmware and initialize DRX-K */
6779 if (state->microcode_name) {
6780 if (config->load_firmware_sync) {
6781 const struct firmware *fw = NULL;
6783 status = request_firmware(&fw, state->microcode_name,
6784 state->i2c->dev.parent);
6787 load_firmware_cb(fw, state);
6789 status = request_firmware_nowait(THIS_MODULE, 1,
6790 state->microcode_name,
6791 state->i2c->dev.parent,
6793 state, load_firmware_cb);
6796 "drxk: failed to request a firmware\n");
6800 } else if (init_drxk(state) < 0)
6804 /* Initialize stats */
6805 p = &state->frontend.dtv_property_cache;
6806 p->strength.len = 1;
6808 p->block_error.len = 1;
6809 p->block_count.len = 1;
6810 p->pre_bit_error.len = 1;
6811 p->pre_bit_count.len = 1;
6812 p->post_bit_error.len = 1;
6813 p->post_bit_count.len = 1;
6815 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6816 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6817 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6818 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6819 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6820 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6821 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6822 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6824 printk(KERN_INFO "drxk: frontend initialized.\n");
6825 return &state->frontend;
6828 printk(KERN_ERR "drxk: not found\n");
6832 EXPORT_SYMBOL(drxk_attach);
6834 MODULE_DESCRIPTION("DRX-K driver");
6835 MODULE_AUTHOR("Ralph Metzler");
6836 MODULE_LICENSE("GPL");