2 Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
3 Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
5 Copyright (C) 2009 TurboSight.com
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/slab.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/firmware.h>
29 #include "dvb_frontend.h"
34 #define dprintk(args...) \
40 /* as of March 2009 current DS3000 firmware version is 1.78 */
41 /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
42 #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
44 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
45 #define DS3000_XTAL_FREQ 27000 /* in kHz */
47 /* Register values to initialise the demod in DVB-S mode */
48 static u8 ds3000_dvbs_init_tab[] = {
132 /* Register values to initialise the demod in DVB-S2 mode */
133 static u8 ds3000_dvbs2_init_tab[] = {
232 struct ds3000_state {
233 struct i2c_adapter *i2c;
234 const struct ds3000_config *config;
235 struct dvb_frontend frontend;
236 /* previous uncorrected block counter for DVB-S2 */
240 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
242 u8 buf[] = { reg, data };
243 struct i2c_msg msg = { .addr = state->config->demod_address,
244 .flags = 0, .buf = buf, .len = 2 };
247 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
249 err = i2c_transfer(state->i2c, &msg, 1);
251 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
252 " value == 0x%02x)\n", __func__, err, reg, data);
259 static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
261 u8 buf[] = { reg, data };
262 struct i2c_msg msg = { .addr = 0x60,
263 .flags = 0, .buf = buf, .len = 2 };
266 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
268 ds3000_writereg(state, 0x03, 0x11);
269 err = i2c_transfer(state->i2c, &msg, 1);
271 printk("%s: writereg error(err == %i, reg == 0x%02x,"
272 " value == 0x%02x)\n", __func__, err, reg, data);
279 /* I2C write for 8k firmware load */
280 static int ds3000_writeFW(struct ds3000_state *state, int reg,
281 const u8 *data, u16 len)
283 int i, ret = -EREMOTEIO;
287 buf = kmalloc(33, GFP_KERNEL);
289 printk(KERN_ERR "Unable to kmalloc\n");
296 msg.addr = state->config->demod_address;
301 for (i = 0; i < len; i += 32) {
302 memcpy(buf + 1, data + i, 32);
304 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
306 ret = i2c_transfer(state->i2c, &msg, 1);
308 printk(KERN_ERR "%s: write error(err == %i, "
309 "reg == 0x%02x\n", __func__, ret, reg);
320 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
325 struct i2c_msg msg[] = {
327 .addr = state->config->demod_address,
332 .addr = state->config->demod_address,
339 ret = i2c_transfer(state->i2c, msg, 2);
342 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
346 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
351 static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
356 struct i2c_msg msg[] = {
370 ds3000_writereg(state, 0x03, 0x12);
371 ret = i2c_transfer(state->i2c, msg, 2);
374 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
378 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
383 static int ds3000_load_firmware(struct dvb_frontend *fe,
384 const struct firmware *fw);
386 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
388 struct ds3000_state *state = fe->demodulator_priv;
389 const struct firmware *fw;
392 dprintk("%s()\n", __func__);
394 ret = ds3000_readreg(state, 0xb2);
399 /* request the firmware, this will block until someone uploads it */
400 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
401 DS3000_DEFAULT_FIRMWARE);
402 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
403 state->i2c->dev.parent);
404 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
406 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
407 "found?)\n", __func__);
411 ret = ds3000_load_firmware(fe, fw);
413 printk("%s: Writing firmware to device failed\n", __func__);
415 release_firmware(fw);
417 dprintk("%s: Firmware upload %s\n", __func__,
418 ret == 0 ? "complete" : "failed");
423 static int ds3000_load_firmware(struct dvb_frontend *fe,
424 const struct firmware *fw)
426 struct ds3000_state *state = fe->demodulator_priv;
428 dprintk("%s\n", __func__);
429 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
433 fw->data[fw->size - 2],
434 fw->data[fw->size - 1]);
436 /* Begin the firmware load process */
437 ds3000_writereg(state, 0xb2, 0x01);
438 /* write the entire firmware */
439 ds3000_writeFW(state, 0xb0, fw->data, fw->size);
440 ds3000_writereg(state, 0xb2, 0x00);
445 static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
447 struct ds3000_state *state = fe->demodulator_priv;
450 dprintk("%s(%d)\n", __func__, voltage);
452 data = ds3000_readreg(state, 0xa2);
453 data |= 0x03; /* bit0 V/H, bit1 off/on */
463 case SEC_VOLTAGE_OFF:
467 ds3000_writereg(state, 0xa2, data);
472 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
474 struct ds3000_state *state = fe->demodulator_priv;
475 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
480 switch (c->delivery_system) {
482 lock = ds3000_readreg(state, 0xd1);
483 if ((lock & 0x07) == 0x07)
484 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
485 FE_HAS_VITERBI | FE_HAS_SYNC |
490 lock = ds3000_readreg(state, 0x0d);
491 if ((lock & 0x8f) == 0x8f)
492 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
493 FE_HAS_VITERBI | FE_HAS_SYNC |
501 dprintk("%s: status = 0x%02x\n", __func__, lock);
506 /* read DS3000 BER value */
507 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
509 struct ds3000_state *state = fe->demodulator_priv;
510 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
512 u32 ber_reading, lpdc_frames;
514 dprintk("%s()\n", __func__);
516 switch (c->delivery_system) {
518 /* set the number of bytes checked during
520 ds3000_writereg(state, 0xf9, 0x04);
521 /* read BER estimation status */
522 data = ds3000_readreg(state, 0xf8);
523 /* check if BER estimation is ready */
524 if ((data & 0x10) == 0) {
525 /* this is the number of error bits,
526 to calculate the bit error rate
528 *ber = (ds3000_readreg(state, 0xf7) << 8) |
529 ds3000_readreg(state, 0xf6);
530 /* start counting error bits */
531 /* need to be set twice
532 otherwise it fails sometimes */
534 ds3000_writereg(state, 0xf8, data);
535 ds3000_writereg(state, 0xf8, data);
537 /* used to indicate that BER estimation
538 is not ready, i.e. BER is unknown */
542 /* read the number of LPDC decoded frames */
543 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
544 (ds3000_readreg(state, 0xd6) << 8) |
545 ds3000_readreg(state, 0xd5);
546 /* read the number of packets with bad CRC */
547 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
548 ds3000_readreg(state, 0xf7);
549 if (lpdc_frames > 750) {
550 /* clear LPDC frame counters */
551 ds3000_writereg(state, 0xd1, 0x01);
552 /* clear bad packets counter */
553 ds3000_writereg(state, 0xf9, 0x01);
554 /* enable bad packets counter */
555 ds3000_writereg(state, 0xf9, 0x00);
556 /* enable LPDC frame counters */
557 ds3000_writereg(state, 0xd1, 0x00);
560 /* used to indicate that BER estimation is not ready,
561 i.e. BER is unknown */
571 /* read TS2020 signal strength */
572 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
573 u16 *signal_strength)
575 struct ds3000_state *state = fe->demodulator_priv;
576 u16 sig_reading, sig_strength;
579 dprintk("%s()\n", __func__);
581 rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
582 bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
589 sig_reading = rfgain * 2 + bbgain * 3;
591 sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
593 /* cook the value to be suitable for szap-s2 human readable output */
594 *signal_strength = sig_strength * 1000;
596 dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
597 sig_reading, *signal_strength);
602 /* calculate DS3000 snr value in dB */
603 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
605 struct ds3000_state *state = fe->demodulator_priv;
606 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
607 u8 snr_reading, snr_value;
608 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
609 static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
610 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
611 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
612 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
614 static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
615 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
616 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
617 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
618 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
619 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
620 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
621 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
622 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
623 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
624 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
625 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
626 0x49e9, 0x4a20, 0x4a57
629 dprintk("%s()\n", __func__);
631 switch (c->delivery_system) {
633 snr_reading = ds3000_readreg(state, 0xff);
635 if (snr_reading == 0)
638 if (snr_reading > 20)
640 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
641 /* cook the value to be suitable for szap-s2
642 human readable output */
643 *snr = snr_value * 8 * 655;
645 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
649 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
650 (ds3000_readreg(state, 0x8d) << 4);
651 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
652 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
657 if (dvbs2_noise_reading == 0) {
659 /* cook the value to be suitable for szap-s2
660 human readable output */
664 if (tmp > dvbs2_noise_reading) {
665 snr_reading = tmp / dvbs2_noise_reading;
666 if (snr_reading > 80)
668 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
669 /* cook the value to be suitable for szap-s2
670 human readable output */
671 *snr = snr_value * 5 * 655;
673 snr_reading = dvbs2_noise_reading / tmp;
674 if (snr_reading > 80)
676 *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
678 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
688 /* read DS3000 uncorrected blocks */
689 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
691 struct ds3000_state *state = fe->demodulator_priv;
692 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
696 dprintk("%s()\n", __func__);
698 switch (c->delivery_system) {
700 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
701 ds3000_readreg(state, 0xf4);
702 data = ds3000_readreg(state, 0xf8);
703 /* clear packet counters */
705 ds3000_writereg(state, 0xf8, data);
706 /* enable packet counters */
708 ds3000_writereg(state, 0xf8, data);
711 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
712 ds3000_readreg(state, 0xe1);
713 if (_ucblocks > state->prevUCBS2)
714 *ucblocks = _ucblocks - state->prevUCBS2;
716 *ucblocks = state->prevUCBS2 - _ucblocks;
717 state->prevUCBS2 = _ucblocks;
726 static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
728 struct ds3000_state *state = fe->demodulator_priv;
731 dprintk("%s(%d)\n", __func__, tone);
732 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
733 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
737 data = ds3000_readreg(state, 0xa2);
739 ds3000_writereg(state, 0xa2, data);
743 dprintk("%s: setting tone on\n", __func__);
744 data = ds3000_readreg(state, 0xa1);
747 ds3000_writereg(state, 0xa1, data);
750 dprintk("%s: setting tone off\n", __func__);
751 data = ds3000_readreg(state, 0xa2);
753 ds3000_writereg(state, 0xa2, data);
760 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
761 struct dvb_diseqc_master_cmd *d)
763 struct ds3000_state *state = fe->demodulator_priv;
767 /* Dump DiSEqC message */
768 dprintk("%s(", __func__);
769 for (i = 0 ; i < d->msg_len;) {
770 dprintk("0x%02x", d->msg[i]);
771 if (++i < d->msg_len)
775 /* enable DiSEqC message send pin */
776 data = ds3000_readreg(state, 0xa2);
778 ds3000_writereg(state, 0xa2, data);
781 for (i = 0; i < d->msg_len; i++)
782 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
784 data = ds3000_readreg(state, 0xa1);
785 /* clear DiSEqC message length and status,
786 enable DiSEqC message send */
788 /* set DiSEqC mode, modulation active during 33 pulses,
789 set DiSEqC message length */
790 data |= ((d->msg_len - 1) << 3) | 0x07;
791 ds3000_writereg(state, 0xa1, data);
793 /* wait up to 150ms for DiSEqC transmission to complete */
794 for (i = 0; i < 15; i++) {
795 data = ds3000_readreg(state, 0xa1);
796 if ((data & 0x40) == 0)
801 /* DiSEqC timeout after 150ms */
803 data = ds3000_readreg(state, 0xa1);
806 ds3000_writereg(state, 0xa1, data);
808 data = ds3000_readreg(state, 0xa2);
811 ds3000_writereg(state, 0xa2, data);
816 data = ds3000_readreg(state, 0xa2);
819 ds3000_writereg(state, 0xa2, data);
824 /* Send DiSEqC burst */
825 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
826 fe_sec_mini_cmd_t burst)
828 struct ds3000_state *state = fe->demodulator_priv;
832 dprintk("%s()\n", __func__);
834 data = ds3000_readreg(state, 0xa2);
836 ds3000_writereg(state, 0xa2, data);
839 if (burst == SEC_MINI_A)
840 /* Unmodulated tone burst */
841 ds3000_writereg(state, 0xa1, 0x02);
842 else if (burst == SEC_MINI_B)
843 /* Modulated tone burst */
844 ds3000_writereg(state, 0xa1, 0x01);
849 for (i = 0; i < 5; i++) {
850 data = ds3000_readreg(state, 0xa1);
851 if ((data & 0x40) == 0)
857 data = ds3000_readreg(state, 0xa1);
860 ds3000_writereg(state, 0xa1, data);
862 data = ds3000_readreg(state, 0xa2);
865 ds3000_writereg(state, 0xa2, data);
870 data = ds3000_readreg(state, 0xa2);
873 ds3000_writereg(state, 0xa2, data);
878 static void ds3000_release(struct dvb_frontend *fe)
880 struct ds3000_state *state = fe->demodulator_priv;
881 dprintk("%s\n", __func__);
885 static struct dvb_frontend_ops ds3000_ops;
887 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
888 struct i2c_adapter *i2c)
890 struct ds3000_state *state = NULL;
893 dprintk("%s\n", __func__);
895 /* allocate memory for the internal state */
896 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
898 printk(KERN_ERR "Unable to kmalloc\n");
902 state->config = config;
904 state->prevUCBS2 = 0;
906 /* check if the demod is present */
907 ret = ds3000_readreg(state, 0x00) & 0xfe;
909 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
913 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
914 ds3000_readreg(state, 0x02),
915 ds3000_readreg(state, 0x01));
917 memcpy(&state->frontend.ops, &ds3000_ops,
918 sizeof(struct dvb_frontend_ops));
919 state->frontend.demodulator_priv = state;
920 return &state->frontend;
927 EXPORT_SYMBOL(ds3000_attach);
929 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
930 s32 carrier_offset_khz)
932 struct ds3000_state *state = fe->demodulator_priv;
935 tmp = carrier_offset_khz;
937 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
942 ds3000_writereg(state, 0x5f, tmp >> 8);
943 ds3000_writereg(state, 0x5e, tmp & 0xff);
948 static int ds3000_set_frontend(struct dvb_frontend *fe)
950 struct ds3000_state *state = fe->demodulator_priv;
951 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
955 u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4;
960 dprintk("%s() ", __func__);
962 if (state->config->set_ts_params)
963 state->config->set_ts_params(fe, 0);
966 ds3000_tuner_writereg(state, 0x07, 0x02);
967 ds3000_tuner_writereg(state, 0x10, 0x00);
968 ds3000_tuner_writereg(state, 0x60, 0x79);
969 ds3000_tuner_writereg(state, 0x08, 0x01);
970 ds3000_tuner_writereg(state, 0x00, 0x01);
973 /* calculate and set freq divider */
974 if (c->frequency < 1146000) {
975 ds3000_tuner_writereg(state, 0x10, 0x11);
977 ndiv = ((c->frequency * (6 + 8) * 4) +
978 (DS3000_XTAL_FREQ / 2)) /
979 DS3000_XTAL_FREQ - 1024;
981 ds3000_tuner_writereg(state, 0x10, 0x01);
982 ndiv = ((c->frequency * (6 + 8) * 2) +
983 (DS3000_XTAL_FREQ / 2)) /
984 DS3000_XTAL_FREQ - 1024;
987 ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
988 ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
991 ds3000_tuner_writereg(state, 0x03, 0x06);
992 ds3000_tuner_writereg(state, 0x51, 0x0f);
993 ds3000_tuner_writereg(state, 0x51, 0x1f);
994 ds3000_tuner_writereg(state, 0x50, 0x10);
995 ds3000_tuner_writereg(state, 0x50, 0x00);
999 ds3000_tuner_writereg(state, 0x51, 0x17);
1000 ds3000_tuner_writereg(state, 0x51, 0x1f);
1001 ds3000_tuner_writereg(state, 0x50, 0x08);
1002 ds3000_tuner_writereg(state, 0x50, 0x00);
1005 value = ds3000_tuner_readreg(state, 0x3d);
1007 if ((value > 4) && (value < 15)) {
1011 value = ((value << 3) | 0x01) & 0x79;
1014 ds3000_tuner_writereg(state, 0x60, value);
1015 ds3000_tuner_writereg(state, 0x51, 0x17);
1016 ds3000_tuner_writereg(state, 0x51, 0x1f);
1017 ds3000_tuner_writereg(state, 0x50, 0x08);
1018 ds3000_tuner_writereg(state, 0x50, 0x00);
1020 /* set low-pass filter period */
1021 ds3000_tuner_writereg(state, 0x04, 0x2e);
1022 ds3000_tuner_writereg(state, 0x51, 0x1b);
1023 ds3000_tuner_writereg(state, 0x51, 0x1f);
1024 ds3000_tuner_writereg(state, 0x50, 0x04);
1025 ds3000_tuner_writereg(state, 0x50, 0x00);
1028 f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000;
1029 if ((c->symbol_rate / 1000) < 5000)
1036 /* set low-pass filter baseband */
1037 value = ds3000_tuner_readreg(state, 0x26);
1038 mlpf = 0x2e * 207 / ((value << 1) + 151);
1039 mlpf_max = mlpf * 135 / 100;
1040 mlpf_min = mlpf * 78 / 100;
1044 /* rounded to the closest integer */
1045 nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
1046 / (2766 * DS3000_XTAL_FREQ);
1052 /* rounded to the closest integer */
1053 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1054 (1000 * f3db / 2)) / (1000 * f3db);
1056 if (mlpf_new < mlpf_min) {
1058 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1059 (1000 * f3db / 2)) / (1000 * f3db);
1062 if (mlpf_new > mlpf_max)
1063 mlpf_new = mlpf_max;
1065 ds3000_tuner_writereg(state, 0x04, mlpf_new);
1066 ds3000_tuner_writereg(state, 0x06, nlpf);
1067 ds3000_tuner_writereg(state, 0x51, 0x1b);
1068 ds3000_tuner_writereg(state, 0x51, 0x1f);
1069 ds3000_tuner_writereg(state, 0x50, 0x04);
1070 ds3000_tuner_writereg(state, 0x50, 0x00);
1074 ds3000_tuner_writereg(state, 0x51, 0x1e);
1075 ds3000_tuner_writereg(state, 0x51, 0x1f);
1076 ds3000_tuner_writereg(state, 0x50, 0x01);
1077 ds3000_tuner_writereg(state, 0x50, 0x00);
1080 offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
1081 / (6 + 8) / (div4 + 1) / 2 - c->frequency;
1083 /* ds3000 global reset */
1084 ds3000_writereg(state, 0x07, 0x80);
1085 ds3000_writereg(state, 0x07, 0x00);
1086 /* ds3000 build-in uC reset */
1087 ds3000_writereg(state, 0xb2, 0x01);
1088 /* ds3000 software reset */
1089 ds3000_writereg(state, 0x00, 0x01);
1091 switch (c->delivery_system) {
1093 /* initialise the demod in DVB-S mode */
1094 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
1095 ds3000_writereg(state,
1096 ds3000_dvbs_init_tab[i],
1097 ds3000_dvbs_init_tab[i + 1]);
1098 value = ds3000_readreg(state, 0xfe);
1101 ds3000_writereg(state, 0xfe, value);
1104 /* initialise the demod in DVB-S2 mode */
1105 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1106 ds3000_writereg(state,
1107 ds3000_dvbs2_init_tab[i],
1108 ds3000_dvbs2_init_tab[i + 1]);
1109 if (c->symbol_rate >= 30000000)
1110 ds3000_writereg(state, 0xfe, 0x54);
1112 ds3000_writereg(state, 0xfe, 0x98);
1118 /* enable 27MHz clock output */
1119 ds3000_writereg(state, 0x29, 0x80);
1120 /* enable ac coupling */
1121 ds3000_writereg(state, 0x25, 0x8a);
1123 /* enhance symbol rate performance */
1124 if ((c->symbol_rate / 1000) <= 5000) {
1125 value = 29777 / (c->symbol_rate / 1000) + 1;
1128 ds3000_writereg(state, 0xc3, 0x0d);
1129 ds3000_writereg(state, 0xc8, value);
1130 ds3000_writereg(state, 0xc4, 0x10);
1131 ds3000_writereg(state, 0xc7, 0x0e);
1132 } else if ((c->symbol_rate / 1000) <= 10000) {
1133 value = 92166 / (c->symbol_rate / 1000) + 1;
1136 ds3000_writereg(state, 0xc3, 0x07);
1137 ds3000_writereg(state, 0xc8, value);
1138 ds3000_writereg(state, 0xc4, 0x09);
1139 ds3000_writereg(state, 0xc7, 0x12);
1140 } else if ((c->symbol_rate / 1000) <= 20000) {
1141 value = 64516 / (c->symbol_rate / 1000) + 1;
1142 ds3000_writereg(state, 0xc3, value);
1143 ds3000_writereg(state, 0xc8, 0x0e);
1144 ds3000_writereg(state, 0xc4, 0x07);
1145 ds3000_writereg(state, 0xc7, 0x18);
1147 value = 129032 / (c->symbol_rate / 1000) + 1;
1148 ds3000_writereg(state, 0xc3, value);
1149 ds3000_writereg(state, 0xc8, 0x0a);
1150 ds3000_writereg(state, 0xc4, 0x05);
1151 ds3000_writereg(state, 0xc7, 0x24);
1154 /* normalized symbol rate rounded to the closest integer */
1155 value = (((c->symbol_rate / 1000) << 16) +
1156 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
1157 ds3000_writereg(state, 0x61, value & 0x00ff);
1158 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1160 /* co-channel interference cancellation disabled */
1161 ds3000_writereg(state, 0x56, 0x00);
1163 /* equalizer disabled */
1164 ds3000_writereg(state, 0x76, 0x00);
1166 /*ds3000_writereg(state, 0x08, 0x03);
1167 ds3000_writereg(state, 0xfd, 0x22);
1168 ds3000_writereg(state, 0x08, 0x07);
1169 ds3000_writereg(state, 0xfd, 0x42);
1170 ds3000_writereg(state, 0x08, 0x07);*/
1172 if (state->config->ci_mode) {
1173 switch (c->delivery_system) {
1176 ds3000_writereg(state, 0xfd, 0x80);
1179 ds3000_writereg(state, 0xfd, 0x01);
1184 /* ds3000 out of software reset */
1185 ds3000_writereg(state, 0x00, 0x00);
1186 /* start ds3000 build-in uC */
1187 ds3000_writereg(state, 0xb2, 0x00);
1189 ds3000_set_carrier_offset(fe, offset_khz);
1191 for (i = 0; i < 30 ; i++) {
1192 ds3000_read_status(fe, &status);
1193 if (status & FE_HAS_LOCK)
1202 static int ds3000_tune(struct dvb_frontend *fe,
1204 unsigned int mode_flags,
1205 unsigned int *delay,
1206 fe_status_t *status)
1209 int ret = ds3000_set_frontend(fe);
1216 return ds3000_read_status(fe, status);
1219 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1221 dprintk("%s()\n", __func__);
1222 return DVBFE_ALGO_HW;
1226 * Initialise or wake up device
1228 * Power config will reset and load initial firmware if required
1230 static int ds3000_initfe(struct dvb_frontend *fe)
1232 struct ds3000_state *state = fe->demodulator_priv;
1235 dprintk("%s()\n", __func__);
1237 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1241 ds3000_tuner_writereg(state, 0x42, 0x73);
1242 ds3000_tuner_writereg(state, 0x05, 0x01);
1243 ds3000_tuner_writereg(state, 0x62, 0xf5);
1244 /* Load the firmware if required */
1245 ret = ds3000_firmware_ondemand(fe);
1247 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1254 /* Put device to sleep */
1255 static int ds3000_sleep(struct dvb_frontend *fe)
1257 dprintk("%s()\n", __func__);
1261 static struct dvb_frontend_ops ds3000_ops = {
1262 .delsys = { SYS_DVBS, SYS_DVBS2},
1264 .name = "Montage Technology DS3000/TS2020",
1265 .frequency_min = 950000,
1266 .frequency_max = 2150000,
1267 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1268 .frequency_tolerance = 5000,
1269 .symbol_rate_min = 1000000,
1270 .symbol_rate_max = 45000000,
1271 .caps = FE_CAN_INVERSION_AUTO |
1272 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1273 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1274 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1275 FE_CAN_2G_MODULATION |
1276 FE_CAN_QPSK | FE_CAN_RECOVER
1279 .release = ds3000_release,
1281 .init = ds3000_initfe,
1282 .sleep = ds3000_sleep,
1283 .read_status = ds3000_read_status,
1284 .read_ber = ds3000_read_ber,
1285 .read_signal_strength = ds3000_read_signal_strength,
1286 .read_snr = ds3000_read_snr,
1287 .read_ucblocks = ds3000_read_ucblocks,
1288 .set_voltage = ds3000_set_voltage,
1289 .set_tone = ds3000_set_tone,
1290 .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1291 .diseqc_send_burst = ds3000_diseqc_send_burst,
1292 .get_frontend_algo = ds3000_get_algo,
1294 .set_frontend = ds3000_set_frontend,
1295 .tune = ds3000_tune,
1298 module_param(debug, int, 0644);
1299 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1301 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
1302 "DS3000/TS2020 hardware");
1303 MODULE_AUTHOR("Konstantin Dimitrov");
1304 MODULE_LICENSE("GPL");
1305 MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE);