2 * Driver for it913x-fe Frontend
4 * with support for on chip it9137 integral tuner
6 * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com)
7 * IT9137 Copyright (C) ITE Tech Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
30 #include "dvb_frontend.h"
31 #include "it913x-fe.h"
32 #include "it913x-fe-priv.h"
34 static int it913x_debug;
36 module_param_named(debug, it913x_debug, int, 0644);
37 MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
39 #define dprintk(level, args...) do { \
40 if (level & it913x_debug) \
41 printk(KERN_DEBUG "it913x-fe: " args); \
44 #define deb_info(args...) dprintk(0x01, args)
45 #define debug_data_snipet(level, name, p) \
46 dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \
47 *p, *(p+1), *(p+2), *(p+3), *(p+4), \
48 *(p+5), *(p+6), *(p+7));
49 #define info(format, arg...) \
50 printk(KERN_INFO "it913x-fe: " format "\n" , ## arg)
52 struct it913x_fe_state {
53 struct dvb_frontend frontend;
54 struct i2c_adapter *i2c_adap;
55 struct ite_config *config;
58 fe_modulation_t constellation;
59 fe_transmit_mode_t transmission_mode;
64 struct adctable *table;
65 fe_status_t it913x_status;
73 static int it913x_read_reg(struct it913x_fe_state *state,
74 u32 reg, u8 *data, u8 count)
77 u8 pro = PRO_DMOD; /* All reads from demodulator */
79 struct i2c_msg msg[2] = {
80 { .addr = state->i2c_addr + (pro << 1), .flags = 0,
81 .buf = b, .len = sizeof(b) },
82 { .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD,
83 .buf = data, .len = count }
85 b[0] = (u8) reg >> 24;
86 b[1] = (u8)(reg >> 16) & 0xff;
87 b[2] = (u8)(reg >> 8) & 0xff;
88 b[3] = (u8) reg & 0xff;
90 ret = i2c_transfer(state->i2c_adap, msg, 2);
95 static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg)
99 ret = it913x_read_reg(state, reg, &b[0], sizeof(b));
100 return (ret < 0) ? -ENODEV : b[0];
103 static int it913x_write(struct it913x_fe_state *state,
104 u8 pro, u32 reg, u8 buf[], u8 count)
107 struct i2c_msg msg[1] = {
108 { .addr = state->i2c_addr + (pro << 1), .flags = 0,
109 .buf = b, .len = count + 4 }
113 b[0] = (u8) reg >> 24;
114 b[1] = (u8)(reg >> 16) & 0xff;
115 b[2] = (u8)(reg >> 8) & 0xff;
116 b[3] = (u8) reg & 0xff;
117 memcpy(&b[4], buf, count);
119 ret = i2c_transfer(state->i2c_adap, msg, 1);
127 static int it913x_write_reg(struct it913x_fe_state *state,
128 u8 pro, u32 reg, u32 data)
135 b[1] = (data >> 16) & 0xff;
136 b[2] = (data >> 8) & 0xff;
138 /* expand write as needed */
141 else if (data < 0x1000)
143 else if (data < 0x100000)
148 ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s);
153 static int it913x_fe_script_loader(struct it913x_fe_state *state,
154 struct it913xset *loadscript)
157 if (loadscript == NULL)
160 for (i = 0; i < 1000; ++i) {
161 if (loadscript[i].pro == 0xff)
163 ret = it913x_write(state, loadscript[i].pro,
164 loadscript[i].address,
165 loadscript[i].reg, loadscript[i].count);
172 static int it913x_init_tuner(struct it913x_fe_state *state)
176 u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2};
179 reg = it913x_read_reg_u8(state, 0xec86);
182 state->tun_clk_mode = reg;
183 state->tun_xtal = 2000;
191 state->tun_clk_mode = reg;
192 state->tun_xtal = 640;
198 reg = it913x_read_reg_u8(state, 0xed03);
202 else if (reg < ARRAY_SIZE(nv))
207 for (i = 0; i < 50; i++) {
208 ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b));
209 reg = (b[1] << 8) + b[0];
216 state->tun_fn_min = state->tun_xtal * reg;
217 state->tun_fn_min /= (state->tun_fdiv * nv_val);
218 deb_info("Tuner fn_min %d", state->tun_fn_min);
220 if (state->config->chip_ver > 1)
223 for (i = 0; i < 50; i++) {
224 reg = it913x_read_reg_u8(state, 0xec82);
233 return it913x_write_reg(state, PRO_DMOD, 0xed81, val);
236 static int it9137_set_tuner(struct it913x_fe_state *state,
237 u32 bandwidth, u32 frequency_m)
239 struct it913xset *set_tuner = set_it9137_template;
241 u32 frequency = frequency_m / 1000;
242 u32 freq, temp_f, tmp;
250 if (state->config->firmware_ver == 1)
251 set_tuner = set_it9135_template;
253 set_tuner = set_it9137_template;
255 deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth);
257 if (frequency >= 51000 && frequency <= 440000) {
260 } else if (frequency > 440000 && frequency <= 484000) {
263 } else if (frequency > 484000 && frequency <= 533000) {
266 } else if (frequency > 533000 && frequency <= 587000) {
269 } else if (frequency > 587000 && frequency <= 645000) {
272 } else if (frequency > 645000 && frequency <= 710000) {
275 } else if (frequency > 710000 && frequency <= 782000) {
278 } else if (frequency > 782000 && frequency <= 860000) {
281 } else if (frequency > 1450000 && frequency <= 1492000) {
284 } else if (frequency > 1660000 && frequency <= 1685000) {
289 set_tuner[0].reg[0] = lna_band;
307 set_tuner[1].reg[0] = bw;
308 set_tuner[2].reg[0] = 0xa0 | (l_band << 3);
310 if (frequency > 53000 && frequency <= 74000) {
313 } else if (frequency > 74000 && frequency <= 111000) {
316 } else if (frequency > 111000 && frequency <= 148000) {
319 } else if (frequency > 148000 && frequency <= 222000) {
322 } else if (frequency > 222000 && frequency <= 296000) {
325 } else if (frequency > 296000 && frequency <= 445000) {
328 } else if (frequency > 445000 && frequency <= state->tun_fn_min) {
331 } else if (frequency > state->tun_fn_min && frequency <= 950000) {
334 } else if (frequency > 1450000 && frequency <= 1680000) {
340 reg = it913x_read_reg_u8(state, 0xed81);
341 iqik_m_cal = (u16)reg * n_div;
344 if (state->tun_clk_mode == 0)
345 iqik_m_cal = (iqik_m_cal * 9) >> 5;
349 iqik_m_cal = 0x40 - iqik_m_cal;
350 if (state->tun_clk_mode == 0)
351 iqik_m_cal = ~((iqik_m_cal * 9) >> 5);
353 iqik_m_cal = ~(iqik_m_cal >> 1);
356 temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv;
357 freq = temp_f / state->tun_xtal;
358 tmp = freq * state->tun_xtal;
360 if ((temp_f - tmp) >= (state->tun_xtal >> 1))
363 freq += (u32) n << 13;
364 /* Frequency OMEGA_IQIK_M_CAL_MID*/
365 temp_f = freq + (u32)iqik_m_cal;
367 set_tuner[3].reg[0] = temp_f & 0xff;
368 set_tuner[4].reg[0] = (temp_f >> 8) & 0xff;
370 deb_info("High Frequency = %04x", temp_f);
372 /* Lower frequency */
373 set_tuner[5].reg[0] = freq & 0xff;
374 set_tuner[6].reg[0] = (freq >> 8) & 0xff;
376 deb_info("low Frequency = %04x", freq);
378 ret = it913x_fe_script_loader(state, set_tuner);
380 return (ret < 0) ? -ENODEV : 0;
383 static int it913x_fe_select_bw(struct it913x_fe_state *state,
384 u32 bandwidth, u32 adcFrequency)
389 u16 bfsfcw_fftinx_ratio;
390 u16 fftinx_bfsfcw_ratio;
395 deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency);
412 ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw);
414 if (state->table == NULL)
418 coeff[0] = state->table[bw].coeff_1_2048;
419 coeff[1] = state->table[bw].coeff_2_2k;
420 coeff[2] = state->table[bw].coeff_1_8191;
421 coeff[3] = state->table[bw].coeff_1_8192;
422 coeff[4] = state->table[bw].coeff_1_8193;
423 coeff[5] = state->table[bw].coeff_2_8k;
424 coeff[6] = state->table[bw].coeff_1_4096;
425 coeff[7] = state->table[bw].coeff_2_4k;
426 bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio;
427 fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio;
430 ret = it913x_read_reg_u8(state, ADC_X_2);
438 /* Build Buffer for COEFF Registers */
439 for (i = 0; i < 8; i++) {
440 if (adcmultiplier == 1)
442 buffer[count++] = (coeff[i] >> 24) & 0x3;
443 buffer[count++] = (coeff[i] >> 16) & 0xff;
444 buffer[count++] = (coeff[i] >> 8) & 0xff;
445 buffer[count++] = coeff[i] & 0xff;
448 /* bfsfcw_fftinx_ratio register 0x21-0x22 */
449 buffer[count++] = bfsfcw_fftinx_ratio & 0xff;
450 buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff;
451 /* fftinx_bfsfcw_ratio register 0x23-0x24 */
452 buffer[count++] = fftinx_bfsfcw_ratio & 0xff;
453 buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff;
454 /* start at COEFF_1_2048 and write through to fftinx_bfsfcw_ratio*/
455 ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count);
457 for (i = 0; i < 42; i += 8)
458 debug_data_snipet(0x1, "Buffer", &buffer[i]);
465 static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status)
467 struct it913x_fe_state *state = fe->demodulator_priv;
469 fe_status_t old_status = state->it913x_status;
472 if (state->it913x_status == 0) {
473 ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
475 *status |= FE_HAS_SIGNAL;
476 for (i = 0; i < 40; i++) {
477 ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK);
483 *status |= FE_HAS_CARRIER
486 state->it913x_status = *status;
490 if (state->it913x_status & FE_HAS_SYNC) {
491 ret = it913x_read_reg_u8(state, TPSD_LOCK);
493 *status |= FE_HAS_LOCK
494 | state->it913x_status;
496 state->it913x_status = 0;
497 if (old_status != state->it913x_status)
498 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret);
504 /* FEC values based on fe_code_rate_t non supported values 0*/
505 int it913x_qpsk_pval[] = {0, -93, -91, -90, 0, -89, -88};
506 int it913x_16qam_pval[] = {0, -87, -85, -84, 0, -83, -82};
507 int it913x_64qam_pval[] = {0, -82, -80, -78, 0, -77, -76};
509 static int it913x_get_signal_strength(struct dvb_frontend *fe)
511 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
512 struct it913x_fe_state *state = fe->demodulator_priv;
517 ret = it913x_read_reg_u8(state, VAR_P_INBAND);
521 /* VHF/UHF gain offset */
522 if (state->frequency < 300000000)
527 temp = (ret - 100) - lna_gain_os;
529 if (state->priority == PRIORITY_HIGH)
530 code_rate = p->code_rate_HP;
532 code_rate = p->code_rate_LP;
534 if (code_rate >= ARRAY_SIZE(it913x_qpsk_pval))
537 deb_info("Reg VAR_P_INBAND:%d Calc Offset Value:%d", ret, temp);
539 /* Apply FEC offset values*/
540 switch (p->modulation) {
542 temp -= it913x_qpsk_pval[code_rate];
545 temp -= it913x_16qam_pval[code_rate];
548 temp -= it913x_64qam_pval[code_rate];
556 else if ((-15 <= temp) && (temp < 0))
557 ret = (2 * (temp + 15)) / 3;
558 else if ((0 <= temp) && (temp < 20))
560 else if ((20 <= temp) && (temp < 35))
561 ret = (2 * (temp - 20)) / 3 + 90;
565 deb_info("Signal Strength :%d", ret);
570 static int it913x_fe_read_signal_strength(struct dvb_frontend *fe,
573 struct it913x_fe_state *state = fe->demodulator_priv;
575 if (state->config->read_slevel) {
576 if (state->it913x_status & FE_HAS_SIGNAL)
577 ret = it913x_read_reg_u8(state, SIGNAL_LEVEL);
579 ret = it913x_get_signal_strength(fe);
582 *strength = (u16)((u32)ret * 0xffff / 0x64);
584 return (ret < 0) ? -ENODEV : 0;
587 static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr)
589 struct it913x_fe_state *state = fe->demodulator_priv;
592 u32 snr_val, snr_min, snr_max;
595 ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg));
597 snr_val = (u32)(reg[2] << 16) | (reg[1] << 8) | reg[0];
599 ret |= it913x_read_reg(state, 0xf78b, reg, 1);
603 if (state->transmission_mode == TRANSMISSION_MODE_2K)
605 else if (state->transmission_mode == TRANSMISSION_MODE_4K)
608 if (state->constellation == QPSK) {
611 } else if (state->constellation == QAM_16) {
614 } else if (state->constellation == QAM_64) {
620 if (snr_val < snr_min)
622 else if (snr_val < snr_max) {
623 temp = (snr_val - snr_min) >> 5;
625 temp /= (snr_max - snr_min) >> 5;
630 return (ret < 0) ? -ENODEV : 0;
633 static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
635 struct it913x_fe_state *state = fe->demodulator_priv;
637 /* Read Aborted Packets and Pre-Viterbi error rate 5 bytes */
638 it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg));
639 state->ucblocks += (u32)(reg[1] << 8) | reg[0];
640 *ber = (u32)(reg[4] << 16) | (reg[3] << 8) | reg[2];
644 static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
646 struct it913x_fe_state *state = fe->demodulator_priv;
649 /* Aborted Packets */
650 ret = it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg));
651 state->ucblocks += (u32)(reg[1] << 8) | reg[0];
652 *ucblocks = state->ucblocks;
656 static int it913x_fe_get_frontend(struct dvb_frontend *fe)
658 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
659 struct it913x_fe_state *state = fe->demodulator_priv;
662 it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg));
665 p->modulation = fe_con[reg[3]];
668 p->transmission_mode = fe_mode[reg[0]];
671 p->guard_interval = fe_gi[reg[1]];
674 p->hierarchy = fe_hi[reg[2]];
676 state->priority = reg[5];
678 p->code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE;
679 p->code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE;
681 /* Update internal state to reflect the autodetected props */
682 state->constellation = p->modulation;
683 state->transmission_mode = p->transmission_mode;
688 static int it913x_fe_set_frontend(struct dvb_frontend *fe)
690 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
691 struct it913x_fe_state *state = fe->demodulator_priv;
693 u8 empty_ch, last_ch;
695 state->it913x_status = 0;
698 it913x_fe_select_bw(state, p->bandwidth_hz,
699 state->adcFrequency);
701 /* Training Mode Off */
702 it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0);
704 /* Clear Empty Channel */
705 it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0);
708 it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0);
710 it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
712 if ((p->frequency >= 51000000) && (p->frequency <= 230000000))
714 else if ((p->frequency >= 350000000) && (p->frequency <= 900000000))
716 else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000))
721 it913x_write_reg(state, PRO_DMOD, FREE_BAND, i);
723 deb_info("Frontend Set Tuner Type %02x", state->tuner_type);
724 switch (state->tuner_type) {
731 it9137_set_tuner(state,
732 p->bandwidth_hz, p->frequency);
735 if (fe->ops.tuner_ops.set_params) {
736 fe->ops.tuner_ops.set_params(fe);
737 if (fe->ops.i2c_gate_ctrl)
738 fe->ops.i2c_gate_ctrl(fe, 0);
743 it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
745 it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
747 for (i = 0; i < 40; ++i) {
748 empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
749 if (last_ch == 1 && empty_ch == 1)
751 if (last_ch == 2 && empty_ch == 2)
756 for (i = 0; i < 40; ++i) {
757 if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1)
762 state->frequency = p->frequency;
766 static int it913x_fe_suspend(struct it913x_fe_state *state)
771 ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1);
773 ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
775 for (i = 0; i < 128; i++) {
776 ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1);
784 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8);
786 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
788 ret |= it913x_fe_script_loader(state, it9137_tuner_off);
790 return (ret < 0) ? -ENODEV : 0;
794 /* Power Up Tuner on -> Frontend suspend off -> Tuner clk on */
795 /* Power Down Frontend suspend on -> Tuner clk off -> Tuner off */
797 static int it913x_fe_sleep(struct dvb_frontend *fe)
799 struct it913x_fe_state *state = fe->demodulator_priv;
800 return it913x_fe_suspend(state);
803 static u32 compute_div(u32 a, u32 b, u32 x)
814 for (i = 0; i < x; i++) {
823 res = (c << x) + res;
828 static int it913x_fe_start(struct it913x_fe_state *state)
830 struct it913xset *set_lna;
831 struct it913xset *set_mode;
833 u8 adf = (state->config->adf & 0xf);
837 if (state->config->chip_ver == 1)
838 ret = it913x_init_tuner(state);
840 info("ADF table value :%02x", adf);
843 state->crystalFrequency = fe_clockTable[adf].xtal ;
844 state->table = fe_clockTable[adf].table;
845 state->adcFrequency = state->table->adcFrequency;
847 adc = compute_div(state->adcFrequency, 1000000ul, 19ul);
848 xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul);
853 /* Set LED indicator on GPIOH3 */
854 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1);
855 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1);
856 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
858 ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type);
859 ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01);
860 ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01);
863 b[1] = (xtal >> 8) & 0xff;
864 b[2] = (xtal >> 16) & 0xff;
866 ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4);
869 b[1] = (adc >> 8) & 0xff;
870 b[2] = (adc >> 16) & 0xff;
871 ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3);
873 if (state->config->adc_x2)
874 ret |= it913x_write_reg(state, PRO_DMOD, ADC_X_2, 0x01);
878 ret |= it913x_write(state, PRO_DMOD, 0x0029, b, 3);
880 info("Crystal Frequency :%d Adc Frequency :%d ADC X2: %02x",
881 state->crystalFrequency, state->adcFrequency,
882 state->config->adc_x2);
883 deb_info("Xtal value :%04x Adc value :%04x", xtal, adc);
888 /* v1 or v2 tuner script */
889 if (state->config->chip_ver > 1)
890 ret = it913x_fe_script_loader(state, it9135_v2);
892 ret = it913x_fe_script_loader(state, it9135_v1);
897 switch (state->tuner_type) {
917 info("Tuner LNA type :%02x", state->tuner_type);
919 ret = it913x_fe_script_loader(state, set_lna);
923 if (state->config->chip_ver == 2) {
924 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1);
925 ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0);
926 ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0);
927 ret |= it913x_init_tuner(state);
932 /* Always solo frontend */
933 set_mode = set_solo_fe;
934 ret |= it913x_fe_script_loader(state, set_mode);
936 ret |= it913x_fe_suspend(state);
937 return (ret < 0) ? -ENODEV : 0;
940 static int it913x_fe_init(struct dvb_frontend *fe)
942 struct it913x_fe_state *state = fe->demodulator_priv;
944 /* Power Up Tuner - common all versions */
945 ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1);
947 ret |= it913x_fe_script_loader(state, init_1);
949 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0);
951 ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0);
953 return (ret < 0) ? -ENODEV : 0;
956 static void it913x_fe_release(struct dvb_frontend *fe)
958 struct it913x_fe_state *state = fe->demodulator_priv;
962 static struct dvb_frontend_ops it913x_fe_ofdm_ops;
964 struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
965 u8 i2c_addr, struct ite_config *config)
967 struct it913x_fe_state *state = NULL;
970 /* allocate memory for the internal state */
971 state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL);
977 state->i2c_adap = i2c_adap;
978 state->i2c_addr = i2c_addr;
979 state->config = config;
981 switch (state->config->tuner_id_0) {
987 state->tuner_type = state->config->tuner_id_0;
991 state->tuner_type = IT9135_38;
994 ret = it913x_fe_start(state);
999 /* create dvb_frontend */
1000 memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops,
1001 sizeof(struct dvb_frontend_ops));
1002 state->frontend.demodulator_priv = state;
1004 return &state->frontend;
1009 EXPORT_SYMBOL(it913x_fe_attach);
1011 static struct dvb_frontend_ops it913x_fe_ofdm_ops = {
1012 .delsys = { SYS_DVBT },
1014 .name = "it913x-fe DVB-T",
1015 .frequency_min = 51000000,
1016 .frequency_max = 1680000000,
1017 .frequency_stepsize = 62500,
1018 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1019 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1020 FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
1021 FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1022 FE_CAN_TRANSMISSION_MODE_AUTO |
1023 FE_CAN_GUARD_INTERVAL_AUTO |
1024 FE_CAN_HIERARCHY_AUTO,
1027 .release = it913x_fe_release,
1029 .init = it913x_fe_init,
1030 .sleep = it913x_fe_sleep,
1032 .set_frontend = it913x_fe_set_frontend,
1033 .get_frontend = it913x_fe_get_frontend,
1035 .read_status = it913x_fe_read_status,
1036 .read_signal_strength = it913x_fe_read_signal_strength,
1037 .read_snr = it913x_fe_read_snr,
1038 .read_ber = it913x_fe_read_ber,
1039 .read_ucblocks = it913x_fe_read_ucblocks,
1042 MODULE_DESCRIPTION("it913x Frontend and it9137 tuner");
1043 MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
1044 MODULE_VERSION("1.15");
1045 MODULE_LICENSE("GPL");