2 * Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
4 * Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/delay.h>
25 #include <linux/dvb/frontend.h>
26 #include <linux/i2c.h>
27 #include <linux/slab.h>
29 #include "dvb_frontend.h"
32 #include "itd1000_priv.h"
35 module_param(debug, int, 0644);
36 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
38 #define itd_dbg(args...) do { \
40 printk(KERN_DEBUG "ITD1000: " args);\
44 #define itd_warn(args...) do { \
45 printk(KERN_WARNING "ITD1000: " args); \
48 #define itd_info(args...) do { \
49 printk(KERN_INFO "ITD1000: " args); \
52 /* don't write more than one byte with flexcop behind */
53 static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
56 struct i2c_msg msg = {
57 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
60 memcpy(&buf[1], v, len);
62 /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */
64 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
65 printk(KERN_WARNING "itd1000 I2C write failed\n");
71 static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
74 struct i2c_msg msg[2] = {
75 { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
76 { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
79 /* ugly flexcop workaround */
80 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
82 if (i2c_transfer(state->i2c, msg, 2) != 2) {
83 itd_warn("itd1000 I2C read failed\n");
89 static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
91 int ret = itd1000_write_regs(state, r, &v, 1);
99 u8 pgaext : 4; /* PLLFH */
100 u8 bbgvmin : 4; /* BBGVMIN */
101 } itd1000_lpf_pga[] = {
103 { 5200000, 0x8, 0x3 },
104 { 12200000, 0x4, 0x3 },
105 { 15400000, 0x2, 0x3 },
106 { 19800000, 0x2, 0x3 },
107 { 21500000, 0x2, 0x3 },
108 { 24500000, 0x2, 0x3 },
109 { 28400000, 0x2, 0x3 },
110 { 33400000, 0x2, 0x3 },
111 { 34400000, 0x1, 0x4 },
112 { 34400000, 0x1, 0x4 },
113 { 38400000, 0x1, 0x4 },
114 { 38400000, 0x1, 0x4 },
115 { 40400000, 0x1, 0x4 },
116 { 45400000, 0x1, 0x4 },
119 static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
122 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd;
123 u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f;
124 u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
125 u8 bw = itd1000_read_reg(state, BW) & 0xf0;
127 itd_dbg("symbol_rate = %d\n", symbol_rate);
129 /* not sure what is that ? - starting to download the table */
130 itd1000_write_reg(state, CON1, con1 | (1 << 1));
132 for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
133 if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
134 itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
135 itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4));
136 itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
137 itd1000_write_reg(state, BW, bw | (i & 0x0f));
141 itd1000_write_reg(state, CON1, con1 | (0 << 1));
147 } itd1000_vcorg[] = {
155 { 8, 500000 }, /* this is intentional. */
165 static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
168 u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
169 u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
172 /* reserved bit again (reset ?) */
173 itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
175 for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
176 if (freq_khz < itd1000_vcorg[i].fmax_rg) {
177 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
180 adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
182 itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
185 if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
186 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
187 } else if (adcout < 2) {
188 if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
189 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
196 static const struct {
198 u8 values[10]; /* RFTR, RFST1 - RFST9 */
199 } itd1000_fre_values[] = {
200 { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
201 { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
202 { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
203 { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
204 { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
205 { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
206 { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
207 { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
208 { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
209 { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
215 static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
221 plln = (freq_khz * 1000) / 2 / FREF;
223 /* Compute the factional part times 1000 */
224 tmp = plln % 1000000;
228 do_div(tmp, 1000000);
231 state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
232 itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
234 itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
235 itd1000_write_reg(state, PLLNL, plln & 0xff);
236 itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
237 itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
238 itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
240 for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
241 if (freq_khz <= itd1000_fre_values[i].freq) {
242 itd_dbg("fre_values: %d\n", i);
243 itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
244 for (j = 0; j < 9; j++)
245 itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
250 itd1000_set_vco(state, freq_khz);
253 static int itd1000_set_parameters(struct dvb_frontend *fe)
255 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
256 struct itd1000_state *state = fe->tuner_priv;
259 itd1000_set_lo(state, c->frequency);
260 itd1000_set_lpf_bw(state, c->symbol_rate);
262 pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
263 itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
264 itd1000_write_reg(state, PLLCON1, pllcon1);
269 static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
271 struct itd1000_state *state = fe->tuner_priv;
272 *frequency = state->frequency;
276 static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
281 static u8 itd1000_init_tab[][2] = {
282 { PLLCON1, 0x65 }, /* Register does not change */
283 { PLLNH, 0x80 }, /* Bits [7:6] do not change */
284 { RESERVED_0X6D, 0x3b },
285 { VCO_CHP2_I2C, 0x12 },
286 { 0x72, 0xf9 }, /* No such regsister defined */
287 { RESERVED_0X73, 0xff },
288 { RESERVED_0X74, 0xb2 },
289 { RESERVED_0X75, 0xc7 },
293 { RESERVED_0X7E, 0x4f },
294 { 0x82, 0x88 }, /* No such regsister defined */
295 { 0x83, 0x80 }, /* No such regsister defined */
296 { 0x84, 0x80 }, /* No such regsister defined */
297 { RESERVED_0X85, 0x74 },
298 { RESERVED_0X86, 0xff },
299 { RESERVED_0X88, 0x02 },
300 { RESERVED_0X89, 0x16 },
302 { RESERVED_0X94, 0x66 },
303 { RESERVED_0X95, 0x66 },
304 { RESERVED_0X96, 0x77 },
305 { RESERVED_0X97, 0x99 },
306 { RESERVED_0X98, 0xff },
307 { RESERVED_0X99, 0xfc },
308 { RESERVED_0X9A, 0xba },
309 { RESERVED_0X9B, 0xaa },
312 static u8 itd1000_reinit_tab[][2] = {
313 { VCO_CHP1_I2C, 0x8a },
321 static int itd1000_init(struct dvb_frontend *fe)
323 struct itd1000_state *state = fe->tuner_priv;
326 for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
327 itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
329 for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
330 itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
335 static int itd1000_sleep(struct dvb_frontend *fe)
340 static int itd1000_release(struct dvb_frontend *fe)
342 kfree(fe->tuner_priv);
343 fe->tuner_priv = NULL;
347 static const struct dvb_tuner_ops itd1000_tuner_ops = {
349 .name = "Integrant ITD1000",
350 .frequency_min = 950000,
351 .frequency_max = 2150000,
352 .frequency_step = 125, /* kHz for QPSK frontends */
355 .release = itd1000_release,
357 .init = itd1000_init,
358 .sleep = itd1000_sleep,
360 .set_params = itd1000_set_parameters,
361 .get_frequency = itd1000_get_frequency,
362 .get_bandwidth = itd1000_get_bandwidth
366 struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
368 struct itd1000_state *state = NULL;
371 state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
378 i = itd1000_read_reg(state, 0);
383 itd_info("successfully identified (ID: %d)\n", i);
385 memset(state->shadow, 0xff, sizeof(state->shadow));
386 for (i = 0x65; i < 0x9c; i++)
387 state->shadow[i] = itd1000_read_reg(state, i);
389 memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
391 fe->tuner_priv = state;
395 EXPORT_SYMBOL(itd1000_attach);
397 MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
398 MODULE_DESCRIPTION("Integrant ITD1000 driver");
399 MODULE_LICENSE("GPL");