2 * Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
4 * Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org>
6 * LGDT3304 support by Jarod Wilson <jarod@redhat.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <asm/div64.h>
25 #include <linux/dvb/frontend.h>
26 #include <linux/slab.h>
31 module_param(debug, int, 0644);
32 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
37 #define lg_printk(kern, fmt, arg...) \
38 printk(kern "%s: " fmt, __func__, ##arg)
40 #define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3305: " fmt, ##arg)
41 #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
42 #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
43 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
44 lg_printk(KERN_DEBUG, fmt, ##arg)
45 #define lg_reg(fmt, arg...) if (debug & DBG_REG) \
46 lg_printk(KERN_DEBUG, fmt, ##arg)
48 #define lg_fail(ret) \
53 lg_err("error %d on line %d\n", ret, __LINE__); \
57 struct lgdt3305_state {
58 struct i2c_adapter *i2c_adap;
59 const struct lgdt3305_config *cfg;
61 struct dvb_frontend frontend;
63 enum fe_modulation current_modulation;
64 u32 current_frequency;
68 /* ------------------------------------------------------------------------ */
70 /* FIXME: verify & document the LGDT3304 registers */
72 #define LGDT3305_GEN_CTRL_1 0x0000
73 #define LGDT3305_GEN_CTRL_2 0x0001
74 #define LGDT3305_GEN_CTRL_3 0x0002
75 #define LGDT3305_GEN_STATUS 0x0003
76 #define LGDT3305_GEN_CONTROL 0x0007
77 #define LGDT3305_GEN_CTRL_4 0x000a
78 #define LGDT3305_DGTL_AGC_REF_1 0x0012
79 #define LGDT3305_DGTL_AGC_REF_2 0x0013
80 #define LGDT3305_CR_CTR_FREQ_1 0x0106
81 #define LGDT3305_CR_CTR_FREQ_2 0x0107
82 #define LGDT3305_CR_CTR_FREQ_3 0x0108
83 #define LGDT3305_CR_CTR_FREQ_4 0x0109
84 #define LGDT3305_CR_MSE_1 0x011b
85 #define LGDT3305_CR_MSE_2 0x011c
86 #define LGDT3305_CR_LOCK_STATUS 0x011d
87 #define LGDT3305_CR_CTRL_7 0x0126
88 #define LGDT3305_AGC_POWER_REF_1 0x0300
89 #define LGDT3305_AGC_POWER_REF_2 0x0301
90 #define LGDT3305_AGC_DELAY_PT_1 0x0302
91 #define LGDT3305_AGC_DELAY_PT_2 0x0303
92 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306
93 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307
94 #define LGDT3305_IFBW_1 0x0308
95 #define LGDT3305_IFBW_2 0x0309
96 #define LGDT3305_AGC_CTRL_1 0x030c
97 #define LGDT3305_AGC_CTRL_4 0x0314
98 #define LGDT3305_EQ_MSE_1 0x0413
99 #define LGDT3305_EQ_MSE_2 0x0414
100 #define LGDT3305_EQ_MSE_3 0x0415
101 #define LGDT3305_PT_MSE_1 0x0417
102 #define LGDT3305_PT_MSE_2 0x0418
103 #define LGDT3305_PT_MSE_3 0x0419
104 #define LGDT3305_FEC_BLOCK_CTRL 0x0504
105 #define LGDT3305_FEC_LOCK_STATUS 0x050a
106 #define LGDT3305_FEC_PKT_ERR_1 0x050c
107 #define LGDT3305_FEC_PKT_ERR_2 0x050d
108 #define LGDT3305_TP_CTRL_1 0x050e
109 #define LGDT3305_BERT_PERIOD 0x0801
110 #define LGDT3305_BERT_ERROR_COUNT_1 0x080a
111 #define LGDT3305_BERT_ERROR_COUNT_2 0x080b
112 #define LGDT3305_BERT_ERROR_COUNT_3 0x080c
113 #define LGDT3305_BERT_ERROR_COUNT_4 0x080d
115 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
118 u8 buf[] = { reg >> 8, reg & 0xff, val };
119 struct i2c_msg msg = {
120 .addr = state->cfg->i2c_addr, .flags = 0,
121 .buf = buf, .len = 3,
124 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
126 ret = i2c_transfer(state->i2c_adap, &msg, 1);
129 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
130 msg.buf[0], msg.buf[1], msg.buf[2], ret);
139 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
142 u8 reg_buf[] = { reg >> 8, reg & 0xff };
143 struct i2c_msg msg[] = {
144 { .addr = state->cfg->i2c_addr,
145 .flags = 0, .buf = reg_buf, .len = 2 },
146 { .addr = state->cfg->i2c_addr,
147 .flags = I2C_M_RD, .buf = val, .len = 1 },
150 lg_reg("reg: 0x%04x\n", reg);
152 ret = i2c_transfer(state->i2c_adap, msg, 2);
155 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
156 state->cfg->i2c_addr, reg, ret);
165 #define read_reg(state, reg) \
168 int ret = lgdt3305_read_reg(state, reg, &__val); \
174 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
175 u16 reg, int bit, int onoff)
180 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
182 ret = lgdt3305_read_reg(state, reg, &val);
187 val |= (onoff & 1) << bit;
189 ret = lgdt3305_write_reg(state, reg, val);
194 struct lgdt3305_reg {
199 static int lgdt3305_write_regs(struct lgdt3305_state *state,
200 struct lgdt3305_reg *regs, int len)
204 lg_reg("writing %d registers...\n", len);
206 for (i = 0; i < len - 1; i++) {
207 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
214 /* ------------------------------------------------------------------------ */
216 static int lgdt3305_soft_reset(struct lgdt3305_state *state)
222 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
227 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
232 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
233 enum lgdt3305_mpeg_mode mode)
235 lg_dbg("(%d)\n", mode);
236 return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
239 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state)
243 enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;
244 enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;
245 enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;
247 lg_dbg("edge = %d, valid = %d\n", edge, valid);
249 ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
262 ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
266 ret = lgdt3305_soft_reset(state);
271 static int lgdt3305_set_modulation(struct lgdt3305_state *state,
272 struct dtv_frontend_properties *p)
279 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
285 switch (p->modulation) {
298 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
303 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
304 struct dtv_frontend_properties *p)
308 switch (p->modulation) {
319 lg_dbg("val = %d\n", val);
321 return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
324 /* ------------------------------------------------------------------------ */
326 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
327 struct dtv_frontend_properties *p)
331 switch (p->modulation) {
345 lg_dbg("agc ref: 0x%04x\n", agc_ref);
347 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
348 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
353 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
354 struct dtv_frontend_properties *p)
356 u16 ifbw, rfbw, agcdelay;
358 switch (p->modulation) {
368 /* FIXME: investigate optimal ifbw & rfbw values for the
369 * DT3304 and re-write this switch..case block */
370 if (state->cfg->demod_chip == LGDT3304)
372 else /* (state->cfg->demod_chip == LGDT3305) */
379 if (state->cfg->rf_agc_loop) {
380 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
382 /* rf agc loop filter bandwidth */
383 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
385 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
388 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
390 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
393 lg_dbg("ifbw: 0x%04x\n", ifbw);
395 /* if agc loop filter bandwidth */
396 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
397 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
403 static int lgdt3305_agc_setup(struct lgdt3305_state *state,
404 struct dtv_frontend_properties *p)
408 switch (p->modulation) {
422 lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
424 /* control agc function */
425 switch (state->cfg->demod_chip) {
427 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
428 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
431 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
432 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
438 return lgdt3305_rfagc_loop(state, p);
441 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
442 struct dtv_frontend_properties *p)
446 switch (p->modulation) {
448 if (state->cfg->usref_8vsb)
449 usref = state->cfg->usref_8vsb;
452 if (state->cfg->usref_qam64)
453 usref = state->cfg->usref_qam64;
456 if (state->cfg->usref_qam256)
457 usref = state->cfg->usref_qam256;
464 lg_dbg("set manual mode: 0x%04x\n", usref);
466 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
468 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
469 0xff & (usref >> 8));
470 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
471 0xff & (usref >> 0));
476 /* ------------------------------------------------------------------------ */
478 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
479 struct dtv_frontend_properties *p,
484 lg_dbg("(%d)\n", inversion);
486 switch (p->modulation) {
488 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
489 inversion ? 0xf9 : 0x79);
493 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
494 inversion ? 0xfd : 0xff);
502 static int lgdt3305_set_if(struct lgdt3305_state *state,
503 struct dtv_frontend_properties *p)
506 u8 nco1, nco2, nco3, nco4;
509 switch (p->modulation) {
511 if_freq_khz = state->cfg->vsb_if_khz;
515 if_freq_khz = state->cfg->qam_if_khz;
521 nco = if_freq_khz / 10;
523 switch (p->modulation) {
537 nco1 = (nco >> 24) & 0x3f;
539 nco2 = (nco >> 16) & 0xff;
540 nco3 = (nco >> 8) & 0xff;
543 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
544 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
545 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
546 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
548 lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
549 if_freq_khz, nco1, nco2, nco3, nco4);
554 /* ------------------------------------------------------------------------ */
556 static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
558 struct lgdt3305_state *state = fe->demodulator_priv;
560 if (state->cfg->deny_i2c_rptr)
563 lg_dbg("(%d)\n", enable);
565 return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
569 static int lgdt3305_sleep(struct dvb_frontend *fe)
571 struct lgdt3305_state *state = fe->demodulator_priv;
572 u8 gen_ctrl_3, gen_ctrl_4;
576 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
577 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
579 /* hold in software reset while sleeping */
581 /* tristate the IF-AGC pin */
583 /* tristate the RF-AGC pin */
586 /* disable vsb/qam module */
588 /* disable adc module */
591 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
592 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
597 static int lgdt3305_init(struct dvb_frontend *fe)
599 struct lgdt3305_state *state = fe->demodulator_priv;
602 static struct lgdt3305_reg lgdt3304_init_data[] = {
603 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
604 { .reg = 0x000d, .val = 0x02, },
605 { .reg = 0x000e, .val = 0x02, },
606 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
607 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
608 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
609 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
610 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
611 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
612 { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, },
613 { .reg = 0x0112, .val = 0x17, },
614 { .reg = 0x0113, .val = 0x15, },
615 { .reg = 0x0114, .val = 0x18, },
616 { .reg = 0x0115, .val = 0xff, },
617 { .reg = 0x0116, .val = 0x3c, },
618 { .reg = 0x0214, .val = 0x67, },
619 { .reg = 0x0424, .val = 0x8d, },
620 { .reg = 0x0427, .val = 0x12, },
621 { .reg = 0x0428, .val = 0x4f, },
622 { .reg = LGDT3305_IFBW_1, .val = 0x80, },
623 { .reg = LGDT3305_IFBW_2, .val = 0x00, },
624 { .reg = 0x030a, .val = 0x08, },
625 { .reg = 0x030b, .val = 0x9b, },
626 { .reg = 0x030d, .val = 0x00, },
627 { .reg = 0x030e, .val = 0x1c, },
628 { .reg = 0x0314, .val = 0xe1, },
629 { .reg = 0x000d, .val = 0x82, },
630 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
631 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
634 static struct lgdt3305_reg lgdt3305_init_data[] = {
635 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
636 { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, },
637 { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, },
638 { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, },
639 { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, },
640 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
641 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
642 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
643 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
644 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
645 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
646 { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, },
647 { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, },
648 { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, },
649 { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, },
650 { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, },
651 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
652 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
653 { .reg = LGDT3305_IFBW_1, .val = 0x80, },
654 { .reg = LGDT3305_IFBW_2, .val = 0x00, },
655 { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, },
656 { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, },
657 { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, },
658 { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, },
663 switch (state->cfg->demod_chip) {
665 ret = lgdt3305_write_regs(state, lgdt3304_init_data,
666 ARRAY_SIZE(lgdt3304_init_data));
669 ret = lgdt3305_write_regs(state, lgdt3305_init_data,
670 ARRAY_SIZE(lgdt3305_init_data));
678 ret = lgdt3305_soft_reset(state);
683 static int lgdt3304_set_parameters(struct dvb_frontend *fe)
685 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
686 struct lgdt3305_state *state = fe->demodulator_priv;
689 lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
691 if (fe->ops.tuner_ops.set_params) {
692 ret = fe->ops.tuner_ops.set_params(fe);
693 if (fe->ops.i2c_gate_ctrl)
694 fe->ops.i2c_gate_ctrl(fe, 0);
697 state->current_frequency = p->frequency;
700 ret = lgdt3305_set_modulation(state, p);
704 ret = lgdt3305_passband_digital_agc(state, p);
708 ret = lgdt3305_agc_setup(state, p);
712 /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
713 switch (p->modulation) {
715 lgdt3305_write_reg(state, 0x030d, 0x00);
716 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
717 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
718 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
719 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
723 lgdt3305_write_reg(state, 0x030d, 0x14);
724 ret = lgdt3305_set_if(state, p);
733 ret = lgdt3305_spectral_inversion(state, p,
734 state->cfg->spectral_inversion
739 state->current_modulation = p->modulation;
741 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
745 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
746 ret = lgdt3305_mpeg_mode_polarity(state);
751 static int lgdt3305_set_parameters(struct dvb_frontend *fe)
753 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
754 struct lgdt3305_state *state = fe->demodulator_priv;
757 lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
759 if (fe->ops.tuner_ops.set_params) {
760 ret = fe->ops.tuner_ops.set_params(fe);
761 if (fe->ops.i2c_gate_ctrl)
762 fe->ops.i2c_gate_ctrl(fe, 0);
765 state->current_frequency = p->frequency;
768 ret = lgdt3305_set_modulation(state, p);
772 ret = lgdt3305_passband_digital_agc(state, p);
775 ret = lgdt3305_set_agc_power_ref(state, p);
778 ret = lgdt3305_agc_setup(state, p);
783 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
786 ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
790 ret = lgdt3305_set_if(state, p);
793 ret = lgdt3305_spectral_inversion(state, p,
794 state->cfg->spectral_inversion
799 ret = lgdt3305_set_filter_extension(state, p);
803 state->current_modulation = p->modulation;
805 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
809 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
810 ret = lgdt3305_mpeg_mode_polarity(state);
815 static int lgdt3305_get_frontend(struct dvb_frontend *fe,
816 struct dtv_frontend_properties *p)
818 struct lgdt3305_state *state = fe->demodulator_priv;
822 p->modulation = state->current_modulation;
823 p->frequency = state->current_frequency;
827 /* ------------------------------------------------------------------------ */
829 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
834 char *cr_lock_state = "";
838 ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
842 switch (state->current_modulation) {
848 switch (val & 0x07) {
850 cr_lock_state = "QAM UNLOCK";
853 cr_lock_state = "QAM 1stLock";
856 cr_lock_state = "QAM 2ndLock";
859 cr_lock_state = "QAM FinalLock";
862 cr_lock_state = "CLOCKQAM-INVALID!";
867 if (val & (1 << 7)) {
869 cr_lock_state = "CLOCKVSB";
875 lg_dbg("(%d) %s\n", *locked, cr_lock_state);
880 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
884 int ret, mpeg_lock, fec_lock, viterbi_lock;
888 switch (state->current_modulation) {
891 ret = lgdt3305_read_reg(state,
892 LGDT3305_FEC_LOCK_STATUS, &val);
896 mpeg_lock = (val & (1 << 0)) ? 1 : 0;
897 fec_lock = (val & (1 << 2)) ? 1 : 0;
898 viterbi_lock = (val & (1 << 3)) ? 1 : 0;
900 *locked = mpeg_lock && fec_lock && viterbi_lock;
902 lg_dbg("(%d) %s%s%s\n", *locked,
903 mpeg_lock ? "mpeg lock " : "",
904 fec_lock ? "fec lock " : "",
905 viterbi_lock ? "viterbi lock" : "");
915 static int lgdt3305_read_status(struct dvb_frontend *fe, enum fe_status *status)
917 struct lgdt3305_state *state = fe->demodulator_priv;
919 int ret, signal, inlock, nofecerr, snrgood,
920 cr_lock, fec_lock, sync_lock;
924 ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
928 signal = (val & (1 << 4)) ? 1 : 0;
929 inlock = (val & (1 << 3)) ? 0 : 1;
930 sync_lock = (val & (1 << 2)) ? 1 : 0;
931 nofecerr = (val & (1 << 1)) ? 1 : 0;
932 snrgood = (val & (1 << 0)) ? 1 : 0;
934 lg_dbg("%s%s%s%s%s\n",
935 signal ? "SIGNALEXIST " : "",
936 inlock ? "INLOCK " : "",
937 sync_lock ? "SYNCLOCK " : "",
938 nofecerr ? "NOFECERR " : "",
939 snrgood ? "SNRGOOD " : "");
941 ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
946 *status |= FE_HAS_SIGNAL;
948 *status |= FE_HAS_CARRIER;
950 *status |= FE_HAS_VITERBI;
952 *status |= FE_HAS_SYNC;
954 switch (state->current_modulation) {
957 /* signal bit is unreliable on the DT3304 in QAM mode */
958 if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock))
959 *status |= FE_HAS_SIGNAL;
961 ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
966 *status |= FE_HAS_LOCK;
970 *status |= FE_HAS_LOCK;
979 /* ------------------------------------------------------------------------ */
981 /* borrowed from lgdt330x.c */
982 static u32 calculate_snr(u32 mse, u32 c)
984 if (mse == 0) /* no signal */
989 /* Negative SNR, which is possible, but realisticly the
990 demod will lose lock before the signal gets this bad. The
991 API only allows for unsigned values, so just return 0 */
997 static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
999 struct lgdt3305_state *state = fe->demodulator_priv;
1000 u32 noise; /* noise value */
1001 u32 c; /* per-modulation SNR calculation constant */
1003 switch (state->current_modulation) {
1006 /* Use Phase Tracker Mean-Square Error Register */
1007 /* SNR for ranges from -13.11 to +44.08 */
1008 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
1009 (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
1010 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
1011 c = 73957994; /* log10(25*32^2)*2^24 */
1013 /* Use Equalizer Mean-Square Error Register */
1014 /* SNR for ranges from -16.12 to +44.08 */
1015 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
1016 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
1017 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
1018 c = 73957994; /* log10(25*32^2)*2^24 */
1023 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
1024 (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
1026 c = (state->current_modulation == QAM_64) ?
1027 97939837 : 98026066;
1028 /* log10(688128)*2^24 and log10(696320)*2^24 */
1033 state->snr = calculate_snr(noise, c);
1034 /* report SNR in dB * 10 */
1035 *snr = (state->snr / ((1 << 24) / 10));
1036 lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
1037 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
1042 static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
1045 /* borrowed from lgdt330x.c
1047 * Calculate strength from SNR up to 35dB
1048 * Even though the SNR can go higher than 35dB,
1049 * there is some comfort factor in having a range of
1050 * strong signals that can show at 100%
1052 struct lgdt3305_state *state = fe->demodulator_priv;
1058 ret = fe->ops.read_snr(fe, &snr);
1061 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
1062 /* scale the range 0 - 35*2^24 into 0 - 65535 */
1063 if (state->snr >= 8960 * 0x10000)
1066 *strength = state->snr / 8960;
1071 /* ------------------------------------------------------------------------ */
1073 static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
1079 static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1081 struct lgdt3305_state *state = fe->demodulator_priv;
1084 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
1085 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
1090 static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
1091 struct dvb_frontend_tune_settings
1094 fe_tune_settings->min_delay_ms = 500;
1099 static void lgdt3305_release(struct dvb_frontend *fe)
1101 struct lgdt3305_state *state = fe->demodulator_priv;
1106 static const struct dvb_frontend_ops lgdt3304_ops;
1107 static const struct dvb_frontend_ops lgdt3305_ops;
1109 struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
1110 struct i2c_adapter *i2c_adap)
1112 struct lgdt3305_state *state = NULL;
1116 lg_dbg("(%d-%04x)\n",
1117 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1118 config ? config->i2c_addr : 0);
1120 state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
1124 state->cfg = config;
1125 state->i2c_adap = i2c_adap;
1127 switch (config->demod_chip) {
1129 memcpy(&state->frontend.ops, &lgdt3304_ops,
1130 sizeof(struct dvb_frontend_ops));
1133 memcpy(&state->frontend.ops, &lgdt3305_ops,
1134 sizeof(struct dvb_frontend_ops));
1139 state->frontend.demodulator_priv = state;
1141 /* verify that we're talking to a lg dt3304/5 */
1142 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
1143 if ((lg_fail(ret)) | (val == 0))
1145 ret = lgdt3305_write_reg(state, 0x0808, 0x80);
1148 ret = lgdt3305_read_reg(state, 0x0808, &val);
1149 if ((lg_fail(ret)) | (val != 0x80))
1151 ret = lgdt3305_write_reg(state, 0x0808, 0x00);
1155 state->current_frequency = -1;
1156 state->current_modulation = -1;
1158 return &state->frontend;
1160 lg_warn("unable to detect %s hardware\n",
1161 config->demod_chip ? "LGDT3304" : "LGDT3305");
1165 EXPORT_SYMBOL(lgdt3305_attach);
1167 static const struct dvb_frontend_ops lgdt3304_ops = {
1168 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1170 .name = "LG Electronics LGDT3304 VSB/QAM Frontend",
1171 .frequency_min = 54000000,
1172 .frequency_max = 858000000,
1173 .frequency_stepsize = 62500,
1174 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1176 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
1177 .init = lgdt3305_init,
1178 .sleep = lgdt3305_sleep,
1179 .set_frontend = lgdt3304_set_parameters,
1180 .get_frontend = lgdt3305_get_frontend,
1181 .get_tune_settings = lgdt3305_get_tune_settings,
1182 .read_status = lgdt3305_read_status,
1183 .read_ber = lgdt3305_read_ber,
1184 .read_signal_strength = lgdt3305_read_signal_strength,
1185 .read_snr = lgdt3305_read_snr,
1186 .read_ucblocks = lgdt3305_read_ucblocks,
1187 .release = lgdt3305_release,
1190 static const struct dvb_frontend_ops lgdt3305_ops = {
1191 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1193 .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
1194 .frequency_min = 54000000,
1195 .frequency_max = 858000000,
1196 .frequency_stepsize = 62500,
1197 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1199 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
1200 .init = lgdt3305_init,
1201 .sleep = lgdt3305_sleep,
1202 .set_frontend = lgdt3305_set_parameters,
1203 .get_frontend = lgdt3305_get_frontend,
1204 .get_tune_settings = lgdt3305_get_tune_settings,
1205 .read_status = lgdt3305_read_status,
1206 .read_ber = lgdt3305_read_ber,
1207 .read_signal_strength = lgdt3305_read_signal_strength,
1208 .read_snr = lgdt3305_read_snr,
1209 .read_ucblocks = lgdt3305_read_ucblocks,
1210 .release = lgdt3305_release,
1213 MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
1214 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
1215 MODULE_LICENSE("GPL");
1216 MODULE_VERSION("0.2");