2 * Montage Technology M88DS3103/M88RS6000 demodulator driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include "m88ds3103_priv.h"
19 static struct dvb_frontend_ops m88ds3103_ops;
21 /* write single register with mask */
22 static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
23 u8 reg, u8 mask, u8 val)
28 /* no need for read if whole reg is written */
30 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
39 return regmap_bulk_write(dev->regmap, reg, &val, 1);
42 /* write reg val table using reg addr auto increment */
43 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
44 const struct m88ds3103_reg_val *tab, int tab_len)
46 struct i2c_client *client = dev->client;
50 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
57 for (i = 0, j = 0; i < tab_len; i++, j++) {
60 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
61 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
62 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
72 dev_dbg(&client->dev, "failed=%d\n", ret);
77 * Get the demodulator AGC PWM voltage setting supplied to the tuner.
79 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
81 struct m88ds3103_dev *dev = fe->demodulator_priv;
85 ret = regmap_read(dev->regmap, 0x3f, &tmp);
90 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
92 static int m88ds3103_read_status(struct dvb_frontend *fe,
93 enum fe_status *status)
95 struct m88ds3103_dev *dev = fe->demodulator_priv;
96 struct i2c_client *client = dev->client;
97 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
109 switch (c->delivery_system) {
111 ret = regmap_read(dev->regmap, 0xd1, &utmp);
115 if ((utmp & 0x07) == 0x07)
116 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
117 FE_HAS_VITERBI | FE_HAS_SYNC |
121 ret = regmap_read(dev->regmap, 0x0d, &utmp);
125 if ((utmp & 0x8f) == 0x8f)
126 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
127 FE_HAS_VITERBI | FE_HAS_SYNC |
131 dev_dbg(&client->dev, "invalid delivery_system\n");
136 dev->fe_status = *status;
137 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
140 if (dev->fe_status & FE_HAS_VITERBI) {
141 unsigned int cnr, noise, signal, noise_tot, signal_tot;
144 /* more iterations for more accurate estimation */
145 #define M88DS3103_SNR_ITERATIONS 3
147 switch (c->delivery_system) {
151 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
152 ret = regmap_read(dev->regmap, 0xff, &utmp);
159 /* use of single register limits max value to 15 dB */
160 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
161 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
163 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
169 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
170 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
174 noise = buf[1] << 6; /* [13:6] */
175 noise |= buf[0] & 0x3f; /* [5:0] */
177 signal = buf[2] * buf[2];
181 signal_tot += signal;
184 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
185 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
187 /* SNR(X) dB = 10 * log10(X) dB */
188 if (signal > noise) {
189 itmp = signal / noise;
190 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
194 dev_dbg(&client->dev, "invalid delivery_system\n");
200 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
201 c->cnr.stat[0].svalue = cnr;
203 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
206 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
210 if (dev->fe_status & FE_HAS_LOCK) {
211 unsigned int utmp, post_bit_error, post_bit_count;
213 switch (c->delivery_system) {
215 ret = regmap_write(dev->regmap, 0xf9, 0x04);
219 ret = regmap_read(dev->regmap, 0xf8, &utmp);
223 /* measurement ready? */
224 if (!(utmp & 0x10)) {
225 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
229 post_bit_error = buf[1] << 8 | buf[0] << 0;
230 post_bit_count = 0x800000;
231 dev->post_bit_error += post_bit_error;
232 dev->post_bit_count += post_bit_count;
233 dev->dvbv3_ber = post_bit_error;
235 /* restart measurement */
237 ret = regmap_write(dev->regmap, 0xf8, utmp);
243 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
247 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
251 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
255 post_bit_error = buf[1] << 8 | buf[0] << 0;
256 post_bit_count = 32 * utmp; /* TODO: FEC */
257 dev->post_bit_error += post_bit_error;
258 dev->post_bit_count += post_bit_count;
259 dev->dvbv3_ber = post_bit_error;
261 /* restart measurement */
262 ret = regmap_write(dev->regmap, 0xd1, 0x01);
266 ret = regmap_write(dev->regmap, 0xf9, 0x01);
270 ret = regmap_write(dev->regmap, 0xf9, 0x00);
274 ret = regmap_write(dev->regmap, 0xd1, 0x00);
280 dev_dbg(&client->dev, "invalid delivery_system\n");
285 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
286 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
287 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
288 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
290 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
291 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
296 dev_dbg(&client->dev, "failed=%d\n", ret);
300 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
302 struct m88ds3103_dev *dev = fe->demodulator_priv;
303 struct i2c_client *client = dev->client;
304 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
306 const struct m88ds3103_reg_val *init;
307 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
309 u16 u16tmp, divide_ratio = 0;
310 u32 tuner_frequency, target_mclk;
313 dev_dbg(&client->dev,
314 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
315 c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
316 c->inversion, c->pilot, c->rolloff);
324 ret = regmap_write(dev->regmap, 0x07, 0x80);
328 ret = regmap_write(dev->regmap, 0x07, 0x00);
332 /* Disable demod clock path */
333 if (dev->chip_id == M88RS6000_CHIP_ID) {
334 ret = regmap_write(dev->regmap, 0x06, 0xe0);
340 if (fe->ops.tuner_ops.set_params) {
341 ret = fe->ops.tuner_ops.set_params(fe);
346 if (fe->ops.tuner_ops.get_frequency) {
347 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
352 * Use nominal target frequency as tuner driver does not provide
353 * actual frequency used. Carrier offset calculation is not
356 tuner_frequency = c->frequency;
359 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
360 if (dev->chip_id == M88RS6000_CHIP_ID) {
361 if (c->symbol_rate > 45010000)
362 dev->mclk_khz = 110250;
364 dev->mclk_khz = 96000;
366 if (c->delivery_system == SYS_DVBS)
369 target_mclk = 144000;
371 /* Enable demod clock path */
372 ret = regmap_write(dev->regmap, 0x06, 0x00);
375 usleep_range(10000, 20000);
377 /* set M88DS3103 mclk and ts mclk. */
378 dev->mclk_khz = 96000;
380 switch (dev->cfg->ts_mode) {
381 case M88DS3103_TS_SERIAL:
382 case M88DS3103_TS_SERIAL_D7:
383 target_mclk = dev->cfg->ts_clk;
385 case M88DS3103_TS_PARALLEL:
386 case M88DS3103_TS_CI:
387 if (c->delivery_system == SYS_DVBS)
390 if (c->symbol_rate < 18000000)
392 else if (c->symbol_rate < 28000000)
393 target_mclk = 144000;
395 target_mclk = 192000;
399 dev_dbg(&client->dev, "invalid ts_mode\n");
404 switch (target_mclk) {
406 u8tmp1 = 0x02; /* 0b10 */
407 u8tmp2 = 0x01; /* 0b01 */
410 u8tmp1 = 0x00; /* 0b00 */
411 u8tmp2 = 0x01; /* 0b01 */
414 u8tmp1 = 0x03; /* 0b11 */
415 u8tmp2 = 0x00; /* 0b00 */
418 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
421 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
426 ret = regmap_write(dev->regmap, 0xb2, 0x01);
430 ret = regmap_write(dev->regmap, 0x00, 0x01);
434 switch (c->delivery_system) {
436 if (dev->chip_id == M88RS6000_CHIP_ID) {
437 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
438 init = m88rs6000_dvbs_init_reg_vals;
440 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
441 init = m88ds3103_dvbs_init_reg_vals;
445 if (dev->chip_id == M88RS6000_CHIP_ID) {
446 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
447 init = m88rs6000_dvbs2_init_reg_vals;
449 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
450 init = m88ds3103_dvbs2_init_reg_vals;
454 dev_dbg(&client->dev, "invalid delivery_system\n");
459 /* program init table */
460 if (c->delivery_system != dev->delivery_system) {
461 ret = m88ds3103_wr_reg_val_tab(dev, init, len);
466 if (dev->chip_id == M88RS6000_CHIP_ID) {
467 if ((c->delivery_system == SYS_DVBS2)
468 && ((c->symbol_rate / 1000) <= 5000)) {
469 ret = regmap_write(dev->regmap, 0xc0, 0x04);
475 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
479 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
482 ret = regmap_write(dev->regmap, 0xf1, 0x01);
485 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
490 switch (dev->cfg->ts_mode) {
491 case M88DS3103_TS_SERIAL:
495 case M88DS3103_TS_SERIAL_D7:
499 case M88DS3103_TS_PARALLEL:
502 case M88DS3103_TS_CI:
506 dev_dbg(&client->dev, "invalid ts_mode\n");
511 if (dev->cfg->ts_clk_pol)
515 ret = regmap_write(dev->regmap, 0xfd, u8tmp);
519 switch (dev->cfg->ts_mode) {
520 case M88DS3103_TS_SERIAL:
521 case M88DS3103_TS_SERIAL_D7:
522 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
529 if (dev->cfg->ts_clk) {
530 divide_ratio = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
531 u8tmp1 = divide_ratio / 2;
532 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
536 dev_dbg(&client->dev,
537 "target_mclk=%d ts_clk=%d divide_ratio=%d\n",
538 target_mclk, dev->cfg->ts_clk, divide_ratio);
542 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
544 /* u8tmp2[5:0] => ea[5:0] */
547 ret = regmap_bulk_read(dev->regmap, 0xfe, &u8tmp, 1);
551 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
552 ret = regmap_write(dev->regmap, 0xfe, u8tmp);
556 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
557 ret = regmap_write(dev->regmap, 0xea, u8tmp);
561 if (c->symbol_rate <= 3000000)
563 else if (c->symbol_rate <= 10000000)
568 ret = regmap_write(dev->regmap, 0xc3, 0x08);
572 ret = regmap_write(dev->regmap, 0xc8, u8tmp);
576 ret = regmap_write(dev->regmap, 0xc4, 0x08);
580 ret = regmap_write(dev->regmap, 0xc7, 0x00);
584 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, dev->mclk_khz / 2);
585 buf[0] = (u16tmp >> 0) & 0xff;
586 buf[1] = (u16tmp >> 8) & 0xff;
587 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
591 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
595 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
599 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
603 dev_dbg(&client->dev, "carrier offset=%d\n",
604 (tuner_frequency - c->frequency));
606 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
607 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk_khz);
611 buf[0] = (s32tmp >> 0) & 0xff;
612 buf[1] = (s32tmp >> 8) & 0xff;
613 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
617 ret = regmap_write(dev->regmap, 0x00, 0x00);
621 ret = regmap_write(dev->regmap, 0xb2, 0x00);
625 dev->delivery_system = c->delivery_system;
629 dev_dbg(&client->dev, "failed=%d\n", ret);
633 static int m88ds3103_init(struct dvb_frontend *fe)
635 struct m88ds3103_dev *dev = fe->demodulator_priv;
636 struct i2c_client *client = dev->client;
637 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
638 int ret, len, remaining;
640 const struct firmware *fw = NULL;
643 dev_dbg(&client->dev, "\n");
645 /* set cold state by default */
648 /* wake up device from sleep */
649 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
652 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
655 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
659 /* firmware status */
660 ret = regmap_read(dev->regmap, 0xb9, &utmp);
664 dev_dbg(&client->dev, "firmware=%02x\n", utmp);
667 goto skip_fw_download;
669 /* global reset, global diseqc reset, golbal fec reset */
670 ret = regmap_write(dev->regmap, 0x07, 0xe0);
673 ret = regmap_write(dev->regmap, 0x07, 0x00);
677 /* cold state - try to download firmware */
678 dev_info(&client->dev, "found a '%s' in cold state\n",
679 m88ds3103_ops.info.name);
681 if (dev->chip_id == M88RS6000_CHIP_ID)
682 fw_file = M88RS6000_FIRMWARE;
684 fw_file = M88DS3103_FIRMWARE;
685 /* request the firmware, this will block and timeout */
686 ret = request_firmware(&fw, fw_file, &client->dev);
688 dev_err(&client->dev, "firmware file '%s' not found\n", fw_file);
692 dev_info(&client->dev, "downloading firmware from file '%s'\n",
695 ret = regmap_write(dev->regmap, 0xb2, 0x01);
697 goto error_fw_release;
699 for (remaining = fw->size; remaining > 0;
700 remaining -= (dev->cfg->i2c_wr_max - 1)) {
702 if (len > (dev->cfg->i2c_wr_max - 1))
703 len = (dev->cfg->i2c_wr_max - 1);
705 ret = regmap_bulk_write(dev->regmap, 0xb0,
706 &fw->data[fw->size - remaining], len);
708 dev_err(&client->dev, "firmware download failed=%d\n",
710 goto error_fw_release;
714 ret = regmap_write(dev->regmap, 0xb2, 0x00);
716 goto error_fw_release;
718 release_firmware(fw);
721 ret = regmap_read(dev->regmap, 0xb9, &utmp);
726 dev_info(&client->dev, "firmware did not run\n");
731 dev_info(&client->dev, "found a '%s' in warm state\n",
732 m88ds3103_ops.info.name);
733 dev_info(&client->dev, "firmware version: %X.%X\n",
734 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
740 /* init stats here in order signal app which stats are supported */
742 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
743 c->post_bit_error.len = 1;
744 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
745 c->post_bit_count.len = 1;
746 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
750 release_firmware(fw);
752 dev_dbg(&client->dev, "failed=%d\n", ret);
756 static int m88ds3103_sleep(struct dvb_frontend *fe)
758 struct m88ds3103_dev *dev = fe->demodulator_priv;
759 struct i2c_client *client = dev->client;
763 dev_dbg(&client->dev, "\n");
766 dev->delivery_system = SYS_UNDEFINED;
769 if (dev->chip_id == M88RS6000_CHIP_ID)
773 ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
778 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
781 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
784 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
790 dev_dbg(&client->dev, "failed=%d\n", ret);
794 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
796 struct m88ds3103_dev *dev = fe->demodulator_priv;
797 struct i2c_client *client = dev->client;
798 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
802 dev_dbg(&client->dev, "\n");
804 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
809 switch (c->delivery_system) {
811 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
815 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
819 switch ((buf[0] >> 2) & 0x01) {
821 c->inversion = INVERSION_OFF;
824 c->inversion = INVERSION_ON;
828 switch ((buf[1] >> 5) & 0x07) {
830 c->fec_inner = FEC_7_8;
833 c->fec_inner = FEC_5_6;
836 c->fec_inner = FEC_3_4;
839 c->fec_inner = FEC_2_3;
842 c->fec_inner = FEC_1_2;
845 dev_dbg(&client->dev, "invalid fec_inner\n");
848 c->modulation = QPSK;
852 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
856 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
860 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
864 switch ((buf[0] >> 0) & 0x0f) {
866 c->fec_inner = FEC_2_5;
869 c->fec_inner = FEC_1_2;
872 c->fec_inner = FEC_3_5;
875 c->fec_inner = FEC_2_3;
878 c->fec_inner = FEC_3_4;
881 c->fec_inner = FEC_4_5;
884 c->fec_inner = FEC_5_6;
887 c->fec_inner = FEC_8_9;
890 c->fec_inner = FEC_9_10;
893 dev_dbg(&client->dev, "invalid fec_inner\n");
896 switch ((buf[0] >> 5) & 0x01) {
898 c->pilot = PILOT_OFF;
905 switch ((buf[0] >> 6) & 0x07) {
907 c->modulation = QPSK;
910 c->modulation = PSK_8;
913 c->modulation = APSK_16;
916 c->modulation = APSK_32;
919 dev_dbg(&client->dev, "invalid modulation\n");
922 switch ((buf[1] >> 7) & 0x01) {
924 c->inversion = INVERSION_OFF;
927 c->inversion = INVERSION_ON;
931 switch ((buf[2] >> 0) & 0x03) {
933 c->rolloff = ROLLOFF_35;
936 c->rolloff = ROLLOFF_25;
939 c->rolloff = ROLLOFF_20;
942 dev_dbg(&client->dev, "invalid rolloff\n");
946 dev_dbg(&client->dev, "invalid delivery_system\n");
951 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
955 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
956 dev->mclk_khz * 1000 / 0x10000;
960 dev_dbg(&client->dev, "failed=%d\n", ret);
964 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
966 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
968 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
969 *snr = div_s64(c->cnr.stat[0].svalue, 100);
976 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
978 struct m88ds3103_dev *dev = fe->demodulator_priv;
980 *ber = dev->dvbv3_ber;
985 static int m88ds3103_set_tone(struct dvb_frontend *fe,
986 enum fe_sec_tone_mode fe_sec_tone_mode)
988 struct m88ds3103_dev *dev = fe->demodulator_priv;
989 struct i2c_client *client = dev->client;
991 unsigned int utmp, tone, reg_a1_mask;
993 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
1000 switch (fe_sec_tone_mode) {
1010 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
1015 utmp = tone << 7 | dev->cfg->envelope_mode << 5;
1016 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1021 ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
1027 dev_dbg(&client->dev, "failed=%d\n", ret);
1031 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1032 enum fe_sec_voltage fe_sec_voltage)
1034 struct m88ds3103_dev *dev = fe->demodulator_priv;
1035 struct i2c_client *client = dev->client;
1038 bool voltage_sel, voltage_dis;
1040 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1047 switch (fe_sec_voltage) {
1048 case SEC_VOLTAGE_18:
1050 voltage_dis = false;
1052 case SEC_VOLTAGE_13:
1053 voltage_sel = false;
1054 voltage_dis = false;
1056 case SEC_VOLTAGE_OFF:
1057 voltage_sel = false;
1061 dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1066 /* output pin polarity */
1067 voltage_sel ^= dev->cfg->lnb_hv_pol;
1068 voltage_dis ^= dev->cfg->lnb_en_pol;
1070 utmp = voltage_dis << 1 | voltage_sel << 0;
1071 ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
1077 dev_dbg(&client->dev, "failed=%d\n", ret);
1081 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1082 struct dvb_diseqc_master_cmd *diseqc_cmd)
1084 struct m88ds3103_dev *dev = fe->demodulator_priv;
1085 struct i2c_client *client = dev->client;
1088 unsigned long timeout;
1090 dev_dbg(&client->dev, "msg=%*ph\n",
1091 diseqc_cmd->msg_len, diseqc_cmd->msg);
1098 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1103 utmp = dev->cfg->envelope_mode << 5;
1104 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1108 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1109 diseqc_cmd->msg_len);
1113 ret = regmap_write(dev->regmap, 0xa1,
1114 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1118 /* wait DiSEqC TX ready */
1119 #define SEND_MASTER_CMD_TIMEOUT 120
1120 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1122 /* DiSEqC message typical period is 54 ms */
1123 usleep_range(50000, 54000);
1125 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1126 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1129 utmp = (utmp >> 6) & 0x1;
1133 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1134 jiffies_to_msecs(jiffies) -
1135 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1137 dev_dbg(&client->dev, "diseqc tx timeout\n");
1139 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1144 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1155 dev_dbg(&client->dev, "failed=%d\n", ret);
1159 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1160 enum fe_sec_mini_cmd fe_sec_mini_cmd)
1162 struct m88ds3103_dev *dev = fe->demodulator_priv;
1163 struct i2c_client *client = dev->client;
1165 unsigned int utmp, burst;
1166 unsigned long timeout;
1168 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1175 utmp = dev->cfg->envelope_mode << 5;
1176 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1180 switch (fe_sec_mini_cmd) {
1188 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1193 ret = regmap_write(dev->regmap, 0xa1, burst);
1197 /* wait DiSEqC TX ready */
1198 #define SEND_BURST_TIMEOUT 40
1199 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1201 /* DiSEqC ToneBurst period is 12.5 ms */
1202 usleep_range(8500, 12500);
1204 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1205 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1208 utmp = (utmp >> 6) & 0x1;
1212 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1213 jiffies_to_msecs(jiffies) -
1214 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1216 dev_dbg(&client->dev, "diseqc tx timeout\n");
1218 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1223 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1234 dev_dbg(&client->dev, "failed=%d\n", ret);
1238 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1239 struct dvb_frontend_tune_settings *s)
1241 s->min_delay_ms = 3000;
1246 static void m88ds3103_release(struct dvb_frontend *fe)
1248 struct m88ds3103_dev *dev = fe->demodulator_priv;
1249 struct i2c_client *client = dev->client;
1251 i2c_unregister_device(client);
1254 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1256 struct m88ds3103_dev *dev = mux_priv;
1257 struct i2c_client *client = dev->client;
1259 struct i2c_msg msg = {
1260 .addr = client->addr,
1266 /* Open tuner I2C repeater for 1 xfer, closes automatically */
1267 ret = __i2c_transfer(client->adapter, &msg, 1);
1269 dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1279 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1280 * proper I2C client for legacy media attach binding.
1281 * New users must use I2C client binding directly!
1283 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1284 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1286 struct i2c_client *client;
1287 struct i2c_board_info board_info;
1288 struct m88ds3103_platform_data pdata;
1290 pdata.clk = cfg->clock;
1291 pdata.i2c_wr_max = cfg->i2c_wr_max;
1292 pdata.ts_mode = cfg->ts_mode;
1293 pdata.ts_clk = cfg->ts_clk;
1294 pdata.ts_clk_pol = cfg->ts_clk_pol;
1295 pdata.spec_inv = cfg->spec_inv;
1296 pdata.agc = cfg->agc;
1297 pdata.agc_inv = cfg->agc_inv;
1298 pdata.clk_out = cfg->clock_out;
1299 pdata.envelope_mode = cfg->envelope_mode;
1300 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1301 pdata.lnb_en_pol = cfg->lnb_en_pol;
1302 pdata.attach_in_use = true;
1304 memset(&board_info, 0, sizeof(board_info));
1305 strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1306 board_info.addr = cfg->i2c_addr;
1307 board_info.platform_data = &pdata;
1308 client = i2c_new_device(i2c, &board_info);
1309 if (!client || !client->dev.driver)
1312 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1313 return pdata.get_dvb_frontend(client);
1315 EXPORT_SYMBOL(m88ds3103_attach);
1317 static struct dvb_frontend_ops m88ds3103_ops = {
1318 .delsys = {SYS_DVBS, SYS_DVBS2},
1320 .name = "Montage Technology M88DS3103",
1321 .frequency_min = 950000,
1322 .frequency_max = 2150000,
1323 .frequency_tolerance = 5000,
1324 .symbol_rate_min = 1000000,
1325 .symbol_rate_max = 45000000,
1326 .caps = FE_CAN_INVERSION_AUTO |
1338 FE_CAN_2G_MODULATION
1341 .release = m88ds3103_release,
1343 .get_tune_settings = m88ds3103_get_tune_settings,
1345 .init = m88ds3103_init,
1346 .sleep = m88ds3103_sleep,
1348 .set_frontend = m88ds3103_set_frontend,
1349 .get_frontend = m88ds3103_get_frontend,
1351 .read_status = m88ds3103_read_status,
1352 .read_snr = m88ds3103_read_snr,
1353 .read_ber = m88ds3103_read_ber,
1355 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1356 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1358 .set_tone = m88ds3103_set_tone,
1359 .set_voltage = m88ds3103_set_voltage,
1362 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1364 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1366 dev_dbg(&client->dev, "\n");
1371 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1373 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1375 dev_dbg(&client->dev, "\n");
1377 return dev->i2c_adapter;
1380 static int m88ds3103_probe(struct i2c_client *client,
1381 const struct i2c_device_id *id)
1383 struct m88ds3103_dev *dev;
1384 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1388 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1394 dev->client = client;
1395 dev->config.clock = pdata->clk;
1396 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1397 dev->config.ts_mode = pdata->ts_mode;
1398 dev->config.ts_clk = pdata->ts_clk;
1399 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1400 dev->config.spec_inv = pdata->spec_inv;
1401 dev->config.agc_inv = pdata->agc_inv;
1402 dev->config.clock_out = pdata->clk_out;
1403 dev->config.envelope_mode = pdata->envelope_mode;
1404 dev->config.agc = pdata->agc;
1405 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1406 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1407 dev->cfg = &dev->config;
1409 dev->regmap_config.reg_bits = 8,
1410 dev->regmap_config.val_bits = 8,
1411 dev->regmap_config.lock_arg = dev,
1412 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1413 if (IS_ERR(dev->regmap)) {
1414 ret = PTR_ERR(dev->regmap);
1418 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1419 ret = regmap_read(dev->regmap, 0x00, &utmp);
1423 dev->chip_id = utmp >> 1;
1424 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1426 switch (dev->chip_id) {
1427 case M88RS6000_CHIP_ID:
1428 case M88DS3103_CHIP_ID:
1434 switch (dev->cfg->clock_out) {
1435 case M88DS3103_CLOCK_OUT_DISABLED:
1438 case M88DS3103_CLOCK_OUT_ENABLED:
1441 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1449 /* 0x29 register is defined differently for m88rs6000. */
1450 /* set internal tuner address to 0x21 */
1451 if (dev->chip_id == M88RS6000_CHIP_ID)
1454 ret = regmap_write(dev->regmap, 0x29, utmp);
1459 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1462 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1465 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1469 /* create mux i2c adapter for tuner */
1470 dev->i2c_adapter = i2c_add_mux_adapter(client->adapter, &client->dev,
1471 dev, 0, 0, 0, m88ds3103_select,
1473 if (dev->i2c_adapter == NULL) {
1478 /* create dvb_frontend */
1479 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1480 if (dev->chip_id == M88RS6000_CHIP_ID)
1481 strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1482 sizeof(dev->fe.ops.info.name));
1483 if (!pdata->attach_in_use)
1484 dev->fe.ops.release = NULL;
1485 dev->fe.demodulator_priv = dev;
1486 i2c_set_clientdata(client, dev);
1488 /* setup callbacks */
1489 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1490 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1495 dev_dbg(&client->dev, "failed=%d\n", ret);
1499 static int m88ds3103_remove(struct i2c_client *client)
1501 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1503 dev_dbg(&client->dev, "\n");
1505 i2c_del_mux_adapter(dev->i2c_adapter);
1511 static const struct i2c_device_id m88ds3103_id_table[] = {
1515 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1517 static struct i2c_driver m88ds3103_driver = {
1519 .name = "m88ds3103",
1520 .suppress_bind_attrs = true,
1522 .probe = m88ds3103_probe,
1523 .remove = m88ds3103_remove,
1524 .id_table = m88ds3103_id_table,
1527 module_i2c_driver(m88ds3103_driver);
1529 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1530 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1531 MODULE_LICENSE("GPL");
1532 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1533 MODULE_FIRMWARE(M88RS6000_FIRMWARE);