2 * Montage M88DS3103 demodulator driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "m88ds3103_priv.h"
23 static struct dvb_frontend_ops m88ds3103_ops;
25 /* write multiple registers */
26 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
27 u8 reg, const u8 *val, int len)
30 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
32 u8 buf[MAX_WR_XFER_LEN];
33 struct i2c_msg msg[1] = {
35 .addr = priv->cfg->i2c_addr,
42 if (WARN_ON(len > MAX_WR_LEN))
46 memcpy(&buf[1], val, len);
48 mutex_lock(&priv->i2c_mutex);
49 ret = i2c_transfer(priv->i2c, msg, 1);
50 mutex_unlock(&priv->i2c_mutex);
54 dev_warn(&priv->i2c->dev,
55 "%s: i2c wr failed=%d reg=%02x len=%d\n",
56 KBUILD_MODNAME, ret, reg, len);
63 /* read multiple registers */
64 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
65 u8 reg, u8 *val, int len)
68 #define MAX_RD_XFER_LEN (MAX_RD_LEN)
70 u8 buf[MAX_RD_XFER_LEN];
71 struct i2c_msg msg[2] = {
73 .addr = priv->cfg->i2c_addr,
78 .addr = priv->cfg->i2c_addr,
85 if (WARN_ON(len > MAX_RD_LEN))
88 mutex_lock(&priv->i2c_mutex);
89 ret = i2c_transfer(priv->i2c, msg, 2);
90 mutex_unlock(&priv->i2c_mutex);
92 memcpy(val, buf, len);
95 dev_warn(&priv->i2c->dev,
96 "%s: i2c rd failed=%d reg=%02x len=%d\n",
97 KBUILD_MODNAME, ret, reg, len);
104 /* write single register */
105 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
107 return m88ds3103_wr_regs(priv, reg, &val, 1);
110 /* read single register */
111 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
113 return m88ds3103_rd_regs(priv, reg, val, 1);
116 /* write single register with mask */
117 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
118 u8 reg, u8 val, u8 mask)
123 /* no need for read if whole reg is written */
125 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
134 return m88ds3103_wr_regs(priv, reg, &val, 1);
137 /* read single register with mask */
138 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
139 u8 reg, u8 *val, u8 mask)
144 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
150 /* find position of the first bit */
151 for (i = 0; i < 8; i++) {
152 if ((mask >> i) & 0x01)
160 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
162 struct m88ds3103_priv *priv = fe->demodulator_priv;
163 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
174 switch (c->delivery_system) {
176 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
181 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
182 FE_HAS_VITERBI | FE_HAS_SYNC |
186 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
191 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
192 FE_HAS_VITERBI | FE_HAS_SYNC |
196 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
202 priv->fe_status = *status;
204 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
205 __func__, u8tmp, *status);
209 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
213 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
215 struct m88ds3103_priv *priv = fe->demodulator_priv;
216 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
218 const struct m88ds3103_reg_val *init;
219 u8 u8tmp, u8tmp1, u8tmp2;
221 u16 u16tmp, divide_ratio;
222 u32 tuner_frequency, target_mclk, ts_clk;
224 dev_dbg(&priv->i2c->dev,
225 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
226 __func__, c->delivery_system,
227 c->modulation, c->frequency, c->symbol_rate,
228 c->inversion, c->pilot, c->rolloff);
236 if (fe->ops.tuner_ops.set_params) {
237 ret = fe->ops.tuner_ops.set_params(fe);
242 if (fe->ops.tuner_ops.get_frequency) {
243 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
249 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
253 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
257 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
261 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
265 switch (c->delivery_system) {
267 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
268 init = m88ds3103_dvbs_init_reg_vals;
272 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
273 init = m88ds3103_dvbs2_init_reg_vals;
275 switch (priv->cfg->ts_mode) {
276 case M88DS3103_TS_SERIAL:
277 case M88DS3103_TS_SERIAL_D7:
278 if (c->symbol_rate < 18000000)
281 target_mclk = 144000;
283 case M88DS3103_TS_PARALLEL:
284 case M88DS3103_TS_PARALLEL_12:
285 case M88DS3103_TS_PARALLEL_16:
286 case M88DS3103_TS_PARALLEL_19_2:
287 case M88DS3103_TS_CI:
288 if (c->symbol_rate < 18000000)
290 else if (c->symbol_rate < 28000000)
291 target_mclk = 144000;
293 target_mclk = 192000;
296 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
303 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
309 /* program init table */
310 if (c->delivery_system != priv->delivery_system) {
311 dev_dbg(&priv->i2c->dev, "%s: program init\n", __func__);
312 for (i = 0; i < len; i++) {
313 ret = m88ds3103_wr_reg(priv, init[i].reg, init[i].val);
319 u8tmp1 = 0; /* silence compiler warning */
320 switch (priv->cfg->ts_mode) {
321 case M88DS3103_TS_SERIAL:
326 case M88DS3103_TS_SERIAL_D7:
331 case M88DS3103_TS_PARALLEL:
335 case M88DS3103_TS_PARALLEL_12:
339 case M88DS3103_TS_PARALLEL_16:
343 case M88DS3103_TS_PARALLEL_19_2:
347 case M88DS3103_TS_CI:
352 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
358 ret = m88ds3103_wr_reg_mask(priv, 0xfd, u8tmp, 0x05);
362 switch (priv->cfg->ts_mode) {
363 case M88DS3103_TS_SERIAL:
364 case M88DS3103_TS_SERIAL_D7:
365 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
371 divide_ratio = DIV_ROUND_UP(target_mclk, ts_clk);
372 u8tmp1 = divide_ratio / 2;
373 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
380 dev_dbg(&priv->i2c->dev,
381 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
382 __func__, target_mclk, ts_clk, divide_ratio);
386 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
388 /* u8tmp2[5:0] => ea[5:0] */
391 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
395 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
396 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
400 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
401 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
405 switch (target_mclk) {
407 u8tmp1 = 0x00; /* 0b00 */
408 u8tmp2 = 0x03; /* 0b11 */
411 u8tmp1 = 0x02; /* 0b10 */
412 u8tmp2 = 0x01; /* 0b01 */
415 u8tmp1 = 0x01; /* 0b01 */
416 u8tmp2 = 0x01; /* 0b01 */
419 u8tmp1 = 0x00; /* 0b00 */
420 u8tmp2 = 0x01; /* 0b01 */
423 u8tmp1 = 0x03; /* 0b11 */
424 u8tmp2 = 0x00; /* 0b00 */
427 dev_dbg(&priv->i2c->dev, "%s: invalid target_mclk\n", __func__);
432 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
436 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
440 if (c->symbol_rate <= 3000000)
442 else if (c->symbol_rate <= 10000000)
447 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
451 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
455 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
459 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
463 u16tmp = (((c->symbol_rate / 1000) << 15) + (M88DS3103_MCLK_KHZ / 4)) /
464 (M88DS3103_MCLK_KHZ / 2);
465 buf[0] = (u16tmp >> 0) & 0xff;
466 buf[1] = (u16tmp >> 8) & 0xff;
467 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
471 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
475 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
479 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
483 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
484 (tuner_frequency - c->frequency));
486 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
487 s32tmp = (2 * s32tmp + M88DS3103_MCLK_KHZ) / (2 * M88DS3103_MCLK_KHZ);
491 buf[0] = (s32tmp >> 0) & 0xff;
492 buf[1] = (s32tmp >> 8) & 0xff;
493 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
497 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
501 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
505 priv->delivery_system = c->delivery_system;
509 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
513 static int m88ds3103_init(struct dvb_frontend *fe)
515 struct m88ds3103_priv *priv = fe->demodulator_priv;
516 int ret, len, remaining;
517 const struct firmware *fw = NULL;
518 u8 *fw_file = M88DS3103_FIRMWARE;
520 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
522 /* set cold state by default */
525 /* wake up device from sleep */
526 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
530 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
534 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
539 ret = m88ds3103_wr_reg(priv, 0x07, 0x60);
543 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
547 /* firmware status */
548 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
552 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
555 goto skip_fw_download;
557 /* cold state - try to download firmware */
558 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
559 KBUILD_MODNAME, m88ds3103_ops.info.name);
561 /* request the firmware, this will block and timeout */
562 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
564 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
565 KBUILD_MODNAME, fw_file);
569 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
570 KBUILD_MODNAME, fw_file);
572 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
576 for (remaining = fw->size; remaining > 0;
577 remaining -= (priv->cfg->i2c_wr_max - 1)) {
579 if (len > (priv->cfg->i2c_wr_max - 1))
580 len = (priv->cfg->i2c_wr_max - 1);
582 ret = m88ds3103_wr_regs(priv, 0xb0,
583 &fw->data[fw->size - remaining], len);
585 dev_err(&priv->i2c->dev,
586 "%s: firmware download failed=%d\n",
587 KBUILD_MODNAME, ret);
592 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
596 release_firmware(fw);
599 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
604 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
610 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
611 KBUILD_MODNAME, m88ds3103_ops.info.name);
612 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
613 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
622 release_firmware(fw);
624 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
628 static int m88ds3103_sleep(struct dvb_frontend *fe)
630 struct m88ds3103_priv *priv = fe->demodulator_priv;
632 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
634 priv->delivery_system = SYS_UNDEFINED;
637 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01);
642 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
646 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
650 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
656 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
660 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
662 struct m88ds3103_priv *priv = fe->demodulator_priv;
663 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
666 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
668 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
673 switch (c->delivery_system) {
675 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
679 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
683 switch ((buf[0] >> 2) & 0x01) {
685 c->inversion = INVERSION_OFF;
688 c->inversion = INVERSION_ON;
691 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n",
695 switch ((buf[1] >> 5) & 0x07) {
697 c->fec_inner = FEC_7_8;
700 c->fec_inner = FEC_5_6;
703 c->fec_inner = FEC_3_4;
706 c->fec_inner = FEC_2_3;
709 c->fec_inner = FEC_1_2;
712 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
716 c->modulation = QPSK;
720 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
724 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
728 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
732 switch ((buf[0] >> 0) & 0x0f) {
734 c->fec_inner = FEC_2_5;
737 c->fec_inner = FEC_1_2;
740 c->fec_inner = FEC_3_5;
743 c->fec_inner = FEC_2_3;
746 c->fec_inner = FEC_3_4;
749 c->fec_inner = FEC_4_5;
752 c->fec_inner = FEC_5_6;
755 c->fec_inner = FEC_8_9;
758 c->fec_inner = FEC_9_10;
761 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
765 switch ((buf[0] >> 5) & 0x01) {
767 c->pilot = PILOT_OFF;
773 dev_dbg(&priv->i2c->dev, "%s: invalid pilot\n",
777 switch ((buf[0] >> 6) & 0x07) {
779 c->modulation = QPSK;
782 c->modulation = PSK_8;
785 c->modulation = APSK_16;
788 c->modulation = APSK_32;
791 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
795 switch ((buf[1] >> 7) & 0x01) {
797 c->inversion = INVERSION_OFF;
800 c->inversion = INVERSION_ON;
803 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n",
807 switch ((buf[2] >> 0) & 0x03) {
809 c->rolloff = ROLLOFF_35;
812 c->rolloff = ROLLOFF_25;
815 c->rolloff = ROLLOFF_20;
818 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
823 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
829 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
833 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
834 M88DS3103_MCLK_KHZ * 1000 / 0x10000;
838 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
842 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
844 struct m88ds3103_priv *priv = fe->demodulator_priv;
845 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
849 u32 noise_tot, signal_tot;
850 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
851 /* reports SNR in resolution of 0.1 dB */
853 /* more iterations for more accurate estimation */
854 #define M88DS3103_SNR_ITERATIONS 3
856 switch (c->delivery_system) {
860 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
861 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
868 /* use of one register limits max value to 15 dB */
869 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
870 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
872 *snr = 100ul * intlog2(tmp) / intlog2(10);
880 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
881 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
885 noise = buf[1] << 6; /* [13:6] */
886 noise |= buf[0] & 0x3f; /* [5:0] */
888 signal = buf[2] * buf[2];
892 signal_tot += signal;
895 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
896 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
898 /* SNR(X) dB = 10 * log10(X) dB */
899 if (signal > noise) {
900 tmp = signal / noise;
901 *snr = 100ul * intlog10(tmp) / (1 << 24);
906 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
914 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
919 static int m88ds3103_set_tone(struct dvb_frontend *fe,
920 fe_sec_tone_mode_t fe_sec_tone_mode)
922 struct m88ds3103_priv *priv = fe->demodulator_priv;
924 u8 u8tmp, tone, reg_a1_mask;
925 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
933 switch (fe_sec_tone_mode) {
943 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
949 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
950 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
955 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
961 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
965 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
966 struct dvb_diseqc_master_cmd *diseqc_cmd)
968 struct m88ds3103_priv *priv = fe->demodulator_priv;
971 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
972 diseqc_cmd->msg_len, diseqc_cmd->msg);
979 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
984 u8tmp = priv->cfg->envelope_mode << 5;
985 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
989 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
990 diseqc_cmd->msg_len);
994 ret = m88ds3103_wr_reg(priv, 0xa1,
995 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
999 /* DiSEqC message typical period is 54 ms */
1000 usleep_range(40000, 60000);
1002 /* wait DiSEqC TX ready */
1003 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1004 usleep_range(5000, 10000);
1006 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1011 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1014 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1016 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1021 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1032 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1036 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1037 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1039 struct m88ds3103_priv *priv = fe->demodulator_priv;
1042 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1050 u8tmp = priv->cfg->envelope_mode << 5;
1051 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1055 switch (fe_sec_mini_cmd) {
1063 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1069 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1073 /* DiSEqC ToneBurst period is 12.5 ms */
1074 usleep_range(11000, 20000);
1076 /* wait DiSEqC TX ready */
1077 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1078 usleep_range(800, 2000);
1080 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1085 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1087 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1092 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1099 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1103 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1104 struct dvb_frontend_tune_settings *s)
1106 s->min_delay_ms = 3000;
1111 static void m88ds3103_release(struct dvb_frontend *fe)
1113 struct m88ds3103_priv *priv = fe->demodulator_priv;
1114 i2c_del_mux_adapter(priv->i2c_adapter);
1118 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1120 struct m88ds3103_priv *priv = mux_priv;
1122 struct i2c_msg gate_open_msg[1] = {
1124 .addr = priv->cfg->i2c_addr,
1131 mutex_lock(&priv->i2c_mutex);
1133 /* open tuner I2C repeater for 1 xfer, closes automatically */
1134 ret = i2c_transfer(priv->i2c, gate_open_msg, 1);
1136 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
1137 KBUILD_MODNAME, ret);
1147 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1150 struct m88ds3103_priv *priv = mux_priv;
1152 mutex_unlock(&priv->i2c_mutex);
1157 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1158 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1161 struct m88ds3103_priv *priv;
1164 /* allocate memory for the internal priv */
1165 priv = kzalloc(sizeof(struct m88ds3103_priv), GFP_KERNEL);
1168 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1174 mutex_init(&priv->i2c_mutex);
1176 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id);
1180 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1189 switch (priv->cfg->clock_out) {
1190 case M88DS3103_CLOCK_OUT_DISABLED:
1193 case M88DS3103_CLOCK_OUT_ENABLED:
1196 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1203 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1208 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1212 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1216 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1220 /* create mux i2c adapter for tuner */
1221 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1222 m88ds3103_select, m88ds3103_deselect);
1223 if (priv->i2c_adapter == NULL)
1226 *tuner_i2c_adapter = priv->i2c_adapter;
1228 /* create dvb_frontend */
1229 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1230 priv->fe.demodulator_priv = priv;
1234 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1238 EXPORT_SYMBOL(m88ds3103_attach);
1240 static struct dvb_frontend_ops m88ds3103_ops = {
1241 .delsys = { SYS_DVBS, SYS_DVBS2 },
1243 .name = "Montage M88DS3103",
1244 .frequency_min = 950000,
1245 .frequency_max = 2150000,
1246 .frequency_tolerance = 5000,
1247 .symbol_rate_min = 1000000,
1248 .symbol_rate_max = 45000000,
1249 .caps = FE_CAN_INVERSION_AUTO |
1261 FE_CAN_2G_MODULATION
1264 .release = m88ds3103_release,
1266 .get_tune_settings = m88ds3103_get_tune_settings,
1268 .init = m88ds3103_init,
1269 .sleep = m88ds3103_sleep,
1271 .set_frontend = m88ds3103_set_frontend,
1272 .get_frontend = m88ds3103_get_frontend,
1274 .read_status = m88ds3103_read_status,
1275 .read_snr = m88ds3103_read_snr,
1277 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1278 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1280 .set_tone = m88ds3103_set_tone,
1283 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1284 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1285 MODULE_LICENSE("GPL");
1286 MODULE_FIRMWARE(M88DS3103_FIRMWARE);