2 * Montage M88DS3103 demodulator driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include "m88ds3103_priv.h"
19 static struct dvb_frontend_ops m88ds3103_ops;
21 /* write multiple registers */
22 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
23 u8 reg, const u8 *val, int len)
26 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
28 u8 buf[MAX_WR_XFER_LEN];
29 struct i2c_msg msg[1] = {
31 .addr = priv->cfg->i2c_addr,
38 if (WARN_ON(len > MAX_WR_LEN))
42 memcpy(&buf[1], val, len);
44 mutex_lock(&priv->i2c_mutex);
45 ret = i2c_transfer(priv->i2c, msg, 1);
46 mutex_unlock(&priv->i2c_mutex);
50 dev_warn(&priv->i2c->dev,
51 "%s: i2c wr failed=%d reg=%02x len=%d\n",
52 KBUILD_MODNAME, ret, reg, len);
59 /* read multiple registers */
60 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
61 u8 reg, u8 *val, int len)
64 #define MAX_RD_XFER_LEN (MAX_RD_LEN)
66 u8 buf[MAX_RD_XFER_LEN];
67 struct i2c_msg msg[2] = {
69 .addr = priv->cfg->i2c_addr,
74 .addr = priv->cfg->i2c_addr,
81 if (WARN_ON(len > MAX_RD_LEN))
84 mutex_lock(&priv->i2c_mutex);
85 ret = i2c_transfer(priv->i2c, msg, 2);
86 mutex_unlock(&priv->i2c_mutex);
88 memcpy(val, buf, len);
91 dev_warn(&priv->i2c->dev,
92 "%s: i2c rd failed=%d reg=%02x len=%d\n",
93 KBUILD_MODNAME, ret, reg, len);
100 /* write single register */
101 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
103 return m88ds3103_wr_regs(priv, reg, &val, 1);
106 /* read single register */
107 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
109 return m88ds3103_rd_regs(priv, reg, val, 1);
112 /* write single register with mask */
113 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
114 u8 reg, u8 val, u8 mask)
119 /* no need for read if whole reg is written */
121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
130 return m88ds3103_wr_regs(priv, reg, &val, 1);
133 /* read single register with mask */
134 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
135 u8 reg, u8 *val, u8 mask)
140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
146 /* find position of the first bit */
147 for (i = 0; i < 8; i++) {
148 if ((mask >> i) & 0x01)
156 /* write reg val table using reg addr auto increment */
157 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
158 const struct m88ds3103_reg_val *tab, int tab_len)
162 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
169 for (i = 0, j = 0; i < tab_len; i++, j++) {
172 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
173 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
174 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
184 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
188 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
190 struct m88ds3103_priv *priv = fe->demodulator_priv;
191 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
202 switch (c->delivery_system) {
204 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
209 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
210 FE_HAS_VITERBI | FE_HAS_SYNC |
214 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
219 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
220 FE_HAS_VITERBI | FE_HAS_SYNC |
224 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
230 priv->fe_status = *status;
232 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
233 __func__, u8tmp, *status);
237 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
241 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
243 struct m88ds3103_priv *priv = fe->demodulator_priv;
244 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
246 const struct m88ds3103_reg_val *init;
247 u8 u8tmp, u8tmp1, u8tmp2;
249 u16 u16tmp, divide_ratio;
250 u32 tuner_frequency, target_mclk, ts_clk;
252 dev_dbg(&priv->i2c->dev,
253 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
254 __func__, c->delivery_system,
255 c->modulation, c->frequency, c->symbol_rate,
256 c->inversion, c->pilot, c->rolloff);
264 if (fe->ops.tuner_ops.set_params) {
265 ret = fe->ops.tuner_ops.set_params(fe);
270 if (fe->ops.tuner_ops.get_frequency) {
271 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
277 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
281 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
285 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
289 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
293 switch (c->delivery_system) {
295 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
296 init = m88ds3103_dvbs_init_reg_vals;
300 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
301 init = m88ds3103_dvbs2_init_reg_vals;
303 switch (priv->cfg->ts_mode) {
304 case M88DS3103_TS_SERIAL:
305 case M88DS3103_TS_SERIAL_D7:
306 if (c->symbol_rate < 18000000)
309 target_mclk = 144000;
311 case M88DS3103_TS_PARALLEL:
312 case M88DS3103_TS_PARALLEL_12:
313 case M88DS3103_TS_PARALLEL_16:
314 case M88DS3103_TS_PARALLEL_19_2:
315 case M88DS3103_TS_CI:
316 if (c->symbol_rate < 18000000)
318 else if (c->symbol_rate < 28000000)
319 target_mclk = 144000;
321 target_mclk = 192000;
324 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
331 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
337 /* program init table */
338 if (c->delivery_system != priv->delivery_system) {
339 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
344 u8tmp1 = 0; /* silence compiler warning */
345 switch (priv->cfg->ts_mode) {
346 case M88DS3103_TS_SERIAL:
351 case M88DS3103_TS_SERIAL_D7:
356 case M88DS3103_TS_PARALLEL:
360 case M88DS3103_TS_PARALLEL_12:
364 case M88DS3103_TS_PARALLEL_16:
368 case M88DS3103_TS_PARALLEL_19_2:
372 case M88DS3103_TS_CI:
377 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
383 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
387 switch (priv->cfg->ts_mode) {
388 case M88DS3103_TS_SERIAL:
389 case M88DS3103_TS_SERIAL_D7:
390 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
396 divide_ratio = DIV_ROUND_UP(target_mclk, ts_clk);
397 u8tmp1 = divide_ratio / 2;
398 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
405 dev_dbg(&priv->i2c->dev,
406 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
407 __func__, target_mclk, ts_clk, divide_ratio);
411 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
413 /* u8tmp2[5:0] => ea[5:0] */
416 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
420 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
421 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
425 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
426 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
430 switch (target_mclk) {
432 u8tmp1 = 0x00; /* 0b00 */
433 u8tmp2 = 0x03; /* 0b11 */
436 u8tmp1 = 0x02; /* 0b10 */
437 u8tmp2 = 0x01; /* 0b01 */
440 u8tmp1 = 0x01; /* 0b01 */
441 u8tmp2 = 0x01; /* 0b01 */
444 u8tmp1 = 0x00; /* 0b00 */
445 u8tmp2 = 0x01; /* 0b01 */
448 u8tmp1 = 0x03; /* 0b11 */
449 u8tmp2 = 0x00; /* 0b00 */
452 dev_dbg(&priv->i2c->dev, "%s: invalid target_mclk\n", __func__);
457 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
461 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
465 if (c->symbol_rate <= 3000000)
467 else if (c->symbol_rate <= 10000000)
472 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
476 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
480 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
484 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
488 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, M88DS3103_MCLK_KHZ / 2);
489 buf[0] = (u16tmp >> 0) & 0xff;
490 buf[1] = (u16tmp >> 8) & 0xff;
491 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
495 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
499 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
503 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
507 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
508 (tuner_frequency - c->frequency));
510 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
511 s32tmp = DIV_ROUND_CLOSEST(s32tmp, M88DS3103_MCLK_KHZ);
515 buf[0] = (s32tmp >> 0) & 0xff;
516 buf[1] = (s32tmp >> 8) & 0xff;
517 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
521 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
525 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
529 priv->delivery_system = c->delivery_system;
533 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
537 static int m88ds3103_init(struct dvb_frontend *fe)
539 struct m88ds3103_priv *priv = fe->demodulator_priv;
540 int ret, len, remaining;
541 const struct firmware *fw = NULL;
542 u8 *fw_file = M88DS3103_FIRMWARE;
544 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
546 /* set cold state by default */
549 /* wake up device from sleep */
550 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
554 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
558 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
563 ret = m88ds3103_wr_reg(priv, 0x07, 0x60);
567 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
571 /* firmware status */
572 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
576 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
579 goto skip_fw_download;
581 /* cold state - try to download firmware */
582 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
583 KBUILD_MODNAME, m88ds3103_ops.info.name);
585 /* request the firmware, this will block and timeout */
586 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
588 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
589 KBUILD_MODNAME, fw_file);
593 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
594 KBUILD_MODNAME, fw_file);
596 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
600 for (remaining = fw->size; remaining > 0;
601 remaining -= (priv->cfg->i2c_wr_max - 1)) {
603 if (len > (priv->cfg->i2c_wr_max - 1))
604 len = (priv->cfg->i2c_wr_max - 1);
606 ret = m88ds3103_wr_regs(priv, 0xb0,
607 &fw->data[fw->size - remaining], len);
609 dev_err(&priv->i2c->dev,
610 "%s: firmware download failed=%d\n",
611 KBUILD_MODNAME, ret);
616 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
620 release_firmware(fw);
623 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
628 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
634 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
635 KBUILD_MODNAME, m88ds3103_ops.info.name);
636 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
637 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
646 release_firmware(fw);
648 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
652 static int m88ds3103_sleep(struct dvb_frontend *fe)
654 struct m88ds3103_priv *priv = fe->demodulator_priv;
656 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
658 priv->delivery_system = SYS_UNDEFINED;
661 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01);
666 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
670 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
674 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
680 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
684 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
686 struct m88ds3103_priv *priv = fe->demodulator_priv;
687 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
690 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
692 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
697 switch (c->delivery_system) {
699 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
703 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
707 switch ((buf[0] >> 2) & 0x01) {
709 c->inversion = INVERSION_OFF;
712 c->inversion = INVERSION_ON;
716 switch ((buf[1] >> 5) & 0x07) {
718 c->fec_inner = FEC_7_8;
721 c->fec_inner = FEC_5_6;
724 c->fec_inner = FEC_3_4;
727 c->fec_inner = FEC_2_3;
730 c->fec_inner = FEC_1_2;
733 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
737 c->modulation = QPSK;
741 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
745 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
749 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
753 switch ((buf[0] >> 0) & 0x0f) {
755 c->fec_inner = FEC_2_5;
758 c->fec_inner = FEC_1_2;
761 c->fec_inner = FEC_3_5;
764 c->fec_inner = FEC_2_3;
767 c->fec_inner = FEC_3_4;
770 c->fec_inner = FEC_4_5;
773 c->fec_inner = FEC_5_6;
776 c->fec_inner = FEC_8_9;
779 c->fec_inner = FEC_9_10;
782 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
786 switch ((buf[0] >> 5) & 0x01) {
788 c->pilot = PILOT_OFF;
795 switch ((buf[0] >> 6) & 0x07) {
797 c->modulation = QPSK;
800 c->modulation = PSK_8;
803 c->modulation = APSK_16;
806 c->modulation = APSK_32;
809 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
813 switch ((buf[1] >> 7) & 0x01) {
815 c->inversion = INVERSION_OFF;
818 c->inversion = INVERSION_ON;
822 switch ((buf[2] >> 0) & 0x03) {
824 c->rolloff = ROLLOFF_35;
827 c->rolloff = ROLLOFF_25;
830 c->rolloff = ROLLOFF_20;
833 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
838 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
844 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
848 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
849 M88DS3103_MCLK_KHZ * 1000 / 0x10000;
853 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
857 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
859 struct m88ds3103_priv *priv = fe->demodulator_priv;
860 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
864 u32 noise_tot, signal_tot;
865 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
866 /* reports SNR in resolution of 0.1 dB */
868 /* more iterations for more accurate estimation */
869 #define M88DS3103_SNR_ITERATIONS 3
871 switch (c->delivery_system) {
875 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
876 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
883 /* use of one register limits max value to 15 dB */
884 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
885 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
887 *snr = 100ul * intlog2(tmp) / intlog2(10);
895 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
896 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
900 noise = buf[1] << 6; /* [13:6] */
901 noise |= buf[0] & 0x3f; /* [5:0] */
903 signal = buf[2] * buf[2];
907 signal_tot += signal;
910 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
911 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
913 /* SNR(X) dB = 10 * log10(X) dB */
914 if (signal > noise) {
915 tmp = signal / noise;
916 *snr = 100ul * intlog10(tmp) / (1 << 24);
922 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
930 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
935 static int m88ds3103_set_tone(struct dvb_frontend *fe,
936 fe_sec_tone_mode_t fe_sec_tone_mode)
938 struct m88ds3103_priv *priv = fe->demodulator_priv;
940 u8 u8tmp, tone, reg_a1_mask;
941 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
949 switch (fe_sec_tone_mode) {
959 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
965 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
966 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
971 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
977 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
981 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
982 struct dvb_diseqc_master_cmd *diseqc_cmd)
984 struct m88ds3103_priv *priv = fe->demodulator_priv;
987 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
988 diseqc_cmd->msg_len, diseqc_cmd->msg);
995 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1000 u8tmp = priv->cfg->envelope_mode << 5;
1001 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1005 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1006 diseqc_cmd->msg_len);
1010 ret = m88ds3103_wr_reg(priv, 0xa1,
1011 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1015 /* DiSEqC message typical period is 54 ms */
1016 usleep_range(40000, 60000);
1018 /* wait DiSEqC TX ready */
1019 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1020 usleep_range(5000, 10000);
1022 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1027 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1030 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1032 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1037 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1048 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1052 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1053 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1055 struct m88ds3103_priv *priv = fe->demodulator_priv;
1058 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1066 u8tmp = priv->cfg->envelope_mode << 5;
1067 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1071 switch (fe_sec_mini_cmd) {
1079 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1085 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1089 /* DiSEqC ToneBurst period is 12.5 ms */
1090 usleep_range(11000, 20000);
1092 /* wait DiSEqC TX ready */
1093 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1094 usleep_range(800, 2000);
1096 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1101 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1103 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1108 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1115 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1119 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1120 struct dvb_frontend_tune_settings *s)
1122 s->min_delay_ms = 3000;
1127 static void m88ds3103_release(struct dvb_frontend *fe)
1129 struct m88ds3103_priv *priv = fe->demodulator_priv;
1130 i2c_del_mux_adapter(priv->i2c_adapter);
1134 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1136 struct m88ds3103_priv *priv = mux_priv;
1138 struct i2c_msg gate_open_msg[1] = {
1140 .addr = priv->cfg->i2c_addr,
1147 mutex_lock(&priv->i2c_mutex);
1149 /* open tuner I2C repeater for 1 xfer, closes automatically */
1150 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
1152 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
1153 KBUILD_MODNAME, ret);
1163 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1166 struct m88ds3103_priv *priv = mux_priv;
1168 mutex_unlock(&priv->i2c_mutex);
1173 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1174 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1177 struct m88ds3103_priv *priv;
1180 /* allocate memory for the internal priv */
1181 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1184 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1190 mutex_init(&priv->i2c_mutex);
1192 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id);
1196 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1205 switch (priv->cfg->clock_out) {
1206 case M88DS3103_CLOCK_OUT_DISABLED:
1209 case M88DS3103_CLOCK_OUT_ENABLED:
1212 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1219 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1224 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1228 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1232 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1236 /* create mux i2c adapter for tuner */
1237 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1238 m88ds3103_select, m88ds3103_deselect);
1239 if (priv->i2c_adapter == NULL)
1242 *tuner_i2c_adapter = priv->i2c_adapter;
1244 /* create dvb_frontend */
1245 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1246 priv->fe.demodulator_priv = priv;
1250 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1254 EXPORT_SYMBOL(m88ds3103_attach);
1256 static struct dvb_frontend_ops m88ds3103_ops = {
1257 .delsys = { SYS_DVBS, SYS_DVBS2 },
1259 .name = "Montage M88DS3103",
1260 .frequency_min = 950000,
1261 .frequency_max = 2150000,
1262 .frequency_tolerance = 5000,
1263 .symbol_rate_min = 1000000,
1264 .symbol_rate_max = 45000000,
1265 .caps = FE_CAN_INVERSION_AUTO |
1277 FE_CAN_2G_MODULATION
1280 .release = m88ds3103_release,
1282 .get_tune_settings = m88ds3103_get_tune_settings,
1284 .init = m88ds3103_init,
1285 .sleep = m88ds3103_sleep,
1287 .set_frontend = m88ds3103_set_frontend,
1288 .get_frontend = m88ds3103_get_frontend,
1290 .read_status = m88ds3103_read_status,
1291 .read_snr = m88ds3103_read_snr,
1293 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1294 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1296 .set_tone = m88ds3103_set_tone,
1299 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1300 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1301 MODULE_LICENSE("GPL");
1302 MODULE_FIRMWARE(M88DS3103_FIRMWARE);