2 * Montage M88DS3103/M88RS6000 demodulator driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include "m88ds3103_priv.h"
19 static struct dvb_frontend_ops m88ds3103_ops;
21 /* write multiple registers */
22 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
23 u8 reg, const u8 *val, int len)
26 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
28 u8 buf[MAX_WR_XFER_LEN];
29 struct i2c_msg msg[1] = {
31 .addr = priv->cfg->i2c_addr,
38 if (WARN_ON(len > MAX_WR_LEN))
42 memcpy(&buf[1], val, len);
44 mutex_lock(&priv->i2c_mutex);
45 ret = i2c_transfer(priv->i2c, msg, 1);
46 mutex_unlock(&priv->i2c_mutex);
50 dev_warn(&priv->i2c->dev,
51 "%s: i2c wr failed=%d reg=%02x len=%d\n",
52 KBUILD_MODNAME, ret, reg, len);
59 /* read multiple registers */
60 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
61 u8 reg, u8 *val, int len)
64 #define MAX_RD_XFER_LEN (MAX_RD_LEN)
66 u8 buf[MAX_RD_XFER_LEN];
67 struct i2c_msg msg[2] = {
69 .addr = priv->cfg->i2c_addr,
74 .addr = priv->cfg->i2c_addr,
81 if (WARN_ON(len > MAX_RD_LEN))
84 mutex_lock(&priv->i2c_mutex);
85 ret = i2c_transfer(priv->i2c, msg, 2);
86 mutex_unlock(&priv->i2c_mutex);
88 memcpy(val, buf, len);
91 dev_warn(&priv->i2c->dev,
92 "%s: i2c rd failed=%d reg=%02x len=%d\n",
93 KBUILD_MODNAME, ret, reg, len);
100 /* write single register */
101 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
103 return m88ds3103_wr_regs(priv, reg, &val, 1);
106 /* read single register */
107 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
109 return m88ds3103_rd_regs(priv, reg, val, 1);
112 /* write single register with mask */
113 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
114 u8 reg, u8 val, u8 mask)
119 /* no need for read if whole reg is written */
121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
130 return m88ds3103_wr_regs(priv, reg, &val, 1);
133 /* read single register with mask */
134 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
135 u8 reg, u8 *val, u8 mask)
140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
146 /* find position of the first bit */
147 for (i = 0; i < 8; i++) {
148 if ((mask >> i) & 0x01)
156 /* write reg val table using reg addr auto increment */
157 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
158 const struct m88ds3103_reg_val *tab, int tab_len)
163 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
170 for (i = 0, j = 0; i < tab_len; i++, j++) {
173 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
174 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
175 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
185 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
189 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
191 struct m88ds3103_priv *priv = fe->demodulator_priv;
192 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
203 switch (c->delivery_system) {
205 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
210 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
211 FE_HAS_VITERBI | FE_HAS_SYNC |
215 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
220 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
221 FE_HAS_VITERBI | FE_HAS_SYNC |
225 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
231 priv->fe_status = *status;
233 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
234 __func__, u8tmp, *status);
238 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
242 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
244 struct m88ds3103_priv *priv = fe->demodulator_priv;
245 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
247 const struct m88ds3103_reg_val *init;
248 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
250 u16 u16tmp, divide_ratio = 0;
251 u32 tuner_frequency, target_mclk;
254 dev_dbg(&priv->i2c->dev,
255 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
256 __func__, c->delivery_system,
257 c->modulation, c->frequency, c->symbol_rate,
258 c->inversion, c->pilot, c->rolloff);
266 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
270 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
274 /* Disable demod clock path */
275 if (priv->chip_id == M88RS6000_CHIP_ID) {
276 ret = m88ds3103_wr_reg(priv, 0x06, 0xe0);
282 if (fe->ops.tuner_ops.set_params) {
283 ret = fe->ops.tuner_ops.set_params(fe);
288 if (fe->ops.tuner_ops.get_frequency) {
289 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
294 * Use nominal target frequency as tuner driver does not provide
295 * actual frequency used. Carrier offset calculation is not
298 tuner_frequency = c->frequency;
301 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
302 if (priv->chip_id == M88RS6000_CHIP_ID) {
303 if (c->symbol_rate > 45010000)
304 priv->mclk_khz = 110250;
306 priv->mclk_khz = 96000;
308 if (c->delivery_system == SYS_DVBS)
311 target_mclk = 144000;
313 /* Enable demod clock path */
314 ret = m88ds3103_wr_reg(priv, 0x06, 0x00);
317 usleep_range(10000, 20000);
319 /* set M88DS3103 mclk and ts mclk. */
320 priv->mclk_khz = 96000;
322 switch (priv->cfg->ts_mode) {
323 case M88DS3103_TS_SERIAL:
324 case M88DS3103_TS_SERIAL_D7:
325 target_mclk = priv->cfg->ts_clk;
327 case M88DS3103_TS_PARALLEL:
328 case M88DS3103_TS_CI:
329 if (c->delivery_system == SYS_DVBS)
332 if (c->symbol_rate < 18000000)
334 else if (c->symbol_rate < 28000000)
335 target_mclk = 144000;
337 target_mclk = 192000;
341 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
347 switch (target_mclk) {
349 u8tmp1 = 0x02; /* 0b10 */
350 u8tmp2 = 0x01; /* 0b01 */
353 u8tmp1 = 0x00; /* 0b00 */
354 u8tmp2 = 0x01; /* 0b01 */
357 u8tmp1 = 0x03; /* 0b11 */
358 u8tmp2 = 0x00; /* 0b00 */
361 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
364 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
369 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
373 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
377 switch (c->delivery_system) {
379 if (priv->chip_id == M88RS6000_CHIP_ID) {
380 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
381 init = m88rs6000_dvbs_init_reg_vals;
383 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
384 init = m88ds3103_dvbs_init_reg_vals;
388 if (priv->chip_id == M88RS6000_CHIP_ID) {
389 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
390 init = m88rs6000_dvbs2_init_reg_vals;
392 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
393 init = m88ds3103_dvbs2_init_reg_vals;
397 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
403 /* program init table */
404 if (c->delivery_system != priv->delivery_system) {
405 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
410 if (priv->chip_id == M88RS6000_CHIP_ID) {
411 if ((c->delivery_system == SYS_DVBS2)
412 && ((c->symbol_rate / 1000) <= 5000)) {
413 ret = m88ds3103_wr_reg(priv, 0xc0, 0x04);
419 ret = m88ds3103_wr_regs(priv, 0x8a, buf, 3);
423 ret = m88ds3103_wr_reg_mask(priv, 0x9d, 0x08, 0x08);
426 ret = m88ds3103_wr_reg(priv, 0xf1, 0x01);
429 ret = m88ds3103_wr_reg_mask(priv, 0x30, 0x80, 0x80);
434 switch (priv->cfg->ts_mode) {
435 case M88DS3103_TS_SERIAL:
439 case M88DS3103_TS_SERIAL_D7:
443 case M88DS3103_TS_PARALLEL:
446 case M88DS3103_TS_CI:
450 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
455 if (priv->cfg->ts_clk_pol)
459 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
463 switch (priv->cfg->ts_mode) {
464 case M88DS3103_TS_SERIAL:
465 case M88DS3103_TS_SERIAL_D7:
466 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
473 if (priv->cfg->ts_clk) {
474 divide_ratio = DIV_ROUND_UP(target_mclk, priv->cfg->ts_clk);
475 u8tmp1 = divide_ratio / 2;
476 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
480 dev_dbg(&priv->i2c->dev,
481 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
482 __func__, target_mclk, priv->cfg->ts_clk, divide_ratio);
486 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
488 /* u8tmp2[5:0] => ea[5:0] */
491 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
495 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
496 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
500 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
501 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
505 if (c->symbol_rate <= 3000000)
507 else if (c->symbol_rate <= 10000000)
512 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
516 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
520 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
524 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
528 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, priv->mclk_khz / 2);
529 buf[0] = (u16tmp >> 0) & 0xff;
530 buf[1] = (u16tmp >> 8) & 0xff;
531 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
535 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
539 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
543 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
547 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
548 (tuner_frequency - c->frequency));
550 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
551 s32tmp = DIV_ROUND_CLOSEST(s32tmp, priv->mclk_khz);
555 buf[0] = (s32tmp >> 0) & 0xff;
556 buf[1] = (s32tmp >> 8) & 0xff;
557 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
561 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
565 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
569 priv->delivery_system = c->delivery_system;
573 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
577 static int m88ds3103_init(struct dvb_frontend *fe)
579 struct m88ds3103_priv *priv = fe->demodulator_priv;
580 int ret, len, remaining;
581 const struct firmware *fw = NULL;
585 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
587 /* set cold state by default */
590 /* wake up device from sleep */
591 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
595 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
599 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
603 /* firmware status */
604 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
608 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
611 goto skip_fw_download;
613 /* global reset, global diseqc reset, golbal fec reset */
614 ret = m88ds3103_wr_reg(priv, 0x07, 0xe0);
618 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
622 /* cold state - try to download firmware */
623 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
624 KBUILD_MODNAME, m88ds3103_ops.info.name);
626 if (priv->chip_id == M88RS6000_CHIP_ID)
627 fw_file = M88RS6000_FIRMWARE;
629 fw_file = M88DS3103_FIRMWARE;
630 /* request the firmware, this will block and timeout */
631 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
633 dev_err(&priv->i2c->dev, "%s: firmware file '%s' not found\n",
634 KBUILD_MODNAME, fw_file);
638 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
639 KBUILD_MODNAME, fw_file);
641 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
643 goto error_fw_release;
645 for (remaining = fw->size; remaining > 0;
646 remaining -= (priv->cfg->i2c_wr_max - 1)) {
648 if (len > (priv->cfg->i2c_wr_max - 1))
649 len = (priv->cfg->i2c_wr_max - 1);
651 ret = m88ds3103_wr_regs(priv, 0xb0,
652 &fw->data[fw->size - remaining], len);
654 dev_err(&priv->i2c->dev,
655 "%s: firmware download failed=%d\n",
656 KBUILD_MODNAME, ret);
657 goto error_fw_release;
661 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
663 goto error_fw_release;
665 release_firmware(fw);
668 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
673 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
679 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
680 KBUILD_MODNAME, m88ds3103_ops.info.name);
681 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
682 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
691 release_firmware(fw);
693 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
697 static int m88ds3103_sleep(struct dvb_frontend *fe)
699 struct m88ds3103_priv *priv = fe->demodulator_priv;
703 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
705 priv->delivery_system = SYS_UNDEFINED;
708 if (priv->chip_id == M88RS6000_CHIP_ID)
712 ret = m88ds3103_wr_reg_mask(priv, u8tmp, 0x00, 0x01);
717 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
721 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
725 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
731 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
735 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
737 struct m88ds3103_priv *priv = fe->demodulator_priv;
738 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
742 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
744 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
749 switch (c->delivery_system) {
751 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
755 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
759 switch ((buf[0] >> 2) & 0x01) {
761 c->inversion = INVERSION_OFF;
764 c->inversion = INVERSION_ON;
768 switch ((buf[1] >> 5) & 0x07) {
770 c->fec_inner = FEC_7_8;
773 c->fec_inner = FEC_5_6;
776 c->fec_inner = FEC_3_4;
779 c->fec_inner = FEC_2_3;
782 c->fec_inner = FEC_1_2;
785 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
789 c->modulation = QPSK;
793 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
797 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
801 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
805 switch ((buf[0] >> 0) & 0x0f) {
807 c->fec_inner = FEC_2_5;
810 c->fec_inner = FEC_1_2;
813 c->fec_inner = FEC_3_5;
816 c->fec_inner = FEC_2_3;
819 c->fec_inner = FEC_3_4;
822 c->fec_inner = FEC_4_5;
825 c->fec_inner = FEC_5_6;
828 c->fec_inner = FEC_8_9;
831 c->fec_inner = FEC_9_10;
834 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
838 switch ((buf[0] >> 5) & 0x01) {
840 c->pilot = PILOT_OFF;
847 switch ((buf[0] >> 6) & 0x07) {
849 c->modulation = QPSK;
852 c->modulation = PSK_8;
855 c->modulation = APSK_16;
858 c->modulation = APSK_32;
861 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
865 switch ((buf[1] >> 7) & 0x01) {
867 c->inversion = INVERSION_OFF;
870 c->inversion = INVERSION_ON;
874 switch ((buf[2] >> 0) & 0x03) {
876 c->rolloff = ROLLOFF_35;
879 c->rolloff = ROLLOFF_25;
882 c->rolloff = ROLLOFF_20;
885 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
890 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
896 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
900 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
901 priv->mclk_khz * 1000 / 0x10000;
905 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
909 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
911 struct m88ds3103_priv *priv = fe->demodulator_priv;
912 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
916 u32 noise_tot, signal_tot;
918 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
919 /* reports SNR in resolution of 0.1 dB */
921 /* more iterations for more accurate estimation */
922 #define M88DS3103_SNR_ITERATIONS 3
924 switch (c->delivery_system) {
928 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
929 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
936 /* use of one register limits max value to 15 dB */
937 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
938 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
940 *snr = div_u64((u64) 100 * intlog2(tmp), intlog2(10));
948 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
949 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
953 noise = buf[1] << 6; /* [13:6] */
954 noise |= buf[0] & 0x3f; /* [5:0] */
956 signal = buf[2] * buf[2];
960 signal_tot += signal;
963 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
964 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
966 /* SNR(X) dB = 10 * log10(X) dB */
967 if (signal > noise) {
968 tmp = signal / noise;
969 *snr = div_u64((u64) 100 * intlog10(tmp), (1 << 24));
975 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
983 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
987 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
989 struct m88ds3103_priv *priv = fe->demodulator_priv;
990 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
995 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
997 switch (c->delivery_system) {
999 ret = m88ds3103_wr_reg(priv, 0xf9, 0x04);
1003 ret = m88ds3103_rd_reg(priv, 0xf8, &u8tmp);
1007 if (!(u8tmp & 0x10)) {
1010 ret = m88ds3103_rd_regs(priv, 0xf6, buf, 2);
1014 priv->ber = (buf[1] << 8) | (buf[0] << 0);
1016 /* restart counters */
1017 ret = m88ds3103_wr_reg(priv, 0xf8, u8tmp);
1023 ret = m88ds3103_rd_regs(priv, 0xd5, buf, 3);
1027 utmp = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0);
1030 ret = m88ds3103_rd_regs(priv, 0xf7, buf, 2);
1034 priv->ber = (buf[1] << 8) | (buf[0] << 0);
1036 /* restart counters */
1037 ret = m88ds3103_wr_reg(priv, 0xd1, 0x01);
1041 ret = m88ds3103_wr_reg(priv, 0xf9, 0x01);
1045 ret = m88ds3103_wr_reg(priv, 0xf9, 0x00);
1049 ret = m88ds3103_wr_reg(priv, 0xd1, 0x00);
1055 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
1065 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1069 static int m88ds3103_set_tone(struct dvb_frontend *fe,
1070 fe_sec_tone_mode_t fe_sec_tone_mode)
1072 struct m88ds3103_priv *priv = fe->demodulator_priv;
1074 u8 u8tmp, tone, reg_a1_mask;
1076 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
1084 switch (fe_sec_tone_mode) {
1094 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
1100 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
1101 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1106 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
1112 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1116 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1117 fe_sec_voltage_t fe_sec_voltage)
1119 struct m88ds3103_priv *priv = fe->demodulator_priv;
1122 bool voltage_sel, voltage_dis;
1124 dev_dbg(&priv->i2c->dev, "%s: fe_sec_voltage=%d\n", __func__,
1132 switch (fe_sec_voltage) {
1133 case SEC_VOLTAGE_18:
1135 voltage_dis = false;
1137 case SEC_VOLTAGE_13:
1138 voltage_sel = false;
1139 voltage_dis = false;
1141 case SEC_VOLTAGE_OFF:
1142 voltage_sel = false;
1146 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_voltage\n",
1152 /* output pin polarity */
1153 voltage_sel ^= priv->cfg->lnb_hv_pol;
1154 voltage_dis ^= priv->cfg->lnb_en_pol;
1156 u8tmp = voltage_dis << 1 | voltage_sel << 0;
1157 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0x03);
1163 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1167 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1168 struct dvb_diseqc_master_cmd *diseqc_cmd)
1170 struct m88ds3103_priv *priv = fe->demodulator_priv;
1174 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
1175 diseqc_cmd->msg_len, diseqc_cmd->msg);
1182 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1187 u8tmp = priv->cfg->envelope_mode << 5;
1188 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1192 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1193 diseqc_cmd->msg_len);
1197 ret = m88ds3103_wr_reg(priv, 0xa1,
1198 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1202 /* DiSEqC message typical period is 54 ms */
1203 usleep_range(40000, 60000);
1205 /* wait DiSEqC TX ready */
1206 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1207 usleep_range(5000, 10000);
1209 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1214 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1217 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1219 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1224 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1235 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1239 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1240 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1242 struct m88ds3103_priv *priv = fe->demodulator_priv;
1246 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1254 u8tmp = priv->cfg->envelope_mode << 5;
1255 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1259 switch (fe_sec_mini_cmd) {
1267 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1273 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1277 /* DiSEqC ToneBurst period is 12.5 ms */
1278 usleep_range(11000, 20000);
1280 /* wait DiSEqC TX ready */
1281 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1282 usleep_range(800, 2000);
1284 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1289 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1291 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1296 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1303 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1307 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1308 struct dvb_frontend_tune_settings *s)
1310 s->min_delay_ms = 3000;
1315 static void m88ds3103_release(struct dvb_frontend *fe)
1317 struct m88ds3103_priv *priv = fe->demodulator_priv;
1319 i2c_del_mux_adapter(priv->i2c_adapter);
1323 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1325 struct m88ds3103_priv *priv = mux_priv;
1327 struct i2c_msg gate_open_msg[1] = {
1329 .addr = priv->cfg->i2c_addr,
1336 mutex_lock(&priv->i2c_mutex);
1338 /* open tuner I2C repeater for 1 xfer, closes automatically */
1339 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
1341 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
1342 KBUILD_MODNAME, ret);
1352 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1355 struct m88ds3103_priv *priv = mux_priv;
1357 mutex_unlock(&priv->i2c_mutex);
1362 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1363 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1366 struct m88ds3103_priv *priv;
1369 /* allocate memory for the internal priv */
1370 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1373 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1379 mutex_init(&priv->i2c_mutex);
1381 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1382 ret = m88ds3103_rd_reg(priv, 0x00, &chip_id);
1387 dev_info(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1390 case M88RS6000_CHIP_ID:
1391 case M88DS3103_CHIP_ID:
1396 priv->chip_id = chip_id;
1398 switch (priv->cfg->clock_out) {
1399 case M88DS3103_CLOCK_OUT_DISABLED:
1402 case M88DS3103_CLOCK_OUT_ENABLED:
1405 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1412 /* 0x29 register is defined differently for m88rs6000. */
1413 /* set internal tuner address to 0x21 */
1414 if (chip_id == M88RS6000_CHIP_ID)
1417 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1422 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1426 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1430 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1434 /* create mux i2c adapter for tuner */
1435 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1436 m88ds3103_select, m88ds3103_deselect);
1437 if (priv->i2c_adapter == NULL)
1440 *tuner_i2c_adapter = priv->i2c_adapter;
1442 /* create dvb_frontend */
1443 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1444 if (priv->chip_id == M88RS6000_CHIP_ID)
1445 strncpy(priv->fe.ops.info.name,
1446 "Montage M88RS6000", sizeof(priv->fe.ops.info.name));
1447 priv->fe.demodulator_priv = priv;
1451 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1455 EXPORT_SYMBOL(m88ds3103_attach);
1457 static struct dvb_frontend_ops m88ds3103_ops = {
1458 .delsys = { SYS_DVBS, SYS_DVBS2 },
1460 .name = "Montage M88DS3103",
1461 .frequency_min = 950000,
1462 .frequency_max = 2150000,
1463 .frequency_tolerance = 5000,
1464 .symbol_rate_min = 1000000,
1465 .symbol_rate_max = 45000000,
1466 .caps = FE_CAN_INVERSION_AUTO |
1478 FE_CAN_2G_MODULATION
1481 .release = m88ds3103_release,
1483 .get_tune_settings = m88ds3103_get_tune_settings,
1485 .init = m88ds3103_init,
1486 .sleep = m88ds3103_sleep,
1488 .set_frontend = m88ds3103_set_frontend,
1489 .get_frontend = m88ds3103_get_frontend,
1491 .read_status = m88ds3103_read_status,
1492 .read_snr = m88ds3103_read_snr,
1493 .read_ber = m88ds3103_read_ber,
1495 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1496 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1498 .set_tone = m88ds3103_set_tone,
1499 .set_voltage = m88ds3103_set_voltage,
1502 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1503 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1504 MODULE_LICENSE("GPL");
1505 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1506 MODULE_FIRMWARE(M88RS6000_FIRMWARE);