2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
4 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/slab.h>
27 #include "dvb_frontend.h"
29 #include "mb86a16_priv.h"
31 static unsigned int verbose = 5;
32 module_param(verbose, int, 0644);
34 #define ABS(x) ((x) < 0 ? (-x) : (x))
36 struct mb86a16_state {
37 struct i2c_adapter *i2c_adap;
38 const struct mb86a16_config *config;
39 struct dvb_frontend frontend;
41 /* tuning parameters */
52 #define MB86A16_ERROR 0
53 #define MB86A16_NOTICE 1
54 #define MB86A16_INFO 2
55 #define MB86A16_DEBUG 3
57 #define dprintk(x, y, z, format, arg...) do { \
59 if ((x > MB86A16_ERROR) && (x > y)) \
60 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
61 else if ((x > MB86A16_NOTICE) && (x > y)) \
62 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
63 else if ((x > MB86A16_INFO) && (x > y)) \
64 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
65 else if ((x > MB86A16_DEBUG) && (x > y)) \
66 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
69 printk(format, ##arg); \
73 #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
74 #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
76 static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
79 u8 buf[] = { reg, val };
81 struct i2c_msg msg = {
82 .addr = state->config->demod_address,
88 dprintk(verbose, MB86A16_DEBUG, 1,
89 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
90 state->config->demod_address, buf[0], buf[1]);
92 ret = i2c_transfer(state->i2c_adap, &msg, 1);
94 return (ret != 1) ? -EREMOTEIO : 0;
97 static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
103 struct i2c_msg msg[] = {
105 .addr = state->config->demod_address,
110 .addr = state->config->demod_address,
116 ret = i2c_transfer(state->i2c_adap, msg, 2);
118 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)",
130 static int CNTM_set(struct mb86a16_state *state,
131 unsigned char timint1,
132 unsigned char timint2,
137 val = (timint1 << 4) | (timint2 << 2) | cnext;
138 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
144 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
148 static int smrt_set(struct mb86a16_state *state, int rate)
152 unsigned char STOFS0, STOFS1;
154 m = 1 << state->deci;
155 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
157 STOFS0 = tmp & 0x0ff;
158 STOFS1 = (tmp & 0xf00) >> 8;
160 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
164 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
166 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
171 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
175 static int srst(struct mb86a16_state *state)
177 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
182 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
187 static int afcex_data_set(struct mb86a16_state *state,
188 unsigned char AFCEX_L,
189 unsigned char AFCEX_H)
191 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
193 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
198 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
203 static int afcofs_data_set(struct mb86a16_state *state,
204 unsigned char AFCEX_L,
205 unsigned char AFCEX_H)
207 if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
209 if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
214 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
218 static int stlp_set(struct mb86a16_state *state,
222 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
227 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
231 static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
233 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
235 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
240 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
244 static int initial_set(struct mb86a16_state *state)
246 if (stlp_set(state, 5, 7))
250 if (afcex_data_set(state, 0, 0))
254 if (afcofs_data_set(state, 0, 0))
258 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
260 if (mb86a16_write(state, 0x2f, 0x21) < 0)
262 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
264 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
266 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
268 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
270 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
272 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
274 if (mb86a16_write(state, 0x54, 0xff) < 0)
276 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
282 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
286 static int S01T_set(struct mb86a16_state *state,
290 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
295 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
300 static int EN_set(struct mb86a16_state *state,
306 val = 0x7a | (cren << 7) | (afcen << 2);
307 if (mb86a16_write(state, 0x49, val) < 0)
312 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
316 static int AFCEXEN_set(struct mb86a16_state *state,
324 else if (smrt > 9375)
326 else if (smrt > 2250)
331 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
337 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
341 static int DAGC_data_set(struct mb86a16_state *state,
345 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
351 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
355 static void smrt_info_get(struct mb86a16_state *state, int rate)
358 state->deci = 0; state->csel = 0; state->rsel = 0;
359 } else if (rate >= 30001) {
360 state->deci = 0; state->csel = 0; state->rsel = 1;
361 } else if (rate >= 26251) {
362 state->deci = 0; state->csel = 1; state->rsel = 0;
363 } else if (rate >= 22501) {
364 state->deci = 0; state->csel = 1; state->rsel = 1;
365 } else if (rate >= 18751) {
366 state->deci = 1; state->csel = 0; state->rsel = 0;
367 } else if (rate >= 15001) {
368 state->deci = 1; state->csel = 0; state->rsel = 1;
369 } else if (rate >= 13126) {
370 state->deci = 1; state->csel = 1; state->rsel = 0;
371 } else if (rate >= 11251) {
372 state->deci = 1; state->csel = 1; state->rsel = 1;
373 } else if (rate >= 9376) {
374 state->deci = 2; state->csel = 0; state->rsel = 0;
375 } else if (rate >= 7501) {
376 state->deci = 2; state->csel = 0; state->rsel = 1;
377 } else if (rate >= 6563) {
378 state->deci = 2; state->csel = 1; state->rsel = 0;
379 } else if (rate >= 5626) {
380 state->deci = 2; state->csel = 1; state->rsel = 1;
381 } else if (rate >= 4688) {
382 state->deci = 3; state->csel = 0; state->rsel = 0;
383 } else if (rate >= 3751) {
384 state->deci = 3; state->csel = 0; state->rsel = 1;
385 } else if (rate >= 3282) {
386 state->deci = 3; state->csel = 1; state->rsel = 0;
387 } else if (rate >= 2814) {
388 state->deci = 3; state->csel = 1; state->rsel = 1;
389 } else if (rate >= 2344) {
390 state->deci = 4; state->csel = 0; state->rsel = 0;
391 } else if (rate >= 1876) {
392 state->deci = 4; state->csel = 0; state->rsel = 1;
393 } else if (rate >= 1641) {
394 state->deci = 4; state->csel = 1; state->rsel = 0;
395 } else if (rate >= 1407) {
396 state->deci = 4; state->csel = 1; state->rsel = 1;
397 } else if (rate >= 1172) {
398 state->deci = 5; state->csel = 0; state->rsel = 0;
399 } else if (rate >= 939) {
400 state->deci = 5; state->csel = 0; state->rsel = 1;
401 } else if (rate >= 821) {
402 state->deci = 5; state->csel = 1; state->rsel = 0;
404 state->deci = 5; state->csel = 1; state->rsel = 1;
407 if (state->csel == 0)
408 state->master_clk = 92000;
410 state->master_clk = 61333;
414 static int signal_det(struct mb86a16_state *state,
428 if (CNTM_set(state, 2, 1, 2) < 0) {
429 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
434 if (CNTM_set(state, 3, 1, 2) < 0) {
435 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
440 for (i = 0; i < 3; i++) {
442 smrtd = smrt * 98 / 100;
446 smrtd = smrt * 102 / 100;
447 smrt_info_get(state, smrtd);
448 smrt_set(state, smrtd);
450 wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
453 msleep_interruptible(10);
454 if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
455 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
459 if ((S[1] > S[0] * 112 / 100) &&
460 (S[1] > S[2] * 112 / 100)) {
468 if (CNTM_set(state, 0, 1, 2) < 0) {
469 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
476 static int rf_val_set(struct mb86a16_state *state,
481 unsigned char C, F, B;
483 unsigned char rf_val[5];
488 else if (smrt > 18875)
490 else if (smrt > 5500)
497 else if (smrt > 9375)
499 else if (smrt > 4625)
525 M = f * (1 << R) / 2;
527 rf_val[0] = 0x01 | (C << 3) | (F << 1);
528 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
529 rf_val[2] = (M & 0x00ff0) >> 4;
530 rf_val[3] = ((M & 0x0000f) << 4) | B;
533 if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
535 if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
537 if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
539 if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
541 if (mb86a16_write(state, 0x25, 0x01) < 0)
544 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
551 static int afcerr_chk(struct mb86a16_state *state)
553 unsigned char AFCM_L, AFCM_H ;
557 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
559 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
562 AFCM = (AFCM_H << 8) + AFCM_L;
568 afcerr = afcm * state->master_clk / 8192;
573 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
577 static int dagcm_val_get(struct mb86a16_state *state)
580 unsigned char DAGCM_H, DAGCM_L;
582 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
584 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
587 DAGCM = (DAGCM_H << 8) + DAGCM_L;
592 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
596 static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status)
599 struct mb86a16_state *state = fe->demodulator_priv;
603 if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
605 if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
607 if ((stat > 25) && (stat2 > 25))
608 *status |= FE_HAS_SIGNAL;
609 if ((stat > 45) && (stat2 > 45))
610 *status |= FE_HAS_CARRIER;
612 if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
616 *status |= FE_HAS_SYNC;
618 *status |= FE_HAS_VITERBI;
620 if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
623 if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
624 *status |= FE_HAS_LOCK;
629 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
633 static int sync_chk(struct mb86a16_state *state,
639 if (mb86a16_read(state, 0x0d, &val) != 2)
642 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
644 *VIRM = (val & 0x1c) >> 2;
648 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
653 static int freqerr_chk(struct mb86a16_state *state,
658 unsigned char CRM, AFCML, AFCMH;
659 unsigned char temp1, temp2, temp3;
661 int crrerr, afcerr; /* kHz */
662 int frqerr; /* MHz */
663 int afcen, afcexen = 0;
664 int R, M, fOSC, fOSC_OFS;
666 if (mb86a16_read(state, 0x43, &CRM) != 2)
674 crrerr = smrt * crm / 256;
675 if (mb86a16_read(state, 0x49, &temp1) != 2)
678 afcen = (temp1 & 0x04) >> 2;
680 if (mb86a16_read(state, 0x2a, &temp1) != 2)
682 afcexen = (temp1 & 0x20) >> 5;
686 if (mb86a16_read(state, 0x0e, &AFCML) != 2)
688 if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
690 } else if (afcexen == 1) {
691 if (mb86a16_read(state, 0x2b, &AFCML) != 2)
693 if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
696 if ((afcen == 1) || (afcexen == 1)) {
697 smrt_info_get(state, smrt);
698 AFCM = ((AFCMH & 0x01) << 8) + AFCML;
704 afcerr = afcm * state->master_clk / 8192;
708 if (mb86a16_read(state, 0x22, &temp1) != 2)
710 if (mb86a16_read(state, 0x23, &temp2) != 2)
712 if (mb86a16_read(state, 0x24, &temp3) != 2)
715 R = (temp1 & 0xe0) >> 5;
716 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
722 fOSC_OFS = fOSC - fTP;
724 if (unit == 0) { /* MHz */
725 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
726 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
728 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
730 frqerr = crrerr + afcerr + fOSC_OFS * 1000;
735 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
739 static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
751 static void swp_info_get(struct mb86a16_state *state,
758 unsigned char *AFCEX_L,
759 unsigned char *AFCEX_H)
764 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
767 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
769 *fOSC = (crnt_swp_freq + 500) / 1000;
771 if (*fOSC >= crnt_swp_freq)
772 *afcex_freq = *fOSC * 1000 - crnt_swp_freq;
774 *afcex_freq = crnt_swp_freq - *fOSC * 1000;
776 AFCEX = *afcex_freq * 8192 / state->master_clk;
777 *AFCEX_L = AFCEX & 0x00ff;
778 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
782 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
783 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
787 if ((i % 2 == 1) && (v <= vmax)) {
788 /* positive v (case 1) */
789 if ((v - 1 == vmin) &&
790 (*(V + 30 + v) >= 0) &&
791 (*(V + 30 + v - 1) >= 0) &&
792 (*(V + 30 + v - 1) > *(V + 30 + v)) &&
793 (*(V + 30 + v - 1) > SIGMIN)) {
795 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
796 *SIG1 = *(V + 30 + v - 1);
797 } else if ((v == vmax) &&
798 (*(V + 30 + v) >= 0) &&
799 (*(V + 30 + v - 1) >= 0) &&
800 (*(V + 30 + v) > *(V + 30 + v - 1)) &&
801 (*(V + 30 + v) > SIGMIN)) {
803 swp_freq = fOSC * 1000 + afcex_freq;
804 *SIG1 = *(V + 30 + v);
805 } else if ((*(V + 30 + v) > 0) &&
806 (*(V + 30 + v - 1) > 0) &&
807 (*(V + 30 + v - 2) > 0) &&
808 (*(V + 30 + v - 3) > 0) &&
809 (*(V + 30 + v - 1) > *(V + 30 + v)) &&
810 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
811 ((*(V + 30 + v - 1) > SIGMIN) ||
812 (*(V + 30 + v - 2) > SIGMIN))) {
814 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
815 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
816 *SIG1 = *(V + 30 + v - 1);
818 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
819 *SIG1 = *(V + 30 + v - 2);
821 } else if ((v == vmax) &&
822 (*(V + 30 + v) >= 0) &&
823 (*(V + 30 + v - 1) >= 0) &&
824 (*(V + 30 + v - 2) >= 0) &&
825 (*(V + 30 + v) > *(V + 30 + v - 2)) &&
826 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
827 ((*(V + 30 + v) > SIGMIN) ||
828 (*(V + 30 + v - 1) > SIGMIN))) {
830 if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
831 swp_freq = fOSC * 1000 + afcex_freq;
832 *SIG1 = *(V + 30 + v);
834 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
835 *SIG1 = *(V + 30 + v - 1);
840 } else if ((i % 2 == 0) && (v >= vmin)) {
841 /* Negative v (case 1) */
842 if ((*(V + 30 + v) > 0) &&
843 (*(V + 30 + v + 1) > 0) &&
844 (*(V + 30 + v + 2) > 0) &&
845 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
846 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
847 (*(V + 30 + v + 1) > SIGMIN)) {
849 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
850 *SIG1 = *(V + 30 + v + 1);
851 } else if ((v + 1 == vmax) &&
852 (*(V + 30 + v) >= 0) &&
853 (*(V + 30 + v + 1) >= 0) &&
854 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
855 (*(V + 30 + v + 1) > SIGMIN)) {
857 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
858 *SIG1 = *(V + 30 + v);
859 } else if ((v == vmin) &&
860 (*(V + 30 + v) > 0) &&
861 (*(V + 30 + v + 1) > 0) &&
862 (*(V + 30 + v + 2) > 0) &&
863 (*(V + 30 + v) > *(V + 30 + v + 1)) &&
864 (*(V + 30 + v) > *(V + 30 + v + 2)) &&
865 (*(V + 30 + v) > SIGMIN)) {
867 swp_freq = fOSC * 1000 + afcex_freq;
868 *SIG1 = *(V + 30 + v);
869 } else if ((*(V + 30 + v) >= 0) &&
870 (*(V + 30 + v + 1) >= 0) &&
871 (*(V + 30 + v + 2) >= 0) &&
872 (*(V + 30 + v + 3) >= 0) &&
873 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
874 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
875 ((*(V + 30 + v + 1) > SIGMIN) ||
876 (*(V + 30 + v + 2) > SIGMIN))) {
878 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
879 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
880 *SIG1 = *(V + 30 + v + 1);
882 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
883 *SIG1 = *(V + 30 + v + 2);
885 } else if ((*(V + 30 + v) >= 0) &&
886 (*(V + 30 + v + 1) >= 0) &&
887 (*(V + 30 + v + 2) >= 0) &&
888 (*(V + 30 + v + 3) >= 0) &&
889 (*(V + 30 + v) > *(V + 30 + v + 2)) &&
890 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
891 (*(V + 30 + v) > *(V + 30 + v + 3)) &&
892 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
893 ((*(V + 30 + v) > SIGMIN) ||
894 (*(V + 30 + v + 1) > SIGMIN))) {
896 if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
897 swp_freq = fOSC * 1000 + afcex_freq;
898 *SIG1 = *(V + 30 + v);
900 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
901 *SIG1 = *(V + 30 + v + 1);
903 } else if ((v + 2 == vmin) &&
904 (*(V + 30 + v) >= 0) &&
905 (*(V + 30 + v + 1) >= 0) &&
906 (*(V + 30 + v + 2) >= 0) &&
907 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
908 (*(V + 30 + v + 2) > *(V + 30 + v)) &&
909 ((*(V + 30 + v + 1) > SIGMIN) ||
910 (*(V + 30 + v + 2) > SIGMIN))) {
912 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
913 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
914 *SIG1 = *(V + 30 + v + 1);
916 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
917 *SIG1 = *(V + 30 + v + 2);
919 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
920 swp_freq = fOSC * 1000;
921 *SIG1 = *(V + 30 + v);
930 static void swp_info_get2(struct mb86a16_state *state,
936 unsigned char *AFCEX_L,
937 unsigned char *AFCEX_H)
942 *fOSC = (swp_freq + 1000) / 2000 * 2;
944 *fOSC = (swp_freq + 500) / 1000;
946 if (*fOSC >= swp_freq)
947 *afcex_freq = *fOSC * 1000 - swp_freq;
949 *afcex_freq = swp_freq - *fOSC * 1000;
951 AFCEX = *afcex_freq * 8192 / state->master_clk;
952 *AFCEX_L = AFCEX & 0x00ff;
953 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
956 static void afcex_info_get(struct mb86a16_state *state,
958 unsigned char *AFCEX_L,
959 unsigned char *AFCEX_H)
963 AFCEX = afcex_freq * 8192 / state->master_clk;
964 *AFCEX_L = AFCEX & 0x00ff;
965 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
968 static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
971 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
972 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
979 static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
981 /* Viterbi Rate, IQ Settings */
982 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
983 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
990 static int FEC_srst(struct mb86a16_state *state)
992 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
993 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1000 static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
1002 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
1003 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1010 static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
1012 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
1013 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1021 static int mb86a16_set_fe(struct mb86a16_state *state)
1034 unsigned char CREN, AFCEN, AFCEXEN;
1036 unsigned char TIMINT1, TIMINT2, TIMEXT;
1037 unsigned char S0T, S1T;
1039 /* unsigned char S2T, S3T; */
1040 unsigned char S4T, S5T;
1041 unsigned char AFCEX_L, AFCEX_H;
1044 unsigned char ETH, VIA;
1050 int vmax_his, vmin_his;
1051 int swp_freq, prev_swp_freq[20];
1057 int temp_freq, delta_freq;
1065 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
1068 swp_ofs = state->srate / 4;
1070 for (i = 0; i < 60; i++)
1073 for (i = 0; i < 20; i++)
1074 prev_swp_freq[i] = 0;
1078 for (n = 0; ((n < 3) && (ret == -1)); n++) {
1080 iq_vt_set(state, 0);
1091 if (initial_set(state) < 0) {
1092 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
1095 if (DAGC_data_set(state, 3, 2) < 0) {
1096 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1099 if (EN_set(state, CREN, AFCEN) < 0) {
1100 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1101 return -1; /* (0, 0) */
1103 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1104 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1105 return -1; /* (1, smrt) = (1, symbolrate) */
1107 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
1108 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
1109 return -1; /* (0, 1, 2) */
1111 if (S01T_set(state, S1T, S0T) < 0) {
1112 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1113 return -1; /* (0, 0) */
1115 smrt_info_get(state, state->srate);
1116 if (smrt_set(state, state->srate) < 0) {
1117 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
1121 R = vco_dev_get(state, state->srate);
1123 fOSC_start = state->frequency;
1126 if (state->frequency % 2 == 0) {
1127 fOSC_start = state->frequency;
1129 fOSC_start = state->frequency + 1;
1130 if (fOSC_start > 2150)
1131 fOSC_start = state->frequency - 1;
1135 ftemp = fOSC_start * 1000;
1138 ftemp = ftemp + swp_ofs;
1142 if (ftemp > 2150000) {
1146 if ((ftemp == 2150000) ||
1147 (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
1153 ftemp = fOSC_start * 1000;
1156 ftemp = ftemp - swp_ofs;
1160 if (ftemp < 950000) {
1164 if ((ftemp == 950000) ||
1165 (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
1170 wait_t = (8000 + state->srate / 2) / state->srate;
1184 swp_info_get(state, fOSC_start, state->srate,
1185 v, R, swp_ofs, &fOSC,
1186 &afcex_freq, &AFCEX_L, &AFCEX_H);
1189 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1190 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1194 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1195 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1198 if (srst(state) < 0) {
1199 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1202 msleep_interruptible(wait_t);
1204 if (mb86a16_read(state, 0x37, &SIG1) != 2) {
1205 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1209 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
1210 SIG1MIN, fOSC, afcex_freq,
1211 swp_ofs, &SIG1); /* changed */
1214 for (j = 0; j < prev_freq_num; j++) {
1215 if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
1217 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
1220 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
1221 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
1222 prev_swp_freq[prev_freq_num] = swp_freq;
1224 swp_info_get2(state, state->srate, R, swp_freq,
1226 &AFCEX_L, &AFCEX_H);
1228 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1229 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1232 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1233 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1236 signal = signal_det(state, state->srate, &SIG1);
1238 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
1241 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
1242 smrt_info_get(state, state->srate);
1243 if (smrt_set(state, state->srate) < 0) {
1244 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1255 if ((i % 2 == 1) && (vmax_his == 1))
1257 if ((i % 2 == 0) && (vmin_his == 1))
1265 if ((vmax_his == 1) && (vmin_his == 1))
1270 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
1277 if (S01T_set(state, S1T, S0T) < 0) {
1278 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1281 smrt_info_get(state, state->srate);
1282 if (smrt_set(state, state->srate) < 0) {
1283 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1286 if (EN_set(state, CREN, AFCEN) < 0) {
1287 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1290 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1291 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1294 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
1295 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1296 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
1299 if (srst(state) < 0) {
1300 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1304 wait_t = 200000 / state->master_clk + 200000 / state->srate;
1306 afcerr = afcerr_chk(state);
1310 swp_freq = fOSC * 1000 + afcerr ;
1312 if (state->srate >= 1500)
1313 smrt_d = state->srate / 3;
1315 smrt_d = state->srate / 2;
1316 smrt_info_get(state, smrt_d);
1317 if (smrt_set(state, smrt_d) < 0) {
1318 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1321 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
1322 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1325 R = vco_dev_get(state, smrt_d);
1326 if (DAGC_data_set(state, 2, 0) < 0) {
1327 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1330 for (i = 0; i < 3; i++) {
1331 temp_freq = swp_freq + (i - 1) * state->srate / 8;
1332 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1333 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1334 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1337 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1338 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1341 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1343 dagcm[i] = dagcm_val_get(state);
1345 if ((dagcm[0] > dagcm[1]) &&
1346 (dagcm[0] > dagcm[2]) &&
1347 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
1349 temp_freq = swp_freq - 2 * state->srate / 8;
1350 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1351 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1352 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1355 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1356 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
1359 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1361 dagcm[3] = dagcm_val_get(state);
1362 if (dagcm[3] > dagcm[1])
1363 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
1366 } else if ((dagcm[2] > dagcm[1]) &&
1367 (dagcm[2] > dagcm[0]) &&
1368 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
1370 temp_freq = swp_freq + 2 * state->srate / 8;
1371 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1372 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1373 dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
1376 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1377 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
1380 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1382 dagcm[3] = dagcm_val_get(state);
1383 if (dagcm[3] > dagcm[1])
1384 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
1391 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
1392 swp_freq += delta_freq;
1393 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
1394 if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
1395 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
1404 if (S01T_set(state, S1T, S0T) < 0) {
1405 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1408 if (DAGC_data_set(state, 0, 0) < 0) {
1409 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1412 R = vco_dev_get(state, state->srate);
1413 smrt_info_get(state, state->srate);
1414 if (smrt_set(state, state->srate) < 0) {
1415 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1418 if (EN_set(state, CREN, AFCEN) < 0) {
1419 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1422 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1423 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1426 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1427 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1428 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1431 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1432 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1435 if (srst(state) < 0) {
1436 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1439 wait_t = 7 + (10000 + state->srate / 2) / state->srate;
1442 msleep_interruptible(wait_t);
1443 if (mb86a16_read(state, 0x37, &SIG1) != 2) {
1444 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1449 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
1450 wait_t = 7 + (917504 + state->srate / 2) / state->srate;
1451 } else if (SIG1 > 105) {
1452 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1453 wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
1454 } else if (SIG1 > 85) {
1455 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1456 wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
1457 } else if (SIG1 > 65) {
1458 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1459 wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
1461 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1462 wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
1464 wait_t *= 2; /* FOS */
1465 S2T_set(state, S2T);
1466 S45T_set(state, S4T, S5T);
1467 Vi_set(state, ETH, VIA);
1469 msleep_interruptible(wait_t);
1470 sync = sync_chk(state, &VIRM);
1471 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
1476 wait_t = (786432 + state->srate / 2) / state->srate;
1478 wait_t = (1572864 + state->srate / 2) / state->srate;
1479 if (state->srate < 5000)
1480 /* FIXME ! , should be a long wait ! */
1481 msleep_interruptible(wait_t);
1483 msleep_interruptible(wait_t);
1485 if (sync_chk(state, &junk) == 0) {
1486 iq_vt_set(state, 1);
1490 /* 1/2, 2/3, 3/4, 7/8 */
1492 wait_t = (786432 + state->srate / 2) / state->srate;
1494 wait_t = (1572864 + state->srate / 2) / state->srate;
1495 msleep_interruptible(wait_t);
1498 dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
1504 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
1508 sync = sync_chk(state, &junk);
1510 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
1511 freqerr_chk(state, state->frequency, state->srate, 1);
1517 mb86a16_read(state, 0x15, &agcval);
1518 mb86a16_read(state, 0x26, &cnmval);
1519 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
1524 static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
1525 struct dvb_diseqc_master_cmd *cmd)
1527 struct mb86a16_state *state = fe->demodulator_priv;
1531 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
1533 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
1535 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
1540 if (cmd->msg_len > 5 || cmd->msg_len < 4)
1543 for (i = 0; i < cmd->msg_len; i++) {
1544 if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
1551 msleep_interruptible(10);
1553 if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
1555 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1561 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1565 static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe,
1566 enum fe_sec_mini_cmd burst)
1568 struct mb86a16_state *state = fe->demodulator_priv;
1572 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1574 MB86A16_DCC1_TBO) < 0)
1576 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1580 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1581 MB86A16_DCC1_TBEN) < 0)
1583 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1590 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1594 static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
1596 struct mb86a16_state *state = fe->demodulator_priv;
1600 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
1602 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1603 MB86A16_DCC1_CTOE) < 0)
1606 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1610 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
1612 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
1614 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
1623 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1627 static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe)
1629 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1630 struct mb86a16_state *state = fe->demodulator_priv;
1632 state->frequency = p->frequency / 1000;
1633 state->srate = p->symbol_rate / 1000;
1635 if (!mb86a16_set_fe(state)) {
1636 dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
1637 return DVBFE_ALGO_SEARCH_SUCCESS;
1640 dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
1641 return DVBFE_ALGO_SEARCH_FAILED;
1644 static void mb86a16_release(struct dvb_frontend *fe)
1646 struct mb86a16_state *state = fe->demodulator_priv;
1650 static int mb86a16_init(struct dvb_frontend *fe)
1655 static int mb86a16_sleep(struct dvb_frontend *fe)
1660 static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
1662 u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
1665 struct mb86a16_state *state = fe->demodulator_priv;
1668 if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
1670 if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
1672 if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
1674 if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
1676 if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
1678 /* BER monitor invalid when BER_EN = 0 */
1679 if (ber_mon & 0x04) {
1680 /* coarse, fast calculation */
1681 *ber = ber_tab & 0x1f;
1682 dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
1683 if (ber_mon & 0x01) {
1685 * BER_SEL = 1, The monitored BER is the estimated
1686 * value with a Reed-Solomon decoder error amount at
1687 * the deinterleaver output.
1688 * monitored BER is expressed as a 20 bit output in total
1690 ber_rst = ber_mon >> 3;
1691 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
1702 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
1705 * BER_SEL = 0, The monitored BER is the estimated
1706 * value with a Viterbi decoder error amount at the
1707 * QPSK demodulator output.
1708 * monitored BER is expressed as a 24 bit output in total
1710 ber_tim = ber_mon >> 1;
1711 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
1718 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
1723 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1727 static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1730 struct mb86a16_state *state = fe->demodulator_priv;
1733 if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
1734 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1738 *strength = ((0xff - agcm) * 100) / 256;
1739 dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
1740 *strength = (0xffff - 0xff) + agcm;
1750 static const struct cnr cnr_tab[] = {
1774 static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
1776 struct mb86a16_state *state = fe->demodulator_priv;
1778 int low_tide = 2, high_tide = 30, q_level;
1782 if (mb86a16_read(state, 0x26, &cn) != 2) {
1783 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1787 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
1788 if (cn < cnr_tab[i].cn_reg) {
1789 *snr = cnr_tab[i].cn_val;
1793 q_level = (*snr * 100) / (high_tide - low_tide);
1794 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
1795 *snr = (0xffff - 0xff) + *snr;
1800 static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1803 struct mb86a16_state *state = fe->demodulator_priv;
1805 if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
1806 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1814 static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
1816 return DVBFE_ALGO_CUSTOM;
1819 static const struct dvb_frontend_ops mb86a16_ops = {
1820 .delsys = { SYS_DVBS },
1822 .name = "Fujitsu MB86A16 DVB-S",
1823 .frequency_min = 950000,
1824 .frequency_max = 2150000,
1825 .frequency_stepsize = 3000,
1826 .frequency_tolerance = 0,
1827 .symbol_rate_min = 1000000,
1828 .symbol_rate_max = 45000000,
1829 .symbol_rate_tolerance = 500,
1830 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1831 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1832 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1835 .release = mb86a16_release,
1837 .get_frontend_algo = mb86a16_frontend_algo,
1838 .search = mb86a16_search,
1839 .init = mb86a16_init,
1840 .sleep = mb86a16_sleep,
1841 .read_status = mb86a16_read_status,
1843 .read_ber = mb86a16_read_ber,
1844 .read_signal_strength = mb86a16_read_signal_strength,
1845 .read_snr = mb86a16_read_snr,
1846 .read_ucblocks = mb86a16_read_ucblocks,
1848 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
1849 .diseqc_send_burst = mb86a16_send_diseqc_burst,
1850 .set_tone = mb86a16_set_tone,
1853 struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
1854 struct i2c_adapter *i2c_adap)
1857 struct mb86a16_state *state = NULL;
1859 state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
1863 state->config = config;
1864 state->i2c_adap = i2c_adap;
1866 mb86a16_read(state, 0x7f, &dev_id);
1870 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
1871 state->frontend.demodulator_priv = state;
1872 state->frontend.ops.set_voltage = state->config->set_voltage;
1874 return &state->frontend;
1879 EXPORT_SYMBOL(mb86a16_attach);
1880 MODULE_LICENSE("GPL");
1881 MODULE_AUTHOR("Manu Abraham");