2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab
5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
20 #include "dvb_frontend.h"
25 enum mb86a20s_bandwidth {
27 MB86A20S_13SEG_PARTIAL = 1,
32 static u8 mb86a20s_subchannel[] = {
33 0xb0, 0xc0, 0xd0, 0xe0,
34 0xf0, 0x00, 0x10, 0x20,
37 struct mb86a20s_state {
38 struct i2c_adapter *i2c;
39 const struct mb86a20s_config *config;
42 struct dvb_frontend frontend;
45 enum mb86a20s_bandwidth bw;
49 u32 estimated_rate[NUM_LAYERS];
50 unsigned long get_strength_time;
60 #define BER_SAMPLING_RATE 1 /* Seconds */
63 * Initialization sequence: Use whatevere default values that PV SBTVD
64 * does on its initialisation, obtained via USB snoop
66 static struct regdata mb86a20s_init1[] = {
70 { 0x50, 0xd1 }, { 0x51, 0x20 },
73 static struct regdata mb86a20s_init2[] = {
74 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
78 { 0x04, 0x08 }, { 0x05, 0x03 },
79 { 0x04, 0x0e }, { 0x05, 0x00 },
80 { 0x04, 0x0f }, { 0x05, 0x37 },
81 { 0x04, 0x0b }, { 0x05, 0x78 },
82 { 0x04, 0x00 }, { 0x05, 0x00 },
83 { 0x04, 0x01 }, { 0x05, 0x1e },
84 { 0x04, 0x02 }, { 0x05, 0x07 },
85 { 0x04, 0x03 }, { 0x05, 0xd0 },
86 { 0x04, 0x09 }, { 0x05, 0x00 },
87 { 0x04, 0x0a }, { 0x05, 0xff },
88 { 0x04, 0x27 }, { 0x05, 0x00 },
89 { 0x04, 0x28 }, { 0x05, 0x00 },
90 { 0x04, 0x1e }, { 0x05, 0x00 },
91 { 0x04, 0x29 }, { 0x05, 0x64 },
92 { 0x04, 0x32 }, { 0x05, 0x02 },
93 { 0x04, 0x14 }, { 0x05, 0x02 },
94 { 0x04, 0x04 }, { 0x05, 0x00 },
95 { 0x04, 0x05 }, { 0x05, 0x22 },
96 { 0x04, 0x06 }, { 0x05, 0x0e },
97 { 0x04, 0x07 }, { 0x05, 0xd8 },
98 { 0x04, 0x12 }, { 0x05, 0x00 },
99 { 0x04, 0x13 }, { 0x05, 0xff },
100 { 0x04, 0x15 }, { 0x05, 0x4e },
101 { 0x04, 0x16 }, { 0x05, 0x20 },
104 * On this demod, when the bit count reaches the count below,
105 * it collects the bit error count. The bit counters are initialized
106 * to 65535 here. This warrants that all of them will be quickly
107 * calculated when device gets locked. As TMCC is parsed, the values
108 * will be adjusted later in the driver's code.
110 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
111 { 0x50, 0xa7 }, { 0x51, 0x00 },
112 { 0x50, 0xa8 }, { 0x51, 0xff },
113 { 0x50, 0xa9 }, { 0x51, 0xff },
114 { 0x50, 0xaa }, { 0x51, 0x00 },
115 { 0x50, 0xab }, { 0x51, 0xff },
116 { 0x50, 0xac }, { 0x51, 0xff },
117 { 0x50, 0xad }, { 0x51, 0x00 },
118 { 0x50, 0xae }, { 0x51, 0xff },
119 { 0x50, 0xaf }, { 0x51, 0xff },
122 * On this demod, post BER counts blocks. When the count reaches the
123 * value below, it collects the block error count. The block counters
124 * are initialized to 127 here. This warrants that all of them will be
125 * quickly calculated when device gets locked. As TMCC is parsed, the
126 * values will be adjusted later in the driver's code.
128 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
129 { 0x50, 0xdc }, { 0x51, 0x00 },
130 { 0x50, 0xdd }, { 0x51, 0x7f },
131 { 0x50, 0xde }, { 0x51, 0x00 },
132 { 0x50, 0xdf }, { 0x51, 0x7f },
133 { 0x50, 0xe0 }, { 0x51, 0x00 },
134 { 0x50, 0xe1 }, { 0x51, 0x7f },
137 * On this demod, when the block count reaches the count below,
138 * it collects the block error count. The block counters are initialized
139 * to 127 here. This warrants that all of them will be quickly
140 * calculated when device gets locked. As TMCC is parsed, the values
141 * will be adjusted later in the driver's code.
143 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
144 { 0x50, 0xb2 }, { 0x51, 0x00 },
145 { 0x50, 0xb3 }, { 0x51, 0x7f },
146 { 0x50, 0xb4 }, { 0x51, 0x00 },
147 { 0x50, 0xb5 }, { 0x51, 0x7f },
148 { 0x50, 0xb6 }, { 0x51, 0x00 },
149 { 0x50, 0xb7 }, { 0x51, 0x7f },
151 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
152 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
153 { 0x45, 0x04 }, /* CN symbol 4 */
154 { 0x48, 0x04 }, /* CN manual mode */
156 { 0x50, 0xd6 }, { 0x51, 0x1f },
157 { 0x50, 0xd2 }, { 0x51, 0x03 },
158 { 0x50, 0xd7 }, { 0x51, 0xbf },
159 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff },
160 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c },
162 { 0x04, 0x40 }, { 0x05, 0x00 },
163 { 0x28, 0x00 }, { 0x2b, 0x08 },
164 { 0x28, 0x05 }, { 0x2b, 0x00 },
166 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f },
167 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 },
168 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 },
169 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 },
170 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 },
171 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
172 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 },
173 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 },
174 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b },
175 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 },
176 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d },
177 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 },
178 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b },
179 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
180 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 },
181 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 },
182 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 },
183 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
184 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
185 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef },
186 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 },
187 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 },
188 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d },
189 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 },
190 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba },
191 { 0x50, 0x1e }, { 0x51, 0x5d },
192 { 0x50, 0x22 }, { 0x51, 0x00 },
193 { 0x50, 0x23 }, { 0x51, 0xc8 },
194 { 0x50, 0x24 }, { 0x51, 0x00 },
195 { 0x50, 0x25 }, { 0x51, 0xf0 },
196 { 0x50, 0x26 }, { 0x51, 0x00 },
197 { 0x50, 0x27 }, { 0x51, 0xc3 },
198 { 0x50, 0x39 }, { 0x51, 0x02 },
201 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
205 static struct regdata mb86a20s_reset_reception[] = {
212 static struct regdata mb86a20s_per_ber_reset[] = {
213 { 0x53, 0x00 }, /* pre BER Counter reset */
216 { 0x5f, 0x00 }, /* post BER Counter reset */
219 { 0x50, 0xb1 }, /* PER Counter reset */
225 * I2C read/write functions and macros
228 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
229 u8 i2c_addr, u8 reg, u8 data)
231 u8 buf[] = { reg, data };
232 struct i2c_msg msg = {
233 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
237 rc = i2c_transfer(state->i2c, &msg, 1);
239 dev_err(&state->i2c->dev,
240 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
241 __func__, rc, reg, data);
248 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
249 u8 i2c_addr, struct regdata *rd, int size)
253 for (i = 0; i < size; i++) {
254 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
262 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
267 struct i2c_msg msg[] = {
268 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
269 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
272 rc = i2c_transfer(state->i2c, msg, 2);
275 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
277 return (rc < 0) ? rc : -EIO;
283 #define mb86a20s_readreg(state, reg) \
284 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
285 #define mb86a20s_writereg(state, reg, val) \
286 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
287 #define mb86a20s_writeregdata(state, regdata) \
288 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
289 regdata, ARRAY_SIZE(regdata))
292 * Ancillary internal routines (likely compiled inlined)
294 * The functions below assume that gateway lock has already obtained
297 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
299 struct mb86a20s_state *state = fe->demodulator_priv;
304 val = mb86a20s_readreg(state, 0x0a) & 0xf;
309 *status |= FE_HAS_SIGNAL;
312 *status |= FE_HAS_CARRIER;
315 *status |= FE_HAS_VITERBI;
318 *status |= FE_HAS_SYNC;
320 if (val >= 8) /* Maybe 9? */
321 *status |= FE_HAS_LOCK;
323 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
324 __func__, *status, val);
329 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
331 struct mb86a20s_state *state = fe->demodulator_priv;
332 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
334 unsigned rf_max, rf_min, rf;
336 if (state->get_strength_time &&
337 (!time_after(jiffies, state->get_strength_time)))
338 return c->strength.stat[0].uvalue;
340 /* Reset its value if an error happen */
341 c->strength.stat[0].uvalue = 0;
343 /* Does a binary search to get RF strength */
347 rf = (rf_max + rf_min) / 2;
348 rc = mb86a20s_writereg(state, 0x04, 0x1f);
351 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
354 rc = mb86a20s_writereg(state, 0x04, 0x20);
357 rc = mb86a20s_writereg(state, 0x05, rf);
361 rc = mb86a20s_readreg(state, 0x02);
365 rf_min = (rf_max + rf_min) / 2;
367 rf_max = (rf_max + rf_min) / 2;
368 if (rf_max - rf_min < 4) {
369 rf = (rf_max + rf_min) / 2;
371 /* Rescale it from 2^12 (4096) to 2^16 */
372 rf = rf << (16 - 12);
376 dev_dbg(&state->i2c->dev,
377 "%s: signal strength = %d (%d < RF=%d < %d)\n",
378 __func__, rf, rf_min, rf >> 4, rf_max);
379 c->strength.stat[0].uvalue = rf;
380 state->get_strength_time = jiffies +
381 msecs_to_jiffies(1000);
387 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
391 static unsigned char reg[] = {
392 [0] = 0x86, /* Layer A */
393 [1] = 0x8a, /* Layer B */
394 [2] = 0x8e, /* Layer C */
397 if (layer >= ARRAY_SIZE(reg))
399 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
402 rc = mb86a20s_readreg(state, 0x6e);
405 switch ((rc >> 4) & 0x07) {
419 static int mb86a20s_get_fec(struct mb86a20s_state *state,
424 static unsigned char reg[] = {
425 [0] = 0x87, /* Layer A */
426 [1] = 0x8b, /* Layer B */
427 [2] = 0x8f, /* Layer C */
430 if (layer >= ARRAY_SIZE(reg))
432 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
435 rc = mb86a20s_readreg(state, 0x6e);
438 switch ((rc >> 4) & 0x07) {
454 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
458 int interleaving[] = {
462 static unsigned char reg[] = {
463 [0] = 0x88, /* Layer A */
464 [1] = 0x8c, /* Layer B */
465 [2] = 0x90, /* Layer C */
468 if (layer >= ARRAY_SIZE(reg))
470 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
473 rc = mb86a20s_readreg(state, 0x6e);
477 return interleaving[(rc >> 4) & 0x07];
480 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
484 static unsigned char reg[] = {
485 [0] = 0x89, /* Layer A */
486 [1] = 0x8d, /* Layer B */
487 [2] = 0x91, /* Layer C */
490 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
492 if (layer >= ARRAY_SIZE(reg))
495 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
498 rc = mb86a20s_readreg(state, 0x6e);
501 count = (rc >> 4) & 0x0f;
503 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
508 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
510 struct mb86a20s_state *state = fe->demodulator_priv;
511 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
513 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
515 /* Fixed parameters */
516 c->delivery_system = SYS_ISDBT;
517 c->bandwidth_hz = 6000000;
519 /* Initialize values that will be later autodetected */
520 c->isdbt_layer_enabled = 0;
521 c->transmission_mode = TRANSMISSION_MODE_AUTO;
522 c->guard_interval = GUARD_INTERVAL_AUTO;
523 c->isdbt_sb_mode = 0;
524 c->isdbt_sb_segment_count = 0;
528 * Estimates the bit rate using the per-segment bit rate given by
529 * ABNT/NBR 15601 spec (table 4).
531 static u32 isdbt_rate[3][5][4] = {
533 { 280850, 312060, 330420, 340430 }, /* 1/2 */
534 { 374470, 416080, 440560, 453910 }, /* 2/3 */
535 { 421280, 468090, 495630, 510650 }, /* 3/4 */
536 { 468090, 520100, 550700, 567390 }, /* 5/6 */
537 { 491500, 546110, 578230, 595760 }, /* 7/8 */
539 { 561710, 624130, 660840, 680870 }, /* 1/2 */
540 { 748950, 832170, 881120, 907820 }, /* 2/3 */
541 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
542 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
543 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
545 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
546 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
547 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
548 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
549 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
553 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
554 u32 modulation, u32 forward_error_correction,
558 struct mb86a20s_state *state = fe->demodulator_priv;
563 * If modulation/fec/guard is not detected, the default is
564 * to consider the lowest bit rate, to avoid taking too long time
567 switch (modulation) {
581 switch (forward_error_correction) {
601 switch (guard_interval) {
603 case GUARD_INTERVAL_1_4:
606 case GUARD_INTERVAL_1_8:
609 case GUARD_INTERVAL_1_16:
612 case GUARD_INTERVAL_1_32:
617 /* Samples BER at BER_SAMPLING_RATE seconds */
618 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
620 /* Avoids sampling too quickly or to overflow the register */
623 else if (rate > (1 << 24) - 1)
624 rate = (1 << 24) - 1;
626 dev_dbg(&state->i2c->dev,
627 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
628 __func__, 'A' + layer,
629 segment * isdbt_rate[mod][fec][guard]/1000,
632 state->estimated_rate[layer] = rate;
635 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
637 struct mb86a20s_state *state = fe->demodulator_priv;
638 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
641 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
643 /* Reset frontend cache to default values */
644 mb86a20s_reset_frontend_cache(fe);
646 /* Check for partial reception */
647 rc = mb86a20s_writereg(state, 0x6d, 0x85);
650 rc = mb86a20s_readreg(state, 0x6e);
653 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
655 /* Get per-layer data */
657 for (layer = 0; layer < NUM_LAYERS; layer++) {
658 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
659 __func__, 'A' + layer);
661 rc = mb86a20s_get_segment_count(state, layer);
663 goto noperlayer_error;
664 if (rc >= 0 && rc < 14) {
665 c->layer[layer].segment_count = rc;
667 c->layer[layer].segment_count = 0;
668 state->estimated_rate[layer] = 0;
671 c->isdbt_layer_enabled |= 1 << layer;
672 rc = mb86a20s_get_modulation(state, layer);
674 goto noperlayer_error;
675 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
677 c->layer[layer].modulation = rc;
678 rc = mb86a20s_get_fec(state, layer);
680 goto noperlayer_error;
681 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
683 c->layer[layer].fec = rc;
684 rc = mb86a20s_get_interleaving(state, layer);
686 goto noperlayer_error;
687 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
689 c->layer[layer].interleaving = rc;
690 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
693 c->layer[layer].segment_count);
696 rc = mb86a20s_writereg(state, 0x6d, 0x84);
699 if ((rc & 0x60) == 0x20) {
700 c->isdbt_sb_mode = 1;
701 /* At least, one segment should exist */
702 if (!c->isdbt_sb_segment_count)
703 c->isdbt_sb_segment_count = 1;
706 /* Get transmission mode and guard interval */
707 rc = mb86a20s_readreg(state, 0x07);
710 c->transmission_mode = TRANSMISSION_MODE_AUTO;
711 if ((rc & 0x60) == 0x20) {
712 /* Only modes 2 and 3 are supported */
713 switch ((rc >> 2) & 0x03) {
715 c->transmission_mode = TRANSMISSION_MODE_4K;
718 c->transmission_mode = TRANSMISSION_MODE_8K;
722 c->guard_interval = GUARD_INTERVAL_AUTO;
724 /* Guard interval 1/32 is not supported */
727 c->guard_interval = GUARD_INTERVAL_1_4;
730 c->guard_interval = GUARD_INTERVAL_1_8;
733 c->guard_interval = GUARD_INTERVAL_1_16;
741 /* per-layer info is incomplete; discard all per-layer */
742 c->isdbt_layer_enabled = 0;
747 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
749 struct mb86a20s_state *state = fe->demodulator_priv;
750 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
753 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
755 /* Reset the counters, if the channel changed */
756 if (state->last_frequency != c->frequency) {
757 memset(&c->cnr, 0, sizeof(c->cnr));
758 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
759 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
760 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
761 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
762 memset(&c->block_error, 0, sizeof(c->block_error));
763 memset(&c->block_count, 0, sizeof(c->block_count));
765 state->last_frequency = c->frequency;
768 /* Clear status for most stats */
770 /* BER/PER counter reset */
771 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
775 /* CNR counter reset */
776 rc = mb86a20s_readreg(state, 0x45);
780 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
783 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
787 /* MER counter reset */
788 rc = mb86a20s_writereg(state, 0x50, 0x50);
791 rc = mb86a20s_readreg(state, 0x51);
795 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
798 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
804 dev_err(&state->i2c->dev,
805 "%s: Can't reset FE statistics (error %d).\n",
811 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
813 u32 *error, u32 *count)
815 struct mb86a20s_state *state = fe->demodulator_priv;
818 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
820 if (layer >= NUM_LAYERS)
823 /* Check if the BER measures are already available */
824 rc = mb86a20s_readreg(state, 0x54);
828 /* Check if data is available for that layer */
829 if (!(rc & (1 << layer))) {
830 dev_dbg(&state->i2c->dev,
831 "%s: preBER for layer %c is not available yet.\n",
832 __func__, 'A' + layer);
836 /* Read Bit Error Count */
837 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
841 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
845 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
850 dev_dbg(&state->i2c->dev,
851 "%s: bit error before Viterbi for layer %c: %d.\n",
852 __func__, 'A' + layer, *error);
855 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
858 rc = mb86a20s_readreg(state, 0x51);
862 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
865 rc = mb86a20s_readreg(state, 0x51);
869 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
872 rc = mb86a20s_readreg(state, 0x51);
877 dev_dbg(&state->i2c->dev,
878 "%s: bit count before Viterbi for layer %c: %d.\n",
879 __func__, 'A' + layer, *count);
883 * As we get TMCC data from the frontend, we can better estimate the
884 * BER bit counters, in order to do the BER measure during a longer
885 * time. Use those data, if available, to update the bit count
889 if (state->estimated_rate[layer]
890 && state->estimated_rate[layer] != *count) {
891 dev_dbg(&state->i2c->dev,
892 "%s: updating layer %c preBER counter to %d.\n",
893 __func__, 'A' + layer, state->estimated_rate[layer]);
895 /* Turn off BER before Viterbi */
896 rc = mb86a20s_writereg(state, 0x52, 0x00);
898 /* Update counter for this layer */
899 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
902 rc = mb86a20s_writereg(state, 0x51,
903 state->estimated_rate[layer] >> 16);
906 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
909 rc = mb86a20s_writereg(state, 0x51,
910 state->estimated_rate[layer] >> 8);
913 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
916 rc = mb86a20s_writereg(state, 0x51,
917 state->estimated_rate[layer]);
921 /* Turn on BER before Viterbi */
922 rc = mb86a20s_writereg(state, 0x52, 0x01);
924 /* Reset all preBER counters */
925 rc = mb86a20s_writereg(state, 0x53, 0x00);
928 rc = mb86a20s_writereg(state, 0x53, 0x07);
930 /* Reset counter to collect new data */
931 rc = mb86a20s_readreg(state, 0x53);
935 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
938 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
944 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
946 u32 *error, u32 *count)
948 struct mb86a20s_state *state = fe->demodulator_priv;
949 u32 counter, collect_rate;
952 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
954 if (layer >= NUM_LAYERS)
957 /* Check if the BER measures are already available */
958 rc = mb86a20s_readreg(state, 0x60);
962 /* Check if data is available for that layer */
963 if (!(rc & (1 << layer))) {
964 dev_dbg(&state->i2c->dev,
965 "%s: post BER for layer %c is not available yet.\n",
966 __func__, 'A' + layer);
970 /* Read Bit Error Count */
971 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
975 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
979 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
984 dev_dbg(&state->i2c->dev,
985 "%s: post bit error for layer %c: %d.\n",
986 __func__, 'A' + layer, *error);
989 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
992 rc = mb86a20s_readreg(state, 0x51);
996 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
999 rc = mb86a20s_readreg(state, 0x51);
1003 *count = counter * 204 * 8;
1005 dev_dbg(&state->i2c->dev,
1006 "%s: post bit count for layer %c: %d.\n",
1007 __func__, 'A' + layer, *count);
1010 * As we get TMCC data from the frontend, we can better estimate the
1011 * BER bit counters, in order to do the BER measure during a longer
1012 * time. Use those data, if available, to update the bit count
1016 if (!state->estimated_rate[layer])
1017 goto reset_measurement;
1019 collect_rate = state->estimated_rate[layer] / 204 / 8;
1020 if (collect_rate < 32)
1022 if (collect_rate > 65535)
1023 collect_rate = 65535;
1024 if (collect_rate != counter) {
1025 dev_dbg(&state->i2c->dev,
1026 "%s: updating postBER counter on layer %c to %d.\n",
1027 __func__, 'A' + layer, collect_rate);
1029 /* Turn off BER after Viterbi */
1030 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1032 /* Update counter for this layer */
1033 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1036 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1039 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1042 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1046 /* Turn on BER after Viterbi */
1047 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1049 /* Reset all preBER counters */
1050 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1053 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1059 /* Reset counter to collect new data */
1060 rc = mb86a20s_readreg(state, 0x5f);
1064 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1067 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1072 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1074 u32 *error, u32 *count)
1076 struct mb86a20s_state *state = fe->demodulator_priv;
1079 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1081 if (layer >= NUM_LAYERS)
1084 /* Check if the PER measures are already available */
1085 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1088 rc = mb86a20s_readreg(state, 0x51);
1092 /* Check if data is available for that layer */
1094 if (!(rc & (1 << layer))) {
1095 dev_dbg(&state->i2c->dev,
1096 "%s: block counts for layer %c aren't available yet.\n",
1097 __func__, 'A' + layer);
1101 /* Read Packet error Count */
1102 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1105 rc = mb86a20s_readreg(state, 0x51);
1109 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1112 rc = mb86a20s_readreg(state, 0x51);
1116 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1117 __func__, 'A' + layer, *error);
1119 /* Read Bit Count */
1120 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1123 rc = mb86a20s_readreg(state, 0x51);
1127 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1130 rc = mb86a20s_readreg(state, 0x51);
1135 dev_dbg(&state->i2c->dev,
1136 "%s: block count for layer %c: %d.\n",
1137 __func__, 'A' + layer, *count);
1140 * As we get TMCC data from the frontend, we can better estimate the
1141 * BER bit counters, in order to do the BER measure during a longer
1142 * time. Use those data, if available, to update the bit count
1146 if (!state->estimated_rate[layer])
1147 goto reset_measurement;
1149 collect_rate = state->estimated_rate[layer] / 204 / 8;
1150 if (collect_rate < 32)
1152 if (collect_rate > 65535)
1153 collect_rate = 65535;
1155 if (collect_rate != *count) {
1156 dev_dbg(&state->i2c->dev,
1157 "%s: updating PER counter on layer %c to %d.\n",
1158 __func__, 'A' + layer, collect_rate);
1160 /* Stop PER measurement */
1161 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1164 rc = mb86a20s_writereg(state, 0x51, 0x00);
1168 /* Update this layer's counter */
1169 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1172 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1175 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1178 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1182 /* start PER measurement */
1183 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1186 rc = mb86a20s_writereg(state, 0x51, 0x07);
1190 /* Reset all counters to collect new data */
1191 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1194 rc = mb86a20s_writereg(state, 0x51, 0x07);
1197 rc = mb86a20s_writereg(state, 0x51, 0x00);
1203 /* Reset counter to collect new data */
1204 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1207 rc = mb86a20s_readreg(state, 0x51);
1211 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1214 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1219 struct linear_segments {
1224 * All tables below return a dB/1000 measurement
1227 static const struct linear_segments cnr_to_db_table[] = {
1261 static const struct linear_segments cnr_64qam_table[] = {
1295 static const struct linear_segments cnr_16qam_table[] = {
1329 static const struct linear_segments cnr_qpsk_table[] = {
1363 static u32 interpolate_value(u32 value, const struct linear_segments *segments,
1370 if (value >= segments[0].x)
1371 return segments[0].y;
1372 if (value < segments[len-1].x)
1373 return segments[len-1].y;
1375 for (i = 1; i < len - 1; i++) {
1376 /* If value is identical, no need to interpolate */
1377 if (value == segments[i].x)
1378 return segments[i].y;
1379 if (value > segments[i].x)
1383 /* Linear interpolation between the two (x,y) points */
1384 dy = segments[i].y - segments[i - 1].y;
1385 dx = segments[i - 1].x - segments[i].x;
1386 tmp64 = value - segments[i].x;
1389 ret = segments[i].y - tmp64;
1394 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1396 struct mb86a20s_state *state = fe->demodulator_priv;
1397 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1398 u32 cnr_linear, cnr;
1401 /* Check if CNR is available */
1402 rc = mb86a20s_readreg(state, 0x45);
1407 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1413 rc = mb86a20s_readreg(state, 0x46);
1416 cnr_linear = rc << 8;
1418 rc = mb86a20s_readreg(state, 0x46);
1423 cnr = interpolate_value(cnr_linear,
1424 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1426 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1427 c->cnr.stat[0].svalue = cnr;
1429 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1430 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1432 /* CNR counter reset */
1433 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1436 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1441 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1443 struct mb86a20s_state *state = fe->demodulator_priv;
1444 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1447 const struct linear_segments *segs;
1450 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1452 /* Check if the measures are already available */
1453 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1456 rc = mb86a20s_readreg(state, 0x51);
1460 /* Check if data is available */
1462 dev_dbg(&state->i2c->dev,
1463 "%s: MER measures aren't available yet.\n", __func__);
1467 /* Read all layers */
1468 for (layer = 0; layer < NUM_LAYERS; layer++) {
1469 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1470 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1474 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1477 rc = mb86a20s_readreg(state, 0x51);
1481 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1484 rc = mb86a20s_readreg(state, 0x51);
1488 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1491 rc = mb86a20s_readreg(state, 0x51);
1496 switch (c->layer[layer].modulation) {
1499 segs = cnr_qpsk_table;
1500 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1503 segs = cnr_16qam_table;
1504 segs_len = ARRAY_SIZE(cnr_16qam_table);
1508 segs = cnr_64qam_table;
1509 segs_len = ARRAY_SIZE(cnr_64qam_table);
1512 cnr = interpolate_value(mer, segs, segs_len);
1514 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1515 c->cnr.stat[1 + layer].svalue = cnr;
1517 dev_dbg(&state->i2c->dev,
1518 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1519 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1523 /* Start a new MER measurement */
1524 /* MER counter reset */
1525 rc = mb86a20s_writereg(state, 0x50, 0x50);
1528 rc = mb86a20s_readreg(state, 0x51);
1533 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1536 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1543 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1545 struct mb86a20s_state *state = fe->demodulator_priv;
1546 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1549 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1551 /* Fill the length of each status counter */
1553 /* Only global stats */
1554 c->strength.len = 1;
1556 /* Per-layer stats - 3 layers + global */
1557 c->cnr.len = NUM_LAYERS + 1;
1558 c->pre_bit_error.len = NUM_LAYERS + 1;
1559 c->pre_bit_count.len = NUM_LAYERS + 1;
1560 c->post_bit_error.len = NUM_LAYERS + 1;
1561 c->post_bit_count.len = NUM_LAYERS + 1;
1562 c->block_error.len = NUM_LAYERS + 1;
1563 c->block_count.len = NUM_LAYERS + 1;
1565 /* Signal is always available */
1566 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1567 c->strength.stat[0].uvalue = 0;
1569 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1570 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1571 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1572 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1573 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1574 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1575 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1576 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1577 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1581 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1583 struct mb86a20s_state *state = fe->demodulator_priv;
1584 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1586 u32 bit_error = 0, bit_count = 0;
1587 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1588 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1589 u32 block_error = 0, block_count = 0;
1590 u32 t_block_error = 0, t_block_count = 0;
1591 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1594 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1596 mb86a20s_get_main_CNR(fe);
1598 /* Get per-layer stats */
1599 mb86a20s_get_blk_error_layer_CNR(fe);
1602 * At state 7, only CNR is available
1603 * For BER measures, state=9 is required
1604 * FIXME: we may get MER measures with state=8
1609 for (layer = 0; layer < NUM_LAYERS; layer++) {
1610 if (c->isdbt_layer_enabled & (1 << layer)) {
1611 /* Layer is active and has rc segments */
1614 /* Handle BER before vterbi */
1615 rc = mb86a20s_get_pre_ber(fe, layer,
1616 &bit_error, &bit_count);
1618 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1619 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1620 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1621 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1622 } else if (rc != -EBUSY) {
1624 * If an I/O error happened,
1625 * measures are now unavailable
1627 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1628 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1629 dev_err(&state->i2c->dev,
1630 "%s: Can't get BER for layer %c (error %d).\n",
1631 __func__, 'A' + layer, rc);
1633 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1636 /* Handle BER post vterbi */
1637 rc = mb86a20s_get_post_ber(fe, layer,
1638 &bit_error, &bit_count);
1640 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1641 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1642 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1643 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1644 } else if (rc != -EBUSY) {
1646 * If an I/O error happened,
1647 * measures are now unavailable
1649 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1650 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1651 dev_err(&state->i2c->dev,
1652 "%s: Can't get BER for layer %c (error %d).\n",
1653 __func__, 'A' + layer, rc);
1655 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1658 /* Handle Block errors for PER/UCB reports */
1659 rc = mb86a20s_get_blk_error(fe, layer,
1663 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1664 c->block_error.stat[1 + layer].uvalue += block_error;
1665 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1666 c->block_count.stat[1 + layer].uvalue += block_count;
1667 } else if (rc != -EBUSY) {
1669 * If an I/O error happened,
1670 * measures are now unavailable
1672 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1673 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1674 dev_err(&state->i2c->dev,
1675 "%s: Can't get PER for layer %c (error %d).\n",
1676 __func__, 'A' + layer, rc);
1679 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1682 /* Update total preBER */
1683 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1684 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1686 /* Update total postBER */
1687 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1688 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1690 /* Update total PER */
1691 t_block_error += c->block_error.stat[1 + layer].uvalue;
1692 t_block_count += c->block_count.stat[1 + layer].uvalue;
1697 * Start showing global count if at least one error count is
1700 if (pre_ber_layers) {
1702 * At least one per-layer BER measure was read. We can now
1703 * calculate the total BER
1705 * Total Bit Error/Count is calculated as the sum of the
1706 * bit errors on all active layers.
1708 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1709 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1710 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1711 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1713 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1714 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1718 * Start showing global count if at least one error count is
1721 if (post_ber_layers) {
1723 * At least one per-layer BER measure was read. We can now
1724 * calculate the total BER
1726 * Total Bit Error/Count is calculated as the sum of the
1727 * bit errors on all active layers.
1729 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1730 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1731 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1732 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1734 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1735 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1740 * At least one per-layer UCB measure was read. We can now
1741 * calculate the total UCB
1743 * Total block Error/Count is calculated as the sum of the
1744 * block errors on all active layers.
1746 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1747 c->block_error.stat[0].uvalue = t_block_error;
1748 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1749 c->block_count.stat[0].uvalue = t_block_count;
1751 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1752 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1759 * The functions below are called via DVB callbacks, so they need to
1760 * properly use the I2C gate control
1763 static int mb86a20s_initfe(struct dvb_frontend *fe)
1765 struct mb86a20s_state *state = fe->demodulator_priv;
1769 u8 regD5 = 1, reg71, reg09 = 0x3a;
1771 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1773 if (fe->ops.i2c_gate_ctrl)
1774 fe->ops.i2c_gate_ctrl(fe, 0);
1776 /* Initialize the frontend */
1777 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1781 if (!state->inversion)
1783 rc = mb86a20s_writereg(state, 0x09, reg09);
1790 rc = mb86a20s_writereg(state, 0x39, reg71);
1793 rc = mb86a20s_writereg(state, 0x71, state->bw);
1796 if (state->subchannel) {
1797 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1802 fclk = state->config->fclk;
1806 /* Adjust IF frequency to match tuner */
1807 if (fe->ops.tuner_ops.get_if_frequency)
1808 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1810 if (!state->if_freq)
1811 state->if_freq = 3300000;
1813 pll = (((u64)1) << 34) * state->if_freq;
1814 do_div(pll, 63 * fclk);
1815 pll = (1 << 25) - pll;
1816 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1819 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1822 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1825 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1828 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1829 __func__, fclk, state->if_freq, (long long)pll);
1831 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1832 pll = state->if_freq * 1677721600L;
1833 do_div(pll, 1628571429L);
1834 rc = mb86a20s_writereg(state, 0x28, 0x20);
1837 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1840 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1843 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1846 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1847 __func__, state->if_freq, (long long)pll);
1849 if (!state->config->is_serial)
1852 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1855 rc = mb86a20s_writereg(state, 0x51, regD5);
1859 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1865 if (fe->ops.i2c_gate_ctrl)
1866 fe->ops.i2c_gate_ctrl(fe, 1);
1869 state->need_init = true;
1870 dev_info(&state->i2c->dev,
1871 "mb86a20s: Init failed. Will try again later\n");
1873 state->need_init = false;
1874 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1879 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1881 struct mb86a20s_state *state = fe->demodulator_priv;
1882 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1884 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1886 if (!c->isdbt_layer_enabled)
1887 c->isdbt_layer_enabled = 7;
1889 if (c->isdbt_layer_enabled == 1)
1890 state->bw = MB86A20S_1SEG;
1891 else if (c->isdbt_partial_reception)
1892 state->bw = MB86A20S_13SEG_PARTIAL;
1894 state->bw = MB86A20S_13SEG;
1896 if (c->inversion == INVERSION_ON)
1897 state->inversion = true;
1899 state->inversion = false;
1901 if (!c->isdbt_sb_mode) {
1902 state->subchannel = 0;
1904 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1905 c->isdbt_sb_subchannel = 0;
1907 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1911 * Gate should already be opened, but it doesn't hurt to
1914 if (fe->ops.i2c_gate_ctrl)
1915 fe->ops.i2c_gate_ctrl(fe, 1);
1916 fe->ops.tuner_ops.set_params(fe);
1918 if (fe->ops.tuner_ops.get_if_frequency)
1919 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1922 * Make it more reliable: if, for some reason, the initial
1923 * device initialization doesn't happen, initialize it when
1924 * a SBTVD parameters are adjusted.
1926 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1927 * the agc callback logic is not called during DVB attach time,
1928 * causing mb86a20s to not be initialized with Kworld SBTVD.
1929 * So, this hack is needed, in order to make Kworld SBTVD to work.
1931 * It is also needed to change the IF after the initial init.
1933 * HACK: Always init the frontend when set_frontend is called:
1934 * it was noticed that, on some devices, it fails to lock on a
1935 * different channel. So, it is better to reset everything, even
1936 * wasting some time, than to loose channel lock.
1938 mb86a20s_initfe(fe);
1940 if (fe->ops.i2c_gate_ctrl)
1941 fe->ops.i2c_gate_ctrl(fe, 0);
1943 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1944 mb86a20s_reset_counters(fe);
1945 mb86a20s_stats_not_ready(fe);
1947 if (fe->ops.i2c_gate_ctrl)
1948 fe->ops.i2c_gate_ctrl(fe, 1);
1953 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1954 fe_status_t *status)
1956 struct mb86a20s_state *state = fe->demodulator_priv;
1959 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1961 if (fe->ops.i2c_gate_ctrl)
1962 fe->ops.i2c_gate_ctrl(fe, 0);
1965 status_nr = mb86a20s_read_status(fe, status);
1966 if (status_nr < 7) {
1967 mb86a20s_stats_not_ready(fe);
1968 mb86a20s_reset_frontend_cache(fe);
1970 if (status_nr < 0) {
1971 dev_err(&state->i2c->dev,
1972 "%s: Can't read frontend lock status\n", __func__);
1976 /* Get signal strength */
1977 rc = mb86a20s_read_signal_strength(fe);
1979 dev_err(&state->i2c->dev,
1980 "%s: Can't reset VBER registers.\n", __func__);
1981 mb86a20s_stats_not_ready(fe);
1982 mb86a20s_reset_frontend_cache(fe);
1984 rc = 0; /* Status is OK */
1988 if (status_nr >= 7) {
1990 rc = mb86a20s_get_frontend(fe);
1992 dev_err(&state->i2c->dev,
1993 "%s: Can't get FE TMCC data.\n", __func__);
1994 rc = 0; /* Status is OK */
1998 /* Get statistics */
1999 rc = mb86a20s_get_stats(fe, status_nr);
2000 if (rc < 0 && rc != -EBUSY) {
2001 dev_err(&state->i2c->dev,
2002 "%s: Can't get FE statistics.\n", __func__);
2006 rc = 0; /* Don't return EBUSY to userspace */
2011 mb86a20s_stats_not_ready(fe);
2014 if (fe->ops.i2c_gate_ctrl)
2015 fe->ops.i2c_gate_ctrl(fe, 1);
2020 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2023 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2026 *strength = c->strength.stat[0].uvalue;
2031 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2034 * get_frontend is now handled together with other stats
2035 * retrival, when read_status() is called, as some statistics
2036 * will depend on the layers detection.
2041 static int mb86a20s_tune(struct dvb_frontend *fe,
2043 unsigned int mode_flags,
2044 unsigned int *delay,
2045 fe_status_t *status)
2047 struct mb86a20s_state *state = fe->demodulator_priv;
2050 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2053 rc = mb86a20s_set_frontend(fe);
2055 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2056 mb86a20s_read_status_and_stats(fe, status);
2061 static void mb86a20s_release(struct dvb_frontend *fe)
2063 struct mb86a20s_state *state = fe->demodulator_priv;
2065 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2070 static struct dvb_frontend_ops mb86a20s_ops;
2072 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2073 struct i2c_adapter *i2c)
2075 struct mb86a20s_state *state;
2078 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2080 /* allocate memory for the internal state */
2081 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
2082 if (state == NULL) {
2084 "%s: unable to allocate memory for state\n", __func__);
2088 /* setup the state */
2089 state->config = config;
2092 /* create dvb_frontend */
2093 memcpy(&state->frontend.ops, &mb86a20s_ops,
2094 sizeof(struct dvb_frontend_ops));
2095 state->frontend.demodulator_priv = state;
2097 /* Check if it is a mb86a20s frontend */
2098 rev = mb86a20s_readreg(state, 0);
2102 "Detected a Fujitsu mb86a20s frontend\n");
2105 "Frontend revision %d is unknown - aborting.\n",
2110 return &state->frontend;
2116 EXPORT_SYMBOL(mb86a20s_attach);
2118 static struct dvb_frontend_ops mb86a20s_ops = {
2119 .delsys = { SYS_ISDBT },
2120 /* Use dib8000 values per default */
2122 .name = "Fujitsu mb86A20s",
2123 .caps = FE_CAN_RECOVER |
2124 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2125 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2126 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2127 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2128 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2129 /* Actually, those values depend on the used tuner */
2130 .frequency_min = 45000000,
2131 .frequency_max = 864000000,
2132 .frequency_stepsize = 62500,
2135 .release = mb86a20s_release,
2137 .init = mb86a20s_initfe,
2138 .set_frontend = mb86a20s_set_frontend,
2139 .get_frontend = mb86a20s_get_frontend_dummy,
2140 .read_status = mb86a20s_read_status_and_stats,
2141 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2142 .tune = mb86a20s_tune,
2145 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2146 MODULE_AUTHOR("Mauro Carvalho Chehab");
2147 MODULE_LICENSE("GPL");