2 * Driver for Zarlink DVB-T MT352 demodulator
4 * Written by Holger Waechtler <holger@qanu.de>
5 * and Daniel Mack <daniel@qanu.de>
7 * AVerMedia AVerTV DVB-T 771 support by
8 * Wolfram Joost <dbox2@frokaschwei.de>
10 * Support for Samsung TDTC9251DH01C(M) tuner
11 * Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
12 * Amauri Celani <acelani@essegi.net>
14 * DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
15 * Christopher Pascoe <c.pascoe@itee.uq.edu.au>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/string.h>
34 #include <linux/slab.h>
36 #include "dvb_frontend.h"
37 #include "mt352_priv.h"
41 struct i2c_adapter* i2c;
42 struct dvb_frontend frontend;
44 /* configuration settings */
45 struct mt352_config config;
49 #define dprintk(args...) \
51 if (debug) printk(KERN_DEBUG "mt352: " args); \
54 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
56 struct mt352_state* state = fe->demodulator_priv;
57 u8 buf[2] = { reg, val };
58 struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
59 .buf = buf, .len = 2 };
60 int err = i2c_transfer(state->i2c, &msg, 1);
62 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
68 static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
71 for (i=0; i < ilen-1; i++)
72 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
78 static int mt352_read_register(struct mt352_state* state, u8 reg)
83 struct i2c_msg msg [] = { { .addr = state->config.demod_address,
85 .buf = b0, .len = 1 },
86 { .addr = state->config.demod_address,
88 .buf = b1, .len = 1 } };
90 ret = i2c_transfer(state->i2c, msg, 2);
93 printk("%s: readreg error (reg=%d, ret==%i)\n",
101 static int mt352_sleep(struct dvb_frontend* fe)
103 static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
105 _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
109 static void mt352_calc_nominal_rate(struct mt352_state* state,
113 u32 adc_clock = 20480; /* 20.340 MHz */
128 if (state->config.adc_clock)
129 adc_clock = state->config.adc_clock;
131 value = 64 * bw * (1<<16) / (7 * 8);
132 value = value * 1000 / adc_clock;
133 dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
134 __func__, bw, adc_clock, value);
139 static void mt352_calc_input_freq(struct mt352_state* state,
142 int adc_clock = 20480; /* 20.480000 MHz */
143 int if2 = 36167; /* 36.166667 MHz */
146 if (state->config.adc_clock)
147 adc_clock = state->config.adc_clock;
148 if (state->config.if2)
149 if2 = state->config.if2;
151 if (adc_clock >= if2 * 2)
154 ife = adc_clock - (if2 % adc_clock);
155 if (ife > adc_clock / 2)
156 ife = adc_clock - ife;
158 value = -16374 * ife / adc_clock;
159 dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
160 __func__, if2, ife, adc_clock, value, value & 0x3fff);
165 static int mt352_set_parameters(struct dvb_frontend *fe)
167 struct dtv_frontend_properties *op = &fe->dtv_property_cache;
168 struct mt352_state* state = fe->demodulator_priv;
169 unsigned char buf[13];
170 static unsigned char tuner_go[] = { 0x5d, 0x01 };
171 static unsigned char fsm_go[] = { 0x5e, 0x01 };
172 unsigned int tps = 0;
174 switch (op->code_rate_HP) {
194 switch (op->code_rate_LP) {
211 if (op->hierarchy == HIERARCHY_AUTO ||
212 op->hierarchy == HIERARCHY_NONE)
218 switch (op->modulation) {
232 switch (op->transmission_mode) {
233 case TRANSMISSION_MODE_2K:
234 case TRANSMISSION_MODE_AUTO:
236 case TRANSMISSION_MODE_8K:
243 switch (op->guard_interval) {
244 case GUARD_INTERVAL_1_32:
245 case GUARD_INTERVAL_AUTO:
247 case GUARD_INTERVAL_1_16:
250 case GUARD_INTERVAL_1_8:
253 case GUARD_INTERVAL_1_4:
260 switch (op->hierarchy) {
278 buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
280 buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */
283 buf[3] = 0x50; // old
284 // buf[3] = 0xf4; // pinnacle
286 mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
287 mt352_calc_input_freq(state, buf+6);
289 if (state->config.no_tuner) {
290 if (fe->ops.tuner_ops.set_params) {
291 fe->ops.tuner_ops.set_params(fe);
292 if (fe->ops.i2c_gate_ctrl)
293 fe->ops.i2c_gate_ctrl(fe, 0);
296 _mt352_write(fe, buf, 8);
297 _mt352_write(fe, fsm_go, 2);
299 if (fe->ops.tuner_ops.calc_regs) {
300 fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
302 _mt352_write(fe, buf, sizeof(buf));
303 _mt352_write(fe, tuner_go, 2);
310 static int mt352_get_parameters(struct dvb_frontend* fe,
311 struct dtv_frontend_properties *op)
313 struct mt352_state* state = fe->demodulator_priv;
317 static const u8 tps_fec_to_api[8] =
329 if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
332 /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
333 * the mt352 sometimes works with the wrong parameters
335 tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
336 div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
337 trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
339 op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
340 op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
342 switch ( (tps >> 13) & 3)
345 op->modulation = QPSK;
348 op->modulation = QAM_16;
351 op->modulation = QAM_64;
354 op->modulation = QAM_AUTO;
358 op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
360 switch ( (tps >> 2) & 3)
363 op->guard_interval = GUARD_INTERVAL_1_32;
366 op->guard_interval = GUARD_INTERVAL_1_16;
369 op->guard_interval = GUARD_INTERVAL_1_8;
372 op->guard_interval = GUARD_INTERVAL_1_4;
375 op->guard_interval = GUARD_INTERVAL_AUTO;
379 switch ( (tps >> 10) & 7)
382 op->hierarchy = HIERARCHY_NONE;
385 op->hierarchy = HIERARCHY_1;
388 op->hierarchy = HIERARCHY_2;
391 op->hierarchy = HIERARCHY_4;
394 op->hierarchy = HIERARCHY_AUTO;
398 op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
401 op->bandwidth_hz = 8000000;
402 else if (trl == 0x64)
403 op->bandwidth_hz = 7000000;
405 op->bandwidth_hz = 6000000;
408 if (mt352_read_register(state, STATUS_2) & 0x02)
409 op->inversion = INVERSION_OFF;
411 op->inversion = INVERSION_ON;
416 static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status)
418 struct mt352_state* state = fe->demodulator_priv;
423 * The MT352 design manual from Zarlink states (page 46-47):
425 * Notes about the TUNER_GO register:
427 * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
428 * byte is copied from the tuner to the STATUS_3 register and
429 * completion of the read operation is indicated by bit-5 of the
430 * INTERRUPT_3 register.
433 if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
435 if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
437 if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
442 *status |= FE_HAS_CARRIER;
444 *status |= FE_HAS_VITERBI;
446 *status |= FE_HAS_LOCK;
448 *status |= FE_HAS_SYNC;
450 *status |= FE_HAS_SIGNAL;
452 if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
453 (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
454 *status &= ~FE_HAS_LOCK;
459 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
461 struct mt352_state* state = fe->demodulator_priv;
463 *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
464 (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
465 (mt352_read_register (state, RS_ERR_CNT_0));
470 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
472 struct mt352_state* state = fe->demodulator_priv;
474 /* align the 12 bit AGC gain with the most significant bits */
475 u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
476 (mt352_read_register(state, AGC_GAIN_0) << 4);
478 /* inverse of gain is signal strength */
483 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
485 struct mt352_state* state = fe->demodulator_priv;
487 u8 _snr = mt352_read_register (state, SNR);
488 *snr = (_snr << 8) | _snr;
493 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
495 struct mt352_state* state = fe->demodulator_priv;
497 *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
498 (mt352_read_register (state, RS_UBC_0));
503 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
505 fe_tune_settings->min_delay_ms = 800;
506 fe_tune_settings->step_size = 0;
507 fe_tune_settings->max_drift = 0;
512 static int mt352_init(struct dvb_frontend* fe)
514 struct mt352_state* state = fe->demodulator_priv;
516 static u8 mt352_reset_attach [] = { RESET, 0xC0 };
518 dprintk("%s: hello\n",__func__);
520 if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
521 (mt352_read_register(state, CONFIG) & 0x20) == 0) {
523 /* Do a "hard" reset */
524 _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
525 return state->config.demod_init(fe);
531 static void mt352_release(struct dvb_frontend* fe)
533 struct mt352_state* state = fe->demodulator_priv;
537 static const struct dvb_frontend_ops mt352_ops;
539 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
540 struct i2c_adapter* i2c)
542 struct mt352_state* state = NULL;
544 /* allocate memory for the internal state */
545 state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
546 if (state == NULL) goto error;
548 /* setup the state */
550 memcpy(&state->config,config,sizeof(struct mt352_config));
552 /* check if the demod is there */
553 if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
555 /* create dvb_frontend */
556 memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
557 state->frontend.demodulator_priv = state;
558 return &state->frontend;
565 static const struct dvb_frontend_ops mt352_ops = {
566 .delsys = { SYS_DVBT },
568 .name = "Zarlink MT352 DVB-T",
569 .frequency_min = 174000000,
570 .frequency_max = 862000000,
571 .frequency_stepsize = 166667,
572 .frequency_tolerance = 0,
573 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
574 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
576 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
577 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
578 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
582 .release = mt352_release,
585 .sleep = mt352_sleep,
586 .write = _mt352_write,
588 .set_frontend = mt352_set_parameters,
589 .get_frontend = mt352_get_parameters,
590 .get_tune_settings = mt352_get_tune_settings,
592 .read_status = mt352_read_status,
593 .read_ber = mt352_read_ber,
594 .read_signal_strength = mt352_read_signal_strength,
595 .read_snr = mt352_read_snr,
596 .read_ucblocks = mt352_read_ucblocks,
599 module_param(debug, int, 0644);
600 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
602 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
603 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
604 MODULE_LICENSE("GPL");
606 EXPORT_SYMBOL(mt352_attach);