2 * Realtek RTL2832 DVB-T demodulator driver
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "rtl2832_priv.h"
23 #include <linux/bitops.h>
26 module_param_named(debug, rtl2832_debug, int, 0644);
27 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
29 #define REG_MASK(b) (BIT(b + 1) - 1)
31 static const struct rtl2832_reg_entry registers[] = {
32 [DVBT_SOFT_RST] = {0x1, 0x1, 2, 2},
33 [DVBT_IIC_REPEAT] = {0x1, 0x1, 3, 3},
34 [DVBT_TR_WAIT_MIN_8K] = {0x1, 0x88, 11, 2},
35 [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
36 [DVBT_EN_BK_TRK] = {0x1, 0xa6, 7, 7},
37 [DVBT_AD_EN_REG] = {0x0, 0x8, 7, 7},
38 [DVBT_AD_EN_REG1] = {0x0, 0x8, 6, 6},
39 [DVBT_EN_BBIN] = {0x1, 0xb1, 0, 0},
40 [DVBT_MGD_THD0] = {0x1, 0x95, 7, 0},
41 [DVBT_MGD_THD1] = {0x1, 0x96, 7, 0},
42 [DVBT_MGD_THD2] = {0x1, 0x97, 7, 0},
43 [DVBT_MGD_THD3] = {0x1, 0x98, 7, 0},
44 [DVBT_MGD_THD4] = {0x1, 0x99, 7, 0},
45 [DVBT_MGD_THD5] = {0x1, 0x9a, 7, 0},
46 [DVBT_MGD_THD6] = {0x1, 0x9b, 7, 0},
47 [DVBT_MGD_THD7] = {0x1, 0x9c, 7, 0},
48 [DVBT_EN_CACQ_NOTCH] = {0x1, 0x61, 4, 4},
49 [DVBT_AD_AV_REF] = {0x0, 0x9, 6, 0},
50 [DVBT_REG_PI] = {0x0, 0xa, 2, 0},
51 [DVBT_PIP_ON] = {0x0, 0x21, 3, 3},
52 [DVBT_SCALE1_B92] = {0x2, 0x92, 7, 0},
53 [DVBT_SCALE1_B93] = {0x2, 0x93, 7, 0},
54 [DVBT_SCALE1_BA7] = {0x2, 0xa7, 7, 0},
55 [DVBT_SCALE1_BA9] = {0x2, 0xa9, 7, 0},
56 [DVBT_SCALE1_BAA] = {0x2, 0xaa, 7, 0},
57 [DVBT_SCALE1_BAB] = {0x2, 0xab, 7, 0},
58 [DVBT_SCALE1_BAC] = {0x2, 0xac, 7, 0},
59 [DVBT_SCALE1_BB0] = {0x2, 0xb0, 7, 0},
60 [DVBT_SCALE1_BB1] = {0x2, 0xb1, 7, 0},
61 [DVBT_KB_P1] = {0x1, 0x64, 3, 1},
62 [DVBT_KB_P2] = {0x1, 0x64, 6, 4},
63 [DVBT_KB_P3] = {0x1, 0x65, 2, 0},
64 [DVBT_OPT_ADC_IQ] = {0x0, 0x6, 5, 4},
65 [DVBT_AD_AVI] = {0x0, 0x9, 1, 0},
66 [DVBT_AD_AVQ] = {0x0, 0x9, 3, 2},
67 [DVBT_K1_CR_STEP12] = {0x2, 0xad, 9, 4},
68 [DVBT_TRK_KS_P2] = {0x1, 0x6f, 2, 0},
69 [DVBT_TRK_KS_I2] = {0x1, 0x70, 5, 3},
70 [DVBT_TR_THD_SET2] = {0x1, 0x72, 3, 0},
71 [DVBT_TRK_KC_P2] = {0x1, 0x73, 5, 3},
72 [DVBT_TRK_KC_I2] = {0x1, 0x75, 2, 0},
73 [DVBT_CR_THD_SET2] = {0x1, 0x76, 7, 6},
74 [DVBT_PSET_IFFREQ] = {0x1, 0x19, 21, 0},
75 [DVBT_SPEC_INV] = {0x1, 0x15, 0, 0},
76 [DVBT_RSAMP_RATIO] = {0x1, 0x9f, 27, 2},
77 [DVBT_CFREQ_OFF_RATIO] = {0x1, 0x9d, 23, 4},
78 [DVBT_FSM_STAGE] = {0x3, 0x51, 6, 3},
79 [DVBT_RX_CONSTEL] = {0x3, 0x3c, 3, 2},
80 [DVBT_RX_HIER] = {0x3, 0x3c, 6, 4},
81 [DVBT_RX_C_RATE_LP] = {0x3, 0x3d, 2, 0},
82 [DVBT_RX_C_RATE_HP] = {0x3, 0x3d, 5, 3},
83 [DVBT_GI_IDX] = {0x3, 0x51, 1, 0},
84 [DVBT_FFT_MODE_IDX] = {0x3, 0x51, 2, 2},
85 [DVBT_RSD_BER_EST] = {0x3, 0x4e, 15, 0},
86 [DVBT_CE_EST_EVM] = {0x4, 0xc, 15, 0},
87 [DVBT_RF_AGC_VAL] = {0x3, 0x5b, 13, 0},
88 [DVBT_IF_AGC_VAL] = {0x3, 0x59, 13, 0},
89 [DVBT_DAGC_VAL] = {0x3, 0x5, 7, 0},
90 [DVBT_SFREQ_OFF] = {0x3, 0x18, 13, 0},
91 [DVBT_CFREQ_OFF] = {0x3, 0x5f, 17, 0},
92 [DVBT_POLAR_RF_AGC] = {0x0, 0xe, 1, 1},
93 [DVBT_POLAR_IF_AGC] = {0x0, 0xe, 0, 0},
94 [DVBT_AAGC_HOLD] = {0x1, 0x4, 5, 5},
95 [DVBT_EN_RF_AGC] = {0x1, 0x4, 6, 6},
96 [DVBT_EN_IF_AGC] = {0x1, 0x4, 7, 7},
97 [DVBT_IF_AGC_MIN] = {0x1, 0x8, 7, 0},
98 [DVBT_IF_AGC_MAX] = {0x1, 0x9, 7, 0},
99 [DVBT_RF_AGC_MIN] = {0x1, 0xa, 7, 0},
100 [DVBT_RF_AGC_MAX] = {0x1, 0xb, 7, 0},
101 [DVBT_IF_AGC_MAN] = {0x1, 0xc, 6, 6},
102 [DVBT_IF_AGC_MAN_VAL] = {0x1, 0xc, 13, 0},
103 [DVBT_RF_AGC_MAN] = {0x1, 0xe, 6, 6},
104 [DVBT_RF_AGC_MAN_VAL] = {0x1, 0xe, 13, 0},
105 [DVBT_DAGC_TRG_VAL] = {0x1, 0x12, 7, 0},
106 [DVBT_AGC_TARG_VAL_0] = {0x1, 0x2, 0, 0},
107 [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3, 7, 0},
108 [DVBT_AAGC_LOOP_GAIN] = {0x1, 0xc7, 5, 1},
109 [DVBT_LOOP_GAIN2_3_0] = {0x1, 0x4, 4, 1},
110 [DVBT_LOOP_GAIN2_4] = {0x1, 0x5, 7, 7},
111 [DVBT_LOOP_GAIN3] = {0x1, 0xc8, 4, 0},
112 [DVBT_VTOP1] = {0x1, 0x6, 5, 0},
113 [DVBT_VTOP2] = {0x1, 0xc9, 5, 0},
114 [DVBT_VTOP3] = {0x1, 0xca, 5, 0},
115 [DVBT_KRF1] = {0x1, 0xcb, 7, 0},
116 [DVBT_KRF2] = {0x1, 0x7, 7, 0},
117 [DVBT_KRF3] = {0x1, 0xcd, 7, 0},
118 [DVBT_KRF4] = {0x1, 0xce, 7, 0},
119 [DVBT_EN_GI_PGA] = {0x1, 0xe5, 0, 0},
120 [DVBT_THD_LOCK_UP] = {0x1, 0xd9, 8, 0},
121 [DVBT_THD_LOCK_DW] = {0x1, 0xdb, 8, 0},
122 [DVBT_THD_UP1] = {0x1, 0xdd, 7, 0},
123 [DVBT_THD_DW1] = {0x1, 0xde, 7, 0},
124 [DVBT_INTER_CNT_LEN] = {0x1, 0xd8, 3, 0},
125 [DVBT_GI_PGA_STATE] = {0x1, 0xe6, 3, 3},
126 [DVBT_EN_AGC_PGA] = {0x1, 0xd7, 0, 0},
127 [DVBT_CKOUTPAR] = {0x1, 0x7b, 5, 5},
128 [DVBT_CKOUT_PWR] = {0x1, 0x7b, 6, 6},
129 [DVBT_SYNC_DUR] = {0x1, 0x7b, 7, 7},
130 [DVBT_ERR_DUR] = {0x1, 0x7c, 0, 0},
131 [DVBT_SYNC_LVL] = {0x1, 0x7c, 1, 1},
132 [DVBT_ERR_LVL] = {0x1, 0x7c, 2, 2},
133 [DVBT_VAL_LVL] = {0x1, 0x7c, 3, 3},
134 [DVBT_SERIAL] = {0x1, 0x7c, 4, 4},
135 [DVBT_SER_LSB] = {0x1, 0x7c, 5, 5},
136 [DVBT_CDIV_PH0] = {0x1, 0x7d, 3, 0},
137 [DVBT_CDIV_PH1] = {0x1, 0x7d, 7, 4},
138 [DVBT_MPEG_IO_OPT_2_2] = {0x0, 0x6, 7, 7},
139 [DVBT_MPEG_IO_OPT_1_0] = {0x0, 0x7, 7, 6},
140 [DVBT_CKOUTPAR_PIP] = {0x0, 0xb7, 4, 4},
141 [DVBT_CKOUT_PWR_PIP] = {0x0, 0xb7, 3, 3},
142 [DVBT_SYNC_LVL_PIP] = {0x0, 0xb7, 2, 2},
143 [DVBT_ERR_LVL_PIP] = {0x0, 0xb7, 1, 1},
144 [DVBT_VAL_LVL_PIP] = {0x0, 0xb7, 0, 0},
145 [DVBT_CKOUTPAR_PID] = {0x0, 0xb9, 4, 4},
146 [DVBT_CKOUT_PWR_PID] = {0x0, 0xb9, 3, 3},
147 [DVBT_SYNC_LVL_PID] = {0x0, 0xb9, 2, 2},
148 [DVBT_ERR_LVL_PID] = {0x0, 0xb9, 1, 1},
149 [DVBT_VAL_LVL_PID] = {0x0, 0xb9, 0, 0},
150 [DVBT_SM_PASS] = {0x1, 0x93, 11, 0},
151 [DVBT_AD7_SETTING] = {0x0, 0x11, 15, 0},
152 [DVBT_RSSI_R] = {0x3, 0x1, 6, 0},
153 [DVBT_ACI_DET_IND] = {0x3, 0x12, 0, 0},
154 [DVBT_REG_MON] = {0x0, 0xd, 1, 0},
155 [DVBT_REG_MONSEL] = {0x0, 0xd, 2, 2},
156 [DVBT_REG_GPE] = {0x0, 0xd, 7, 7},
157 [DVBT_REG_GPO] = {0x0, 0x10, 0, 0},
158 [DVBT_REG_4MSEL] = {0x0, 0x13, 0, 0},
161 /* write multiple hardware registers */
162 static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
166 struct i2c_msg msg[1] = {
168 .addr = priv->cfg.i2c_addr,
176 memcpy(&buf[1], val, len);
178 ret = i2c_transfer(priv->i2c, msg, 1);
182 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \
183 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
189 /* read multiple hardware registers */
190 static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
193 struct i2c_msg msg[2] = {
195 .addr = priv->cfg.i2c_addr,
200 .addr = priv->cfg.i2c_addr,
207 ret = i2c_transfer(priv->i2c, msg, 2);
211 dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \
212 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
218 /* write multiple registers */
219 static int rtl2832_wr_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
224 /* switch bank if needed */
225 if (page != priv->page) {
226 ret = rtl2832_wr(priv, 0x00, &page, 1);
233 return rtl2832_wr(priv, reg, val, len);
236 /* read multiple registers */
237 static int rtl2832_rd_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
242 /* switch bank if needed */
243 if (page != priv->page) {
244 ret = rtl2832_wr(priv, 0x00, &page, 1);
251 return rtl2832_rd(priv, reg, val, len);
254 #if 0 /* currently not used */
255 /* write single register */
256 static int rtl2832_wr_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 val)
258 return rtl2832_wr_regs(priv, reg, page, &val, 1);
262 /* read single register */
263 static int rtl2832_rd_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val)
265 return rtl2832_rd_regs(priv, reg, page, val, 1);
268 static int rtl2832_rd_demod_reg(struct rtl2832_priv *priv, int reg, u32 *val)
282 reg_start_addr = registers[reg].start_address;
283 msb = registers[reg].msb;
284 lsb = registers[reg].lsb;
285 page = registers[reg].page;
287 len = (msb >> 3) + 1;
288 mask = REG_MASK(msb - lsb);
290 ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
295 for (i = 0; i < len; i++)
296 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
298 *val = (reading_tmp >> lsb) & mask;
303 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
308 static int rtl2832_wr_demod_reg(struct rtl2832_priv *priv, int reg, u32 val)
324 reg_start_addr = registers[reg].start_address;
325 msb = registers[reg].msb;
326 lsb = registers[reg].lsb;
327 page = registers[reg].page;
329 len = (msb >> 3) + 1;
330 mask = REG_MASK(msb - lsb);
333 ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
338 for (i = 0; i < len; i++)
339 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
341 writing_tmp = reading_tmp & ~(mask << lsb);
342 writing_tmp |= ((val & mask) << lsb);
345 for (i = 0; i < len; i++)
346 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
348 ret = rtl2832_wr_regs(priv, reg_start_addr, page, &writing[0], len);
355 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
360 static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
363 struct rtl2832_priv *priv = fe->demodulator_priv;
365 dev_dbg(&priv->i2c->dev, "%s: enable=%d\n", __func__, enable);
367 /* gate already open or close */
368 if (priv->i2c_gate_state == enable)
371 ret = rtl2832_wr_demod_reg(priv, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
375 priv->i2c_gate_state = enable;
379 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
384 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
386 struct rtl2832_priv *priv = fe->demodulator_priv;
389 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
392 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
396 pset_iffreq = if_freq % priv->cfg.xtal;
397 pset_iffreq *= 0x400000;
398 pset_iffreq = div_u64(pset_iffreq, priv->cfg.xtal);
399 pset_iffreq = -pset_iffreq;
400 pset_iffreq = pset_iffreq & 0x3fffff;
401 dev_dbg(&priv->i2c->dev, "%s: if_frequency=%d pset_iffreq=%08x\n",
402 __func__, if_freq, (unsigned)pset_iffreq);
404 ret = rtl2832_wr_demod_reg(priv, DVBT_EN_BBIN, en_bbin);
408 ret = rtl2832_wr_demod_reg(priv, DVBT_PSET_IFFREQ, pset_iffreq);
413 static int rtl2832_init(struct dvb_frontend *fe)
415 struct rtl2832_priv *priv = fe->demodulator_priv;
416 const struct rtl2832_reg_value *init;
419 /* initialization values for the demodulator registers */
420 struct rtl2832_reg_value rtl2832_initial_regs[] = {
421 {DVBT_AD_EN_REG, 0x1},
422 {DVBT_AD_EN_REG1, 0x1},
423 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
424 {DVBT_MGD_THD0, 0x10},
425 {DVBT_MGD_THD1, 0x20},
426 {DVBT_MGD_THD2, 0x20},
427 {DVBT_MGD_THD3, 0x40},
428 {DVBT_MGD_THD4, 0x22},
429 {DVBT_MGD_THD5, 0x32},
430 {DVBT_MGD_THD6, 0x37},
431 {DVBT_MGD_THD7, 0x39},
432 {DVBT_EN_BK_TRK, 0x0},
433 {DVBT_EN_CACQ_NOTCH, 0x0},
434 {DVBT_AD_AV_REF, 0x2a},
437 {DVBT_CDIV_PH0, 0x8},
438 {DVBT_CDIV_PH1, 0x8},
439 {DVBT_SCALE1_B92, 0x4},
440 {DVBT_SCALE1_B93, 0xb0},
441 {DVBT_SCALE1_BA7, 0x78},
442 {DVBT_SCALE1_BA9, 0x28},
443 {DVBT_SCALE1_BAA, 0x59},
444 {DVBT_SCALE1_BAB, 0x83},
445 {DVBT_SCALE1_BAC, 0xd4},
446 {DVBT_SCALE1_BB0, 0x65},
447 {DVBT_SCALE1_BB1, 0x43},
451 {DVBT_K1_CR_STEP12, 0xa},
454 {DVBT_CDIV_PH0, 0x9},
455 {DVBT_CDIV_PH1, 0x9},
456 {DVBT_MPEG_IO_OPT_2_2, 0x0},
457 {DVBT_MPEG_IO_OPT_1_0, 0x0},
458 {DVBT_TRK_KS_P2, 0x4},
459 {DVBT_TRK_KS_I2, 0x7},
460 {DVBT_TR_THD_SET2, 0x6},
461 {DVBT_TRK_KC_I2, 0x5},
462 {DVBT_CR_THD_SET2, 0x1},
465 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
467 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
468 ret = rtl2832_wr_demod_reg(priv, rtl2832_initial_regs[i].reg,
469 rtl2832_initial_regs[i].value);
474 /* load tuner specific settings */
475 dev_dbg(&priv->i2c->dev, "%s: load settings for tuner=%02x\n",
476 __func__, priv->cfg.tuner);
477 switch (priv->cfg.tuner) {
478 case RTL2832_TUNER_FC0012:
479 case RTL2832_TUNER_FC0013:
480 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
481 init = rtl2832_tuner_init_fc0012;
483 case RTL2832_TUNER_TUA9001:
484 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
485 init = rtl2832_tuner_init_tua9001;
487 case RTL2832_TUNER_E4000:
488 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
489 init = rtl2832_tuner_init_e4000;
491 case RTL2832_TUNER_R820T:
492 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
493 init = rtl2832_tuner_init_r820t;
500 for (i = 0; i < len; i++) {
501 ret = rtl2832_wr_demod_reg(priv, init[i].reg, init[i].value);
506 if (!fe->ops.tuner_ops.get_if_frequency) {
507 ret = rtl2832_set_if(fe, priv->cfg.if_dvbt);
513 * r820t NIM code does a software reset here at the demod -
514 * may not be needed, as there's already a software reset at set_params()
518 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
522 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
527 priv->sleeping = false;
532 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
536 static int rtl2832_sleep(struct dvb_frontend *fe)
538 struct rtl2832_priv *priv = fe->demodulator_priv;
540 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
541 priv->sleeping = true;
545 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
546 struct dvb_frontend_tune_settings *s)
548 struct rtl2832_priv *priv = fe->demodulator_priv;
550 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
551 s->min_delay_ms = 1000;
552 s->step_size = fe->ops.info.frequency_stepsize * 2;
553 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
557 static int rtl2832_set_frontend(struct dvb_frontend *fe)
559 struct rtl2832_priv *priv = fe->demodulator_priv;
560 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
562 u64 bw_mode, num, num2;
563 u32 resamp_ratio, cfreq_off_ratio;
564 static u8 bw_params[3][32] = {
565 /* 6 MHz bandwidth */
567 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
568 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
569 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
573 /* 7 MHz bandwidth */
575 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
576 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
577 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
581 /* 8 MHz bandwidth */
583 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
584 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
585 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
591 dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d " \
592 "inversion=%d\n", __func__, c->frequency,
593 c->bandwidth_hz, c->inversion);
596 if (fe->ops.tuner_ops.set_params)
597 fe->ops.tuner_ops.set_params(fe);
599 /* If the frontend has get_if_frequency(), use it */
600 if (fe->ops.tuner_ops.get_if_frequency) {
603 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
607 ret = rtl2832_set_if(fe, if_freq);
612 switch (c->bandwidth_hz) {
626 dev_dbg(&priv->i2c->dev, "%s: invalid bandwidth\n", __func__);
630 for (j = 0; j < sizeof(bw_params[0]); j++) {
631 ret = rtl2832_wr_regs(priv, 0x1c+j, 1, &bw_params[i][j], 1);
636 /* calculate and set resample ratio
637 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
638 * / ConstWithBandwidthMode)
640 num = priv->cfg.xtal * 7;
642 num = div_u64(num, bw_mode);
643 resamp_ratio = num & 0x3ffffff;
644 ret = rtl2832_wr_demod_reg(priv, DVBT_RSAMP_RATIO, resamp_ratio);
648 /* calculate and set cfreq off ratio
649 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
650 * / (CrystalFreqHz * 7))
653 num2 = priv->cfg.xtal * 7;
654 num = div_u64(num, num2);
656 cfreq_off_ratio = num & 0xfffff;
657 ret = rtl2832_wr_demod_reg(priv, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
663 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
667 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
673 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
677 static int rtl2832_get_frontend(struct dvb_frontend *fe)
679 struct rtl2832_priv *priv = fe->demodulator_priv;
680 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
687 ret = rtl2832_rd_regs(priv, 0x3c, 3, buf, 2);
691 ret = rtl2832_rd_reg(priv, 0x51, 3, &buf[2]);
695 dev_dbg(&priv->i2c->dev, "%s: TPS=%*ph\n", __func__, 3, buf);
697 switch ((buf[0] >> 2) & 3) {
699 c->modulation = QPSK;
702 c->modulation = QAM_16;
705 c->modulation = QAM_64;
709 switch ((buf[2] >> 2) & 1) {
711 c->transmission_mode = TRANSMISSION_MODE_2K;
714 c->transmission_mode = TRANSMISSION_MODE_8K;
717 switch ((buf[2] >> 0) & 3) {
719 c->guard_interval = GUARD_INTERVAL_1_32;
722 c->guard_interval = GUARD_INTERVAL_1_16;
725 c->guard_interval = GUARD_INTERVAL_1_8;
728 c->guard_interval = GUARD_INTERVAL_1_4;
732 switch ((buf[0] >> 4) & 7) {
734 c->hierarchy = HIERARCHY_NONE;
737 c->hierarchy = HIERARCHY_1;
740 c->hierarchy = HIERARCHY_2;
743 c->hierarchy = HIERARCHY_4;
747 switch ((buf[1] >> 3) & 7) {
749 c->code_rate_HP = FEC_1_2;
752 c->code_rate_HP = FEC_2_3;
755 c->code_rate_HP = FEC_3_4;
758 c->code_rate_HP = FEC_5_6;
761 c->code_rate_HP = FEC_7_8;
765 switch ((buf[1] >> 0) & 7) {
767 c->code_rate_LP = FEC_1_2;
770 c->code_rate_LP = FEC_2_3;
773 c->code_rate_LP = FEC_3_4;
776 c->code_rate_LP = FEC_5_6;
779 c->code_rate_LP = FEC_7_8;
785 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
789 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
791 struct rtl2832_priv *priv = fe->demodulator_priv;
796 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
800 ret = rtl2832_rd_demod_reg(priv, DVBT_FSM_STAGE, &tmp);
805 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
806 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
808 /* TODO find out if this is also true for rtl2832? */
809 /*else if (tmp == 10) {
810 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
816 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
820 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
822 struct rtl2832_priv *priv = fe->demodulator_priv;
823 int ret, hierarchy, constellation;
826 #define CONSTELLATION_NUM 3
827 #define HIERARCHY_NUM 4
828 static const u32 snr_constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
829 { 85387325, 85387325, 85387325, 85387325 },
830 { 86676178, 86676178, 87167949, 87795660 },
831 { 87659938, 87659938, 87885178, 88241743 },
834 /* reports SNR in resolution of 0.1 dB */
836 ret = rtl2832_rd_reg(priv, 0x3c, 3, &tmp);
840 constellation = (tmp >> 2) & 0x03; /* [3:2] */
841 if (constellation > CONSTELLATION_NUM - 1)
844 hierarchy = (tmp >> 4) & 0x07; /* [6:4] */
845 if (hierarchy > HIERARCHY_NUM - 1)
848 ret = rtl2832_rd_regs(priv, 0x0c, 4, buf, 2);
852 tmp16 = buf[0] << 8 | buf[1];
855 *snr = (snr_constant[constellation][hierarchy] -
856 intlog10(tmp16)) / ((1 << 24) / 100);
862 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
866 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
868 struct rtl2832_priv *priv = fe->demodulator_priv;
872 ret = rtl2832_rd_regs(priv, 0x4e, 3, buf, 2);
876 *ber = buf[0] << 8 | buf[1];
880 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
884 static struct dvb_frontend_ops rtl2832_ops;
886 static void rtl2832_release(struct dvb_frontend *fe)
888 struct rtl2832_priv *priv = fe->demodulator_priv;
890 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
894 struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg,
895 struct i2c_adapter *i2c)
897 struct rtl2832_priv *priv = NULL;
901 dev_dbg(&i2c->dev, "%s:\n", __func__);
903 /* allocate memory for the internal state */
904 priv = kzalloc(sizeof(struct rtl2832_priv), GFP_KERNEL);
910 priv->tuner = cfg->tuner;
911 memcpy(&priv->cfg, cfg, sizeof(struct rtl2832_config));
913 /* check if the demod is there */
914 ret = rtl2832_rd_reg(priv, 0x00, 0x0, &tmp);
918 /* create dvb_frontend */
919 memcpy(&priv->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
920 priv->fe.demodulator_priv = priv;
922 /* TODO implement sleep mode */
923 priv->sleeping = true;
927 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
931 EXPORT_SYMBOL(rtl2832_attach);
933 static struct dvb_frontend_ops rtl2832_ops = {
934 .delsys = { SYS_DVBT },
936 .name = "Realtek RTL2832 (DVB-T)",
937 .frequency_min = 174000000,
938 .frequency_max = 862000000,
939 .frequency_stepsize = 166667,
940 .caps = FE_CAN_FEC_1_2 |
950 FE_CAN_TRANSMISSION_MODE_AUTO |
951 FE_CAN_GUARD_INTERVAL_AUTO |
952 FE_CAN_HIERARCHY_AUTO |
957 .release = rtl2832_release,
959 .init = rtl2832_init,
960 .sleep = rtl2832_sleep,
962 .get_tune_settings = rtl2832_get_tune_settings,
964 .set_frontend = rtl2832_set_frontend,
965 .get_frontend = rtl2832_get_frontend,
967 .read_status = rtl2832_read_status,
968 .read_snr = rtl2832_read_snr,
969 .read_ber = rtl2832_read_ber,
971 .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
974 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
975 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
976 MODULE_LICENSE("GPL");
977 MODULE_VERSION("0.5");