2 * Driver for Silicon Labs Si2161 DVB-T and Si2165 DVB-C/-T Demodulator
4 * Copyright (C) 2013-2014 Matthias Schwarzott <zzam@gentoo.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/slab.h>
27 #include <linux/firmware.h>
29 #include "dvb_frontend.h"
31 #include "si2165_priv.h"
35 * Hauppauge WinTV-HVR-930C-HD B130 / PCTV QuatroStick 521e 1113xx
38 * Hauppauge WinTV-HVR-930C-HD B131 / PCTV QuatroStick 522e 1114xx
39 * uses 24 MHz clock provided by tuner
43 struct i2c_adapter *i2c;
45 struct dvb_frontend fe;
47 struct si2165_config config;
52 /* calculated by xtal and div settings */
62 #define DEBUG_OTHER 0x01
63 #define DEBUG_I2C_WRITE 0x02
64 #define DEBUG_I2C_READ 0x04
65 #define DEBUG_REG_READ 0x08
66 #define DEBUG_REG_WRITE 0x10
67 #define DEBUG_FW_LOAD 0x20
69 static int debug = 0x00;
71 #define dprintk(args...) \
73 if (debug & DEBUG_OTHER) \
74 printk(KERN_DEBUG "si2165: " args); \
77 #define deb_i2c_write(args...) \
79 if (debug & DEBUG_I2C_WRITE) \
80 printk(KERN_DEBUG "si2165: i2c write: " args); \
83 #define deb_i2c_read(args...) \
85 if (debug & DEBUG_I2C_READ) \
86 printk(KERN_DEBUG "si2165: i2c read: " args); \
89 #define deb_readreg(args...) \
91 if (debug & DEBUG_REG_READ) \
92 printk(KERN_DEBUG "si2165: reg read: " args); \
95 #define deb_writereg(args...) \
97 if (debug & DEBUG_REG_WRITE) \
98 printk(KERN_DEBUG "si2165: reg write: " args); \
101 #define deb_fw_load(args...) \
103 if (debug & DEBUG_FW_LOAD) \
104 printk(KERN_DEBUG "si2165: fw load: " args); \
107 static int si2165_write(struct si2165_state *state, const u16 reg,
108 const u8 *src, const int count)
112 u8 buf[2 + 4]; /* write a maximum of 4 bytes of data */
114 if (count + 2 > sizeof(buf)) {
115 dev_warn(&state->i2c->dev,
116 "%s: i2c wr reg=%04x: count=%d is too big!\n",
117 KBUILD_MODNAME, reg, count);
122 memcpy(buf + 2, src, count);
124 msg.addr = state->config.i2c_addr;
129 if (debug & DEBUG_I2C_WRITE)
130 deb_i2c_write("reg: 0x%04x, data: %*ph\n", reg, count, src);
132 ret = i2c_transfer(state->i2c, &msg, 1);
135 dev_err(&state->i2c->dev, "%s: ret == %d\n", __func__, ret);
145 static int si2165_read(struct si2165_state *state,
146 const u16 reg, u8 *val, const int count)
149 u8 reg_buf[] = { reg >> 8, reg & 0xff };
150 struct i2c_msg msg[] = {
151 { .addr = state->config.i2c_addr,
152 .flags = 0, .buf = reg_buf, .len = 2 },
153 { .addr = state->config.i2c_addr,
154 .flags = I2C_M_RD, .buf = val, .len = count },
157 ret = i2c_transfer(state->i2c, msg, 2);
160 dev_err(&state->i2c->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n",
161 __func__, state->config.i2c_addr, reg, ret);
168 if (debug & DEBUG_I2C_READ)
169 deb_i2c_read("reg: 0x%04x, data: %*ph\n", reg, count, val);
174 static int si2165_readreg8(struct si2165_state *state,
175 const u16 reg, u8 *val)
179 ret = si2165_read(state, reg, val, 1);
180 deb_readreg("R(0x%04x)=0x%02x\n", reg, *val);
184 static int si2165_readreg16(struct si2165_state *state,
185 const u16 reg, u16 *val)
189 int ret = si2165_read(state, reg, buf, 2);
190 *val = buf[0] | buf[1] << 8;
191 deb_readreg("R(0x%04x)=0x%04x\n", reg, *val);
195 static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val)
197 return si2165_write(state, reg, &val, 1);
200 static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val)
202 u8 buf[2] = { val & 0xff, (val >> 8) & 0xff };
204 return si2165_write(state, reg, buf, 2);
207 static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val)
209 u8 buf[3] = { val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff };
211 return si2165_write(state, reg, buf, 3);
214 static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val)
222 return si2165_write(state, reg, buf, 4);
225 static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg,
230 int ret = si2165_readreg8(state, reg, &tmp);
239 return si2165_writereg8(state, reg, val);
242 #define REG16(reg, val) { (reg), (val) & 0xff }, { (reg)+1, (val)>>8 & 0xff }
243 struct si2165_reg_value_pair {
248 static int si2165_write_reg_list(struct si2165_state *state,
249 const struct si2165_reg_value_pair *regs,
255 for (i = 0; i < count; i++) {
256 ret = si2165_writereg8(state, regs[i].reg, regs[i].val);
263 static int si2165_get_tune_settings(struct dvb_frontend *fe,
264 struct dvb_frontend_tune_settings *s)
266 s->min_delay_ms = 1000;
270 static int si2165_init_pll(struct si2165_state *state)
272 u32 ref_freq_Hz = state->config.ref_freq_Hz;
273 u8 divr = 1; /* 1..7 */
274 u8 divp = 1; /* only 1 or 4 */
275 u8 divn = 56; /* 1..63 */
281 * hardcoded values can be deleted if calculation is verified
282 * or it yields the same values as the windows driver
284 switch (ref_freq_Hz) {
294 /* ref_freq / divr must be between 4 and 16 MHz */
295 if (ref_freq_Hz > 16000000u)
299 * now select divn and divp such that
300 * fvco is in 1624..1824 MHz
302 if (1624000000u * divr > ref_freq_Hz * 2u * 63u)
305 /* is this already correct regarding rounding? */
306 divn = 1624000000u * divr / (ref_freq_Hz * 2u * divp);
310 /* adc_clk and sys_clk depend on xtal and pll settings */
311 state->fvco_hz = ref_freq_Hz / divr
313 state->adc_clk = state->fvco_hz / (divm * 4u);
314 state->sys_clk = state->fvco_hz / (divl * 2u);
316 /* write pll registers 0x00a0..0x00a3 at once */
319 buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80;
321 return si2165_write(state, 0x00a0, buf, 4);
324 static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl)
326 state->sys_clk = state->fvco_hz / (divl * 2u);
327 return si2165_writereg8(state, 0x00a0, divl); /* pll_divl */
330 static u32 si2165_get_fe_clk(struct si2165_state *state)
332 /* assume Oversampling mode Ovr4 is used */
333 return state->adc_clk;
336 static int si2165_wait_init_done(struct si2165_state *state)
342 for (i = 0; i < 3; ++i) {
343 si2165_readreg8(state, 0x0054, &val);
346 usleep_range(1000, 50000);
348 dev_err(&state->i2c->dev, "%s: init_done was not set\n",
353 static int si2165_upload_firmware_block(struct si2165_state *state,
354 const u8 *data, u32 len, u32 *poffset, u32 block_count)
357 u8 buf_ctrl[4] = { 0x00, 0x00, 0x00, 0xc0 };
360 u32 offset = poffset ? *poffset : 0;
368 "si2165_upload_firmware_block called with len=0x%x offset=0x%x blockcount=0x%x\n",
369 len, offset, block_count);
370 while (offset+12 <= len && cur_block < block_count) {
372 "si2165_upload_firmware_block in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",
373 len, offset, cur_block, block_count);
374 wordcount = data[offset];
375 if (wordcount < 1 || data[offset+1] ||
376 data[offset+2] || data[offset+3]) {
377 dev_warn(&state->i2c->dev,
378 "%s: bad fw data[0..3] = %*ph\n",
379 KBUILD_MODNAME, 4, data);
383 if (offset + 8 + wordcount * 4 > len) {
384 dev_warn(&state->i2c->dev,
385 "%s: len is too small for block len=%d, wordcount=%d\n",
386 KBUILD_MODNAME, len, wordcount);
390 buf_ctrl[0] = wordcount - 1;
392 ret = si2165_write(state, 0x0364, buf_ctrl, 4);
395 ret = si2165_write(state, 0x0368, data+offset+4, 4);
401 while (wordcount > 0) {
402 ret = si2165_write(state, 0x36c, data+offset, 4);
412 "si2165_upload_firmware_block after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",
413 len, offset, cur_block, block_count);
418 deb_fw_load("si2165_upload_firmware_block returned offset=0x%x\n",
426 static int si2165_upload_firmware(struct si2165_state *state)
433 const struct firmware *fw = NULL;
442 switch (state->chip_revcode) {
443 case 0x03: /* revision D */
444 fw_file = SI2165_FIRMWARE_REV_D;
447 dev_info(&state->i2c->dev, "%s: no firmware file for revision=%d\n",
448 KBUILD_MODNAME, state->chip_revcode);
452 /* request the firmware, this will block and timeout */
453 ret = request_firmware(&fw, fw_file, state->i2c->dev.parent);
455 dev_warn(&state->i2c->dev, "%s: firmware file '%s' not found\n",
456 KBUILD_MODNAME, fw_file);
463 dev_info(&state->i2c->dev, "%s: downloading firmware from file '%s' size=%d\n",
464 KBUILD_MODNAME, fw_file, len);
467 dev_warn(&state->i2c->dev, "%s: firmware size is not multiple of 4\n",
473 /* check header (8 bytes) */
475 dev_warn(&state->i2c->dev, "%s: firmware header is missing\n",
481 if (data[0] != 1 || data[1] != 0) {
482 dev_warn(&state->i2c->dev, "%s: firmware file version is wrong\n",
488 patch_version = data[2];
489 block_count = data[4];
490 crc_expected = data[7] << 8 | data[6];
492 /* start uploading fw */
493 /* boot/wdog status */
494 ret = si2165_writereg8(state, 0x0341, 0x00);
498 ret = si2165_writereg8(state, 0x00c0, 0x00);
501 /* boot/wdog status */
502 ret = si2165_readreg8(state, 0x0341, val);
506 /* enable reset on error */
507 ret = si2165_readreg8(state, 0x035c, val);
510 ret = si2165_readreg8(state, 0x035c, val);
513 ret = si2165_writereg8(state, 0x035c, 0x02);
517 /* start right after the header */
520 dev_info(&state->i2c->dev, "%s: si2165_upload_firmware extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n",
521 KBUILD_MODNAME, patch_version, block_count, crc_expected);
523 ret = si2165_upload_firmware_block(state, data, len, &offset, 1);
527 ret = si2165_writereg8(state, 0x0344, patch_version);
532 ret = si2165_writereg8(state, 0x0379, 0x01);
536 ret = si2165_upload_firmware_block(state, data, len,
537 &offset, block_count);
539 dev_err(&state->i2c->dev,
540 "%s: firmware could not be uploaded\n",
546 ret = si2165_readreg16(state, 0x037a, &val16);
550 if (val16 != crc_expected) {
551 dev_err(&state->i2c->dev,
552 "%s: firmware crc mismatch %04x != %04x\n",
553 KBUILD_MODNAME, val16, crc_expected);
558 ret = si2165_upload_firmware_block(state, data, len, &offset, 5);
563 dev_err(&state->i2c->dev,
564 "%s: firmware len mismatch %04x != %04x\n",
565 KBUILD_MODNAME, len, offset);
570 /* reset watchdog error register */
571 ret = si2165_writereg_mask8(state, 0x0341, 0x02, 0x02);
575 /* enable reset on error */
576 ret = si2165_writereg_mask8(state, 0x035c, 0x01, 0x01);
580 dev_info(&state->i2c->dev, "%s: fw load finished\n", KBUILD_MODNAME);
583 state->firmware_loaded = true;
586 release_firmware(fw);
593 static int si2165_init(struct dvb_frontend *fe)
596 struct si2165_state *state = fe->demodulator_priv;
598 u8 patch_version = 0x00;
600 dprintk("%s: called\n", __func__);
603 ret = si2165_writereg8(state, 0x0000, state->config.chip_mode);
606 /* dsp_clock_enable */
607 ret = si2165_writereg8(state, 0x0104, 0x01);
610 ret = si2165_readreg8(state, 0x0000, &val); /* verify chip_mode */
613 if (val != state->config.chip_mode) {
614 dev_err(&state->i2c->dev, "%s: could not set chip_mode\n",
620 ret = si2165_writereg8(state, 0x018b, 0x00);
623 ret = si2165_writereg8(state, 0x0190, 0x01);
626 ret = si2165_writereg8(state, 0x0170, 0x00);
629 ret = si2165_writereg8(state, 0x0171, 0x07);
633 ret = si2165_writereg8(state, 0x0646, 0x00);
636 ret = si2165_writereg8(state, 0x0641, 0x00);
640 ret = si2165_init_pll(state);
644 /* enable chip_init */
645 ret = si2165_writereg8(state, 0x0050, 0x01);
649 ret = si2165_writereg8(state, 0x0096, 0x01);
652 ret = si2165_wait_init_done(state);
656 /* disable chip_init */
657 ret = si2165_writereg8(state, 0x0050, 0x00);
662 ret = si2165_writereg16(state, 0x0470, 0x7530);
666 ret = si2165_readreg8(state, 0x0344, &patch_version);
670 ret = si2165_writereg8(state, 0x00cb, 0x00);
675 ret = si2165_writereg32(state, 0x0348, 0xf4000000);
678 /* boot/wdog status */
679 ret = si2165_readreg8(state, 0x0341, &val);
683 if (patch_version == 0x00) {
684 ret = si2165_upload_firmware(state);
689 /* ts output config */
690 ret = si2165_writereg8(state, 0x04e4, 0x20);
693 ret = si2165_writereg16(state, 0x04ef, 0x00fe);
696 ret = si2165_writereg24(state, 0x04f4, 0x555555);
699 ret = si2165_writereg8(state, 0x04e5, 0x01);
708 static int si2165_sleep(struct dvb_frontend *fe)
711 struct si2165_state *state = fe->demodulator_priv;
713 /* dsp clock disable */
714 ret = si2165_writereg8(state, 0x0104, 0x00);
718 ret = si2165_writereg8(state, 0x0000, SI2165_MODE_OFF);
724 static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status)
728 struct si2165_state *state = fe->demodulator_priv;
730 if (!state->has_dvbt)
734 ret = si2165_readreg8(state, 0x4e0, &fec_lock);
738 if (fec_lock & 0x01) {
739 *status |= FE_HAS_SIGNAL;
740 *status |= FE_HAS_CARRIER;
741 *status |= FE_HAS_VITERBI;
742 *status |= FE_HAS_SYNC;
743 *status |= FE_HAS_LOCK;
749 static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate)
754 oversamp = si2165_get_fe_clk(state);
756 do_div(oversamp, dvb_rate);
757 reg_value = oversamp & 0x3fffffff;
759 dprintk("%s: Write oversamp=%#x\n", __func__, reg_value);
760 return si2165_writereg32(state, 0x00e4, reg_value);
763 static int si2165_set_if_freq_shift(struct si2165_state *state)
765 struct dvb_frontend *fe = &state->fe;
768 u32 fe_clk = si2165_get_fe_clk(state);
771 if (!fe->ops.tuner_ops.get_if_frequency) {
772 dev_err(&state->i2c->dev,
773 "%s: Error: get_if_frequency() not defined at tuner. Can't work without it!\n",
778 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
780 if_freq_shift <<= 29;
782 do_div(if_freq_shift, fe_clk);
783 reg_value = (s32)if_freq_shift;
785 if (state->config.inversion)
786 reg_value = -reg_value;
788 reg_value = reg_value & 0x1fffffff;
790 /* if_freq_shift, usbdump contained 0x023ee08f; */
791 return si2165_writereg32(state, 0x00e8, reg_value);
794 static const struct si2165_reg_value_pair dvbt_regs[] = {
795 /* standard = DVB-T */
798 /* impulsive_noise_remover */
811 /* freq_sync_range */
812 REG16(0x030c, 0x0064),
817 static int si2165_set_frontend_dvbt(struct dvb_frontend *fe)
820 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
821 struct si2165_state *state = fe->demodulator_priv;
824 u32 bw_hz = p->bandwidth_hz;
826 dprintk("%s: called\n", __func__);
828 if (!state->has_dvbt)
831 /* no bandwidth auto-detection */
835 dvb_rate = bw_hz * 8 / 7;
836 bw10k = bw_hz / 10000;
838 ret = si2165_adjust_pll_divl(state, 12);
842 /* bandwidth in 10KHz steps */
843 ret = si2165_writereg16(state, 0x0308, bw10k);
846 ret = si2165_set_oversamp(state, dvb_rate);
850 ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs));
857 static const struct si2165_reg_value_pair dvbc_regs[] = {
858 /* standard = DVB-C */
877 REG16(0x0350, 0x3e80),
881 REG16(0x024c, 0x0000),
882 REG16(0x027c, 0x0000),
888 static int si2165_set_frontend_dvbc(struct dvb_frontend *fe)
890 struct si2165_state *state = fe->demodulator_priv;
892 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
893 const u32 dvb_rate = p->symbol_rate;
894 const u32 bw_hz = p->bandwidth_hz;
896 if (!state->has_dvbc)
902 ret = si2165_adjust_pll_divl(state, 14);
907 ret = si2165_set_oversamp(state, dvb_rate);
911 ret = si2165_writereg32(state, 0x00c4, bw_hz);
915 ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs));
922 static const struct si2165_reg_value_pair agc_rewrite[] = {
930 static int si2165_set_frontend(struct dvb_frontend *fe)
932 struct si2165_state *state = fe->demodulator_priv;
933 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
934 u32 delsys = p->delivery_system;
938 /* initial setting of if freq shift */
939 ret = si2165_set_if_freq_shift(state);
945 ret = si2165_set_frontend_dvbt(fe);
949 case SYS_DVBC_ANNEX_A:
950 ret = si2165_set_frontend_dvbc(fe);
959 ret = si2165_writereg32(state, 0x0348, 0xf4000000);
963 if (fe->ops.tuner_ops.set_params)
964 fe->ops.tuner_ops.set_params(fe);
966 /* recalc if_freq_shift if IF might has changed */
967 ret = si2165_set_if_freq_shift(state);
971 /* boot/wdog status */
972 ret = si2165_readreg8(state, 0x0341, val);
975 ret = si2165_writereg8(state, 0x0341, 0x00);
980 ret = si2165_writereg8(state, 0x00c0, 0x00);
984 ret = si2165_writereg32(state, 0x0384, 0x00000000);
988 /* write adc values after each reset*/
989 ret = si2165_write_reg_list(state, agc_rewrite,
990 ARRAY_SIZE(agc_rewrite));
995 ret = si2165_writereg8(state, 0x02e0, 0x01);
998 /* boot/wdog status */
999 ret = si2165_readreg8(state, 0x0341, val);
1006 static void si2165_release(struct dvb_frontend *fe)
1008 struct si2165_state *state = fe->demodulator_priv;
1010 dprintk("%s: called\n", __func__);
1014 static struct dvb_frontend_ops si2165_ops = {
1016 .name = "Silicon Labs ",
1018 .symbol_rate_min = 1000000,
1019 .symbol_rate_max = 7200000,
1021 .frequency_stepsize = 166667,
1022 .caps = FE_CAN_FEC_1_2 |
1035 FE_CAN_GUARD_INTERVAL_AUTO |
1036 FE_CAN_HIERARCHY_AUTO |
1038 FE_CAN_TRANSMISSION_MODE_AUTO |
1042 .get_tune_settings = si2165_get_tune_settings,
1044 .init = si2165_init,
1045 .sleep = si2165_sleep,
1047 .set_frontend = si2165_set_frontend,
1048 .read_status = si2165_read_status,
1050 .release = si2165_release,
1053 struct dvb_frontend *si2165_attach(const struct si2165_config *config,
1054 struct i2c_adapter *i2c)
1056 struct si2165_state *state = NULL;
1061 const char *chip_name;
1063 if (config == NULL || i2c == NULL)
1066 /* allocate memory for the internal state */
1067 state = kzalloc(sizeof(struct si2165_state), GFP_KERNEL);
1071 /* setup the state */
1073 state->config = *config;
1075 if (state->config.ref_freq_Hz < 4000000
1076 || state->config.ref_freq_Hz > 27000000) {
1077 dev_err(&state->i2c->dev, "%s: ref_freq of %d Hz not supported by this driver\n",
1078 KBUILD_MODNAME, state->config.ref_freq_Hz);
1082 /* create dvb_frontend */
1083 memcpy(&state->fe.ops, &si2165_ops,
1084 sizeof(struct dvb_frontend_ops));
1085 state->fe.demodulator_priv = state;
1088 io_ret = si2165_writereg8(state, 0x0000, state->config.chip_mode);
1092 io_ret = si2165_readreg8(state, 0x0000, &val);
1095 if (val != state->config.chip_mode)
1098 io_ret = si2165_readreg8(state, 0x0023, &state->chip_revcode);
1102 io_ret = si2165_readreg8(state, 0x0118, &state->chip_type);
1107 io_ret = si2165_writereg8(state, 0x0000, SI2165_MODE_OFF);
1111 if (state->chip_revcode < 26)
1112 rev_char = 'A' + state->chip_revcode;
1116 switch (state->chip_type) {
1118 chip_name = "Si2161";
1119 state->has_dvbt = true;
1122 chip_name = "Si2165";
1123 state->has_dvbt = true;
1124 state->has_dvbc = true;
1127 dev_err(&state->i2c->dev, "%s: Unsupported Silicon Labs chip (type %d, rev %d)\n",
1128 KBUILD_MODNAME, state->chip_type, state->chip_revcode);
1132 dev_info(&state->i2c->dev,
1133 "%s: Detected Silicon Labs %s-%c (type %d, rev %d)\n",
1134 KBUILD_MODNAME, chip_name, rev_char, state->chip_type,
1135 state->chip_revcode);
1137 strlcat(state->fe.ops.info.name, chip_name,
1138 sizeof(state->fe.ops.info.name));
1141 if (state->has_dvbt) {
1142 state->fe.ops.delsys[n++] = SYS_DVBT;
1143 strlcat(state->fe.ops.info.name, " DVB-T",
1144 sizeof(state->fe.ops.info.name));
1146 if (state->has_dvbc) {
1147 state->fe.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
1148 strlcat(state->fe.ops.info.name, " DVB-C",
1149 sizeof(state->fe.ops.info.name));
1158 EXPORT_SYMBOL(si2165_attach);
1160 module_param(debug, int, 0644);
1161 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1163 MODULE_DESCRIPTION("Silicon Labs Si2165 DVB-C/-T Demodulator driver");
1164 MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
1165 MODULE_LICENSE("GPL");
1166 MODULE_FIRMWARE(SI2165_FIRMWARE_REV_D);