4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include <linux/i2c.h>
33 #include "stv0367_regs.h"
34 #include "stv0367_priv.h"
37 module_param_named(debug, stvdebug, int, 0644);
40 module_param_named(i2c_debug, i2cdebug, int, 0644);
42 #define dprintk(args...) \
45 printk(KERN_DEBUG args); \
49 struct stv0367cab_state {
50 enum stv0367_cab_signal_type state;
56 int locked; /* channel found */
57 u32 freq_khz; /* found frequency (in kHz) */
58 u32 symbol_rate; /* found symbol rate (in Bds) */
59 enum stv0367cab_mod modulation; /* modulation */
60 fe_spectral_inversion_t spect_inv; /* Spectrum Inversion */
63 struct stv0367ter_state {
65 enum stv0367_ter_signal_type state;
66 enum stv0367_ter_if_iq_mode if_iq_mode;
67 enum stv0367_ter_mode mode;/* mode 2K or 8K */
68 fe_guard_interval_t guard;
69 enum stv0367_ter_hierarchy hierarchy;
71 fe_spectral_inversion_t sense; /* current search spectrum */
72 u8 force; /* force mode/guard */
73 u8 bw; /* channel width 6, 7 or 8 in MHz */
74 u8 pBW; /* channel width used during previous lock */
78 s8 echo_pos; /* echo position */
84 struct stv0367_state {
85 struct dvb_frontend fe;
86 struct i2c_adapter *i2c;
88 const struct stv0367_config *config;
91 struct stv0367cab_state *cab_state;
93 struct stv0367ter_state *ter_state;
101 /* values for STV4100 XTAL=30M int clk=53.125M*/
102 static struct st_register def0367ter[STV0367TER_NBREGS] = {
104 {R367TER_I2CRPT, 0xa0},
105 /* {R367TER_I2CRPT, 0x22},*/
106 {R367TER_TOPCTRL, 0x00},/* for xc5000; was 0x02 */
107 {R367TER_IOCFG0, 0x40},
108 {R367TER_DAC0R, 0x00},
109 {R367TER_IOCFG1, 0x00},
110 {R367TER_DAC1R, 0x00},
111 {R367TER_IOCFG2, 0x62},
112 {R367TER_SDFR, 0x00},
113 {R367TER_STATUS, 0xf8},
114 {R367TER_AUX_CLK, 0x0a},
115 {R367TER_FREESYS1, 0x00},
116 {R367TER_FREESYS2, 0x00},
117 {R367TER_FREESYS3, 0x00},
118 {R367TER_GPIO_CFG, 0x55},
119 {R367TER_GPIO_CMD, 0x00},
120 {R367TER_AGC2MAX, 0xff},
121 {R367TER_AGC2MIN, 0x00},
122 {R367TER_AGC1MAX, 0xff},
123 {R367TER_AGC1MIN, 0x00},
124 {R367TER_AGCR, 0xbc},
125 {R367TER_AGC2TH, 0x00},
126 {R367TER_AGC12C, 0x00},
127 {R367TER_AGCCTRL1, 0x85},
128 {R367TER_AGCCTRL2, 0x1f},
129 {R367TER_AGC1VAL1, 0x00},
130 {R367TER_AGC1VAL2, 0x00},
131 {R367TER_AGC2VAL1, 0x6f},
132 {R367TER_AGC2VAL2, 0x05},
133 {R367TER_AGC2PGA, 0x00},
134 {R367TER_OVF_RATE1, 0x00},
135 {R367TER_OVF_RATE2, 0x00},
136 {R367TER_GAIN_SRC1, 0xaa},/* for xc5000; was 0x2b */
137 {R367TER_GAIN_SRC2, 0xd6},/* for xc5000; was 0x04 */
138 {R367TER_INC_DEROT1, 0x55},
139 {R367TER_INC_DEROT2, 0x55},
140 {R367TER_PPM_CPAMP_DIR, 0x2c},
141 {R367TER_PPM_CPAMP_INV, 0x00},
142 {R367TER_FREESTFE_1, 0x00},
143 {R367TER_FREESTFE_2, 0x1c},
144 {R367TER_DCOFFSET, 0x00},
145 {R367TER_EN_PROCESS, 0x05},
146 {R367TER_SDI_SMOOTHER, 0x80},
147 {R367TER_FE_LOOP_OPEN, 0x1c},
148 {R367TER_FREQOFF1, 0x00},
149 {R367TER_FREQOFF2, 0x00},
150 {R367TER_FREQOFF3, 0x00},
151 {R367TER_TIMOFF1, 0x00},
152 {R367TER_TIMOFF2, 0x00},
154 {R367TER_EPQAUTO, 0x01},
155 {R367TER_SYR_UPDATE, 0xf5},
156 {R367TER_CHPFREE, 0x00},
157 {R367TER_PPM_STATE_MAC, 0x23},
158 {R367TER_INR_THRESHOLD, 0xff},
159 {R367TER_EPQ_TPS_ID_CELL, 0xf9},
160 {R367TER_EPQ_CFG, 0x00},
161 {R367TER_EPQ_STATUS, 0x01},
162 {R367TER_AUTORELOCK, 0x81},
163 {R367TER_BER_THR_VMSB, 0x00},
164 {R367TER_BER_THR_MSB, 0x00},
165 {R367TER_BER_THR_LSB, 0x00},
167 {R367TER_SPECTR_CFG, 0x00},
168 {R367TER_CHC_DUMMY, 0x18},
169 {R367TER_INC_CTL, 0x88},
170 {R367TER_INCTHRES_COR1, 0xb4},
171 {R367TER_INCTHRES_COR2, 0x96},
172 {R367TER_INCTHRES_DET1, 0x0e},
173 {R367TER_INCTHRES_DET2, 0x11},
174 {R367TER_IIR_CELLNB, 0x8d},
175 {R367TER_IIRCX_COEFF1_MSB, 0x00},
176 {R367TER_IIRCX_COEFF1_LSB, 0x00},
177 {R367TER_IIRCX_COEFF2_MSB, 0x09},
178 {R367TER_IIRCX_COEFF2_LSB, 0x18},
179 {R367TER_IIRCX_COEFF3_MSB, 0x14},
180 {R367TER_IIRCX_COEFF3_LSB, 0x9c},
181 {R367TER_IIRCX_COEFF4_MSB, 0x00},
182 {R367TER_IIRCX_COEFF4_LSB, 0x00},
183 {R367TER_IIRCX_COEFF5_MSB, 0x36},
184 {R367TER_IIRCX_COEFF5_LSB, 0x42},
185 {R367TER_FEPATH_CFG, 0x00},
186 {R367TER_PMC1_FUNC, 0x65},
187 {R367TER_PMC1_FOR, 0x00},
188 {R367TER_PMC2_FUNC, 0x00},
189 {R367TER_STATUS_ERR_DA, 0xe0},
190 {R367TER_DIG_AGC_R, 0xfe},
191 {R367TER_COMAGC_TARMSB, 0x0b},
192 {R367TER_COM_AGC_TAR_ENMODE, 0x41},
193 {R367TER_COM_AGC_CFG, 0x3e},
194 {R367TER_COM_AGC_GAIN1, 0x39},
195 {R367TER_AUT_AGC_TARGETMSB, 0x0b},
196 {R367TER_LOCK_DET_MSB, 0x01},
197 {R367TER_AGCTAR_LOCK_LSBS, 0x40},
198 {R367TER_AUT_GAIN_EN, 0xf4},
199 {R367TER_AUT_CFG, 0xf0},
200 {R367TER_LOCKN, 0x23},
201 {R367TER_INT_X_3, 0x00},
202 {R367TER_INT_X_2, 0x03},
203 {R367TER_INT_X_1, 0x8d},
204 {R367TER_INT_X_0, 0xa0},
205 {R367TER_MIN_ERRX_MSB, 0x00},
206 {R367TER_COR_CTL, 0x23},
207 {R367TER_COR_STAT, 0xf6},
208 {R367TER_COR_INTEN, 0x00},
209 {R367TER_COR_INTSTAT, 0x3f},
210 {R367TER_COR_MODEGUARD, 0x03},
211 {R367TER_AGC_CTL, 0x08},
212 {R367TER_AGC_MANUAL1, 0x00},
213 {R367TER_AGC_MANUAL2, 0x00},
214 {R367TER_AGC_TARG, 0x16},
215 {R367TER_AGC_GAIN1, 0x53},
216 {R367TER_AGC_GAIN2, 0x1d},
217 {R367TER_RESERVED_1, 0x00},
218 {R367TER_RESERVED_2, 0x00},
219 {R367TER_RESERVED_3, 0x00},
220 {R367TER_CAS_CTL, 0x44},
221 {R367TER_CAS_FREQ, 0xb3},
222 {R367TER_CAS_DAGCGAIN, 0x12},
223 {R367TER_SYR_CTL, 0x04},
224 {R367TER_SYR_STAT, 0x10},
225 {R367TER_SYR_NCO1, 0x00},
226 {R367TER_SYR_NCO2, 0x00},
227 {R367TER_SYR_OFFSET1, 0x00},
228 {R367TER_SYR_OFFSET2, 0x00},
229 {R367TER_FFT_CTL, 0x00},
230 {R367TER_SCR_CTL, 0x70},
231 {R367TER_PPM_CTL1, 0xf8},
232 {R367TER_TRL_CTL, 0x14},/* for xc5000; was 0xac */
233 {R367TER_TRL_NOMRATE1, 0xae},/* for xc5000; was 0x1e */
234 {R367TER_TRL_NOMRATE2, 0x56},/* for xc5000; was 0x58 */
235 {R367TER_TRL_TIME1, 0x1d},
236 {R367TER_TRL_TIME2, 0xfc},
237 {R367TER_CRL_CTL, 0x24},
238 {R367TER_CRL_FREQ1, 0xad},
239 {R367TER_CRL_FREQ2, 0x9d},
240 {R367TER_CRL_FREQ3, 0xff},
241 {R367TER_CHC_CTL, 0x01},
242 {R367TER_CHC_SNR, 0xf0},
243 {R367TER_BDI_CTL, 0x00},
244 {R367TER_DMP_CTL, 0x00},
245 {R367TER_TPS_RCVD1, 0x30},
246 {R367TER_TPS_RCVD2, 0x02},
247 {R367TER_TPS_RCVD3, 0x01},
248 {R367TER_TPS_RCVD4, 0x00},
249 {R367TER_TPS_ID_CELL1, 0x00},
250 {R367TER_TPS_ID_CELL2, 0x00},
251 {R367TER_TPS_RCVD5_SET1, 0x02},
252 {R367TER_TPS_SET2, 0x02},
253 {R367TER_TPS_SET3, 0x01},
254 {R367TER_TPS_CTL, 0x00},
255 {R367TER_CTL_FFTOSNUM, 0x34},
256 {R367TER_TESTSELECT, 0x09},
257 {R367TER_MSC_REV, 0x0a},
258 {R367TER_PIR_CTL, 0x00},
259 {R367TER_SNR_CARRIER1, 0xa1},
260 {R367TER_SNR_CARRIER2, 0x9a},
261 {R367TER_PPM_CPAMP, 0x2c},
262 {R367TER_TSM_AP0, 0x00},
263 {R367TER_TSM_AP1, 0x00},
264 {R367TER_TSM_AP2 , 0x00},
265 {R367TER_TSM_AP3, 0x00},
266 {R367TER_TSM_AP4, 0x00},
267 {R367TER_TSM_AP5, 0x00},
268 {R367TER_TSM_AP6, 0x00},
269 {R367TER_TSM_AP7, 0x00},
270 {R367TER_TSTRES, 0x00},
271 {R367TER_ANACTRL, 0x0D},/* PLL stoped, restart at init!!! */
272 {R367TER_TSTBUS, 0x00},
273 {R367TER_TSTRATE, 0x00},
274 {R367TER_CONSTMODE, 0x01},
275 {R367TER_CONSTCARR1, 0x00},
276 {R367TER_CONSTCARR2, 0x00},
277 {R367TER_ICONSTEL, 0x0a},
278 {R367TER_QCONSTEL, 0x15},
279 {R367TER_TSTBISTRES0, 0x00},
280 {R367TER_TSTBISTRES1, 0x00},
281 {R367TER_TSTBISTRES2, 0x28},
282 {R367TER_TSTBISTRES3, 0x00},
283 {R367TER_RF_AGC1, 0xff},
284 {R367TER_RF_AGC2, 0x83},
285 {R367TER_ANADIGCTRL, 0x19},
286 {R367TER_PLLMDIV, 0x01},/* for xc5000; was 0x0c */
287 {R367TER_PLLNDIV, 0x06},/* for xc5000; was 0x55 */
288 {R367TER_PLLSETUP, 0x18},
289 {R367TER_DUAL_AD12, 0x0C},/* for xc5000 AGC voltage 1.6V */
290 {R367TER_TSTBIST, 0x00},
291 {R367TER_PAD_COMP_CTRL, 0x00},
292 {R367TER_PAD_COMP_WR, 0x00},
293 {R367TER_PAD_COMP_RD, 0xe0},
294 {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
295 {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
296 {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
297 {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
298 {R367TER_SYR_FLAG, 0x00},
299 {R367TER_CRL_TARGET1, 0x00},
300 {R367TER_CRL_TARGET2, 0x00},
301 {R367TER_CRL_TARGET3, 0x00},
302 {R367TER_CRL_TARGET4, 0x00},
303 {R367TER_CRL_FLAG, 0x00},
304 {R367TER_TRL_TARGET1, 0x00},
305 {R367TER_TRL_TARGET2, 0x00},
306 {R367TER_TRL_CHC, 0x00},
307 {R367TER_CHC_SNR_TARG, 0x00},
308 {R367TER_TOP_TRACK, 0x00},
309 {R367TER_TRACKER_FREE1, 0x00},
310 {R367TER_ERROR_CRL1, 0x00},
311 {R367TER_ERROR_CRL2, 0x00},
312 {R367TER_ERROR_CRL3, 0x00},
313 {R367TER_ERROR_CRL4, 0x00},
314 {R367TER_DEC_NCO1, 0x2c},
315 {R367TER_DEC_NCO2, 0x0f},
316 {R367TER_DEC_NCO3, 0x20},
318 {R367TER_SYR_FFTADJ1, 0x00},
319 {R367TER_SYR_FFTADJ2, 0x00},
320 {R367TER_SYR_CHCADJ1, 0x00},
321 {R367TER_SYR_CHCADJ2, 0x00},
322 {R367TER_SYR_OFF, 0x00},
323 {R367TER_PPM_OFFSET1, 0x00},
324 {R367TER_PPM_OFFSET2, 0x03},
325 {R367TER_TRACKER_FREE2, 0x00},
326 {R367TER_DEBG_LT10, 0x00},
327 {R367TER_DEBG_LT11, 0x00},
328 {R367TER_DEBG_LT12, 0x00},
329 {R367TER_DEBG_LT13, 0x00},
330 {R367TER_DEBG_LT14, 0x00},
331 {R367TER_DEBG_LT15, 0x00},
332 {R367TER_DEBG_LT16, 0x00},
333 {R367TER_DEBG_LT17, 0x00},
334 {R367TER_DEBG_LT18, 0x00},
335 {R367TER_DEBG_LT19, 0x00},
336 {R367TER_DEBG_LT1A, 0x00},
337 {R367TER_DEBG_LT1B, 0x00},
338 {R367TER_DEBG_LT1C, 0x00},
339 {R367TER_DEBG_LT1D, 0x00},
340 {R367TER_DEBG_LT1E, 0x00},
341 {R367TER_DEBG_LT1F, 0x00},
342 {R367TER_RCCFGH, 0x00},
343 {R367TER_RCCFGM, 0x00},
344 {R367TER_RCCFGL, 0x00},
345 {R367TER_RCINSDELH, 0x00},
346 {R367TER_RCINSDELM, 0x00},
347 {R367TER_RCINSDELL, 0x00},
348 {R367TER_RCSTATUS, 0x00},
349 {R367TER_RCSPEED, 0x6f},
350 {R367TER_RCDEBUGM, 0xe7},
351 {R367TER_RCDEBUGL, 0x9b},
352 {R367TER_RCOBSCFG, 0x00},
353 {R367TER_RCOBSM, 0x00},
354 {R367TER_RCOBSL, 0x00},
355 {R367TER_RCFECSPY, 0x00},
356 {R367TER_RCFSPYCFG, 0x00},
357 {R367TER_RCFSPYDATA, 0x00},
358 {R367TER_RCFSPYOUT, 0x00},
359 {R367TER_RCFSTATUS, 0x00},
360 {R367TER_RCFGOODPACK, 0x00},
361 {R367TER_RCFPACKCNT, 0x00},
362 {R367TER_RCFSPYMISC, 0x00},
363 {R367TER_RCFBERCPT4, 0x00},
364 {R367TER_RCFBERCPT3, 0x00},
365 {R367TER_RCFBERCPT2, 0x00},
366 {R367TER_RCFBERCPT1, 0x00},
367 {R367TER_RCFBERCPT0, 0x00},
368 {R367TER_RCFBERERR2, 0x00},
369 {R367TER_RCFBERERR1, 0x00},
370 {R367TER_RCFBERERR0, 0x00},
371 {R367TER_RCFSTATESM, 0x00},
372 {R367TER_RCFSTATESL, 0x00},
373 {R367TER_RCFSPYBER, 0x00},
374 {R367TER_RCFSPYDISTM, 0x00},
375 {R367TER_RCFSPYDISTL, 0x00},
376 {R367TER_RCFSPYOBS7, 0x00},
377 {R367TER_RCFSPYOBS6, 0x00},
378 {R367TER_RCFSPYOBS5, 0x00},
379 {R367TER_RCFSPYOBS4, 0x00},
380 {R367TER_RCFSPYOBS3, 0x00},
381 {R367TER_RCFSPYOBS2, 0x00},
382 {R367TER_RCFSPYOBS1, 0x00},
383 {R367TER_RCFSPYOBS0, 0x00},
384 {R367TER_TSGENERAL, 0x00},
385 {R367TER_RC1SPEED, 0x6f},
386 {R367TER_TSGSTATUS, 0x18},
387 {R367TER_FECM, 0x01},
388 {R367TER_VTH12, 0xff},
389 {R367TER_VTH23, 0xa1},
390 {R367TER_VTH34, 0x64},
391 {R367TER_VTH56, 0x40},
392 {R367TER_VTH67, 0x00},
393 {R367TER_VTH78, 0x2c},
394 {R367TER_VITCURPUN, 0x12},
395 {R367TER_VERROR, 0x01},
396 {R367TER_PRVIT, 0x3f},
397 {R367TER_VAVSRVIT, 0x00},
398 {R367TER_VSTATUSVIT, 0xbd},
399 {R367TER_VTHINUSE, 0xa1},
400 {R367TER_KDIV12, 0x20},
401 {R367TER_KDIV23, 0x40},
402 {R367TER_KDIV34, 0x20},
403 {R367TER_KDIV56, 0x30},
404 {R367TER_KDIV67, 0x00},
405 {R367TER_KDIV78, 0x30},
406 {R367TER_SIGPOWER, 0x54},
407 {R367TER_DEMAPVIT, 0x40},
408 {R367TER_VITSCALE, 0x00},
409 {R367TER_FFEC1PRG, 0x00},
410 {R367TER_FVITCURPUN, 0x12},
411 {R367TER_FVERROR, 0x01},
412 {R367TER_FVSTATUSVIT, 0xbd},
413 {R367TER_DEBUG_LT1, 0x00},
414 {R367TER_DEBUG_LT2, 0x00},
415 {R367TER_DEBUG_LT3, 0x00},
416 {R367TER_TSTSFMET, 0x00},
417 {R367TER_SELOUT, 0x00},
418 {R367TER_TSYNC, 0x00},
419 {R367TER_TSTERR, 0x00},
420 {R367TER_TSFSYNC, 0x00},
421 {R367TER_TSTSFERR, 0x00},
422 {R367TER_TSTTSSF1, 0x01},
423 {R367TER_TSTTSSF2, 0x1f},
424 {R367TER_TSTTSSF3, 0x00},
425 {R367TER_TSTTS1, 0x00},
426 {R367TER_TSTTS2, 0x1f},
427 {R367TER_TSTTS3, 0x01},
428 {R367TER_TSTTS4, 0x00},
429 {R367TER_TSTTSRC, 0x00},
430 {R367TER_TSTTSRS, 0x00},
431 {R367TER_TSSTATEM, 0xb0},
432 {R367TER_TSSTATEL, 0x40},
433 {R367TER_TSCFGH, 0xC0},
434 {R367TER_TSCFGM, 0xc0},/* for xc5000; was 0x00 */
435 {R367TER_TSCFGL, 0x20},
436 {R367TER_TSSYNC, 0x00},
437 {R367TER_TSINSDELH, 0x00},
438 {R367TER_TSINSDELM, 0x00},
439 {R367TER_TSINSDELL, 0x00},
440 {R367TER_TSDIVN, 0x03},
441 {R367TER_TSDIVPM, 0x00},
442 {R367TER_TSDIVPL, 0x00},
443 {R367TER_TSDIVQM, 0x00},
444 {R367TER_TSDIVQL, 0x00},
445 {R367TER_TSDILSTKM, 0x00},
446 {R367TER_TSDILSTKL, 0x00},
447 {R367TER_TSSPEED, 0x40},/* for xc5000; was 0x6f */
448 {R367TER_TSSTATUS, 0x81},
449 {R367TER_TSSTATUS2, 0x6a},
450 {R367TER_TSBITRATEM, 0x0f},
451 {R367TER_TSBITRATEL, 0xc6},
452 {R367TER_TSPACKLENM, 0x00},
453 {R367TER_TSPACKLENL, 0xfc},
454 {R367TER_TSBLOCLENM, 0x0a},
455 {R367TER_TSBLOCLENL, 0x80},
456 {R367TER_TSDLYH, 0x90},
457 {R367TER_TSDLYM, 0x68},
458 {R367TER_TSDLYL, 0x01},
459 {R367TER_TSNPDAV, 0x00},
460 {R367TER_TSBUFSTATH, 0x00},
461 {R367TER_TSBUFSTATM, 0x00},
462 {R367TER_TSBUFSTATL, 0x00},
463 {R367TER_TSDEBUGM, 0xcf},
464 {R367TER_TSDEBUGL, 0x1e},
465 {R367TER_TSDLYSETH, 0x00},
466 {R367TER_TSDLYSETM, 0x68},
467 {R367TER_TSDLYSETL, 0x00},
468 {R367TER_TSOBSCFG, 0x00},
469 {R367TER_TSOBSM, 0x47},
470 {R367TER_TSOBSL, 0x1f},
471 {R367TER_ERRCTRL1, 0x95},
472 {R367TER_ERRCNT1H, 0x80},
473 {R367TER_ERRCNT1M, 0x00},
474 {R367TER_ERRCNT1L, 0x00},
475 {R367TER_ERRCTRL2, 0x95},
476 {R367TER_ERRCNT2H, 0x00},
477 {R367TER_ERRCNT2M, 0x00},
478 {R367TER_ERRCNT2L, 0x00},
479 {R367TER_FECSPY, 0x88},
480 {R367TER_FSPYCFG, 0x2c},
481 {R367TER_FSPYDATA, 0x3a},
482 {R367TER_FSPYOUT, 0x06},
483 {R367TER_FSTATUS, 0x61},
484 {R367TER_FGOODPACK, 0xff},
485 {R367TER_FPACKCNT, 0xff},
486 {R367TER_FSPYMISC, 0x66},
487 {R367TER_FBERCPT4, 0x00},
488 {R367TER_FBERCPT3, 0x00},
489 {R367TER_FBERCPT2, 0x36},
490 {R367TER_FBERCPT1, 0x36},
491 {R367TER_FBERCPT0, 0x14},
492 {R367TER_FBERERR2, 0x00},
493 {R367TER_FBERERR1, 0x03},
494 {R367TER_FBERERR0, 0x28},
495 {R367TER_FSTATESM, 0x00},
496 {R367TER_FSTATESL, 0x02},
497 {R367TER_FSPYBER, 0x00},
498 {R367TER_FSPYDISTM, 0x01},
499 {R367TER_FSPYDISTL, 0x9f},
500 {R367TER_FSPYOBS7, 0xc9},
501 {R367TER_FSPYOBS6, 0x99},
502 {R367TER_FSPYOBS5, 0x08},
503 {R367TER_FSPYOBS4, 0xec},
504 {R367TER_FSPYOBS3, 0x01},
505 {R367TER_FSPYOBS2, 0x0f},
506 {R367TER_FSPYOBS1, 0xf5},
507 {R367TER_FSPYOBS0, 0x08},
508 {R367TER_SFDEMAP, 0x40},
509 {R367TER_SFERROR, 0x00},
510 {R367TER_SFAVSR, 0x30},
511 {R367TER_SFECSTATUS, 0xcc},
512 {R367TER_SFKDIV12, 0x20},
513 {R367TER_SFKDIV23, 0x40},
514 {R367TER_SFKDIV34, 0x20},
515 {R367TER_SFKDIV56, 0x20},
516 {R367TER_SFKDIV67, 0x00},
517 {R367TER_SFKDIV78, 0x20},
518 {R367TER_SFDILSTKM, 0x00},
519 {R367TER_SFDILSTKL, 0x00},
520 {R367TER_SFSTATUS, 0xb5},
521 {R367TER_SFDLYH, 0x90},
522 {R367TER_SFDLYM, 0x60},
523 {R367TER_SFDLYL, 0x01},
524 {R367TER_SFDLYSETH, 0xc0},
525 {R367TER_SFDLYSETM, 0x60},
526 {R367TER_SFDLYSETL, 0x00},
527 {R367TER_SFOBSCFG, 0x00},
528 {R367TER_SFOBSM, 0x47},
529 {R367TER_SFOBSL, 0x05},
530 {R367TER_SFECINFO, 0x40},
531 {R367TER_SFERRCTRL, 0x74},
532 {R367TER_SFERRCNTH, 0x80},
533 {R367TER_SFERRCNTM , 0x00},
534 {R367TER_SFERRCNTL, 0x00},
535 {R367TER_SYMBRATEM, 0x2f},
536 {R367TER_SYMBRATEL, 0x50},
537 {R367TER_SYMBSTATUS, 0x7f},
538 {R367TER_SYMBCFG, 0x00},
539 {R367TER_SYMBFIFOM, 0xf4},
540 {R367TER_SYMBFIFOL, 0x0d},
541 {R367TER_SYMBOFFSM, 0xf0},
542 {R367TER_SYMBOFFSL, 0x2d},
543 {R367TER_DEBUG_LT4, 0x00},
544 {R367TER_DEBUG_LT5, 0x00},
545 {R367TER_DEBUG_LT6, 0x00},
546 {R367TER_DEBUG_LT7, 0x00},
547 {R367TER_DEBUG_LT8, 0x00},
548 {R367TER_DEBUG_LT9, 0x00},
551 #define RF_LOOKUP_TABLE_SIZE 31
552 #define RF_LOOKUP_TABLE2_SIZE 16
553 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
554 s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
556 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
557 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
558 76, 77, 78, 80, 83, 85, 88,
560 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
561 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
562 49, 50, 52, 53, 54, 55, 56,
565 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
566 s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
568 28, 29, 31, 32, 34, 35, 36, 37,
569 38, 39, 40, 41, 42, 43, 44, 45,
571 57, 58, 59, 60, 61, 62, 63, 64,
572 65, 66, 67, 68, 69, 70, 71, 72,
576 static struct st_register def0367cab[STV0367CAB_NBREGS] = {
578 {R367CAB_I2CRPT, 0xa0},
579 /*{R367CAB_I2CRPT, 0x22},*/
580 {R367CAB_TOPCTRL, 0x10},
581 {R367CAB_IOCFG0, 0x80},
582 {R367CAB_DAC0R, 0x00},
583 {R367CAB_IOCFG1, 0x00},
584 {R367CAB_DAC1R, 0x00},
585 {R367CAB_IOCFG2, 0x00},
586 {R367CAB_SDFR, 0x00},
587 {R367CAB_AUX_CLK, 0x00},
588 {R367CAB_FREESYS1, 0x00},
589 {R367CAB_FREESYS2, 0x00},
590 {R367CAB_FREESYS3, 0x00},
591 {R367CAB_GPIO_CFG, 0x55},
592 {R367CAB_GPIO_CMD, 0x01},
593 {R367CAB_TSTRES, 0x00},
594 {R367CAB_ANACTRL, 0x0d},/* was 0x00 need to check - I.M.L.*/
595 {R367CAB_TSTBUS, 0x00},
596 {R367CAB_RF_AGC1, 0xea},
597 {R367CAB_RF_AGC2, 0x82},
598 {R367CAB_ANADIGCTRL, 0x0b},
599 {R367CAB_PLLMDIV, 0x01},
600 {R367CAB_PLLNDIV, 0x08},
601 {R367CAB_PLLSETUP, 0x18},
602 {R367CAB_DUAL_AD12, 0x0C}, /* for xc5000 AGC voltage 1.6V */
603 {R367CAB_TSTBIST, 0x00},
604 {R367CAB_CTRL_1, 0x00},
605 {R367CAB_CTRL_2, 0x03},
606 {R367CAB_IT_STATUS1, 0x2b},
607 {R367CAB_IT_STATUS2, 0x08},
608 {R367CAB_IT_EN1, 0x00},
609 {R367CAB_IT_EN2, 0x00},
610 {R367CAB_CTRL_STATUS, 0x04},
611 {R367CAB_TEST_CTL, 0x00},
612 {R367CAB_AGC_CTL, 0x73},
613 {R367CAB_AGC_IF_CFG, 0x50},
614 {R367CAB_AGC_RF_CFG, 0x00},
615 {R367CAB_AGC_PWM_CFG, 0x03},
616 {R367CAB_AGC_PWR_REF_L, 0x5a},
617 {R367CAB_AGC_PWR_REF_H, 0x00},
618 {R367CAB_AGC_RF_TH_L, 0xff},
619 {R367CAB_AGC_RF_TH_H, 0x07},
620 {R367CAB_AGC_IF_LTH_L, 0x00},
621 {R367CAB_AGC_IF_LTH_H, 0x08},
622 {R367CAB_AGC_IF_HTH_L, 0xff},
623 {R367CAB_AGC_IF_HTH_H, 0x07},
624 {R367CAB_AGC_PWR_RD_L, 0xa0},
625 {R367CAB_AGC_PWR_RD_M, 0xe9},
626 {R367CAB_AGC_PWR_RD_H, 0x03},
627 {R367CAB_AGC_PWM_IFCMD_L, 0xe4},
628 {R367CAB_AGC_PWM_IFCMD_H, 0x00},
629 {R367CAB_AGC_PWM_RFCMD_L, 0xff},
630 {R367CAB_AGC_PWM_RFCMD_H, 0x07},
631 {R367CAB_IQDEM_CFG, 0x01},
632 {R367CAB_MIX_NCO_LL, 0x22},
633 {R367CAB_MIX_NCO_HL, 0x96},
634 {R367CAB_MIX_NCO_HH, 0x55},
635 {R367CAB_SRC_NCO_LL, 0xff},
636 {R367CAB_SRC_NCO_LH, 0x0c},
637 {R367CAB_SRC_NCO_HL, 0xf5},
638 {R367CAB_SRC_NCO_HH, 0x20},
639 {R367CAB_IQDEM_GAIN_SRC_L, 0x06},
640 {R367CAB_IQDEM_GAIN_SRC_H, 0x01},
641 {R367CAB_IQDEM_DCRM_CFG_LL, 0xfe},
642 {R367CAB_IQDEM_DCRM_CFG_LH, 0xff},
643 {R367CAB_IQDEM_DCRM_CFG_HL, 0x0f},
644 {R367CAB_IQDEM_DCRM_CFG_HH, 0x00},
645 {R367CAB_IQDEM_ADJ_COEFF0, 0x34},
646 {R367CAB_IQDEM_ADJ_COEFF1, 0xae},
647 {R367CAB_IQDEM_ADJ_COEFF2, 0x46},
648 {R367CAB_IQDEM_ADJ_COEFF3, 0x77},
649 {R367CAB_IQDEM_ADJ_COEFF4, 0x96},
650 {R367CAB_IQDEM_ADJ_COEFF5, 0x69},
651 {R367CAB_IQDEM_ADJ_COEFF6, 0xc7},
652 {R367CAB_IQDEM_ADJ_COEFF7, 0x01},
653 {R367CAB_IQDEM_ADJ_EN, 0x04},
654 {R367CAB_IQDEM_ADJ_AGC_REF, 0x94},
655 {R367CAB_ALLPASSFILT1, 0xc9},
656 {R367CAB_ALLPASSFILT2, 0x2d},
657 {R367CAB_ALLPASSFILT3, 0xa3},
658 {R367CAB_ALLPASSFILT4, 0xfb},
659 {R367CAB_ALLPASSFILT5, 0xf6},
660 {R367CAB_ALLPASSFILT6, 0x45},
661 {R367CAB_ALLPASSFILT7, 0x6f},
662 {R367CAB_ALLPASSFILT8, 0x7e},
663 {R367CAB_ALLPASSFILT9, 0x05},
664 {R367CAB_ALLPASSFILT10, 0x0a},
665 {R367CAB_ALLPASSFILT11, 0x51},
666 {R367CAB_TRL_AGC_CFG, 0x20},
667 {R367CAB_TRL_LPF_CFG, 0x28},
668 {R367CAB_TRL_LPF_ACQ_GAIN, 0x44},
669 {R367CAB_TRL_LPF_TRK_GAIN, 0x22},
670 {R367CAB_TRL_LPF_OUT_GAIN, 0x03},
671 {R367CAB_TRL_LOCKDET_LTH, 0x04},
672 {R367CAB_TRL_LOCKDET_HTH, 0x11},
673 {R367CAB_TRL_LOCKDET_TRGVAL, 0x20},
674 {R367CAB_IQ_QAM, 0x01},
675 {R367CAB_FSM_STATE, 0xa0},
676 {R367CAB_FSM_CTL, 0x08},
677 {R367CAB_FSM_STS, 0x0c},
678 {R367CAB_FSM_SNR0_HTH, 0x00},
679 {R367CAB_FSM_SNR1_HTH, 0x00},
680 {R367CAB_FSM_SNR2_HTH, 0x23},/* 0x00 */
681 {R367CAB_FSM_SNR0_LTH, 0x00},
682 {R367CAB_FSM_SNR1_LTH, 0x00},
683 {R367CAB_FSM_EQA1_HTH, 0x00},
684 {R367CAB_FSM_TEMPO, 0x32},
685 {R367CAB_FSM_CONFIG, 0x03},
686 {R367CAB_EQU_I_TESTTAP_L, 0x11},
687 {R367CAB_EQU_I_TESTTAP_M, 0x00},
688 {R367CAB_EQU_I_TESTTAP_H, 0x00},
689 {R367CAB_EQU_TESTAP_CFG, 0x00},
690 {R367CAB_EQU_Q_TESTTAP_L, 0xff},
691 {R367CAB_EQU_Q_TESTTAP_M, 0x00},
692 {R367CAB_EQU_Q_TESTTAP_H, 0x00},
693 {R367CAB_EQU_TAP_CTRL, 0x00},
694 {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
695 {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
696 {R367CAB_EQU_CTR_HIPOW_L, 0x00},
697 {R367CAB_EQU_CTR_HIPOW_H, 0x00},
698 {R367CAB_EQU_I_EQU_LO, 0xef},
699 {R367CAB_EQU_I_EQU_HI, 0x00},
700 {R367CAB_EQU_Q_EQU_LO, 0xee},
701 {R367CAB_EQU_Q_EQU_HI, 0x00},
702 {R367CAB_EQU_MAPPER, 0xc5},
703 {R367CAB_EQU_SWEEP_RATE, 0x80},
704 {R367CAB_EQU_SNR_LO, 0x64},
705 {R367CAB_EQU_SNR_HI, 0x03},
706 {R367CAB_EQU_GAMMA_LO, 0x00},
707 {R367CAB_EQU_GAMMA_HI, 0x00},
708 {R367CAB_EQU_ERR_GAIN, 0x36},
709 {R367CAB_EQU_RADIUS, 0xaa},
710 {R367CAB_EQU_FFE_MAINTAP, 0x00},
711 {R367CAB_EQU_FFE_LEAKAGE, 0x63},
712 {R367CAB_EQU_FFE_MAINTAP_POS, 0xdf},
713 {R367CAB_EQU_GAIN_WIDE, 0x88},
714 {R367CAB_EQU_GAIN_NARROW, 0x41},
715 {R367CAB_EQU_CTR_LPF_GAIN, 0xd1},
716 {R367CAB_EQU_CRL_LPF_GAIN, 0xa7},
717 {R367CAB_EQU_GLOBAL_GAIN, 0x06},
718 {R367CAB_EQU_CRL_LD_SEN, 0x85},
719 {R367CAB_EQU_CRL_LD_VAL, 0xe2},
720 {R367CAB_EQU_CRL_TFR, 0x20},
721 {R367CAB_EQU_CRL_BISTH_LO, 0x00},
722 {R367CAB_EQU_CRL_BISTH_HI, 0x00},
723 {R367CAB_EQU_SWEEP_RANGE_LO, 0x00},
724 {R367CAB_EQU_SWEEP_RANGE_HI, 0x00},
725 {R367CAB_EQU_CRL_LIMITER, 0x40},
726 {R367CAB_EQU_MODULUS_MAP, 0x90},
727 {R367CAB_EQU_PNT_GAIN, 0xa7},
728 {R367CAB_FEC_AC_CTR_0, 0x16},
729 {R367CAB_FEC_AC_CTR_1, 0x0b},
730 {R367CAB_FEC_AC_CTR_2, 0x88},
731 {R367CAB_FEC_AC_CTR_3, 0x02},
732 {R367CAB_FEC_STATUS, 0x12},
733 {R367CAB_RS_COUNTER_0, 0x7d},
734 {R367CAB_RS_COUNTER_1, 0xd0},
735 {R367CAB_RS_COUNTER_2, 0x19},
736 {R367CAB_RS_COUNTER_3, 0x0b},
737 {R367CAB_RS_COUNTER_4, 0xa3},
738 {R367CAB_RS_COUNTER_5, 0x00},
739 {R367CAB_BERT_0, 0x01},
740 {R367CAB_BERT_1, 0x25},
741 {R367CAB_BERT_2, 0x41},
742 {R367CAB_BERT_3, 0x39},
743 {R367CAB_OUTFORMAT_0, 0xc2},
744 {R367CAB_OUTFORMAT_1, 0x22},
745 {R367CAB_SMOOTHER_2, 0x28},
746 {R367CAB_TSMF_CTRL_0, 0x01},
747 {R367CAB_TSMF_CTRL_1, 0xc6},
748 {R367CAB_TSMF_CTRL_3, 0x43},
749 {R367CAB_TS_ON_ID_0, 0x00},
750 {R367CAB_TS_ON_ID_1, 0x00},
751 {R367CAB_TS_ON_ID_2, 0x00},
752 {R367CAB_TS_ON_ID_3, 0x00},
753 {R367CAB_RE_STATUS_0, 0x00},
754 {R367CAB_RE_STATUS_1, 0x00},
755 {R367CAB_RE_STATUS_2, 0x00},
756 {R367CAB_RE_STATUS_3, 0x00},
757 {R367CAB_TS_STATUS_0, 0x00},
758 {R367CAB_TS_STATUS_1, 0x00},
759 {R367CAB_TS_STATUS_2, 0xa0},
760 {R367CAB_TS_STATUS_3, 0x00},
761 {R367CAB_T_O_ID_0, 0x00},
762 {R367CAB_T_O_ID_1, 0x00},
763 {R367CAB_T_O_ID_2, 0x00},
764 {R367CAB_T_O_ID_3, 0x00},
768 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
771 struct i2c_msg msg = {
772 .addr = state->config->demod_address,
781 memcpy(buf + 2, data, len);
784 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, buf[2]);
786 ret = i2c_transfer(state->i2c, &msg, 1);
788 printk(KERN_ERR "%s: i2c write error!\n", __func__);
790 return (ret != 1) ? -EREMOTEIO : 0;
793 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
795 return stv0367_writeregs(state, reg, &data, 1);
798 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
802 struct i2c_msg msg[] = {
804 .addr = state->config->demod_address,
809 .addr = state->config->demod_address,
820 ret = i2c_transfer(state->i2c, msg, 2);
822 printk(KERN_ERR "%s: i2c read error\n", __func__);
825 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, b1[0]);
830 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
832 u8 position = 0, i = 0;
834 (*mask) = label & 0xff;
836 while ((position == 0) && (i < 8)) {
837 position = ((*mask) >> i) & 0x01;
844 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
848 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
849 extract_mask_pos(label, &mask, &pos);
851 val = mask & (val << pos);
853 reg = (reg & (~mask)) | val;
854 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
858 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
862 extract_mask_pos(label, &mask, &pos);
864 val = mask & (val << pos);
866 (*reg) = ((*reg) & (~mask)) | val;
869 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
874 extract_mask_pos(label, &mask, &pos);
876 val = stv0367_readreg(state, label >> 16);
877 val = (val & mask) >> pos;
882 #if 0 /* Currently, unused */
883 static u8 stv0367_getbits(u8 reg, u32 label)
887 extract_mask_pos(label, &mask, &pos);
889 return (reg & mask) >> pos;
892 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
894 struct stv0367_state *state = fe->demodulator_priv;
895 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
897 dprintk("%s:\n", __func__);
900 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
901 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
903 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
904 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
907 stv0367_writereg(state, R367TER_I2CRPT, tmp);
912 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
914 struct dvb_frontend_ops *frontend_ops = NULL;
915 struct dvb_tuner_ops *tuner_ops = NULL;
919 dprintk("%s:\n", __func__);
923 frontend_ops = &fe->ops;
924 if (&frontend_ops->tuner_ops)
925 tuner_ops = &frontend_ops->tuner_ops;
926 if (tuner_ops->get_frequency) {
927 err = tuner_ops->get_frequency(fe, &freq);
929 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
933 dprintk("%s: frequency=%d\n", __func__, freq);
941 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
943 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
944 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
945 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
946 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
947 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
948 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
950 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
951 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
952 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
953 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
954 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
955 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
957 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
958 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
959 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
960 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
961 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
962 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
966 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
968 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
969 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
970 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
971 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
972 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
973 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
975 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
976 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
977 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
978 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
979 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
980 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
982 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
983 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
984 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
985 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
986 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
987 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
991 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
993 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
994 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
995 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
996 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
997 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
998 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
1000 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
1001 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
1002 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
1003 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
1004 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
1005 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
1008 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
1009 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1010 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1011 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1012 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1013 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
1017 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
1019 u32 mclk_Hz = 0; /* master clock frequency (Hz) */
1022 dprintk("%s:\n", __func__);
1024 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
1025 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
1029 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
1033 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
1037 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
1039 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
1040 n, m, p, mclk_Hz, ExtClk_Hz);
1042 mclk_Hz = ExtClk_Hz;
1044 dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
1049 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
1050 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
1054 dprintk("%s:\n", __func__);
1056 freq = stv0367ter_get_mclk(state, DemodXtal);
1058 if (freq == 53125000)
1059 k = 1; /* equivalent to Xtal 25M on 362*/
1060 else if (freq == 54000000)
1061 k = 0; /* equivalent to Xtal 27M on 362*/
1062 else if (freq == 52500000)
1063 k = 2; /* equivalent to Xtal 30M on 362*/
1067 for (i = 1; i <= 6; i++) {
1068 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
1070 for (j = 1; j <= 5; j++) {
1071 stv0367_writereg(state,
1072 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
1073 MSB(CellsCoeffs[k][i-1][j-1]));
1074 stv0367_writereg(state,
1075 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
1076 LSB(CellsCoeffs[k][i-1][j-1]));
1084 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
1086 dprintk("%s:\n", __func__);
1088 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
1091 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
1092 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1093 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1096 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
1097 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1098 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1101 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
1102 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1103 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1106 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
1107 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1108 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1112 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
1115 dprintk("%s:\n", __func__);
1117 stv0367_writebits(state, F367TER_NRST_IIR, 0);
1119 switch (Bandwidth) {
1121 if (!stv0367ter_filt_coeff_init(state,
1122 CellsCoeffs_6MHz_367cofdm,
1127 if (!stv0367ter_filt_coeff_init(state,
1128 CellsCoeffs_7MHz_367cofdm,
1133 if (!stv0367ter_filt_coeff_init(state,
1134 CellsCoeffs_8MHz_367cofdm,
1142 stv0367_writebits(state, F367TER_NRST_IIR, 1);
1147 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
1152 dprintk("%s:\n", __func__);
1154 com_n = stv0367_readbits(state, F367TER_COM_N);
1156 stv0367_writebits(state, F367TER_COM_N, 0x07);
1158 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
1159 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
1161 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
1162 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
1164 stv0367_writebits(state, F367TER_COM_N, com_n);
1168 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
1170 int local_tempo = 0;
1173 local_tempo = tempo1;
1176 local_tempo = tempo2;
1180 local_tempo = tempo3;
1186 /* msleep(local_tempo); */
1191 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
1194 unsigned short int SYR_var;
1197 dprintk("%s:\n", __func__);
1199 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1201 while ((!SYR_var) && (wd > 0)) {
1202 usleep_range(2000, 3000);
1204 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1208 SYRStatus = FE_TER_NOSYMBOL;
1210 SYRStatus = FE_TER_SYMBOLOK;
1212 dprintk("stv0367ter_check_syr SYRStatus %s\n",
1213 SYR_var == 0 ? "No Symbol" : "OK");
1219 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
1223 s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
1226 dprintk("%s:\n", __func__);
1242 CPAMPMin = 0xffff; /*drives to NOCPAMP */
1246 dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
1248 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1249 while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
1250 usleep_range(1000, 2000);
1252 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1253 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
1255 dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
1256 if (CPAMPvalue < CPAMPMin) {
1257 CPAMPStatus = FE_TER_NOCPAMP;
1258 printk(KERN_ERR "CPAMP failed\n");
1260 printk(KERN_ERR "CPAMP OK !\n");
1261 CPAMPStatus = FE_TER_CPAMPOK;
1267 static enum stv0367_ter_signal_type
1268 stv0367ter_lock_algo(struct stv0367_state *state)
1270 enum stv0367_ter_signal_type ret_flag;
1271 short int wd, tempo;
1272 u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
1275 dprintk("%s:\n", __func__);
1278 return FE_TER_SWNOK;
1282 ret_flag = FE_TER_LOCKOK;
1284 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1286 if (state->config->if_iq_mode != 0)
1287 stv0367_writebits(state, F367TER_COM_N, 0x07);
1289 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
1290 stv0367_writebits(state, F367TER_MODE, 0);
1291 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
1292 usleep_range(5000, 10000);
1294 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1297 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
1298 return FE_TER_NOSYMBOL;
1300 if chip locked on wrong mode first try,
1301 it must lock correctly second try */
1302 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1303 if (stv0367ter_check_cpamp(state, mode) ==
1306 ret_flag = FE_TER_NOCPAMP;
1312 } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
1314 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
1315 tmp2 = stv0367_readreg(state, R367TER_STATUS);
1316 dprintk("state=%p\n", state);
1317 dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
1320 tmp = stv0367_readreg(state, R367TER_PRVIT);
1321 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
1322 dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
1324 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
1325 dprintk("GAIN_SRC1=0x%x\n", tmp);
1327 if ((mode != 0) && (mode != 1) && (mode != 2))
1328 return FE_TER_SWNOK;
1330 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
1332 /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
1333 and set channel predictor in automatic */
1339 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1340 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
1344 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1345 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1349 return FE_TER_SWNOK;
1353 /*reset fec an reedsolo FOR 367 only*/
1354 stv0367_writebits(state, F367TER_RST_SFEC, 1);
1355 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
1356 usleep_range(1000, 2000);
1357 stv0367_writebits(state, F367TER_RST_SFEC, 0);
1358 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
1360 u_var1 = stv0367_readbits(state, F367TER_LK);
1361 u_var2 = stv0367_readbits(state, F367TER_PRF);
1362 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1363 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
1365 wd = stv0367ter_duration(mode, 125, 500, 250);
1366 tempo = stv0367ter_duration(mode, 4, 16, 8);
1368 /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
1369 while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
1370 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1372 u_var1 = stv0367_readbits(state, F367TER_LK);
1373 u_var2 = stv0367_readbits(state, F367TER_PRF);
1374 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1375 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
1379 return FE_TER_NOLOCK;
1383 return FE_TER_NOPRFOUND;
1386 return FE_TER_NOTPS;
1388 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1389 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1393 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1394 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
1395 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
1399 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1400 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
1401 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
1405 return FE_TER_SWNOK;
1408 /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
1409 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
1411 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
1412 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
1413 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
1414 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
1416 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
1418 wd = stv0367ter_duration(mode, 125, 500, 250);
1419 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1421 while ((!u_var4) && (wd >= 0)) {
1422 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1424 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1428 return FE_TER_NOLOCK;
1430 /* for 367 leave COM_N at 0x7 for IQ_mode*/
1431 /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
1433 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
1434 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
1435 ChipWaitOrAbort(state,1);
1439 stv0367_writebits(state,F367TER_COM_N,0x17);
1442 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
1444 dprintk("FE_TER_LOCKOK !!!\n");
1446 return FE_TER_LOCKOK;
1450 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
1451 enum stv0367_ts_mode PathTS)
1454 dprintk("%s:\n", __func__);
1459 stv0367_writebits(state, F367TER_TS_DIS, 0);
1462 /*for removing warning :default we can assume in parallel mode*/
1463 case STV0367_PARALLEL_PUNCT_CLOCK:
1464 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
1465 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
1467 case STV0367_SERIAL_PUNCT_CLOCK:
1468 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
1469 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
1474 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
1475 enum stv0367_clk_pol clock)
1478 dprintk("%s:\n", __func__);
1484 case STV0367_RISINGEDGE_CLOCK:
1485 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
1487 case STV0367_FALLINGEDGE_CLOCK:
1488 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1490 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
1492 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1498 static void stv0367ter_core_sw(struct stv0367_state *state)
1501 dprintk("%s:\n", __func__);
1503 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1504 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1508 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
1510 struct stv0367_state *state = fe->demodulator_priv;
1512 dprintk("%s:\n", __func__);
1515 stv0367_writebits(state, F367TER_STDBY, 1);
1516 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
1517 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
1519 stv0367_writebits(state, F367TER_STDBY, 0);
1520 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
1521 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
1527 static int stv0367ter_sleep(struct dvb_frontend *fe)
1529 return stv0367ter_standby(fe, 1);
1532 static int stv0367ter_init(struct dvb_frontend *fe)
1534 struct stv0367_state *state = fe->demodulator_priv;
1535 struct stv0367ter_state *ter_state = state->ter_state;
1538 dprintk("%s:\n", __func__);
1540 ter_state->pBER = 0;
1542 for (i = 0; i < STV0367TER_NBREGS; i++)
1543 stv0367_writereg(state, def0367ter[i].addr,
1544 def0367ter[i].value);
1546 switch (state->config->xtal) {
1547 /*set internal freq to 53.125MHz */
1549 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
1550 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1551 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1555 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
1556 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
1557 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
1558 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1561 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
1562 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1563 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1567 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
1568 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1570 /*Set TS1 and TS2 to serial or parallel mode */
1571 stv0367ter_set_ts_mode(state, state->config->ts_mode);
1572 stv0367ter_set_clk_pol(state, state->config->clk_pol);
1574 state->chip_id = stv0367_readreg(state, R367TER_ID);
1575 ter_state->first_lock = 0;
1576 ter_state->unlock_counter = 2;
1581 static int stv0367ter_algo(struct dvb_frontend *fe)
1583 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1584 struct stv0367_state *state = fe->demodulator_priv;
1585 struct stv0367ter_state *ter_state = state->ter_state;
1586 int offset = 0, tempo = 0;
1588 u8 /*constell,*/ counter;
1590 s32 timing_offset = 0;
1591 u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
1593 dprintk("%s:\n", __func__);
1595 ter_state->frequency = p->frequency;
1596 ter_state->force = FE_TER_FORCENONE
1597 + stv0367_readbits(state, F367TER_FORCE) * 2;
1598 ter_state->if_iq_mode = state->config->if_iq_mode;
1599 switch (state->config->if_iq_mode) {
1600 case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
1601 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1602 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1603 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1604 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1606 case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
1607 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1608 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1609 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1610 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1612 case FE_TER_IQ_TUNER: /* IQ mode */
1613 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1614 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1615 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1618 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1622 usleep_range(5000, 7000);
1624 switch (p->inversion) {
1625 case INVERSION_AUTO:
1627 dprintk("%s: inversion AUTO\n", __func__);
1628 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1629 stv0367_writebits(state, F367TER_IQ_INVERT,
1632 stv0367_writebits(state, F367TER_INV_SPECTR,
1638 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1639 stv0367_writebits(state, F367TER_IQ_INVERT,
1642 stv0367_writebits(state, F367TER_INV_SPECTR,
1648 if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1649 (ter_state->pBW != ter_state->bw)) {
1650 stv0367ter_agc_iir_lock_detect_set(state);
1652 /*set fine agc target to 180 for LPIF or IQ mode*/
1653 /* set Q_AGCTarget */
1654 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1655 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1656 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1658 /* set Q_AGCTarget */
1659 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1660 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1661 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1663 if (!stv0367_iir_filt_init(state, ter_state->bw,
1664 state->config->xtal))
1666 /*set IIR filter once for 6,7 or 8MHz BW*/
1667 ter_state->pBW = ter_state->bw;
1669 stv0367ter_agc_iir_rst(state);
1672 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1673 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1675 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1677 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1679 ((((ter_state->bw * 64 * (1 << 15) * 100)
1680 / (InternalFreq)) * 10) / 7);
1682 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1684 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1685 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1687 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1688 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1689 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1690 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1691 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1692 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1693 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1694 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1697 ((InternalFreq - state->config->if_khz) * (1 << 16)
1700 dprintk("DEROT temp=0x%x\n", temp);
1701 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1702 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1704 ter_state->echo_pos = 0;
1705 ter_state->ucblocks = 0; /* liplianin */
1706 ter_state->pBER = 0; /* liplianin */
1707 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1709 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1712 ter_state->state = FE_TER_LOCKOK;
1714 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1715 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1717 ter_state->first_lock = 1; /* we know sense now :) */
1719 ter_state->agc_val =
1720 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1721 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1722 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1723 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1725 /* Carrier offset calculation */
1726 stv0367_writebits(state, F367TER_FREEZE, 1);
1727 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1728 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1729 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1730 stv0367_writebits(state, F367TER_FREEZE, 0);
1731 if (offset > 8388607)
1734 offset = offset * 2 / 16384;
1736 if (ter_state->mode == FE_TER_MODE_2K)
1737 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1738 else if (ter_state->mode == FE_TER_MODE_4K)
1739 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1740 else if (ter_state->mode == FE_TER_MODE_8K)
1741 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1743 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1744 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1745 (stv0367_readbits(state,
1746 F367TER_STATUS_INV_SPECRUM) == 1)))
1747 offset = offset * -1;
1750 if (ter_state->bw == 6)
1751 offset = (offset * 6) / 8;
1752 else if (ter_state->bw == 7)
1753 offset = (offset * 7) / 8;
1755 ter_state->frequency += offset;
1757 tempo = 10; /* exit even if timing_offset stays null */
1758 while ((timing_offset == 0) && (tempo > 0)) {
1759 usleep_range(10000, 20000); /*was 20ms */
1760 /* fine tuning of timing offset if required */
1761 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1762 + 256 * stv0367_readbits(state,
1763 F367TER_TRL_TOFFSET_HI);
1764 if (timing_offset >= 32768)
1765 timing_offset -= 65536;
1766 trl_nomrate = (512 * stv0367_readbits(state,
1767 F367TER_TRL_NOMRATE_HI)
1768 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1769 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1771 timing_offset = ((signed)(1000000 / trl_nomrate) *
1772 timing_offset) / 2048;
1776 if (timing_offset <= 0) {
1777 timing_offset = (timing_offset - 11) / 22;
1780 timing_offset = (timing_offset + 11) / 22;
1784 for (counter = 0; counter < abs(timing_offset); counter++) {
1785 trl_nomrate += step;
1786 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1788 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1790 usleep_range(1000, 2000);
1793 usleep_range(5000, 6000);
1794 /* unlocks could happen in case of trl centring big step,
1795 then a core off/on restarts demod */
1796 u_var = stv0367_readbits(state, F367TER_LK);
1799 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1801 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1807 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1809 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1810 struct stv0367_state *state = fe->demodulator_priv;
1811 struct stv0367ter_state *ter_state = state->ter_state;
1814 s8 num_trials, index;
1815 u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1817 stv0367ter_init(fe);
1819 if (fe->ops.tuner_ops.set_params) {
1820 if (fe->ops.i2c_gate_ctrl)
1821 fe->ops.i2c_gate_ctrl(fe, 1);
1822 fe->ops.tuner_ops.set_params(fe);
1823 if (fe->ops.i2c_gate_ctrl)
1824 fe->ops.i2c_gate_ctrl(fe, 0);
1827 switch (p->transmission_mode) {
1829 case TRANSMISSION_MODE_AUTO:
1830 case TRANSMISSION_MODE_2K:
1831 ter_state->mode = FE_TER_MODE_2K;
1833 /* case TRANSMISSION_MODE_4K:
1834 pLook.mode = FE_TER_MODE_4K;
1836 case TRANSMISSION_MODE_8K:
1837 ter_state->mode = FE_TER_MODE_8K;
1841 switch (p->guard_interval) {
1843 case GUARD_INTERVAL_1_32:
1844 case GUARD_INTERVAL_1_16:
1845 case GUARD_INTERVAL_1_8:
1846 case GUARD_INTERVAL_1_4:
1847 ter_state->guard = p->guard_interval;
1849 case GUARD_INTERVAL_AUTO:
1850 ter_state->guard = GUARD_INTERVAL_1_32;
1854 switch (p->bandwidth_hz) {
1856 ter_state->bw = FE_TER_CHAN_BW_6M;
1859 ter_state->bw = FE_TER_CHAN_BW_7M;
1863 ter_state->bw = FE_TER_CHAN_BW_8M;
1866 ter_state->hierarchy = FE_TER_HIER_NONE;
1868 switch (p->inversion) {
1875 if (ter_state->first_lock)
1880 ter_state->state = FE_TER_NOLOCK;
1883 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1884 if (!ter_state->first_lock) {
1885 if (p->inversion == INVERSION_AUTO)
1886 ter_state->sense = SenseTrials[index];
1889 stv0367ter_algo(fe);
1891 if ((ter_state->state == FE_TER_LOCKOK) &&
1892 (p->inversion == INVERSION_AUTO) &&
1894 /* invert spectrum sense */
1895 SenseTrials[index] = SenseTrials[0];
1896 SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1905 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1907 struct stv0367_state *state = fe->demodulator_priv;
1908 struct stv0367ter_state *ter_state = state->ter_state;
1911 /*wait for counting completion*/
1912 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1914 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1916 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1918 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1919 ter_state->ucblocks = errs;
1922 (*ucblocks) = ter_state->ucblocks;
1927 static int stv0367ter_get_frontend(struct dvb_frontend *fe)
1929 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1930 struct stv0367_state *state = fe->demodulator_priv;
1931 struct stv0367ter_state *ter_state = state->ter_state;
1934 enum stv0367_ter_mode mode;
1935 int constell = 0,/* snr = 0,*/ Data = 0;
1937 p->frequency = stv0367_get_tuner_freq(fe);
1938 if ((int)p->frequency < 0)
1939 p->frequency = -p->frequency;
1941 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1943 p->modulation = QPSK;
1944 else if (constell == 1)
1945 p->modulation = QAM_16;
1947 p->modulation = QAM_64;
1949 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1951 /* Get the Hierarchical mode */
1952 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1956 p->hierarchy = HIERARCHY_NONE;
1959 p->hierarchy = HIERARCHY_1;
1962 p->hierarchy = HIERARCHY_2;
1965 p->hierarchy = HIERARCHY_4;
1968 p->hierarchy = HIERARCHY_AUTO;
1972 /* Get the FEC Rate */
1973 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1974 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1976 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1980 p->code_rate_HP = FEC_1_2;
1983 p->code_rate_HP = FEC_2_3;
1986 p->code_rate_HP = FEC_3_4;
1989 p->code_rate_HP = FEC_5_6;
1992 p->code_rate_HP = FEC_7_8;
1995 p->code_rate_HP = FEC_AUTO;
1999 mode = stv0367_readbits(state, F367TER_SYR_MODE);
2002 case FE_TER_MODE_2K:
2003 p->transmission_mode = TRANSMISSION_MODE_2K;
2005 /* case FE_TER_MODE_4K:
2006 p->transmission_mode = TRANSMISSION_MODE_4K;
2008 case FE_TER_MODE_8K:
2009 p->transmission_mode = TRANSMISSION_MODE_8K;
2012 p->transmission_mode = TRANSMISSION_MODE_AUTO;
2015 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2020 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
2022 struct stv0367_state *state = fe->demodulator_priv;
2025 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
2028 usleep_range(2000, 3000);
2029 if (cut == 0x50) /*cut 1.0 cut 1.1*/
2030 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
2032 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
2037 snru32 /= 10;/*average on 10 values*/
2039 *snr = snru32 / 1000;
2045 static int stv0367ter_status(struct dvb_frontend *fe)
2048 struct stv0367_state *state = fe->demodulator_priv;
2049 struct stv0367ter_state *ter_state = state->ter_state;
2052 locked = (stv0367_readbits(state, F367TER_LK));
2054 ter_state->unlock_counter += 1;
2056 ter_state->unlock_counter = 0;
2058 if (ter_state->unlock_counter > 2) {
2059 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2060 (!stv0367_readbits(state, F367TER_LK))) {
2061 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2062 usleep_range(2000, 3000);
2063 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2065 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2066 (stv0367_readbits(state, F367TER_LK));
2074 static int stv0367ter_read_status(struct dvb_frontend *fe, fe_status_t *status)
2076 struct stv0367_state *state = fe->demodulator_priv;
2078 dprintk("%s:\n", __func__);
2082 if (stv0367_readbits(state, F367TER_LK)) {
2083 *status |= FE_HAS_LOCK;
2084 dprintk("%s: stv0367 has locked\n", __func__);
2090 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
2092 struct stv0367_state *state = fe->demodulator_priv;
2093 struct stv0367ter_state *ter_state = state->ter_state;
2094 u32 Errors = 0, tber = 0, temporary = 0;
2095 int abc = 0, def = 0;
2098 /*wait for counting completion*/
2099 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
2100 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
2102 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
2104 + ((u32)stv0367_readbits(state,
2105 F367TER_SFEC_ERR_CNT_LO));
2106 /*measurement not completed, load previous value*/
2108 tber = ter_state->pBER;
2112 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
2113 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
2117 } else if (abc == 0x7) {
2119 temporary = (Errors * 1000000000) / (8 * (1 << 14));
2120 temporary = temporary;
2121 } else if (Errors <= 42) {
2122 temporary = (Errors * 100000000) / (8 * (1 << 14));
2123 temporary = temporary * 10;
2124 } else if (Errors <= 429) {
2125 temporary = (Errors * 10000000) / (8 * (1 << 14));
2126 temporary = temporary * 100;
2127 } else if (Errors <= 4294) {
2128 temporary = (Errors * 1000000) / (8 * (1 << 14));
2129 temporary = temporary * 1000;
2130 } else if (Errors <= 42949) {
2131 temporary = (Errors * 100000) / (8 * (1 << 14));
2132 temporary = temporary * 10000;
2133 } else if (Errors <= 429496) {
2134 temporary = (Errors * 10000) / (8 * (1 << 14));
2135 temporary = temporary * 100000;
2136 } else { /*if (Errors<4294967) 2^22 max error*/
2137 temporary = (Errors * 1000) / (8 * (1 << 14));
2138 temporary = temporary * 100000; /* still to *10 */
2143 /*tber=Errors/(8*(1 <<14));*/
2146 /*tber=Errors/(8*(1 <<16));*/
2147 tber = temporary / 4;
2149 /*tber=Errors/(8*(1 <<18));*/
2150 tber = temporary / 16;
2152 /*tber=Errors/(8*(1 <<20));*/
2153 tber = temporary / 64;
2155 /*tber=Errors/(8*(1 <<22));*/
2156 tber = temporary / 256;
2158 /* should not pass here*/
2161 if ((Errors < 4294967) && (Errors > 429496))
2166 /* save actual value */
2167 ter_state->pBER = tber;
2174 static u32 stv0367ter_get_per(struct stv0367_state *state)
2176 struct stv0367ter_state *ter_state = state->ter_state;
2177 u32 Errors = 0, Per = 0, temporary = 0;
2178 int abc = 0, def = 0, cpt = 0;
2180 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2181 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
2182 usleep_range(1000, 2000);
2183 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2185 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2187 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2190 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2191 def = stv0367_readbits(state, F367TER_NUM_EVT1);
2195 else if (abc == 0x9) {
2197 temporary = (Errors * 1000000000) / (8 * (1 << 8));
2198 temporary = temporary;
2199 } else if (Errors <= 42) {
2200 temporary = (Errors * 100000000) / (8 * (1 << 8));
2201 temporary = temporary * 10;
2202 } else if (Errors <= 429) {
2203 temporary = (Errors * 10000000) / (8 * (1 << 8));
2204 temporary = temporary * 100;
2205 } else if (Errors <= 4294) {
2206 temporary = (Errors * 1000000) / (8 * (1 << 8));
2207 temporary = temporary * 1000;
2208 } else if (Errors <= 42949) {
2209 temporary = (Errors * 100000) / (8 * (1 << 8));
2210 temporary = temporary * 10000;
2211 } else { /*if(Errors<=429496) 2^16 errors max*/
2212 temporary = (Errors * 10000) / (8 * (1 << 8));
2213 temporary = temporary * 100000;
2218 /*Per=Errors/(1 << 8);*/
2221 /*Per=Errors/(1 << 10);*/
2222 Per = temporary / 4;
2224 /*Per=Errors/(1 << 12);*/
2225 Per = temporary / 16;
2227 /*Per=Errors/(1 << 14);*/
2228 Per = temporary / 64;
2230 /*Per=Errors/(1 << 16);*/
2231 Per = temporary / 256;
2236 /* save actual value */
2237 ter_state->pPER = Per;
2242 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
2243 struct dvb_frontend_tune_settings
2246 fe_tune_settings->min_delay_ms = 1000;
2247 fe_tune_settings->step_size = 0;
2248 fe_tune_settings->max_drift = 0;
2253 static void stv0367_release(struct dvb_frontend *fe)
2255 struct stv0367_state *state = fe->demodulator_priv;
2257 kfree(state->ter_state);
2258 kfree(state->cab_state);
2262 static struct dvb_frontend_ops stv0367ter_ops = {
2263 .delsys = { SYS_DVBT },
2265 .name = "ST STV0367 DVB-T",
2266 .frequency_min = 47000000,
2267 .frequency_max = 862000000,
2268 .frequency_stepsize = 15625,
2269 .frequency_tolerance = 0,
2270 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2271 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2273 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2274 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
2275 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
2276 FE_CAN_INVERSION_AUTO |
2279 .release = stv0367_release,
2280 .init = stv0367ter_init,
2281 .sleep = stv0367ter_sleep,
2282 .i2c_gate_ctrl = stv0367ter_gate_ctrl,
2283 .set_frontend = stv0367ter_set_frontend,
2284 .get_frontend = stv0367ter_get_frontend,
2285 .get_tune_settings = stv0367_get_tune_settings,
2286 .read_status = stv0367ter_read_status,
2287 .read_ber = stv0367ter_read_ber,/* too slow */
2288 /* .read_signal_strength = stv0367_read_signal_strength,*/
2289 .read_snr = stv0367ter_read_snr,
2290 .read_ucblocks = stv0367ter_read_ucblocks,
2293 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
2294 struct i2c_adapter *i2c)
2296 struct stv0367_state *state = NULL;
2297 struct stv0367ter_state *ter_state = NULL;
2299 /* allocate memory for the internal state */
2300 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2303 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
2304 if (ter_state == NULL)
2307 /* setup the state */
2309 state->config = config;
2310 state->ter_state = ter_state;
2311 state->fe.ops = stv0367ter_ops;
2312 state->fe.demodulator_priv = state;
2313 state->chip_id = stv0367_readreg(state, 0xf000);
2315 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2317 /* check if the demod is there */
2318 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2328 EXPORT_SYMBOL(stv0367ter_attach);
2330 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
2332 struct stv0367_state *state = fe->demodulator_priv;
2334 dprintk("%s:\n", __func__);
2336 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
2341 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
2343 struct stv0367_state *state = fe->demodulator_priv;
2344 u32 mclk_Hz = 0;/* master clock frequency (Hz) */
2348 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
2349 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
2353 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
2357 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
2362 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
2363 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
2366 mclk_Hz = ExtClk_Hz;
2368 dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
2373 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
2375 u32 ADCClk_Hz = ExtClk_Hz;
2377 ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
2382 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
2384 enum stv0367cab_mod QAMSize)
2387 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
2389 /* Set Registers settings specific to the QAM size */
2391 case FE_CAB_MOD_QAM4:
2392 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2394 case FE_CAB_MOD_QAM16:
2395 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
2396 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2397 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2398 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2399 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2400 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2401 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2402 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
2404 case FE_CAB_MOD_QAM32:
2405 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2406 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
2407 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2408 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2409 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
2410 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
2411 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2412 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2414 case FE_CAB_MOD_QAM64:
2415 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
2416 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2417 if (SymbolRate > 45000000) {
2418 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2419 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2420 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
2421 } else if (SymbolRate > 25000000) {
2422 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2423 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2424 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2426 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2427 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2428 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2430 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2431 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2432 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
2434 case FE_CAB_MOD_QAM128:
2435 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2436 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
2437 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2438 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
2439 if (SymbolRate > 45000000)
2440 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2441 else if (SymbolRate > 25000000)
2442 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2444 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
2446 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
2447 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2448 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2450 case FE_CAB_MOD_QAM256:
2451 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
2452 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2453 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2454 if (SymbolRate > 45000000)
2455 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2456 else if (SymbolRate > 25000000)
2457 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2459 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2461 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2462 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
2463 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2464 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2466 case FE_CAB_MOD_QAM512:
2467 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2469 case FE_CAB_MOD_QAM1024:
2470 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2479 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
2480 u32 adc_hz, s32 derot_hz)
2485 adc_khz = adc_hz / 1000;
2487 dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
2490 if (derot_hz < 1000000)
2491 derot_hz = adc_hz / 4; /* ZIF operation */
2492 if (derot_hz > adc_hz)
2493 derot_hz = derot_hz - adc_hz;
2494 sampled_if = (u32)derot_hz / 1000;
2495 sampled_if *= 32768;
2496 sampled_if /= adc_khz;
2500 if (sampled_if > 8388607)
2501 sampled_if = 8388607;
2503 dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
2505 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
2506 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
2507 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
2512 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
2516 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
2517 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
2518 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
2521 sampled_if *= (adc_hz / 1000);
2523 sampled_if /= 32768;
2528 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
2529 u32 mclk_hz, u32 SymbolRate,
2530 enum stv0367cab_mod QAMSize)
2532 u32 QamSizeCorr = 0;
2533 u32 u32_tmp = 0, u32_tmp1 = 0;
2536 dprintk("%s:\n", __func__);
2538 /* Set Correction factor of SRC gain */
2540 case FE_CAB_MOD_QAM4:
2543 case FE_CAB_MOD_QAM16:
2546 case FE_CAB_MOD_QAM32:
2549 case FE_CAB_MOD_QAM64:
2552 case FE_CAB_MOD_QAM128:
2555 case FE_CAB_MOD_QAM256:
2558 case FE_CAB_MOD_QAM512:
2561 case FE_CAB_MOD_QAM1024:
2568 /* Transfer ratio calculation */
2570 u32_tmp = 256 * SymbolRate;
2571 u32_tmp = u32_tmp / adc_hz;
2573 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2575 /* Symbol rate and SRC gain calculation */
2576 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2578 u32_tmp = SymbolRate;
2579 u32_tmp1 = SymbolRate;
2581 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2582 /* Symbol rate calculation */
2583 u32_tmp *= 2048; /* 2048 = 2^11 */
2584 u32_tmp = u32_tmp / adp_khz;
2585 u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2586 u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2587 u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2589 /* SRC Gain Calculation */
2590 u32_tmp1 *= 2048; /* *2*2^10 */
2591 u32_tmp1 /= 439; /* *2/878 */
2592 u32_tmp1 *= 256; /* *2^8 */
2593 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2594 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2595 u32_tmp1 = u32_tmp1 / 10000000;
2597 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2598 /* Symbol rate calculation */
2599 u32_tmp *= 1024 ; /* 1024 = 2**10 */
2600 u32_tmp = u32_tmp / adp_khz;
2601 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2602 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2603 u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2605 /* SRC Gain Calculation */
2606 u32_tmp1 *= 1024; /* *2*2^9 */
2607 u32_tmp1 /= 439; /* *2/878 */
2608 u32_tmp1 *= 256; /* *2^8 */
2609 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2610 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2611 u32_tmp1 = u32_tmp1 / 5000000;
2612 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2613 /* Symbol rate calculation */
2614 u32_tmp *= 512 ; /* 512 = 2**9 */
2615 u32_tmp = u32_tmp / adp_khz;
2616 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2617 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2618 u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2620 /* SRC Gain Calculation */
2621 u32_tmp1 *= 512; /* *2*2^8 */
2622 u32_tmp1 /= 439; /* *2/878 */
2623 u32_tmp1 *= 256; /* *2^8 */
2624 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2625 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2626 u32_tmp1 = u32_tmp1 / 2500000;
2628 /* Symbol rate calculation */
2629 u32_tmp *= 256 ; /* 256 = 2**8 */
2630 u32_tmp = u32_tmp / adp_khz;
2631 u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2632 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2633 u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2635 /* SRC Gain Calculation */
2636 u32_tmp1 *= 256; /* 2*2^7 */
2637 u32_tmp1 /= 439; /* *2/878 */
2638 u32_tmp1 *= 256; /* *2^8 */
2639 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2640 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2641 u32_tmp1 = u32_tmp1 / 1250000;
2645 /* Filters' coefficients are calculated and written
2646 into registers only if the filters are enabled */
2647 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2648 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2650 /* AllPass filter must be enabled
2651 when the adjacents filter is used */
2652 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2653 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2655 /* AllPass filter must be disabled
2656 when the adjacents filter is not used */
2658 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2660 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2661 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2662 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2663 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2665 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2666 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2671 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2676 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2677 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2678 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2679 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2681 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2683 if (regsym < 134217728) { /* 134217728L = 2**27*/
2684 regsym = regsym * 32; /* 32 = 2**5 */
2685 regsym = regsym / 32768; /* 32768L = 2**15 */
2686 regsym = adp_khz * regsym; /* AdpClk in kHz */
2687 regsym = regsym / 128; /* 128 = 2**7 */
2688 regsym *= 125 ; /* 125 = 1000/2**3 */
2689 regsym /= 2048 ; /* 2048 = 2**11 */
2690 } else if (regsym < 268435456) { /* 268435456L = 2**28 */
2691 regsym = regsym * 16; /* 16 = 2**4 */
2692 regsym = regsym / 32768; /* 32768L = 2**15 */
2693 regsym = adp_khz * regsym; /* AdpClk in kHz */
2694 regsym = regsym / 128; /* 128 = 2**7 */
2695 regsym *= 125 ; /* 125 = 1000/2**3*/
2696 regsym /= 1024 ; /* 256 = 2**10*/
2697 } else if (regsym < 536870912) { /* 536870912L = 2**29*/
2698 regsym = regsym * 8; /* 8 = 2**3 */
2699 regsym = regsym / 32768; /* 32768L = 2**15 */
2700 regsym = adp_khz * regsym; /* AdpClk in kHz */
2701 regsym = regsym / 128; /* 128 = 2**7 */
2702 regsym *= 125 ; /* 125 = 1000/2**3 */
2703 regsym /= 512 ; /* 128 = 2**9 */
2705 regsym = regsym * 4; /* 4 = 2**2 */
2706 regsym = regsym / 32768; /* 32768L = 2**15 */
2707 regsym = adp_khz * regsym; /* AdpClk in kHz */
2708 regsym = regsym / 128; /* 128 = 2**7 */
2709 regsym *= 125 ; /* 125 = 1000/2**3 */
2710 regsym /= 256 ; /* 64 = 2**8 */
2716 static int stv0367cab_read_status(struct dvb_frontend *fe, fe_status_t *status)
2718 struct stv0367_state *state = fe->demodulator_priv;
2720 dprintk("%s:\n", __func__);
2724 if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
2725 *status |= FE_HAS_LOCK;
2726 dprintk("%s: stv0367 has locked\n", __func__);
2732 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2734 struct stv0367_state *state = fe->demodulator_priv;
2736 dprintk("%s:\n", __func__);
2739 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2740 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2741 stv0367_writebits(state, F367CAB_STDBY, 1);
2742 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2743 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2744 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2745 stv0367_writebits(state, F367CAB_POFFQ, 1);
2746 stv0367_writebits(state, F367CAB_POFFI, 1);
2748 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2749 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2750 stv0367_writebits(state, F367CAB_STDBY, 0);
2751 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2752 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2753 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2754 stv0367_writebits(state, F367CAB_POFFQ, 0);
2755 stv0367_writebits(state, F367CAB_POFFI, 0);
2761 static int stv0367cab_sleep(struct dvb_frontend *fe)
2763 return stv0367cab_standby(fe, 1);
2766 static int stv0367cab_init(struct dvb_frontend *fe)
2768 struct stv0367_state *state = fe->demodulator_priv;
2769 struct stv0367cab_state *cab_state = state->cab_state;
2772 dprintk("%s:\n", __func__);
2774 for (i = 0; i < STV0367CAB_NBREGS; i++)
2775 stv0367_writereg(state, def0367cab[i].addr,
2776 def0367cab[i].value);
2778 switch (state->config->ts_mode) {
2779 case STV0367_DVBCI_CLOCK:
2780 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2781 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2783 case STV0367_SERIAL_PUNCT_CLOCK:
2784 case STV0367_SERIAL_CONT_CLOCK:
2785 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2787 case STV0367_PARALLEL_PUNCT_CLOCK:
2788 case STV0367_OUTPUTMODE_DEFAULT:
2789 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2793 switch (state->config->clk_pol) {
2794 case STV0367_RISINGEDGE_CLOCK:
2795 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2797 case STV0367_FALLINGEDGE_CLOCK:
2798 case STV0367_CLOCKPOLARITY_DEFAULT:
2799 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2803 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2805 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2807 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2809 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2811 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2813 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2814 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2819 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2820 struct dtv_frontend_properties *p)
2822 struct stv0367cab_state *cab_state = state->cab_state;
2823 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2824 u32 QAMFEC_Lock, QAM_Lock, u32_tmp,
2825 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2826 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2830 dprintk("%s:\n", __func__);
2832 /* Timeouts calculation */
2833 /* A max lock time of 25 ms is allowed for delayed AGC */
2835 /* 100000 symbols needed by the TRL as a maximum value */
2836 TRLTimeOut = 100000000 / p->symbol_rate;
2837 /* CRLSymbols is the needed number of symbols to achieve a lock
2838 within [-4%, +4%] of the symbol rate.
2839 CRL timeout is calculated
2840 for a lock within [-search_range, +search_range].
2841 EQL timeout can be changed depending on
2842 the micro-reflections we want to handle.
2843 A characterization must be performed
2844 with these echoes to get new timeout values.
2846 switch (p->modulation) {
2848 CRLSymbols = 150000;
2852 CRLSymbols = 250000;
2856 CRLSymbols = 200000;
2860 CRLSymbols = 250000;
2864 CRLSymbols = 250000;
2868 CRLSymbols = 200000;
2873 if (pIntParams->search_range < 0) {
2874 CRLTimeOut = (25 * CRLSymbols *
2875 (-pIntParams->search_range / 1000)) /
2876 (pIntParams->symbol_rate / 1000);
2879 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2880 (p->symbol_rate / 1000);
2882 CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2883 /* Timeouts below 50ms are coerced */
2884 if (CRLTimeOut < 50)
2886 /* A maximum of 100 TS packets is needed to get FEC lock even in case
2887 the spectrum inversion needs to be changed.
2888 This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2891 DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2893 dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2895 /* Reset the TRL to ensure nothing starts until the
2896 AGC is stable which ensures a better lock time
2898 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2899 /* Set AGC accumulation time to minimum and lock threshold to maximum
2900 in order to speed up the AGC lock */
2901 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2902 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2903 /* Modulus Mapper is disabled */
2904 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2905 /* Disable the sweep function */
2906 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2907 /* The sweep function is never used, Sweep rate must be set to 0 */
2908 /* Set the derotator frequency in Hz */
2909 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2910 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2911 /* Disable the Allpass Filter when the symbol rate is out of range */
2912 if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2913 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2914 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2917 /* Check if the tuner is locked */
2918 tuner_lock = stv0367cab_tuner_get_status(fe);
2919 if (tuner_lock == 0)
2920 return FE_367CAB_NOTUNER;
2922 /* Relase the TRL to start demodulator acquisition */
2923 /* Wait for QAM lock */
2925 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2927 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2928 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2931 * We don't wait longer, the frequency/phase offset
2934 LockTime = DemodTimeOut;
2935 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2938 * We don't wait longer, either there is no signal or
2939 * it is not the right symbol rate or it is an analog
2943 LockTime = DemodTimeOut;
2944 u32_tmp = stv0367_readbits(state,
2945 F367CAB_AGC_PWR_WORD_LO) +
2946 (stv0367_readbits(state,
2947 F367CAB_AGC_PWR_WORD_ME) << 8) +
2948 (stv0367_readbits(state,
2949 F367CAB_AGC_PWR_WORD_HI) << 16);
2950 if (u32_tmp >= 131072)
2951 u32_tmp = 262144 - u32_tmp;
2952 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2953 F367CAB_AGC_IF_BWSEL)));
2955 if (u32_tmp < stv0367_readbits(state,
2956 F367CAB_AGC_PWRREF_LO) +
2957 256 * stv0367_readbits(state,
2958 F367CAB_AGC_PWRREF_HI) - 10)
2961 usleep_range(10000, 20000);
2964 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2965 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2967 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2969 } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2970 (LockTime < DemodTimeOut));
2972 dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2974 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2975 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2976 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2977 dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2979 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2980 dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2982 if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2983 /* Wait for FEC lock */
2986 usleep_range(5000, 7000);
2988 QAMFEC_Lock = stv0367_readbits(state,
2989 F367CAB_QAMFEC_LOCK);
2990 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2995 signalType = FE_CAB_DATAOK;
2996 cab_state->modulation = p->modulation;
2997 cab_state->spect_inv = stv0367_readbits(state,
3000 /* not clear for me */
3001 if (state->config->if_khz != 0) {
3002 if (state->config->if_khz > cab_state->adc_clk / 1000) {
3003 cab_state->freq_khz =
3004 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3005 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3006 - cab_state->adc_clk / 1000 + state->config->if_khz;
3008 cab_state->freq_khz =
3009 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3010 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3011 + state->config->if_khz;
3014 cab_state->freq_khz =
3015 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
3016 stv0367cab_get_derot_freq(state,
3017 cab_state->adc_clk) -
3018 cab_state->adc_clk / 4000;
3021 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
3023 cab_state->locked = 1;
3025 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
3029 signalType = FE_CAB_NOAGC;
3032 signalType = FE_CAB_NOTIMING;
3035 signalType = FE_CAB_TIMINGOK;
3038 signalType = FE_CAB_NOCARRIER;
3041 signalType = FE_CAB_CARRIEROK;
3044 signalType = FE_CAB_NOBLIND;
3047 signalType = FE_CAB_BLINDOK;
3050 signalType = FE_CAB_NODEMOD;
3053 signalType = FE_CAB_DEMODOK;
3056 signalType = FE_CAB_DEMODOK;
3059 signalType = FE_CAB_NODEMOD;
3062 signalType = FE_CAB_NOBLIND;
3065 signalType = FE_CAB_NOSIGNAL;
3073 /* Set the AGC control values to tracking values */
3074 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
3078 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
3080 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3081 struct stv0367_state *state = fe->demodulator_priv;
3082 struct stv0367cab_state *cab_state = state->cab_state;
3083 enum stv0367cab_mod QAMSize = 0;
3085 dprintk("%s: freq = %d, srate = %d\n", __func__,
3086 p->frequency, p->symbol_rate);
3088 cab_state->derot_offset = 0;
3090 switch (p->modulation) {
3092 QAMSize = FE_CAB_MOD_QAM16;
3095 QAMSize = FE_CAB_MOD_QAM32;
3098 QAMSize = FE_CAB_MOD_QAM64;
3101 QAMSize = FE_CAB_MOD_QAM128;
3104 QAMSize = FE_CAB_MOD_QAM256;
3110 stv0367cab_init(fe);
3112 /* Tuner Frequency Setting */
3113 if (fe->ops.tuner_ops.set_params) {
3114 if (fe->ops.i2c_gate_ctrl)
3115 fe->ops.i2c_gate_ctrl(fe, 1);
3116 fe->ops.tuner_ops.set_params(fe);
3117 if (fe->ops.i2c_gate_ctrl)
3118 fe->ops.i2c_gate_ctrl(fe, 0);
3121 stv0367cab_SetQamSize(
3126 stv0367cab_set_srate(state,
3131 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3132 cab_state->state = stv0367cab_algo(state, p);
3136 static int stv0367cab_get_frontend(struct dvb_frontend *fe)
3138 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3139 struct stv0367_state *state = fe->demodulator_priv;
3140 struct stv0367cab_state *cab_state = state->cab_state;
3142 enum stv0367cab_mod QAMSize;
3144 dprintk("%s:\n", __func__);
3146 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3148 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3150 case FE_CAB_MOD_QAM16:
3151 p->modulation = QAM_16;
3153 case FE_CAB_MOD_QAM32:
3154 p->modulation = QAM_32;
3156 case FE_CAB_MOD_QAM64:
3157 p->modulation = QAM_64;
3159 case FE_CAB_MOD_QAM128:
3160 p->modulation = QAM_128;
3163 p->modulation = QAM_256;
3169 p->frequency = stv0367_get_tuner_freq(fe);
3171 dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
3173 if (state->config->if_khz == 0) {
3175 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3176 cab_state->adc_clk / 4000);
3180 if (state->config->if_khz > cab_state->adc_clk / 1000)
3181 p->frequency += (state->config->if_khz
3182 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3183 - cab_state->adc_clk / 1000);
3185 p->frequency += (state->config->if_khz
3186 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3192 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3193 u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
3195 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3196 stv0367cab_GetPacketsCount(state, Monitor_results);
3201 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
3203 struct stv0367_state *state = fe->demodulator_priv;
3208 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
3211 s32 RfAgcPwm = 0, IfAgcPwm = 0;
3214 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
3217 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
3218 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
3219 RfAgcPwm = 100 * RfAgcPwm / 1023;
3222 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
3223 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
3224 if (IfAgcPwm >= 2048)
3229 IfAgcPwm = 100 * IfAgcPwm / 4095;
3231 /* For DTT75467 on NIM */
3232 if (RfAgcPwm < 90 && IfAgcPwm < 28) {
3233 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
3234 if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
3235 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
3239 if (i == RF_LOOKUP_TABLE_SIZE)
3241 } else { /*if IF AGC>10*/
3242 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
3243 if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
3244 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
3248 if (i == RF_LOOKUP_TABLE2_SIZE)
3254 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
3256 struct stv0367_state *state = fe->demodulator_priv;
3258 s32 signal = stv0367cab_get_rf_lvl(state);
3260 dprintk("%s: signal=%d dBm\n", __func__, signal);
3265 *strength = (22 + signal) * (-1311);
3267 dprintk("%s: strength=%d\n", __func__, (*strength));
3272 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
3274 struct stv0367_state *state = fe->demodulator_priv;
3275 u32 noisepercentage;
3276 enum stv0367cab_mod QAMSize;
3277 u32 regval = 0, temp = 0;
3280 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3282 case FE_CAB_MOD_QAM4:
3285 case FE_CAB_MOD_QAM16:
3288 case FE_CAB_MOD_QAM32:
3291 case FE_CAB_MOD_QAM64:
3294 case FE_CAB_MOD_QAM128:
3297 case FE_CAB_MOD_QAM256:
3300 case FE_CAB_MOD_QAM512:
3303 case FE_CAB_MOD_QAM1024:
3311 for (i = 0; i < 10; i++) {
3312 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
3313 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
3316 regval /= 10; /*for average over 10 times in for loop above*/
3319 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
3323 /* table values, not needed to calculate logarithms */
3325 noisepercentage = 100;
3326 else if (temp >= 3981)
3327 noisepercentage = 93;
3328 else if (temp >= 3162)
3329 noisepercentage = 86;
3330 else if (temp >= 2512)
3331 noisepercentage = 79;
3332 else if (temp >= 1995)
3333 noisepercentage = 72;
3334 else if (temp >= 1585)
3335 noisepercentage = 65;
3336 else if (temp >= 1259)
3337 noisepercentage = 58;
3338 else if (temp >= 1000)
3339 noisepercentage = 50;
3340 else if (temp >= 794)
3341 noisepercentage = 43;
3342 else if (temp >= 501)
3343 noisepercentage = 36;
3344 else if (temp >= 316)
3345 noisepercentage = 29;
3346 else if (temp >= 200)
3347 noisepercentage = 22;
3348 else if (temp >= 158)
3349 noisepercentage = 14;
3350 else if (temp >= 126)
3351 noisepercentage = 7;
3353 noisepercentage = 0;
3355 dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
3357 *snr = (noisepercentage * 65535) / 100;
3362 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3364 struct stv0367_state *state = fe->demodulator_priv;
3365 int corrected, tscount;
3367 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
3368 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
3369 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
3370 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
3371 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
3372 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
3374 dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
3375 __func__, *ucblocks, corrected, tscount);
3380 static struct dvb_frontend_ops stv0367cab_ops = {
3381 .delsys = { SYS_DVBC_ANNEX_A },
3383 .name = "ST STV0367 DVB-C",
3384 .frequency_min = 47000000,
3385 .frequency_max = 862000000,
3386 .frequency_stepsize = 62500,
3387 .symbol_rate_min = 870000,
3388 .symbol_rate_max = 11700000,
3389 .caps = 0x400 |/* FE_CAN_QAM_4 */
3390 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
3391 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3392 FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
3394 .release = stv0367_release,
3395 .init = stv0367cab_init,
3396 .sleep = stv0367cab_sleep,
3397 .i2c_gate_ctrl = stv0367cab_gate_ctrl,
3398 .set_frontend = stv0367cab_set_frontend,
3399 .get_frontend = stv0367cab_get_frontend,
3400 .read_status = stv0367cab_read_status,
3401 /* .read_ber = stv0367cab_read_ber, */
3402 .read_signal_strength = stv0367cab_read_strength,
3403 .read_snr = stv0367cab_read_snr,
3404 .read_ucblocks = stv0367cab_read_ucblcks,
3405 .get_tune_settings = stv0367_get_tune_settings,
3408 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
3409 struct i2c_adapter *i2c)
3411 struct stv0367_state *state = NULL;
3412 struct stv0367cab_state *cab_state = NULL;
3414 /* allocate memory for the internal state */
3415 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3418 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3419 if (cab_state == NULL)
3422 /* setup the state */
3424 state->config = config;
3425 cab_state->search_range = 280000;
3426 state->cab_state = cab_state;
3427 state->fe.ops = stv0367cab_ops;
3428 state->fe.demodulator_priv = state;
3429 state->chip_id = stv0367_readreg(state, 0xf000);
3431 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3433 /* check if the demod is there */
3434 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3444 EXPORT_SYMBOL(stv0367cab_attach);
3446 MODULE_PARM_DESC(debug, "Set debug");
3447 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3449 MODULE_AUTHOR("Igor M. Liplianin");
3450 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3451 MODULE_LICENSE("GPL");