drivers/media/dvb-frontends/stv0367.c

   1 /*
   2  * stv0367.c
   3  *
   4  * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
   5  *
   6  * Copyright (C) ST Microelectronics.
   7  * Copyright (C) 2010,2011 NetUP Inc.
   8  * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/string.h>
  25 #include <linux/slab.h>
  26 #include <linux/i2c.h>
  27
  28 #include "stv0367.h"
  29 #include "stv0367_defs.h"
  30 #include "stv0367_regs.h"
  31 #include "stv0367_priv.h"
  32
  33 /* Max transfer size done by I2C transfer functions */
  34 #define MAX_XFER_SIZE  64
  35
  36 static int stvdebug;
  37 module_param_named(debug, stvdebug, int, 0644);
  38
  39 static int i2cdebug;
  40 module_param_named(i2c_debug, i2cdebug, int, 0644);
  41
  42 #define dprintk(args...) \
  43         do { \
  44                 if (stvdebug) \
  45                         printk(KERN_DEBUG args); \
  46         } while (0)
  47         /* DVB-C */
  48
  49 enum active_demod_state { demod_none, demod_ter, demod_cab };
  50
  51 struct stv0367cab_state {
  52         enum stv0367_cab_signal_type    state;
  53         u32     mclk;
  54         u32     adc_clk;
  55         s32     search_range;
  56         s32     derot_offset;
  57         /* results */
  58         int locked;                     /* channel found                */
  59         u32 freq_khz;                   /* found frequency (in kHz)     */
  60         u32 symbol_rate;                /* found symbol rate (in Bds)   */
  61         enum fe_spectral_inversion spect_inv; /* Spectrum Inversion     */
  62         u32 qamfec_status_reg;          /* status reg to poll for FEC Lock */
  63 };
  64
  65 struct stv0367ter_state {
  66         /* DVB-T */
  67         enum stv0367_ter_signal_type state;
  68         enum stv0367_ter_if_iq_mode if_iq_mode;
  69         enum stv0367_ter_mode mode;/* mode 2K or 8K */
  70         enum fe_guard_interval guard;
  71         enum stv0367_ter_hierarchy hierarchy;
  72         u32 frequency;
  73         enum fe_spectral_inversion sense; /*  current search spectrum */
  74         u8  force; /* force mode/guard */
  75         u8  bw; /* channel width 6, 7 or 8 in MHz */
  76         u8  pBW; /* channel width used during previous lock */
  77         u32 pBER;
  78         u32 pPER;
  79         u32 ucblocks;
  80         s8  echo_pos; /* echo position */
  81         u8  first_lock;
  82         u8  unlock_counter;
  83         u32 agc_val;
  84 };
  85
  86 struct stv0367_state {
  87         struct dvb_frontend fe;
  88         struct i2c_adapter *i2c;
  89         /* config settings */
  90         const struct stv0367_config *config;
  91         u8 chip_id;
  92         /* DVB-C */
  93         struct stv0367cab_state *cab_state;
  94         /* DVB-T */
  95         struct stv0367ter_state *ter_state;
  96         /* flags for operation control */
  97         u8 use_i2c_gatectrl;
  98         u8 deftabs;
  99         u8 reinit_on_setfrontend;
 100         u8 auto_if_khz;
 101         enum active_demod_state activedemod;
 102 };
 103
 104 #define RF_LOOKUP_TABLE_SIZE  31
 105 #define RF_LOOKUP_TABLE2_SIZE 16
 106 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
 107 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
 108         {/*AGC1*/
 109                 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
 110                 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
 111                 76, 77, 78, 80, 83, 85, 88,
 112         }, {/*RF(dbm)*/
 113                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 114                 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
 115                 49, 50, 52, 53, 54, 55, 56,
 116         }
 117 };
 118 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
 119 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
 120         {/*AGC2*/
 121                 28, 29, 31, 32, 34, 35, 36, 37,
 122                 38, 39, 40, 41, 42, 43, 44, 45,
 123         }, {/*RF(dbm)*/
 124                 57, 58, 59, 60, 61, 62, 63, 64,
 125                 65, 66, 67, 68, 69, 70, 71, 72,
 126         }
 127 };
 128
 129 static
 130 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
 131 {
 132         u8 buf[MAX_XFER_SIZE];
 133         struct i2c_msg msg = {
 134                 .addr = state->config->demod_address,
 135                 .flags = 0,
 136                 .buf = buf,
 137                 .len = len + 2
 138         };
 139         int ret;
 140
 141         if (2 + len > sizeof(buf)) {
 142                 printk(KERN_WARNING
 143                        "%s: i2c wr reg=%04x: len=%d is too big!\n",
 144                        KBUILD_MODNAME, reg, len);
 145                 return -EINVAL;
 146         }
 147
 148
 149         buf[0] = MSB(reg);
 150         buf[1] = LSB(reg);
 151         memcpy(buf + 2, data, len);
 152
 153         if (i2cdebug)
 154                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 155                         state->config->demod_address, reg, buf[2]);
 156
 157         ret = i2c_transfer(state->i2c, &msg, 1);
 158         if (ret != 1)
 159                 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
 160                         __func__, state->config->demod_address, reg, buf[2]);
 161
 162         return (ret != 1) ? -EREMOTEIO : 0;
 163 }
 164
 165 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
 166 {
 167         return stv0367_writeregs(state, reg, &data, 1);
 168 }
 169
 170 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
 171 {
 172         u8 b0[] = { 0, 0 };
 173         u8 b1[] = { 0 };
 174         struct i2c_msg msg[] = {
 175                 {
 176                         .addr = state->config->demod_address,
 177                         .flags = 0,
 178                         .buf = b0,
 179                         .len = 2
 180                 }, {
 181                         .addr = state->config->demod_address,
 182                         .flags = I2C_M_RD,
 183                         .buf = b1,
 184                         .len = 1
 185                 }
 186         };
 187         int ret;
 188
 189         b0[0] = MSB(reg);
 190         b0[1] = LSB(reg);
 191
 192         ret = i2c_transfer(state->i2c, msg, 2);
 193         if (ret != 2)
 194                 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
 195                         __func__, state->config->demod_address, reg, b1[0]);
 196
 197         if (i2cdebug)
 198                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 199                         state->config->demod_address, reg, b1[0]);
 200
 201         return b1[0];
 202 }
 203
 204 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
 205 {
 206         u8 position = 0, i = 0;
 207
 208         (*mask) = label & 0xff;
 209
 210         while ((position == 0) && (i < 8)) {
 211                 position = ((*mask) >> i) & 0x01;
 212                 i++;
 213         }
 214
 215         (*pos) = (i - 1);
 216 }
 217
 218 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
 219 {
 220         u8 reg, mask, pos;
 221
 222         reg = stv0367_readreg(state, (label >> 16) & 0xffff);
 223         extract_mask_pos(label, &mask, &pos);
 224
 225         val = mask & (val << pos);
 226
 227         reg = (reg & (~mask)) | val;
 228         stv0367_writereg(state, (label >> 16) & 0xffff, reg);
 229
 230 }
 231
 232 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
 233 {
 234         u8 mask, pos;
 235
 236         extract_mask_pos(label, &mask, &pos);
 237
 238         val = mask & (val << pos);
 239
 240         (*reg) = ((*reg) & (~mask)) | val;
 241 }
 242
 243 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
 244 {
 245         u8 val = 0xff;
 246         u8 mask, pos;
 247
 248         extract_mask_pos(label, &mask, &pos);
 249
 250         val = stv0367_readreg(state, label >> 16);
 251         val = (val & mask) >> pos;
 252
 253         return val;
 254 }
 255
 256 #if 0 /* Currently, unused */
 257 static u8 stv0367_getbits(u8 reg, u32 label)
 258 {
 259         u8 mask, pos;
 260
 261         extract_mask_pos(label, &mask, &pos);
 262
 263         return (reg & mask) >> pos;
 264 }
 265 #endif
 266
 267 static void stv0367_write_table(struct stv0367_state *state,
 268                                 const struct st_register *deftab)
 269 {
 270         int i = 0;
 271
 272         while (1) {
 273                 if (!deftab[i].addr)
 274                         break;
 275                 stv0367_writereg(state, deftab[i].addr, deftab[i].value);
 276                 i++;
 277         }
 278 }
 279
 280 static void stv0367_pll_setup(struct stv0367_state *state,
 281                                 u32 icspeed, u32 xtal)
 282 {
 283         /* note on regs: R367TER_* and R367CAB_* defines each point to
 284          * 0xf0d8, so just use R367TER_ for both cases
 285          */
 286
 287         switch (icspeed) {
 288         case STV0367_ICSPEED_58000:
 289                 switch (xtal) {
 290                 default:
 291                 case 27000000:
 292                         dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
 293                         /* PLLMDIV: 27, PLLNDIV: 232 */
 294                         stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
 295                         stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
 296                         break;
 297                 }
 298                 break;
 299         default:
 300         case STV0367_ICSPEED_53125:
 301                 switch (xtal) {
 302                         /* set internal freq to 53.125MHz */
 303                 case 16000000:
 304                         stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
 305                         stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
 306                         break;
 307                 case 25000000:
 308                         stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
 309                         stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
 310                         break;
 311                 default:
 312                 case 27000000:
 313                         dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
 314                         stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
 315                         stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
 316                         break;
 317                 case 30000000:
 318                         stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
 319                         stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
 320                         break;
 321                 }
 322         }
 323
 324         stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
 325 }
 326
 327 static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
 328 {
 329         if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
 330                 state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
 331                 *ifkhz = *ifkhz / 1000; /* hz -> khz */
 332         } else
 333                 *ifkhz = state->config->if_khz;
 334
 335         return 0;
 336 }
 337
 338 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
 339 {
 340         struct stv0367_state *state = fe->demodulator_priv;
 341         u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
 342
 343         dprintk("%s:\n", __func__);
 344
 345         if (enable) {
 346                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
 347                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
 348         } else {
 349                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
 350                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
 351         }
 352
 353         stv0367_writereg(state, R367TER_I2CRPT, tmp);
 354
 355         return 0;
 356 }
 357
 358 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
 359 {
 360         struct dvb_frontend_ops *frontend_ops = &fe->ops;
 361         struct dvb_tuner_ops    *tuner_ops = &frontend_ops->tuner_ops;
 362         u32 freq = 0;
 363         int err = 0;
 364
 365         dprintk("%s:\n", __func__);
 366
 367         if (tuner_ops->get_frequency) {
 368                 err = tuner_ops->get_frequency(fe, &freq);
 369                 if (err < 0) {
 370                         printk(KERN_ERR "%s: Invalid parameter\n", __func__);
 371                         return err;
 372                 }
 373
 374                 dprintk("%s: frequency=%d\n", __func__, freq);
 375
 376         } else
 377                 return -1;
 378
 379         return freq;
 380 }
 381
 382 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
 383         {
 384                 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
 385                 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
 386                 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
 387                 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
 388                 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
 389                 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
 390         }, {
 391                 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
 392                 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
 393                 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
 394                 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
 395                 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
 396                 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
 397         }, {
 398                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 399                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 400                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 401                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 402                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 403                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 404         }
 405 };
 406
 407 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
 408         {
 409                 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
 410                 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
 411                 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
 412                 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
 413                 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
 414                 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
 415         }, {
 416                 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
 417                 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
 418                 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
 419                 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
 420                 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
 421                 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
 422         }, {
 423                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 424                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 425                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 426                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 427                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 428                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 429         }
 430 };
 431
 432 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
 433         {
 434                 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
 435                 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
 436                 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
 437                 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
 438                 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
 439                 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
 440         }, {
 441                 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
 442                 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
 443                 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
 444                 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
 445                 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
 446                 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
 447
 448         }, {
 449                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 450                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 451                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 452                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 453                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 454                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 455         }
 456 };
 457
 458 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
 459 {
 460         u32 mclk_Hz = 0; /* master clock frequency (Hz) */
 461         u32 m, n, p;
 462
 463         dprintk("%s:\n", __func__);
 464
 465         if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
 466                 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
 467                 if (n == 0)
 468                         n = n + 1;
 469
 470                 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
 471                 if (m == 0)
 472                         m = m + 1;
 473
 474                 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
 475                 if (p > 5)
 476                         p = 5;
 477
 478                 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
 479
 480                 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
 481                                 n, m, p, mclk_Hz, ExtClk_Hz);
 482         } else
 483                 mclk_Hz = ExtClk_Hz;
 484
 485         dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
 486
 487         return mclk_Hz;
 488 }
 489
 490 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
 491                                 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
 492 {
 493         int i, j, k, freq;
 494
 495         dprintk("%s:\n", __func__);
 496
 497         freq = stv0367ter_get_mclk(state, DemodXtal);
 498
 499         if (freq == 53125000)
 500                 k = 1; /* equivalent to Xtal 25M on 362*/
 501         else if (freq == 54000000)
 502                 k = 0; /* equivalent to Xtal 27M on 362*/
 503         else if (freq == 52500000)
 504                 k = 2; /* equivalent to Xtal 30M on 362*/
 505         else
 506                 return 0;
 507
 508         for (i = 1; i <= 6; i++) {
 509                 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
 510
 511                 for (j = 1; j <= 5; j++) {
 512                         stv0367_writereg(state,
 513                                 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
 514                                 MSB(CellsCoeffs[k][i-1][j-1]));
 515                         stv0367_writereg(state,
 516                                 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
 517                                 LSB(CellsCoeffs[k][i-1][j-1]));
 518                 }
 519         }
 520
 521         return 1;
 522
 523 }
 524
 525 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
 526 {
 527         dprintk("%s:\n", __func__);
 528
 529         stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
 530
 531         /* Lock detect 1 */
 532         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
 533         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
 534         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
 535
 536         /* Lock detect 2 */
 537         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
 538         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
 539         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
 540
 541         /* Lock detect 3 */
 542         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
 543         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
 544         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
 545
 546         /* Lock detect 4 */
 547         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
 548         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
 549         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
 550
 551 }
 552
 553 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
 554                                                         u32 DemodXtalValue)
 555 {
 556         dprintk("%s:\n", __func__);
 557
 558         stv0367_writebits(state, F367TER_NRST_IIR, 0);
 559
 560         switch (Bandwidth) {
 561         case 6:
 562                 if (!stv0367ter_filt_coeff_init(state,
 563                                 CellsCoeffs_6MHz_367cofdm,
 564                                 DemodXtalValue))
 565                         return 0;
 566                 break;
 567         case 7:
 568                 if (!stv0367ter_filt_coeff_init(state,
 569                                 CellsCoeffs_7MHz_367cofdm,
 570                                 DemodXtalValue))
 571                         return 0;
 572                 break;
 573         case 8:
 574                 if (!stv0367ter_filt_coeff_init(state,
 575                                 CellsCoeffs_8MHz_367cofdm,
 576                                 DemodXtalValue))
 577                         return 0;
 578                 break;
 579         default:
 580                 return 0;
 581         }
 582
 583         stv0367_writebits(state, F367TER_NRST_IIR, 1);
 584
 585         return 1;
 586 }
 587
 588 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
 589 {
 590
 591         u8 com_n;
 592
 593         dprintk("%s:\n", __func__);
 594
 595         com_n = stv0367_readbits(state, F367TER_COM_N);
 596
 597         stv0367_writebits(state, F367TER_COM_N, 0x07);
 598
 599         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
 600         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
 601
 602         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
 603         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
 604
 605         stv0367_writebits(state, F367TER_COM_N, com_n);
 606
 607 }
 608
 609 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
 610 {
 611         int local_tempo = 0;
 612         switch (mode) {
 613         case 0:
 614                 local_tempo = tempo1;
 615                 break;
 616         case 1:
 617                 local_tempo = tempo2;
 618                 break ;
 619
 620         case 2:
 621                 local_tempo = tempo3;
 622                 break;
 623
 624         default:
 625                 break;
 626         }
 627         /*      msleep(local_tempo);  */
 628         return local_tempo;
 629 }
 630
 631 static enum
 632 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
 633 {
 634         int wd = 100;
 635         unsigned short int SYR_var;
 636         s32 SYRStatus;
 637
 638         dprintk("%s:\n", __func__);
 639
 640         SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
 641
 642         while ((!SYR_var) && (wd > 0)) {
 643                 usleep_range(2000, 3000);
 644                 wd -= 2;
 645                 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
 646         }
 647
 648         if (!SYR_var)
 649                 SYRStatus = FE_TER_NOSYMBOL;
 650         else
 651                 SYRStatus =  FE_TER_SYMBOLOK;
 652
 653         dprintk("stv0367ter_check_syr SYRStatus %s\n",
 654                                 SYR_var == 0 ? "No Symbol" : "OK");
 655
 656         return SYRStatus;
 657 }
 658
 659 static enum
 660 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
 661                                                                 s32 FFTmode)
 662 {
 663
 664         s32  CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
 665         int wd = 0;
 666
 667         dprintk("%s:\n", __func__);
 668
 669         switch (FFTmode) {
 670         case 0: /*2k mode*/
 671                 CPAMPMin = 20;
 672                 wd = 10;
 673                 break;
 674         case 1: /*8k mode*/
 675                 CPAMPMin = 80;
 676                 wd = 55;
 677                 break;
 678         case 2: /*4k mode*/
 679                 CPAMPMin = 40;
 680                 wd = 30;
 681                 break;
 682         default:
 683                 CPAMPMin = 0xffff;  /*drives to NOCPAMP */
 684                 break;
 685         }
 686
 687         dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
 688
 689         CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
 690         while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
 691                 usleep_range(1000, 2000);
 692                 wd -= 1;
 693                 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
 694                 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
 695         }
 696         dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
 697         if (CPAMPvalue < CPAMPMin) {
 698                 CPAMPStatus = FE_TER_NOCPAMP;
 699                 dprintk("%s: CPAMP failed\n", __func__);
 700         } else {
 701                 dprintk("%s: CPAMP OK !\n", __func__);
 702                 CPAMPStatus = FE_TER_CPAMPOK;
 703         }
 704
 705         return CPAMPStatus;
 706 }
 707
 708 static enum stv0367_ter_signal_type
 709 stv0367ter_lock_algo(struct stv0367_state *state)
 710 {
 711         enum stv0367_ter_signal_type ret_flag;
 712         short int wd, tempo;
 713         u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
 714         u8 tmp, tmp2;
 715
 716         dprintk("%s:\n", __func__);
 717
 718         if (state == NULL)
 719                 return FE_TER_SWNOK;
 720
 721         try = 0;
 722         do {
 723                 ret_flag = FE_TER_LOCKOK;
 724
 725                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
 726
 727                 if (state->config->if_iq_mode != 0)
 728                         stv0367_writebits(state, F367TER_COM_N, 0x07);
 729
 730                 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
 731                 stv0367_writebits(state, F367TER_MODE, 0);
 732                 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
 733                 usleep_range(5000, 10000);
 734
 735                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
 736
 737
 738                 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
 739                         return FE_TER_NOSYMBOL;
 740                 else { /*
 741                         if chip locked on wrong mode first try,
 742                         it must lock correctly second try */
 743                         mode = stv0367_readbits(state, F367TER_SYR_MODE);
 744                         if (stv0367ter_check_cpamp(state, mode) ==
 745                                                         FE_TER_NOCPAMP) {
 746                                 if (try == 0)
 747                                         ret_flag = FE_TER_NOCPAMP;
 748
 749                         }
 750                 }
 751
 752                 try++;
 753         } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
 754
 755         tmp  = stv0367_readreg(state, R367TER_SYR_STAT);
 756         tmp2 = stv0367_readreg(state, R367TER_STATUS);
 757         dprintk("state=%p\n", state);
 758         dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
 759                                                         mode, tmp, tmp2);
 760
 761         tmp  = stv0367_readreg(state, R367TER_PRVIT);
 762         tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
 763         dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
 764
 765         tmp  = stv0367_readreg(state, R367TER_GAIN_SRC1);
 766         dprintk("GAIN_SRC1=0x%x\n", tmp);
 767
 768         if ((mode != 0) && (mode != 1) && (mode != 2))
 769                 return FE_TER_SWNOK;
 770
 771         /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
 772
 773         /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
 774         and set channel predictor in automatic */
 775 #if 0
 776         switch (guard) {
 777
 778         case 0:
 779         case 1:
 780                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
 781                 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
 782                 break;
 783         case 2:
 784         case 3:
 785                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
 786                 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
 787                 break;
 788
 789         default:
 790                 return FE_TER_SWNOK;
 791         }
 792 #endif
 793
 794         /*reset fec an reedsolo FOR 367 only*/
 795         stv0367_writebits(state, F367TER_RST_SFEC, 1);
 796         stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
 797         usleep_range(1000, 2000);
 798         stv0367_writebits(state, F367TER_RST_SFEC, 0);
 799         stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
 800
 801         u_var1 = stv0367_readbits(state, F367TER_LK);
 802         u_var2 = stv0367_readbits(state, F367TER_PRF);
 803         u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
 804         /*      u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
 805
 806         wd = stv0367ter_duration(mode, 125, 500, 250);
 807         tempo = stv0367ter_duration(mode, 4, 16, 8);
 808
 809         /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4))  && (wd>=0)) */
 810         while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
 811                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
 812                 wd -= tempo;
 813                 u_var1 = stv0367_readbits(state, F367TER_LK);
 814                 u_var2 = stv0367_readbits(state, F367TER_PRF);
 815                 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
 816                 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
 817         }
 818
 819         if (!u_var1)
 820                 return FE_TER_NOLOCK;
 821
 822
 823         if (!u_var2)
 824                 return FE_TER_NOPRFOUND;
 825
 826         if (!u_var3)
 827                 return FE_TER_NOTPS;
 828
 829         guard = stv0367_readbits(state, F367TER_SYR_GUARD);
 830         stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
 831         switch (guard) {
 832         case 0:
 833         case 1:
 834                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
 835                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
 836                 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
 837                 break;
 838         case 2:
 839         case 3:
 840                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
 841                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
 842                 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
 843                 break;
 844
 845         default:
 846                 return FE_TER_SWNOK;
 847         }
 848
 849         /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
 850         if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
 851                         (mode == 1) &&
 852                         (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
 853                 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
 854                 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
 855                 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
 856         } else
 857                 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
 858
 859         wd = stv0367ter_duration(mode, 125, 500, 250);
 860         u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
 861
 862         while ((!u_var4) && (wd >= 0)) {
 863                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
 864                 wd -= tempo;
 865                 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
 866         }
 867
 868         if (!u_var4)
 869                 return FE_TER_NOLOCK;
 870
 871         /* for 367 leave COM_N at 0x7 for IQ_mode*/
 872         /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
 873                 tempo=0;
 874                 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
 875                 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
 876                         ChipWaitOrAbort(state,1);
 877                         tempo+=1;
 878                 }
 879
 880                 stv0367_writebits(state,F367TER_COM_N,0x17);
 881         } */
 882
 883         stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
 884
 885         dprintk("FE_TER_LOCKOK !!!\n");
 886
 887         return  FE_TER_LOCKOK;
 888
 889 }
 890
 891 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
 892                                         enum stv0367_ts_mode PathTS)
 893 {
 894
 895         dprintk("%s:\n", __func__);
 896
 897         if (state == NULL)
 898                 return;
 899
 900         stv0367_writebits(state, F367TER_TS_DIS, 0);
 901         switch (PathTS) {
 902         default:
 903                 /*for removing warning :default we can assume in parallel mode*/
 904         case STV0367_PARALLEL_PUNCT_CLOCK:
 905                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
 906                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
 907                 break;
 908         case STV0367_SERIAL_PUNCT_CLOCK:
 909                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
 910                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
 911                 break;
 912         }
 913 }
 914
 915 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
 916                                         enum stv0367_clk_pol clock)
 917 {
 918
 919         dprintk("%s:\n", __func__);
 920
 921         if (state == NULL)
 922                 return;
 923
 924         switch (clock) {
 925         case STV0367_RISINGEDGE_CLOCK:
 926                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
 927                 break;
 928         case STV0367_FALLINGEDGE_CLOCK:
 929                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
 930                 break;
 931                 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
 932         default:
 933                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
 934                 break;
 935         }
 936 }
 937
 938 #if 0
 939 static void stv0367ter_core_sw(struct stv0367_state *state)
 940 {
 941
 942         dprintk("%s:\n", __func__);
 943
 944         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
 945         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
 946         msleep(350);
 947 }
 948 #endif
 949 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
 950 {
 951         struct stv0367_state *state = fe->demodulator_priv;
 952
 953         dprintk("%s:\n", __func__);
 954
 955         if (standby_on) {
 956                 stv0367_writebits(state, F367TER_STDBY, 1);
 957                 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
 958                 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
 959         } else {
 960                 stv0367_writebits(state, F367TER_STDBY, 0);
 961                 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
 962                 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
 963         }
 964
 965         return 0;
 966 }
 967
 968 static int stv0367ter_sleep(struct dvb_frontend *fe)
 969 {
 970         return stv0367ter_standby(fe, 1);
 971 }
 972
 973 static int stv0367ter_init(struct dvb_frontend *fe)
 974 {
 975         struct stv0367_state *state = fe->demodulator_priv;
 976         struct stv0367ter_state *ter_state = state->ter_state;
 977
 978         dprintk("%s:\n", __func__);
 979
 980         ter_state->pBER = 0;
 981
 982         stv0367_write_table(state,
 983                 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
 984
 985         stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
 986
 987         stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
 988         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
 989
 990         /*Set TS1 and TS2 to serial or parallel mode */
 991         stv0367ter_set_ts_mode(state, state->config->ts_mode);
 992         stv0367ter_set_clk_pol(state, state->config->clk_pol);
 993
 994         state->chip_id = stv0367_readreg(state, R367TER_ID);
 995         ter_state->first_lock = 0;
 996         ter_state->unlock_counter = 2;
 997
 998         return 0;
 999 }
1000
1001 static int stv0367ter_algo(struct dvb_frontend *fe)
1002 {
1003         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1004         struct stv0367_state *state = fe->demodulator_priv;
1005         struct stv0367ter_state *ter_state = state->ter_state;
1006         int offset = 0, tempo = 0;
1007         u8 u_var;
1008         u8 /*constell,*/ counter;
1009         s8 step;
1010         s32 timing_offset = 0;
1011         u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
1012
1013         dprintk("%s:\n", __func__);
1014
1015         stv0367_get_if_khz(state, &ifkhz);
1016
1017         ter_state->frequency = p->frequency;
1018         ter_state->force = FE_TER_FORCENONE
1019                         + stv0367_readbits(state, F367TER_FORCE) * 2;
1020         ter_state->if_iq_mode = state->config->if_iq_mode;
1021         switch (state->config->if_iq_mode) {
1022         case FE_TER_NORMAL_IF_TUNER:  /* Normal IF mode */
1023                 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1024                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1025                 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1026                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1027                 break;
1028         case FE_TER_LONGPATH_IF_TUNER:  /* Long IF mode */
1029                 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1030                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1031                 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1032                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1033                 break;
1034         case FE_TER_IQ_TUNER:  /* IQ mode */
1035                 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1036                 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1037                 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1038                 break;
1039         default:
1040                 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1041                 return -EINVAL;
1042         }
1043
1044         usleep_range(5000, 7000);
1045
1046         switch (p->inversion) {
1047         case INVERSION_AUTO:
1048         default:
1049                 dprintk("%s: inversion AUTO\n", __func__);
1050                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1051                         stv0367_writebits(state, F367TER_IQ_INVERT,
1052                                                 ter_state->sense);
1053                 else
1054                         stv0367_writebits(state, F367TER_INV_SPECTR,
1055                                                 ter_state->sense);
1056
1057                 break;
1058         case INVERSION_ON:
1059         case INVERSION_OFF:
1060                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1061                         stv0367_writebits(state, F367TER_IQ_INVERT,
1062                                                 p->inversion);
1063                 else
1064                         stv0367_writebits(state, F367TER_INV_SPECTR,
1065                                                 p->inversion);
1066
1067                 break;
1068         }
1069
1070         if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1071                                 (ter_state->pBW != ter_state->bw)) {
1072                 stv0367ter_agc_iir_lock_detect_set(state);
1073
1074                 /*set fine agc target to 180 for LPIF or IQ mode*/
1075                 /* set Q_AGCTarget */
1076                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1077                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1078                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1079
1080                 /* set Q_AGCTarget */
1081                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1082                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1083                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1084
1085                 if (!stv0367_iir_filt_init(state, ter_state->bw,
1086                                                 state->config->xtal))
1087                         return -EINVAL;
1088                 /*set IIR filter once for 6,7 or 8MHz BW*/
1089                 ter_state->pBW = ter_state->bw;
1090
1091                 stv0367ter_agc_iir_rst(state);
1092         }
1093
1094         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1095                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1096         else
1097                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1098
1099         InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1100         temp = (int)
1101                 ((((ter_state->bw * 64 * (1 << 15) * 100)
1102                                                 / (InternalFreq)) * 10) / 7);
1103
1104         stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1105         temp = temp / 2;
1106         stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1107         stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1108
1109         temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1110                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1111                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1112         temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1113         stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1114         stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1115         temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1116                         stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1117
1118         temp = (int)
1119                 ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
1120
1121         dprintk("DEROT temp=0x%x\n", temp);
1122         stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1123         stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1124
1125         ter_state->echo_pos = 0;
1126         ter_state->ucblocks = 0; /* liplianin */
1127         ter_state->pBER = 0; /* liplianin */
1128         stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1129
1130         if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1131                 return 0;
1132
1133         ter_state->state = FE_TER_LOCKOK;
1134
1135         ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1136         ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1137
1138         ter_state->first_lock = 1; /* we know sense now :) */
1139
1140         ter_state->agc_val =
1141                         (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1142                         (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1143                         stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1144                         (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1145
1146         /* Carrier offset calculation */
1147         stv0367_writebits(state, F367TER_FREEZE, 1);
1148         offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1149         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1150         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1151         stv0367_writebits(state, F367TER_FREEZE, 0);
1152         if (offset > 8388607)
1153                 offset -= 16777216;
1154
1155         offset = offset * 2 / 16384;
1156
1157         if (ter_state->mode == FE_TER_MODE_2K)
1158                 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1159         else if (ter_state->mode == FE_TER_MODE_4K)
1160                 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1161         else  if (ter_state->mode == FE_TER_MODE_8K)
1162                 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1163
1164         if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1165                 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1166                                 (stv0367_readbits(state,
1167                                         F367TER_STATUS_INV_SPECRUM) == 1)))
1168                         offset = offset * -1;
1169         }
1170
1171         if (ter_state->bw == 6)
1172                 offset = (offset * 6) / 8;
1173         else if (ter_state->bw == 7)
1174                 offset = (offset * 7) / 8;
1175
1176         ter_state->frequency += offset;
1177
1178         tempo = 10;  /* exit even if timing_offset stays null */
1179         while ((timing_offset == 0) && (tempo > 0)) {
1180                 usleep_range(10000, 20000);     /*was 20ms  */
1181                 /* fine tuning of timing offset if required */
1182                 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1183                                 + 256 * stv0367_readbits(state,
1184                                                         F367TER_TRL_TOFFSET_HI);
1185                 if (timing_offset >= 32768)
1186                         timing_offset -= 65536;
1187                 trl_nomrate = (512 * stv0367_readbits(state,
1188                                                         F367TER_TRL_NOMRATE_HI)
1189                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1190                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1191
1192                 timing_offset = ((signed)(1000000 / trl_nomrate) *
1193                                                         timing_offset) / 2048;
1194                 tempo--;
1195         }
1196
1197         if (timing_offset <= 0) {
1198                 timing_offset = (timing_offset - 11) / 22;
1199                 step = -1;
1200         } else {
1201                 timing_offset = (timing_offset + 11) / 22;
1202                 step = 1;
1203         }
1204
1205         for (counter = 0; counter < abs(timing_offset); counter++) {
1206                 trl_nomrate += step;
1207                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1208                                                 trl_nomrate % 2);
1209                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1210                                                 trl_nomrate / 2);
1211                 usleep_range(1000, 2000);
1212         }
1213
1214         usleep_range(5000, 6000);
1215         /* unlocks could happen in case of trl centring big step,
1216         then a core off/on restarts demod */
1217         u_var = stv0367_readbits(state, F367TER_LK);
1218
1219         if (!u_var) {
1220                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1221                 msleep(20);
1222                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1223         }
1224
1225         return 0;
1226 }
1227
1228 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1229 {
1230         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1231         struct stv0367_state *state = fe->demodulator_priv;
1232         struct stv0367ter_state *ter_state = state->ter_state;
1233
1234         /*u8 trials[2]; */
1235         s8 num_trials, index;
1236         u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1237
1238         if (state->reinit_on_setfrontend)
1239                 stv0367ter_init(fe);
1240
1241         if (fe->ops.tuner_ops.set_params) {
1242                 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1243                         fe->ops.i2c_gate_ctrl(fe, 1);
1244                 fe->ops.tuner_ops.set_params(fe);
1245                 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1246                         fe->ops.i2c_gate_ctrl(fe, 0);
1247         }
1248
1249         switch (p->transmission_mode) {
1250         default:
1251         case TRANSMISSION_MODE_AUTO:
1252         case TRANSMISSION_MODE_2K:
1253                 ter_state->mode = FE_TER_MODE_2K;
1254                 break;
1255 /*      case TRANSMISSION_MODE_4K:
1256                 pLook.mode = FE_TER_MODE_4K;
1257                 break;*/
1258         case TRANSMISSION_MODE_8K:
1259                 ter_state->mode = FE_TER_MODE_8K;
1260                 break;
1261         }
1262
1263         switch (p->guard_interval) {
1264         default:
1265         case GUARD_INTERVAL_1_32:
1266         case GUARD_INTERVAL_1_16:
1267         case GUARD_INTERVAL_1_8:
1268         case GUARD_INTERVAL_1_4:
1269                 ter_state->guard = p->guard_interval;
1270                 break;
1271         case GUARD_INTERVAL_AUTO:
1272                 ter_state->guard = GUARD_INTERVAL_1_32;
1273                 break;
1274         }
1275
1276         switch (p->bandwidth_hz) {
1277         case 6000000:
1278                 ter_state->bw = FE_TER_CHAN_BW_6M;
1279                 break;
1280         case 7000000:
1281                 ter_state->bw = FE_TER_CHAN_BW_7M;
1282                 break;
1283         case 8000000:
1284         default:
1285                 ter_state->bw = FE_TER_CHAN_BW_8M;
1286         }
1287
1288         ter_state->hierarchy = FE_TER_HIER_NONE;
1289
1290         switch (p->inversion) {
1291         case INVERSION_OFF:
1292         case INVERSION_ON:
1293                 num_trials = 1;
1294                 break;
1295         default:
1296                 num_trials = 2;
1297                 if (ter_state->first_lock)
1298                         num_trials = 1;
1299                 break;
1300         }
1301
1302         ter_state->state = FE_TER_NOLOCK;
1303         index = 0;
1304
1305         while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1306                 if (!ter_state->first_lock) {
1307                         if (p->inversion == INVERSION_AUTO)
1308                                 ter_state->sense = SenseTrials[index];
1309
1310                 }
1311                 stv0367ter_algo(fe);
1312
1313                 if ((ter_state->state == FE_TER_LOCKOK) &&
1314                                 (p->inversion == INVERSION_AUTO) &&
1315                                                                 (index == 1)) {
1316                         /* invert spectrum sense */
1317                         SenseTrials[index] = SenseTrials[0];
1318                         SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1319                 }
1320
1321                 index++;
1322         }
1323
1324         return 0;
1325 }
1326
1327 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1328 {
1329         struct stv0367_state *state = fe->demodulator_priv;
1330         struct stv0367ter_state *ter_state = state->ter_state;
1331         u32 errs = 0;
1332
1333         /*wait for counting completion*/
1334         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1335                 errs =
1336                         ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1337                         * (1 << 16))
1338                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1339                         * (1 << 8))
1340                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1341                 ter_state->ucblocks = errs;
1342         }
1343
1344         (*ucblocks) = ter_state->ucblocks;
1345
1346         return 0;
1347 }
1348
1349 static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1350                                    struct dtv_frontend_properties *p)
1351 {
1352         struct stv0367_state *state = fe->demodulator_priv;
1353         struct stv0367ter_state *ter_state = state->ter_state;
1354         enum stv0367_ter_mode mode;
1355         int constell = 0,/* snr = 0,*/ Data = 0;
1356
1357         p->frequency = stv0367_get_tuner_freq(fe);
1358         if ((int)p->frequency < 0)
1359                 p->frequency = -p->frequency;
1360
1361         constell = stv0367_readbits(state, F367TER_TPS_CONST);
1362         if (constell == 0)
1363                 p->modulation = QPSK;
1364         else if (constell == 1)
1365                 p->modulation = QAM_16;
1366         else
1367                 p->modulation = QAM_64;
1368
1369         p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1370
1371         /* Get the Hierarchical mode */
1372         Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1373
1374         switch (Data) {
1375         case 0:
1376                 p->hierarchy = HIERARCHY_NONE;
1377                 break;
1378         case 1:
1379                 p->hierarchy = HIERARCHY_1;
1380                 break;
1381         case 2:
1382                 p->hierarchy = HIERARCHY_2;
1383                 break;
1384         case 3:
1385                 p->hierarchy = HIERARCHY_4;
1386                 break;
1387         default:
1388                 p->hierarchy = HIERARCHY_AUTO;
1389                 break; /* error */
1390         }
1391
1392         /* Get the FEC Rate */
1393         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1394                 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1395         else
1396                 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1397
1398         switch (Data) {
1399         case 0:
1400                 p->code_rate_HP = FEC_1_2;
1401                 break;
1402         case 1:
1403                 p->code_rate_HP = FEC_2_3;
1404                 break;
1405         case 2:
1406                 p->code_rate_HP = FEC_3_4;
1407                 break;
1408         case 3:
1409                 p->code_rate_HP = FEC_5_6;
1410                 break;
1411         case 4:
1412                 p->code_rate_HP = FEC_7_8;
1413                 break;
1414         default:
1415                 p->code_rate_HP = FEC_AUTO;
1416                 break; /* error */
1417         }
1418
1419         mode = stv0367_readbits(state, F367TER_SYR_MODE);
1420
1421         switch (mode) {
1422         case FE_TER_MODE_2K:
1423                 p->transmission_mode = TRANSMISSION_MODE_2K;
1424                 break;
1425 /*      case FE_TER_MODE_4K:
1426                 p->transmission_mode = TRANSMISSION_MODE_4K;
1427                 break;*/
1428         case FE_TER_MODE_8K:
1429                 p->transmission_mode = TRANSMISSION_MODE_8K;
1430                 break;
1431         default:
1432                 p->transmission_mode = TRANSMISSION_MODE_AUTO;
1433         }
1434
1435         p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
1436
1437         return 0;
1438 }
1439
1440 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
1441 {
1442         struct stv0367_state *state = fe->demodulator_priv;
1443         u32 snru32 = 0;
1444         int cpt = 0;
1445         u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
1446
1447         while (cpt < 10) {
1448                 usleep_range(2000, 3000);
1449                 if (cut == 0x50) /*cut 1.0 cut 1.1*/
1450                         snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
1451                 else /*cu2.0*/
1452                         snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
1453
1454                 cpt++;
1455         }
1456
1457         snru32 /= 10;/*average on 10 values*/
1458
1459         *snr = snru32 / 1000;
1460
1461         return 0;
1462 }
1463
1464 #if 0
1465 static int stv0367ter_status(struct dvb_frontend *fe)
1466 {
1467
1468         struct stv0367_state *state = fe->demodulator_priv;
1469         struct stv0367ter_state *ter_state = state->ter_state;
1470         int locked = FALSE;
1471
1472         locked = (stv0367_readbits(state, F367TER_LK));
1473         if (!locked)
1474                 ter_state->unlock_counter += 1;
1475         else
1476                 ter_state->unlock_counter = 0;
1477
1478         if (ter_state->unlock_counter > 2) {
1479                 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
1480                                 (!stv0367_readbits(state, F367TER_LK))) {
1481                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1482                         usleep_range(2000, 3000);
1483                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1484                         msleep(350);
1485                         locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
1486                                         (stv0367_readbits(state, F367TER_LK));
1487                 }
1488
1489         }
1490
1491         return locked;
1492 }
1493 #endif
1494 static int stv0367ter_read_status(struct dvb_frontend *fe,
1495                                   enum fe_status *status)
1496 {
1497         struct stv0367_state *state = fe->demodulator_priv;
1498
1499         dprintk("%s:\n", __func__);
1500
1501         *status = 0;
1502
1503         if (stv0367_readbits(state, F367TER_LK)) {
1504                 *status |= FE_HAS_LOCK;
1505                 dprintk("%s: stv0367 has locked\n", __func__);
1506         }
1507
1508         return 0;
1509 }
1510
1511 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
1512 {
1513         struct stv0367_state *state = fe->demodulator_priv;
1514         struct stv0367ter_state *ter_state = state->ter_state;
1515         u32 Errors = 0, tber = 0, temporary = 0;
1516         int abc = 0, def = 0;
1517
1518
1519         /*wait for counting completion*/
1520         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
1521                 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
1522                         * (1 << 16))
1523                         + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
1524                         * (1 << 8))
1525                         + ((u32)stv0367_readbits(state,
1526                                                 F367TER_SFEC_ERR_CNT_LO));
1527         /*measurement not completed, load previous value*/
1528         else {
1529                 tber = ter_state->pBER;
1530                 return 0;
1531         }
1532
1533         abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
1534         def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
1535
1536         if (Errors == 0) {
1537                 tber = 0;
1538         } else if (abc == 0x7) {
1539                 if (Errors <= 4) {
1540                         temporary = (Errors * 1000000000) / (8 * (1 << 14));
1541                         temporary =  temporary;
1542                 } else if (Errors <= 42) {
1543                         temporary = (Errors * 100000000) / (8 * (1 << 14));
1544                         temporary = temporary * 10;
1545                 } else if (Errors <= 429) {
1546                         temporary = (Errors * 10000000) / (8 * (1 << 14));
1547                         temporary = temporary * 100;
1548                 } else if (Errors <= 4294) {
1549                         temporary = (Errors * 1000000) / (8 * (1 << 14));
1550                         temporary = temporary * 1000;
1551                 } else if (Errors <= 42949) {
1552                         temporary = (Errors * 100000) / (8 * (1 << 14));
1553                         temporary = temporary * 10000;
1554                 } else if (Errors <= 429496) {
1555                         temporary = (Errors * 10000) / (8 * (1 << 14));
1556                         temporary = temporary * 100000;
1557                 } else { /*if (Errors<4294967) 2^22 max error*/
1558                         temporary = (Errors * 1000) / (8 * (1 << 14));
1559                         temporary = temporary * 100000; /* still to *10 */
1560                 }
1561
1562                 /* Byte error*/
1563                 if (def == 2)
1564                         /*tber=Errors/(8*(1 <<14));*/
1565                         tber = temporary;
1566                 else if (def == 3)
1567                         /*tber=Errors/(8*(1 <<16));*/
1568                         tber = temporary / 4;
1569                 else if (def == 4)
1570                         /*tber=Errors/(8*(1 <<18));*/
1571                         tber = temporary / 16;
1572                 else if (def == 5)
1573                         /*tber=Errors/(8*(1 <<20));*/
1574                         tber = temporary / 64;
1575                 else if (def == 6)
1576                         /*tber=Errors/(8*(1 <<22));*/
1577                         tber = temporary / 256;
1578                 else
1579                         /* should not pass here*/
1580                         tber = 0;
1581
1582                 if ((Errors < 4294967) && (Errors > 429496))
1583                         tber *= 10;
1584
1585         }
1586
1587         /* save actual value */
1588         ter_state->pBER = tber;
1589
1590         (*ber) = tber;
1591
1592         return 0;
1593 }
1594 #if 0
1595 static u32 stv0367ter_get_per(struct stv0367_state *state)
1596 {
1597         struct stv0367ter_state *ter_state = state->ter_state;
1598         u32 Errors = 0, Per = 0, temporary = 0;
1599         int abc = 0, def = 0, cpt = 0;
1600
1601         while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
1602                         (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
1603                 usleep_range(1000, 2000);
1604                 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1605                         * (1 << 16))
1606                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1607                         * (1 << 8))
1608                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1609                 cpt++;
1610         }
1611         abc = stv0367_readbits(state, F367TER_ERR_SRC1);
1612         def = stv0367_readbits(state, F367TER_NUM_EVT1);
1613
1614         if (Errors == 0)
1615                 Per = 0;
1616         else if (abc == 0x9) {
1617                 if (Errors <= 4) {
1618                         temporary = (Errors * 1000000000) / (8 * (1 << 8));
1619                         temporary =  temporary;
1620                 } else if (Errors <= 42) {
1621                         temporary = (Errors * 100000000) / (8 * (1 << 8));
1622                         temporary = temporary * 10;
1623                 } else if (Errors <= 429) {
1624                         temporary = (Errors * 10000000) / (8 * (1 << 8));
1625                         temporary = temporary * 100;
1626                 } else if (Errors <= 4294) {
1627                         temporary = (Errors * 1000000) / (8 * (1 << 8));
1628                         temporary = temporary * 1000;
1629                 } else if (Errors <= 42949) {
1630                         temporary = (Errors * 100000) / (8 * (1 << 8));
1631                         temporary = temporary * 10000;
1632                 } else { /*if(Errors<=429496)  2^16 errors max*/
1633                         temporary = (Errors * 10000) / (8 * (1 << 8));
1634                         temporary = temporary * 100000;
1635                 }
1636
1637                 /* pkt error*/
1638                 if (def == 2)
1639                         /*Per=Errors/(1 << 8);*/
1640                         Per = temporary;
1641                 else if (def == 3)
1642                         /*Per=Errors/(1 << 10);*/
1643                         Per = temporary / 4;
1644                 else if (def == 4)
1645                         /*Per=Errors/(1 << 12);*/
1646                         Per = temporary / 16;
1647                 else if (def == 5)
1648                         /*Per=Errors/(1 << 14);*/
1649                         Per = temporary / 64;
1650                 else if (def == 6)
1651                         /*Per=Errors/(1 << 16);*/
1652                         Per = temporary / 256;
1653                 else
1654                         Per = 0;
1655
1656         }
1657         /* save actual value */
1658         ter_state->pPER = Per;
1659
1660         return Per;
1661 }
1662 #endif
1663 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
1664                                         struct dvb_frontend_tune_settings
1665                                         *fe_tune_settings)
1666 {
1667         fe_tune_settings->min_delay_ms = 1000;
1668         fe_tune_settings->step_size = 0;
1669         fe_tune_settings->max_drift = 0;
1670
1671         return 0;
1672 }
1673
1674 static void stv0367_release(struct dvb_frontend *fe)
1675 {
1676         struct stv0367_state *state = fe->demodulator_priv;
1677
1678         kfree(state->ter_state);
1679         kfree(state->cab_state);
1680         kfree(state);
1681 }
1682
1683 static const struct dvb_frontend_ops stv0367ter_ops = {
1684         .delsys = { SYS_DVBT },
1685         .info = {
1686                 .name                   = "ST STV0367 DVB-T",
1687                 .frequency_min          = 47000000,
1688                 .frequency_max          = 862000000,
1689                 .frequency_stepsize     = 15625,
1690                 .frequency_tolerance    = 0,
1691                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1692                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
1693                         FE_CAN_FEC_AUTO |
1694                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1695                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
1696                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
1697                         FE_CAN_INVERSION_AUTO |
1698                         FE_CAN_MUTE_TS
1699         },
1700         .release = stv0367_release,
1701         .init = stv0367ter_init,
1702         .sleep = stv0367ter_sleep,
1703         .i2c_gate_ctrl = stv0367ter_gate_ctrl,
1704         .set_frontend = stv0367ter_set_frontend,
1705         .get_frontend = stv0367ter_get_frontend,
1706         .get_tune_settings = stv0367_get_tune_settings,
1707         .read_status = stv0367ter_read_status,
1708         .read_ber = stv0367ter_read_ber,/* too slow */
1709 /*      .read_signal_strength = stv0367_read_signal_strength,*/
1710         .read_snr = stv0367ter_read_snr,
1711         .read_ucblocks = stv0367ter_read_ucblocks,
1712 };
1713
1714 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
1715                                    struct i2c_adapter *i2c)
1716 {
1717         struct stv0367_state *state = NULL;
1718         struct stv0367ter_state *ter_state = NULL;
1719
1720         /* allocate memory for the internal state */
1721         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
1722         if (state == NULL)
1723                 goto error;
1724         ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
1725         if (ter_state == NULL)
1726                 goto error;
1727
1728         /* setup the state */
1729         state->i2c = i2c;
1730         state->config = config;
1731         state->ter_state = ter_state;
1732         state->fe.ops = stv0367ter_ops;
1733         state->fe.demodulator_priv = state;
1734         state->chip_id = stv0367_readreg(state, 0xf000);
1735
1736         /* demod operation options */
1737         state->use_i2c_gatectrl = 1;
1738         state->deftabs = STV0367_DEFTAB_GENERIC;
1739         state->reinit_on_setfrontend = 1;
1740         state->auto_if_khz = 0;
1741
1742         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
1743
1744         /* check if the demod is there */
1745         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
1746                 goto error;
1747
1748         return &state->fe;
1749
1750 error:
1751         kfree(ter_state);
1752         kfree(state);
1753         return NULL;
1754 }
1755 EXPORT_SYMBOL(stv0367ter_attach);
1756
1757 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
1758 {
1759         struct stv0367_state *state = fe->demodulator_priv;
1760
1761         dprintk("%s:\n", __func__);
1762
1763         stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
1764
1765         return 0;
1766 }
1767
1768 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
1769 {
1770         struct stv0367_state *state = fe->demodulator_priv;
1771         u32 mclk_Hz = 0;/* master clock frequency (Hz) */
1772         u32 M, N, P;
1773
1774
1775         if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
1776                 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
1777                 if (N == 0)
1778                         N = N + 1;
1779
1780                 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
1781                 if (M == 0)
1782                         M = M + 1;
1783
1784                 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
1785
1786                 if (P > 5)
1787                         P = 5;
1788
1789                 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
1790                 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
1791                                                                 mclk_Hz);
1792         } else
1793                 mclk_Hz = ExtClk_Hz;
1794
1795         dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
1796
1797         return mclk_Hz;
1798 }
1799
1800 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
1801 {
1802         u32 ADCClk_Hz = ExtClk_Hz;
1803
1804         ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
1805
1806         return ADCClk_Hz;
1807 }
1808
1809 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
1810                                                  u32 SymbolRate,
1811                                                  enum stv0367cab_mod QAMSize)
1812 {
1813         /* Set QAM size */
1814         stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
1815
1816         /* Set Registers settings specific to the QAM size */
1817         switch (QAMSize) {
1818         case FE_CAB_MOD_QAM4:
1819                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1820                 break;
1821         case FE_CAB_MOD_QAM16:
1822                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1823                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1824                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1825                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1826                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1827                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1828                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1829                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1830                 break;
1831         case FE_CAB_MOD_QAM32:
1832                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1833                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1834                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1835                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1836                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1837                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1838                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1839                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1840                 break;
1841         case FE_CAB_MOD_QAM64:
1842                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1843                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1844                 if (SymbolRate > 4500000) {
1845                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1846                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1847                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
1848                 } else if (SymbolRate > 2500000) {
1849                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1850                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1851                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1852                 } else {
1853                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1854                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1855                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1856                 }
1857                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1858                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1859                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1860                 break;
1861         case FE_CAB_MOD_QAM128:
1862                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1863                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1864                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1865                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
1866                 if (SymbolRate > 4500000)
1867                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1868                 else if (SymbolRate > 2500000)
1869                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1870                 else
1871                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1872
1873                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1874                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1875                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1876                 break;
1877         case FE_CAB_MOD_QAM256:
1878                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1879                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1880                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1881                 if (SymbolRate > 4500000)
1882                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1883                 else if (SymbolRate > 2500000)
1884                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1885                 else
1886                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1887
1888                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1889                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1890                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1891                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1892                 break;
1893         case FE_CAB_MOD_QAM512:
1894                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1895                 break;
1896         case FE_CAB_MOD_QAM1024:
1897                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1898                 break;
1899         default:
1900                 break;
1901         }
1902
1903         return QAMSize;
1904 }
1905
1906 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
1907                                         u32 adc_hz, s32 derot_hz)
1908 {
1909         u32 sampled_if = 0;
1910         u32 adc_khz;
1911
1912         adc_khz = adc_hz / 1000;
1913
1914         dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
1915
1916         if (adc_khz != 0) {
1917                 if (derot_hz < 1000000)
1918                         derot_hz = adc_hz / 4; /* ZIF operation */
1919                 if (derot_hz > adc_hz)
1920                         derot_hz = derot_hz - adc_hz;
1921                 sampled_if = (u32)derot_hz / 1000;
1922                 sampled_if *= 32768;
1923                 sampled_if /= adc_khz;
1924                 sampled_if *= 256;
1925         }
1926
1927         if (sampled_if > 8388607)
1928                 sampled_if = 8388607;
1929
1930         dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
1931
1932         stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1933         stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1934         stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
1935
1936         return derot_hz;
1937 }
1938
1939 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
1940 {
1941         u32 sampled_if;
1942
1943         sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
1944                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
1945                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
1946
1947         sampled_if /= 256;
1948         sampled_if *= (adc_hz / 1000);
1949         sampled_if += 1;
1950         sampled_if /= 32768;
1951
1952         return sampled_if;
1953 }
1954
1955 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
1956                         u32 mclk_hz, u32 SymbolRate,
1957                         enum stv0367cab_mod QAMSize)
1958 {
1959         u32 QamSizeCorr = 0;
1960         u32 u32_tmp = 0, u32_tmp1 = 0;
1961         u32 adp_khz;
1962
1963         dprintk("%s:\n", __func__);
1964
1965         /* Set Correction factor of SRC gain */
1966         switch (QAMSize) {
1967         case FE_CAB_MOD_QAM4:
1968                 QamSizeCorr = 1110;
1969                 break;
1970         case FE_CAB_MOD_QAM16:
1971                 QamSizeCorr = 1032;
1972                 break;
1973         case FE_CAB_MOD_QAM32:
1974                 QamSizeCorr =  954;
1975                 break;
1976         case FE_CAB_MOD_QAM64:
1977                 QamSizeCorr =  983;
1978                 break;
1979         case FE_CAB_MOD_QAM128:
1980                 QamSizeCorr =  957;
1981                 break;
1982         case FE_CAB_MOD_QAM256:
1983                 QamSizeCorr =  948;
1984                 break;
1985         case FE_CAB_MOD_QAM512:
1986                 QamSizeCorr =    0;
1987                 break;
1988         case FE_CAB_MOD_QAM1024:
1989                 QamSizeCorr =  944;
1990                 break;
1991         default:
1992                 break;
1993         }
1994
1995         /* Transfer ratio calculation */
1996         if (adc_hz != 0) {
1997                 u32_tmp = 256 * SymbolRate;
1998                 u32_tmp = u32_tmp / adc_hz;
1999         }
2000         stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2001
2002         /* Symbol rate and SRC gain calculation */
2003         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2004         if (adp_khz != 0) {
2005                 u32_tmp = SymbolRate;
2006                 u32_tmp1 = SymbolRate;
2007
2008                 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2009                         /* Symbol rate calculation */
2010                         u32_tmp *= 2048; /* 2048 = 2^11 */
2011                         u32_tmp = u32_tmp / adp_khz;
2012                         u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2013                         u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2014                         u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2015
2016                         /* SRC Gain Calculation */
2017                         u32_tmp1 *= 2048; /* *2*2^10 */
2018                         u32_tmp1 /= 439; /* *2/878 */
2019                         u32_tmp1 *= 256; /* *2^8 */
2020                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2021                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2022                         u32_tmp1 = u32_tmp1 / 10000000;
2023
2024                 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2025                         /* Symbol rate calculation */
2026                         u32_tmp *= 1024 ; /* 1024 = 2**10 */
2027                         u32_tmp = u32_tmp / adp_khz;
2028                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2029                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2030                         u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2031
2032                         /* SRC Gain Calculation */
2033                         u32_tmp1 *= 1024; /* *2*2^9 */
2034                         u32_tmp1 /= 439; /* *2/878 */
2035                         u32_tmp1 *= 256; /* *2^8 */
2036                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2037                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2038                         u32_tmp1 = u32_tmp1 / 5000000;
2039                 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2040                         /* Symbol rate calculation */
2041                         u32_tmp *= 512 ; /* 512 = 2**9 */
2042                         u32_tmp = u32_tmp / adp_khz;
2043                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2044                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2045                         u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2046
2047                         /* SRC Gain Calculation */
2048                         u32_tmp1 *= 512; /* *2*2^8 */
2049                         u32_tmp1 /= 439; /* *2/878 */
2050                         u32_tmp1 *= 256; /* *2^8 */
2051                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2052                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2053                         u32_tmp1 = u32_tmp1 / 2500000;
2054                 } else {
2055                         /* Symbol rate calculation */
2056                         u32_tmp *= 256 ; /* 256 = 2**8 */
2057                         u32_tmp = u32_tmp / adp_khz;
2058                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2059                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2060                         u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2061
2062                         /* SRC Gain Calculation */
2063                         u32_tmp1 *= 256; /* 2*2^7 */
2064                         u32_tmp1 /= 439; /* *2/878 */
2065                         u32_tmp1 *= 256; /* *2^8 */
2066                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2067                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2068                         u32_tmp1 = u32_tmp1 / 1250000;
2069                 }
2070         }
2071 #if 0
2072         /* Filters' coefficients are calculated and written
2073         into registers only if the filters are enabled */
2074         if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2075                 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2076                                                                 SymbolRate);
2077                 /* AllPass filter must be enabled
2078                 when the adjacents filter is used */
2079                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2080                 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2081         } else
2082                 /* AllPass filter must be disabled
2083                 when the adjacents filter is not used */
2084 #endif
2085         stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2086
2087         stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2088         stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2089         stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2090         stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2091
2092         stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2093         stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2094
2095         return SymbolRate ;
2096 }
2097
2098 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2099 {
2100         u32 regsym;
2101         u32 adp_khz;
2102
2103         regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2104                 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2105                 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2106                 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2107
2108         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2109
2110         if (regsym < 134217728) {               /* 134217728L = 2**27*/
2111                 regsym = regsym * 32;           /* 32 = 2**5 */
2112                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2113                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2114                 regsym = regsym / 128;          /* 128 = 2**7 */
2115                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2116                 regsym /= 2048 ;                /* 2048 = 2**11 */
2117         } else if (regsym < 268435456) {        /* 268435456L = 2**28 */
2118                 regsym = regsym * 16;           /* 16 = 2**4 */
2119                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2120                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2121                 regsym = regsym / 128;          /* 128 = 2**7 */
2122                 regsym *= 125 ;                 /* 125 = 1000/2**3*/
2123                 regsym /= 1024 ;                /* 256 = 2**10*/
2124         } else if (regsym < 536870912) {        /* 536870912L = 2**29*/
2125                 regsym = regsym * 8;            /* 8 = 2**3 */
2126                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2127                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2128                 regsym = regsym / 128;          /* 128 = 2**7 */
2129                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2130                 regsym /= 512 ;                 /* 128 = 2**9 */
2131         } else {
2132                 regsym = regsym * 4;            /* 4 = 2**2 */
2133                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2134                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2135                 regsym = regsym / 128;          /* 128 = 2**7 */
2136                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2137                 regsym /= 256 ;                 /* 64 = 2**8 */
2138         }
2139
2140         return regsym;
2141 }
2142
2143 static int stv0367cab_read_status(struct dvb_frontend *fe,
2144                                   enum fe_status *status)
2145 {
2146         struct stv0367_state *state = fe->demodulator_priv;
2147
2148         dprintk("%s:\n", __func__);
2149
2150         *status = 0;
2151
2152         if (stv0367_readbits(state, (state->cab_state->qamfec_status_reg ?
2153                 state->cab_state->qamfec_status_reg : F367CAB_QAMFEC_LOCK))) {
2154                 *status |= FE_HAS_LOCK;
2155                 dprintk("%s: stv0367 has locked\n", __func__);
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2162 {
2163         struct stv0367_state *state = fe->demodulator_priv;
2164
2165         dprintk("%s:\n", __func__);
2166
2167         if (standby_on) {
2168                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2169                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2170                 stv0367_writebits(state, F367CAB_STDBY, 1);
2171                 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2172                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2173                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2174                 stv0367_writebits(state, F367CAB_POFFQ, 1);
2175                 stv0367_writebits(state, F367CAB_POFFI, 1);
2176         } else {
2177                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2178                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2179                 stv0367_writebits(state, F367CAB_STDBY, 0);
2180                 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2181                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2182                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2183                 stv0367_writebits(state, F367CAB_POFFQ, 0);
2184                 stv0367_writebits(state, F367CAB_POFFI, 0);
2185         }
2186
2187         return 0;
2188 }
2189
2190 static int stv0367cab_sleep(struct dvb_frontend *fe)
2191 {
2192         return stv0367cab_standby(fe, 1);
2193 }
2194
2195 static int stv0367cab_init(struct dvb_frontend *fe)
2196 {
2197         struct stv0367_state *state = fe->demodulator_priv;
2198         struct stv0367cab_state *cab_state = state->cab_state;
2199
2200         dprintk("%s:\n", __func__);
2201
2202         stv0367_write_table(state,
2203                 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
2204
2205         switch (state->config->ts_mode) {
2206         case STV0367_DVBCI_CLOCK:
2207                 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2208                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2209                 break;
2210         case STV0367_SERIAL_PUNCT_CLOCK:
2211         case STV0367_SERIAL_CONT_CLOCK:
2212                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2213                 break;
2214         case STV0367_PARALLEL_PUNCT_CLOCK:
2215         case STV0367_OUTPUTMODE_DEFAULT:
2216                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2217                 break;
2218         }
2219
2220         switch (state->config->clk_pol) {
2221         case STV0367_RISINGEDGE_CLOCK:
2222                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2223                 break;
2224         case STV0367_FALLINGEDGE_CLOCK:
2225         case STV0367_CLOCKPOLARITY_DEFAULT:
2226                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2227                 break;
2228         }
2229
2230         stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2231
2232         stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2233
2234         stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2235
2236         stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2237
2238         stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2239
2240         cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2241         cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2242
2243         return 0;
2244 }
2245 static
2246 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2247                                              struct dtv_frontend_properties *p)
2248 {
2249         struct stv0367cab_state *cab_state = state->cab_state;
2250         enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2251         u32     QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
2252                 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2253                 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2254         u8      TrackAGCAccum;
2255         s32     tmp;
2256
2257         dprintk("%s:\n", __func__);
2258
2259         stv0367_get_if_khz(state, &ifkhz);
2260
2261         /* Timeouts calculation */
2262         /* A max lock time of 25 ms is allowed for delayed AGC */
2263         AGCTimeOut = 25;
2264         /* 100000 symbols needed by the TRL as a maximum value */
2265         TRLTimeOut = 100000000 / p->symbol_rate;
2266         /* CRLSymbols is the needed number of symbols to achieve a lock
2267            within [-4%, +4%] of the symbol rate.
2268            CRL timeout is calculated
2269            for a lock within [-search_range, +search_range].
2270            EQL timeout can be changed depending on
2271            the micro-reflections we want to handle.
2272            A characterization must be performed
2273            with these echoes to get new timeout values.
2274         */
2275         switch (p->modulation) {
2276         case QAM_16:
2277                 CRLSymbols = 150000;
2278                 EQLTimeOut = 100;
2279                 break;
2280         case QAM_32:
2281                 CRLSymbols = 250000;
2282                 EQLTimeOut = 100;
2283                 break;
2284         case QAM_64:
2285                 CRLSymbols = 200000;
2286                 EQLTimeOut = 100;
2287                 break;
2288         case QAM_128:
2289                 CRLSymbols = 250000;
2290                 EQLTimeOut = 100;
2291                 break;
2292         case QAM_256:
2293                 CRLSymbols = 250000;
2294                 EQLTimeOut = 100;
2295                 break;
2296         default:
2297                 CRLSymbols = 200000;
2298                 EQLTimeOut = 100;
2299                 break;
2300         }
2301 #if 0
2302         if (pIntParams->search_range < 0) {
2303                 CRLTimeOut = (25 * CRLSymbols *
2304                                 (-pIntParams->search_range / 1000)) /
2305                                         (pIntParams->symbol_rate / 1000);
2306         } else
2307 #endif
2308         CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2309                                         (p->symbol_rate / 1000);
2310
2311         CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2312         /* Timeouts below 50ms are coerced */
2313         if (CRLTimeOut < 50)
2314                 CRLTimeOut = 50;
2315         /* A maximum of 100 TS packets is needed to get FEC lock even in case
2316         the spectrum inversion needs to be changed.
2317            This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2318         */
2319         FECTimeOut = 20;
2320         DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2321
2322         dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2323
2324         /* Reset the TRL to ensure nothing starts until the
2325            AGC is stable which ensures a better lock time
2326         */
2327         stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2328         /* Set AGC accumulation time to minimum and lock threshold to maximum
2329         in order to speed up the AGC lock */
2330         TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2331         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2332         /* Modulus Mapper is disabled */
2333         stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2334         /* Disable the sweep function */
2335         stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2336         /* The sweep function is never used, Sweep rate must be set to 0 */
2337         /* Set the derotator frequency in Hz */
2338         stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2339                 (1000 * (s32)ifkhz + cab_state->derot_offset));
2340         /* Disable the Allpass Filter when the symbol rate is out of range */
2341         if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2342                 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2343                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2344         }
2345 #if 0
2346         /* Check if the tuner is locked */
2347         tuner_lock = stv0367cab_tuner_get_status(fe);
2348         if (tuner_lock == 0)
2349                 return FE_367CAB_NOTUNER;
2350 #endif
2351         /* Release the TRL to start demodulator acquisition */
2352         /* Wait for QAM lock */
2353         LockTime = 0;
2354         stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2355         do {
2356                 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2357                 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2358                                                         (QAM_Lock == 0x04))
2359                         /*
2360                          * We don't wait longer, the frequency/phase offset
2361                          * must be too big
2362                          */
2363                         LockTime = DemodTimeOut;
2364                 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2365                                                         (QAM_Lock == 0x02))
2366                         /*
2367                          * We don't wait longer, either there is no signal or
2368                          * it is not the right symbol rate or it is an analog
2369                          * carrier
2370                          */
2371                 {
2372                         LockTime = DemodTimeOut;
2373                         u32_tmp = stv0367_readbits(state,
2374                                                 F367CAB_AGC_PWR_WORD_LO) +
2375                                         (stv0367_readbits(state,
2376                                                 F367CAB_AGC_PWR_WORD_ME) << 8) +
2377                                         (stv0367_readbits(state,
2378                                                 F367CAB_AGC_PWR_WORD_HI) << 16);
2379                         if (u32_tmp >= 131072)
2380                                 u32_tmp = 262144 - u32_tmp;
2381                         u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2382                                                         F367CAB_AGC_IF_BWSEL)));
2383
2384                         if (u32_tmp < stv0367_readbits(state,
2385                                                 F367CAB_AGC_PWRREF_LO) +
2386                                         256 * stv0367_readbits(state,
2387                                                 F367CAB_AGC_PWRREF_HI) - 10)
2388                                 QAM_Lock = 0x0f;
2389                 } else {
2390                         usleep_range(10000, 20000);
2391                         LockTime += 10;
2392                 }
2393                 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2394                 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2395
2396                 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2397
2398         } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2399                                                 (LockTime < DemodTimeOut));
2400
2401         dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2402
2403         tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2404         dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2405         tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2406         dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2407
2408         tmp  = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2409         dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2410
2411         if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2412                 /* Wait for FEC lock */
2413                 LockTime = 0;
2414                 do {
2415                         usleep_range(5000, 7000);
2416                         LockTime += 5;
2417                         QAMFEC_Lock = stv0367_readbits(state,
2418                                 (state->cab_state->qamfec_status_reg ?
2419                                 state->cab_state->qamfec_status_reg :
2420                                 F367CAB_QAMFEC_LOCK));
2421                 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2422         } else
2423                 QAMFEC_Lock = 0;
2424
2425         if (QAMFEC_Lock) {
2426                 signalType = FE_CAB_DATAOK;
2427                 cab_state->spect_inv = stv0367_readbits(state,
2428                                                         F367CAB_QUAD_INV);
2429 #if 0
2430 /* not clear for me */
2431                 if (ifkhz != 0) {
2432                         if (ifkhz > cab_state->adc_clk / 1000) {
2433                                 cab_state->freq_khz =
2434                                         FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2435                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2436                                 - cab_state->adc_clk / 1000 + ifkhz;
2437                         } else {
2438                                 cab_state->freq_khz =
2439                                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2440                                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2441                                                 + ifkhz;
2442                         }
2443                 } else {
2444                         cab_state->freq_khz =
2445                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
2446                                 stv0367cab_get_derot_freq(state,
2447                                                         cab_state->adc_clk) -
2448                                 cab_state->adc_clk / 4000;
2449                 }
2450 #endif
2451                 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
2452                                                         cab_state->mclk);
2453                 cab_state->locked = 1;
2454
2455                 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
2456         } else {
2457                 switch (QAM_Lock) {
2458                 case 1:
2459                         signalType = FE_CAB_NOAGC;
2460                         break;
2461                 case 2:
2462                         signalType = FE_CAB_NOTIMING;
2463                         break;
2464                 case 3:
2465                         signalType = FE_CAB_TIMINGOK;
2466                         break;
2467                 case 4:
2468                         signalType = FE_CAB_NOCARRIER;
2469                         break;
2470                 case 5:
2471                         signalType = FE_CAB_CARRIEROK;
2472                         break;
2473                 case 7:
2474                         signalType = FE_CAB_NOBLIND;
2475                         break;
2476                 case 8:
2477                         signalType = FE_CAB_BLINDOK;
2478                         break;
2479                 case 10:
2480                         signalType = FE_CAB_NODEMOD;
2481                         break;
2482                 case 11:
2483                         signalType = FE_CAB_DEMODOK;
2484                         break;
2485                 case 12:
2486                         signalType = FE_CAB_DEMODOK;
2487                         break;
2488                 case 13:
2489                         signalType = FE_CAB_NODEMOD;
2490                         break;
2491                 case 14:
2492                         signalType = FE_CAB_NOBLIND;
2493                         break;
2494                 case 15:
2495                         signalType = FE_CAB_NOSIGNAL;
2496                         break;
2497                 default:
2498                         break;
2499                 }
2500
2501         }
2502
2503         /* Set the AGC control values to tracking values */
2504         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
2505         return signalType;
2506 }
2507
2508 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
2509 {
2510         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2511         struct stv0367_state *state = fe->demodulator_priv;
2512         struct stv0367cab_state *cab_state = state->cab_state;
2513         enum stv0367cab_mod QAMSize = 0;
2514
2515         dprintk("%s: freq = %d, srate = %d\n", __func__,
2516                                         p->frequency, p->symbol_rate);
2517
2518         cab_state->derot_offset = 0;
2519
2520         switch (p->modulation) {
2521         case QAM_16:
2522                 QAMSize = FE_CAB_MOD_QAM16;
2523                 break;
2524         case QAM_32:
2525                 QAMSize = FE_CAB_MOD_QAM32;
2526                 break;
2527         case QAM_64:
2528                 QAMSize = FE_CAB_MOD_QAM64;
2529                 break;
2530         case QAM_128:
2531                 QAMSize = FE_CAB_MOD_QAM128;
2532                 break;
2533         case QAM_256:
2534                 QAMSize = FE_CAB_MOD_QAM256;
2535                 break;
2536         default:
2537                 break;
2538         }
2539
2540         if (state->reinit_on_setfrontend)
2541                 stv0367cab_init(fe);
2542
2543         /* Tuner Frequency Setting */
2544         if (fe->ops.tuner_ops.set_params) {
2545                 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2546                         fe->ops.i2c_gate_ctrl(fe, 1);
2547                 fe->ops.tuner_ops.set_params(fe);
2548                 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2549                         fe->ops.i2c_gate_ctrl(fe, 0);
2550         }
2551
2552         stv0367cab_SetQamSize(
2553                         state,
2554                         p->symbol_rate,
2555                         QAMSize);
2556
2557         stv0367cab_set_srate(state,
2558                         cab_state->adc_clk,
2559                         cab_state->mclk,
2560                         p->symbol_rate,
2561                         QAMSize);
2562         /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
2563         cab_state->state = stv0367cab_algo(state, p);
2564         return 0;
2565 }
2566
2567 static int stv0367cab_get_frontend(struct dvb_frontend *fe,
2568                                    struct dtv_frontend_properties *p)
2569 {
2570         struct stv0367_state *state = fe->demodulator_priv;
2571         struct stv0367cab_state *cab_state = state->cab_state;
2572         u32 ifkhz = 0;
2573
2574         enum stv0367cab_mod QAMSize;
2575
2576         dprintk("%s:\n", __func__);
2577
2578         stv0367_get_if_khz(state, &ifkhz);
2579         p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
2580
2581         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2582         switch (QAMSize) {
2583         case FE_CAB_MOD_QAM16:
2584                 p->modulation = QAM_16;
2585                 break;
2586         case FE_CAB_MOD_QAM32:
2587                 p->modulation = QAM_32;
2588                 break;
2589         case FE_CAB_MOD_QAM64:
2590                 p->modulation = QAM_64;
2591                 break;
2592         case FE_CAB_MOD_QAM128:
2593                 p->modulation = QAM_128;
2594                 break;
2595         case FE_CAB_MOD_QAM256:
2596                 p->modulation = QAM_256;
2597                 break;
2598         default:
2599                 break;
2600         }
2601
2602         p->frequency = stv0367_get_tuner_freq(fe);
2603
2604         dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
2605
2606         if (ifkhz == 0) {
2607                 p->frequency +=
2608                         (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
2609                         cab_state->adc_clk / 4000);
2610                 return 0;
2611         }
2612
2613         if (ifkhz > cab_state->adc_clk / 1000)
2614                 p->frequency += (ifkhz
2615                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2616                         - cab_state->adc_clk / 1000);
2617         else
2618                 p->frequency += (ifkhz
2619                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
2620
2621         return 0;
2622 }
2623
2624 #if 0
2625 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
2626                         u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
2627 {
2628         stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
2629         stv0367cab_GetPacketsCount(state, Monitor_results);
2630
2631         return;
2632 }
2633
2634 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
2635 {
2636         struct stv0367_state *state = fe->demodulator_priv;
2637
2638         return 0;
2639 }
2640 #endif
2641 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
2642 {
2643         s32 rfLevel = 0;
2644         s32 RfAgcPwm = 0, IfAgcPwm = 0;
2645         u8 i;
2646
2647         stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
2648
2649         RfAgcPwm =
2650                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
2651                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
2652         RfAgcPwm = 100 * RfAgcPwm / 1023;
2653
2654         IfAgcPwm =
2655                 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
2656                 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
2657         if (IfAgcPwm >= 2048)
2658                 IfAgcPwm -= 2048;
2659         else
2660                 IfAgcPwm += 2048;
2661
2662         IfAgcPwm = 100 * IfAgcPwm / 4095;
2663
2664         /* For DTT75467 on NIM */
2665         if (RfAgcPwm < 90  && IfAgcPwm < 28) {
2666                 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
2667                         if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
2668                                 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
2669                                 break;
2670                         }
2671                 }
2672                 if (i == RF_LOOKUP_TABLE_SIZE)
2673                         rfLevel = -56;
2674         } else { /*if IF AGC>10*/
2675                 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
2676                         if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
2677                                 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
2678                                 break;
2679                         }
2680                 }
2681                 if (i == RF_LOOKUP_TABLE2_SIZE)
2682                         rfLevel = -72;
2683         }
2684         return rfLevel;
2685 }
2686
2687 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
2688 {
2689         struct stv0367_state *state = fe->demodulator_priv;
2690
2691         s32 signal =  stv0367cab_get_rf_lvl(state);
2692
2693         dprintk("%s: signal=%d dBm\n", __func__, signal);
2694
2695         if (signal <= -72)
2696                 *strength = 65535;
2697         else
2698                 *strength = (22 + signal) * (-1311);
2699
2700         dprintk("%s: strength=%d\n", __func__, (*strength));
2701
2702         return 0;
2703 }
2704
2705 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
2706 {
2707         struct stv0367_state *state = fe->demodulator_priv;
2708         u32 noisepercentage;
2709         enum stv0367cab_mod QAMSize;
2710         u32 regval = 0, temp = 0;
2711         int power, i;
2712
2713         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2714         switch (QAMSize) {
2715         case FE_CAB_MOD_QAM4:
2716                 power = 21904;
2717                 break;
2718         case FE_CAB_MOD_QAM16:
2719                 power = 20480;
2720                 break;
2721         case FE_CAB_MOD_QAM32:
2722                 power = 23040;
2723                 break;
2724         case FE_CAB_MOD_QAM64:
2725                 power = 21504;
2726                 break;
2727         case FE_CAB_MOD_QAM128:
2728                 power = 23616;
2729                 break;
2730         case FE_CAB_MOD_QAM256:
2731                 power = 21760;
2732                 break;
2733         case FE_CAB_MOD_QAM512:
2734                 power = 1;
2735                 break;
2736         case FE_CAB_MOD_QAM1024:
2737                 power = 21280;
2738                 break;
2739         default:
2740                 power = 1;
2741                 break;
2742         }
2743
2744         for (i = 0; i < 10; i++) {
2745                 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
2746                         + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
2747         }
2748
2749         regval /= 10; /*for average over 10 times in for loop above*/
2750         if (regval != 0) {
2751                 temp = power
2752                         * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
2753                 temp /= regval;
2754         }
2755
2756         /* table values, not needed to calculate logarithms */
2757         if (temp >= 5012)
2758                 noisepercentage = 100;
2759         else if (temp >= 3981)
2760                 noisepercentage = 93;
2761         else if (temp >= 3162)
2762                 noisepercentage = 86;
2763         else if (temp >= 2512)
2764                 noisepercentage = 79;
2765         else if (temp >= 1995)
2766                 noisepercentage = 72;
2767         else if (temp >= 1585)
2768                 noisepercentage = 65;
2769         else if (temp >= 1259)
2770                 noisepercentage = 58;
2771         else if (temp >= 1000)
2772                 noisepercentage = 50;
2773         else if (temp >= 794)
2774                 noisepercentage = 43;
2775         else if (temp >= 501)
2776                 noisepercentage = 36;
2777         else if (temp >= 316)
2778                 noisepercentage = 29;
2779         else if (temp >= 200)
2780                 noisepercentage = 22;
2781         else if (temp >= 158)
2782                 noisepercentage = 14;
2783         else if (temp >= 126)
2784                 noisepercentage = 7;
2785         else
2786                 noisepercentage = 0;
2787
2788         dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
2789
2790         *snr = (noisepercentage * 65535) / 100;
2791
2792         return 0;
2793 }
2794
2795 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
2796 {
2797         struct stv0367_state *state = fe->demodulator_priv;
2798         int corrected, tscount;
2799
2800         *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
2801                         | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
2802         corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
2803                         | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
2804         tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
2805                         | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
2806
2807         dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
2808                                 __func__, *ucblocks, corrected, tscount);
2809
2810         return 0;
2811 };
2812
2813 static const struct dvb_frontend_ops stv0367cab_ops = {
2814         .delsys = { SYS_DVBC_ANNEX_A },
2815         .info = {
2816                 .name = "ST STV0367 DVB-C",
2817                 .frequency_min = 47000000,
2818                 .frequency_max = 862000000,
2819                 .frequency_stepsize = 62500,
2820                 .symbol_rate_min = 870000,
2821                 .symbol_rate_max = 11700000,
2822                 .caps = 0x400 |/* FE_CAN_QAM_4 */
2823                         FE_CAN_QAM_16 | FE_CAN_QAM_32  |
2824                         FE_CAN_QAM_64 | FE_CAN_QAM_128 |
2825                         FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
2826         },
2827         .release                                = stv0367_release,
2828         .init                                   = stv0367cab_init,
2829         .sleep                                  = stv0367cab_sleep,
2830         .i2c_gate_ctrl                          = stv0367cab_gate_ctrl,
2831         .set_frontend                           = stv0367cab_set_frontend,
2832         .get_frontend                           = stv0367cab_get_frontend,
2833         .read_status                            = stv0367cab_read_status,
2834 /*      .read_ber                               = stv0367cab_read_ber, */
2835         .read_signal_strength                   = stv0367cab_read_strength,
2836         .read_snr                               = stv0367cab_read_snr,
2837         .read_ucblocks                          = stv0367cab_read_ucblcks,
2838         .get_tune_settings                      = stv0367_get_tune_settings,
2839 };
2840
2841 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
2842                                    struct i2c_adapter *i2c)
2843 {
2844         struct stv0367_state *state = NULL;
2845         struct stv0367cab_state *cab_state = NULL;
2846
2847         /* allocate memory for the internal state */
2848         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2849         if (state == NULL)
2850                 goto error;
2851         cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
2852         if (cab_state == NULL)
2853                 goto error;
2854
2855         /* setup the state */
2856         state->i2c = i2c;
2857         state->config = config;
2858         cab_state->search_range = 280000;
2859         cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
2860         state->cab_state = cab_state;
2861         state->fe.ops = stv0367cab_ops;
2862         state->fe.demodulator_priv = state;
2863         state->chip_id = stv0367_readreg(state, 0xf000);
2864
2865         /* demod operation options */
2866         state->use_i2c_gatectrl = 1;
2867         state->deftabs = STV0367_DEFTAB_GENERIC;
2868         state->reinit_on_setfrontend = 1;
2869         state->auto_if_khz = 0;
2870
2871         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2872
2873         /* check if the demod is there */
2874         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2875                 goto error;
2876
2877         return &state->fe;
2878
2879 error:
2880         kfree(cab_state);
2881         kfree(state);
2882         return NULL;
2883 }
2884 EXPORT_SYMBOL(stv0367cab_attach);
2885
2886 /*
2887  * Functions for operation on Digital Devices hardware
2888  */
2889
2890 static void stv0367ddb_setup_ter(struct stv0367_state *state)
2891 {
2892         stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2893         stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2894         stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2895         stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2896         stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2897         stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2898
2899         /* Tuner Setup */
2900         /* Buffer Q disabled, I Enabled, unsigned ADC */
2901         stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2902         stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2903
2904         /* Clock setup */
2905         /* PLL bypassed and disabled */
2906         stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2907         stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2908
2909         /* IC runs at 54 MHz with a 27 MHz crystal */
2910         stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
2911
2912         msleep(50);
2913         /* PLL enabled and used */
2914         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2915
2916         state->activedemod = demod_ter;
2917 }
2918
2919 static void stv0367ddb_setup_cab(struct stv0367_state *state)
2920 {
2921         stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2922         stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2923         stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2924         stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2925         stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2926         stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2927
2928         /* Tuner Setup */
2929         /* Buffer Q disabled, I Enabled, signed ADC */
2930         stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2931         /* ADCQ disabled */
2932         stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2933
2934         /* Clock setup */
2935         /* PLL bypassed and disabled */
2936         stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2937         /* Set QAM */
2938         stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2939
2940         /* IC runs at 58 MHz with a 27 MHz crystal */
2941         stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
2942
2943         msleep(50);
2944         /* PLL enabled and used */
2945         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2946
2947         state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
2948                 state->config->xtal);
2949         state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
2950                 state->config->xtal);
2951
2952         state->activedemod = demod_cab;
2953 }
2954
2955 static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
2956 {
2957         struct stv0367_state *state = fe->demodulator_priv;
2958
2959         switch (fe->dtv_property_cache.delivery_system) {
2960         case SYS_DVBT:
2961                 if (state->activedemod != demod_ter)
2962                         stv0367ddb_setup_ter(state);
2963
2964                 return stv0367ter_set_frontend(fe);
2965         case SYS_DVBC_ANNEX_A:
2966                 if (state->activedemod != demod_cab)
2967                         stv0367ddb_setup_cab(state);
2968
2969                 /* protect against division error oopses */
2970                 if (fe->dtv_property_cache.symbol_rate == 0) {
2971                         printk(KERN_ERR "Invalid symbol rate\n");
2972                         return -EINVAL;
2973                 }
2974
2975                 return stv0367cab_set_frontend(fe);
2976         default:
2977                 break;
2978         }
2979
2980         return -EINVAL;
2981 }
2982
2983 static int stv0367ddb_read_status(struct dvb_frontend *fe,
2984                                   enum fe_status *status)
2985 {
2986         struct stv0367_state *state = fe->demodulator_priv;
2987
2988         switch (state->activedemod) {
2989         case demod_ter:
2990                 return stv0367ter_read_status(fe, status);
2991         case demod_cab:
2992                 return stv0367cab_read_status(fe, status);
2993         default:
2994                 break;
2995         }
2996
2997         return -EINVAL;
2998 }
2999
3000 static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
3001                                    struct dtv_frontend_properties *p)
3002 {
3003         struct stv0367_state *state = fe->demodulator_priv;
3004
3005         switch (state->activedemod) {
3006         case demod_ter:
3007                 return stv0367ter_get_frontend(fe, p);
3008         case demod_cab:
3009                 return stv0367cab_get_frontend(fe, p);
3010         default:
3011                 break;
3012         }
3013
3014         return -EINVAL;
3015 }
3016
3017 static int stv0367ddb_sleep(struct dvb_frontend *fe)
3018 {
3019         struct stv0367_state *state = fe->demodulator_priv;
3020
3021         switch (state->activedemod) {
3022         case demod_ter:
3023                 state->activedemod = demod_none;
3024                 return stv0367ter_sleep(fe);
3025         case demod_cab:
3026                 state->activedemod = demod_none;
3027                 return stv0367cab_sleep(fe);
3028         default:
3029                 break;
3030         }
3031
3032         return -EINVAL;
3033 }
3034
3035 static int stv0367ddb_init(struct stv0367_state *state)
3036 {
3037         struct stv0367ter_state *ter_state = state->ter_state;
3038
3039         stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3040
3041         if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
3042                 stv0367_write_table(state,
3043                         stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
3044
3045         stv0367_write_table(state,
3046                 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
3047
3048         stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3049         stv0367_write_table(state,
3050                 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
3051
3052         stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3053         stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3054         stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3055         stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3056         stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3057         stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3058         stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3059         stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3060
3061         /* OFDM TS Setup */
3062
3063         stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3064         stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3065         stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3066         stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3067
3068         stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3069         stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3070
3071         stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3072
3073         /* Also needed for QAM */
3074         stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3075
3076         stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3077
3078         /* QAM TS setup, note exact format also depends on descrambler */
3079         /* settings */
3080         /* Inverted Clock, Swap, serial */
3081         stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3082
3083         /* Clock setup (PLL bypassed and disabled) */
3084         stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3085
3086         /* IC runs at 58 MHz with a 27 MHz crystal */
3087         stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
3088
3089         /* Tuner setup */
3090         /* Buffer Q disabled, I Enabled, signed ADC */
3091         stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3092         stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3093
3094         /* Improves the C/N lock limit */
3095         stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3096         /* ZIF/IF Automatic mode */
3097         stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3098         /* Improving burst noise performances */
3099         stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3100         /* Improving ACI performances */
3101         stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3102
3103         /* PLL enabled and used */
3104         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3105
3106         stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
3107
3108         ter_state->pBER = 0;
3109         ter_state->first_lock = 0;
3110         ter_state->unlock_counter = 2;
3111
3112         return 0;
3113 }
3114
3115 static const struct dvb_frontend_ops stv0367ddb_ops = {
3116         .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
3117         .info = {
3118                 .name                   = "ST STV0367 DDB DVB-C/T",
3119                 .frequency_min          = 47000000,
3120                 .frequency_max          = 865000000,
3121                 .frequency_stepsize     = 166667,
3122                 .frequency_tolerance    = 0,
3123                 .symbol_rate_min        = 870000,
3124                 .symbol_rate_max        = 11700000,
3125                 .caps = /* DVB-C */
3126                         0x400 |/* FE_CAN_QAM_4 */
3127                         FE_CAN_QAM_16 | FE_CAN_QAM_32  |
3128                         FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3129                         FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
3130                         /* DVB-T */
3131                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
3132                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
3133                         FE_CAN_FEC_AUTO |
3134                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
3135                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
3136                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
3137                         FE_CAN_INVERSION_AUTO |
3138                         FE_CAN_MUTE_TS
3139         },
3140         .release = stv0367_release,
3141         .sleep = stv0367ddb_sleep,
3142         .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
3143         .set_frontend = stv0367ddb_set_frontend,
3144         .get_frontend = stv0367ddb_get_frontend,
3145         .get_tune_settings = stv0367_get_tune_settings,
3146         .read_status = stv0367ddb_read_status,
3147 };
3148
3149 struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
3150                                    struct i2c_adapter *i2c)
3151 {
3152         struct stv0367_state *state = NULL;
3153         struct stv0367ter_state *ter_state = NULL;
3154         struct stv0367cab_state *cab_state = NULL;
3155
3156         /* allocate memory for the internal state */
3157         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3158         if (state == NULL)
3159                 goto error;
3160         ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
3161         if (ter_state == NULL)
3162                 goto error;
3163         cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3164         if (cab_state == NULL)
3165                 goto error;
3166
3167         /* setup the state */
3168         state->i2c = i2c;
3169         state->config = config;
3170         state->ter_state = ter_state;
3171         cab_state->search_range = 280000;
3172         cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
3173         state->cab_state = cab_state;
3174         state->fe.ops = stv0367ddb_ops;
3175         state->fe.demodulator_priv = state;
3176         state->chip_id = stv0367_readreg(state, R367TER_ID);
3177
3178         /* demod operation options */
3179         state->use_i2c_gatectrl = 0;
3180         state->deftabs = STV0367_DEFTAB_DDB;
3181         state->reinit_on_setfrontend = 0;
3182         state->auto_if_khz = 1;
3183         state->activedemod = demod_none;
3184
3185         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3186
3187         /* check if the demod is there */
3188         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3189                 goto error;
3190
3191         dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
3192                 state->fe.ops.info.name, state->chip_id,
3193                 config->demod_address);
3194
3195         stv0367ddb_init(state);
3196
3197         return &state->fe;
3198
3199 error:
3200         kfree(cab_state);
3201         kfree(ter_state);
3202         kfree(state);
3203         return NULL;
3204 }
3205 EXPORT_SYMBOL(stv0367ddb_attach);
3206
3207 MODULE_PARM_DESC(debug, "Set debug");
3208 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3209
3210 MODULE_AUTHOR("Igor M. Liplianin");
3211 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3212 MODULE_LICENSE("GPL");