4 * Driver for ST STV0900 satellite demodulator IC.
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include "stv0900_reg.h"
24 #include "stv0900_priv.h"
26 s32 shiftx(s32 x, int demod, s32 shift)
34 int stv0900_check_signal_presence(struct stv0900_internal *intp,
35 enum fe_stv0900_demod_num demod)
41 int no_signal = FALSE;
43 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
44 | stv0900_read_reg(intp, CFR1);
45 carr_offset = ge2comp(carr_offset, 16);
46 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
47 | stv0900_read_reg(intp, AGC2I0);
48 max_carrier = intp->srch_range[demod] / 1000;
50 max_carrier += (max_carrier / 10);
51 max_carrier = 65536 * (max_carrier / 2);
52 max_carrier /= intp->mclk / 1000;
53 if (max_carrier > 0x4000)
56 if ((agc2_integr > 0x2000)
57 || (carr_offset > (2 * max_carrier))
58 || (carr_offset < (-2 * max_carrier)))
64 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
65 s32 *frequency_inc, s32 *sw_timeout,
67 enum fe_stv0900_demod_num demod)
69 s32 timeout, freq_inc, max_steps, srate, max_carrier;
71 enum fe_stv0900_search_standard standard;
73 srate = intp->symbol_rate[demod];
74 max_carrier = intp->srch_range[demod] / 1000;
75 max_carrier += max_carrier / 10;
76 standard = intp->srch_standard[demod];
78 max_carrier = 65536 * (max_carrier / 2);
79 max_carrier /= intp->mclk / 1000;
81 if (max_carrier > 0x4000)
85 freq_inc /= intp->mclk >> 10;
86 freq_inc = freq_inc << 6;
89 case STV0900_SEARCH_DVBS1:
90 case STV0900_SEARCH_DSS:
94 case STV0900_SEARCH_DVBS2:
98 case STV0900_AUTO_SEARCH:
107 if ((freq_inc > max_carrier) || (freq_inc < 0))
108 freq_inc = max_carrier / 2;
113 timeout /= srate / 1000;
115 if ((timeout > 100) || (timeout < 0))
118 max_steps = (max_carrier / freq_inc) + 1;
120 if ((max_steps > 100) || (max_steps < 0)) {
122 freq_inc = max_carrier / max_steps;
125 *frequency_inc = freq_inc;
126 *sw_timeout = timeout;
131 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
132 s32 FreqIncr, s32 Timeout, int zigzag,
133 s32 MaxStep, enum fe_stv0900_demod_num demod)
141 max_carrier = intp->srch_range[demod] / 1000;
142 max_carrier += (max_carrier / 10);
144 max_carrier = 65536 * (max_carrier / 2);
145 max_carrier /= intp->mclk / 1000;
147 if (max_carrier > 0x4000)
148 max_carrier = 0x4000;
153 freqOffset = -max_carrier + FreqIncr;
158 stv0900_write_reg(intp, DMDISTATE, 0x1c);
159 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
160 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
161 stv0900_write_reg(intp, DMDISTATE, 0x18);
162 stv0900_write_bits(intp, ALGOSWRST, 1);
164 if (intp->chip_id == 0x12) {
165 stv0900_write_bits(intp, RST_HWARE, 1);
166 stv0900_write_bits(intp, RST_HWARE, 0);
169 if (zigzag == TRUE) {
171 freqOffset = -freqOffset - 2 * FreqIncr;
173 freqOffset = -freqOffset;
175 freqOffset += + 2 * FreqIncr;
178 lock = stv0900_get_demod_lock(intp, demod, Timeout);
179 no_signal = stv0900_check_signal_presence(intp, demod);
181 } while ((lock == FALSE)
182 && (no_signal == FALSE)
183 && ((freqOffset - FreqIncr) < max_carrier)
184 && ((freqOffset + FreqIncr) > -max_carrier)
185 && (stepCpt < MaxStep));
187 stv0900_write_bits(intp, ALGOSWRST, 0);
192 static int stv0900_sw_algo(struct stv0900_internal *intp,
193 enum fe_stv0900_demod_num demod)
204 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
206 switch (intp->srch_standard[demod]) {
207 case STV0900_SEARCH_DVBS1:
208 case STV0900_SEARCH_DSS:
209 if (intp->chip_id >= 0x20)
210 stv0900_write_reg(intp, CARFREQ, 0x3b);
212 stv0900_write_reg(intp, CARFREQ, 0xef);
214 stv0900_write_reg(intp, DMDCFGMD, 0x49);
217 case STV0900_SEARCH_DVBS2:
218 if (intp->chip_id >= 0x20)
219 stv0900_write_reg(intp, CORRELABS, 0x79);
221 stv0900_write_reg(intp, CORRELABS, 0x68);
223 stv0900_write_reg(intp, DMDCFGMD, 0x89);
227 case STV0900_AUTO_SEARCH:
229 if (intp->chip_id >= 0x20) {
230 stv0900_write_reg(intp, CARFREQ, 0x3b);
231 stv0900_write_reg(intp, CORRELABS, 0x79);
233 stv0900_write_reg(intp, CARFREQ, 0xef);
234 stv0900_write_reg(intp, CORRELABS, 0x68);
237 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
244 lock = stv0900_search_carr_sw_loop(intp,
250 no_signal = stv0900_check_signal_presence(intp, demod);
253 || (no_signal == TRUE)
254 || (trial_cntr == 2)) {
256 if (intp->chip_id >= 0x20) {
257 stv0900_write_reg(intp, CARFREQ, 0x49);
258 stv0900_write_reg(intp, CORRELABS, 0x9e);
260 stv0900_write_reg(intp, CARFREQ, 0xed);
261 stv0900_write_reg(intp, CORRELABS, 0x88);
264 if ((stv0900_get_bits(intp, HEADER_MODE) ==
265 STV0900_DVBS2_FOUND) &&
267 msleep(sft_stp_tout);
268 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
271 msleep(sft_stp_tout);
272 s2fw = stv0900_get_bits(intp,
279 if (trial_cntr < 2) {
280 if (intp->chip_id >= 0x20)
281 stv0900_write_reg(intp,
285 stv0900_write_reg(intp,
289 stv0900_write_reg(intp,
297 } while ((lock == FALSE)
299 && (no_signal == FALSE));
304 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
306 enum fe_stv0900_demod_num demod)
308 s32 rem1, rem2, intval1, intval2, srate;
310 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
311 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
312 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
313 (stv0900_get_bits(intp, SYMB_FREQ0));
314 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
315 srate, stv0900_get_bits(intp, SYMB_FREQ0),
316 stv0900_get_bits(intp, SYMB_FREQ1),
317 stv0900_get_bits(intp, SYMB_FREQ2),
318 stv0900_get_bits(intp, SYMB_FREQ3));
320 intval1 = (mclk) >> 16;
321 intval2 = (srate) >> 16;
323 rem1 = (mclk) % 0x10000;
324 rem2 = (srate) % 0x10000;
325 srate = (intval1 * intval2) +
326 ((intval1 * rem2) >> 16) +
327 ((intval2 * rem1) >> 16);
332 static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
334 enum fe_stv0900_demod_num demod)
338 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
341 if (srate > 60000000) {
343 symb /= (mclk >> 12);
344 } else if (srate > 6000000) {
346 symb /= (mclk >> 10);
352 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
353 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
356 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
358 enum fe_stv0900_demod_num demod)
362 srate = 105 * (srate / 100);
364 if (srate > 60000000) {
366 symb /= (mclk >> 12);
367 } else if (srate > 6000000) {
369 symb /= (mclk >> 10);
376 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
377 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
379 stv0900_write_reg(intp, SFRUP1, 0x7f);
380 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
384 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
386 enum fe_stv0900_demod_num demod)
390 srate = 95 * (srate / 100);
391 if (srate > 60000000) {
393 symb /= (mclk >> 12);
395 } else if (srate > 6000000) {
397 symb /= (mclk >> 10);
404 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
405 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
408 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
410 enum fe_stv0900_demod_num demod)
415 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
416 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
417 (stv0900_read_reg(intp, TMGREG2 + 2));
419 timingoffset = ge2comp(timingoffset, 24);
422 if (timingoffset == 0)
425 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
431 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
432 enum fe_stv0900_demod_num demod)
436 if (intp->chip_id == 0x10) {
437 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
438 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
439 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
440 } else if (intp->chip_id <= 0x20)
441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
443 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
446 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
463 return srate + (srate * rolloff) / 100;
466 static int stv0900_check_timing_lock(struct stv0900_internal *intp,
467 enum fe_stv0900_demod_num demod)
469 int timingLock = FALSE;
476 car_freq = stv0900_read_reg(intp, CARFREQ);
477 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
478 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
479 stv0900_write_reg(intp, TMGTHRISE, 0x20);
480 stv0900_write_reg(intp, TMGTHFALL, 0x0);
481 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
482 stv0900_write_reg(intp, RTC, 0x80);
483 stv0900_write_reg(intp, RTCS2, 0x40);
484 stv0900_write_reg(intp, CARFREQ, 0x0);
485 stv0900_write_reg(intp, CFRINIT1, 0x0);
486 stv0900_write_reg(intp, CFRINIT0, 0x0);
487 stv0900_write_reg(intp, AGC2REF, 0x65);
488 stv0900_write_reg(intp, DMDISTATE, 0x18);
491 for (i = 0; i < 10; i++) {
492 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
501 stv0900_write_reg(intp, AGC2REF, 0x38);
502 stv0900_write_reg(intp, RTC, 0x88);
503 stv0900_write_reg(intp, RTCS2, 0x68);
504 stv0900_write_reg(intp, CARFREQ, car_freq);
505 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
506 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
511 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
514 struct stv0900_state *state = fe->demodulator_priv;
515 struct stv0900_internal *intp = state->internal;
516 enum fe_stv0900_demod_num demod = state->demod;
530 srate = intp->symbol_rate[d];
531 search_range = intp->srch_range[d];
533 if (srate >= 10000000)
534 locktimeout = demod_timeout / 3;
536 locktimeout = demod_timeout / 2;
538 lock = stv0900_get_demod_lock(intp, d, locktimeout);
543 if (srate >= 10000000) {
544 if (stv0900_check_timing_lock(intp, d) == TRUE) {
545 stv0900_write_reg(intp, DMDISTATE, 0x1f);
546 stv0900_write_reg(intp, DMDISTATE, 0x15);
547 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
554 if (intp->chip_id <= 0x20) {
555 if (srate <= 1000000)
557 else if (srate <= 4000000)
559 else if (srate <= 7000000)
561 else if (srate <= 10000000)
566 if (srate >= 2000000) {
567 timeout = (demod_timeout / 3);
571 timeout = (demod_timeout / 2);
574 currier_step = srate / 4000;
575 timeout = (demod_timeout * 3) / 4;
578 nb_steps = ((search_range / 1000) / currier_step);
580 if ((nb_steps % 2) != 0)
585 else if (nb_steps > 12)
591 if (intp->chip_id <= 0x20) {
592 tuner_freq = intp->freq[d];
593 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
594 intp->rolloff) + intp->symbol_rate[d];
598 while ((current_step <= nb_steps) && (lock == FALSE)) {
600 tuner_freq += (current_step * currier_step);
602 tuner_freq -= (current_step * currier_step);
604 if (intp->chip_id <= 0x20) {
605 if (intp->tuner_type[d] == 3)
606 stv0900_set_tuner_auto(intp, tuner_freq,
609 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
611 stv0900_write_reg(intp, DMDISTATE, 0x1c);
612 stv0900_write_reg(intp, CFRINIT1, 0);
613 stv0900_write_reg(intp, CFRINIT0, 0);
614 stv0900_write_reg(intp, DMDISTATE, 0x1f);
615 stv0900_write_reg(intp, DMDISTATE, 0x15);
617 stv0900_write_reg(intp, DMDISTATE, 0x1c);
618 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
619 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
620 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
621 stv0900_write_reg(intp, DMDISTATE, 0x1f);
622 stv0900_write_reg(intp, DMDISTATE, 0x05);
625 lock = stv0900_get_demod_lock(intp, d, timeout);
633 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
635 enum fe_stv0900_search_algo algo)
638 case STV0900_BLIND_SEARCH:
639 if (srate <= 1500000) {
640 (*demod_timeout) = 1500;
641 (*fec_timeout) = 400;
642 } else if (srate <= 5000000) {
643 (*demod_timeout) = 1000;
644 (*fec_timeout) = 300;
646 (*demod_timeout) = 700;
647 (*fec_timeout) = 100;
651 case STV0900_COLD_START:
652 case STV0900_WARM_START:
654 if (srate <= 1000000) {
655 (*demod_timeout) = 3000;
656 (*fec_timeout) = 1700;
657 } else if (srate <= 2000000) {
658 (*demod_timeout) = 2500;
659 (*fec_timeout) = 1100;
660 } else if (srate <= 5000000) {
661 (*demod_timeout) = 1000;
662 (*fec_timeout) = 550;
663 } else if (srate <= 10000000) {
664 (*demod_timeout) = 700;
665 (*fec_timeout) = 250;
666 } else if (srate <= 20000000) {
667 (*demod_timeout) = 400;
668 (*fec_timeout) = 130;
670 (*demod_timeout) = 300;
671 (*fec_timeout) = 100;
678 if (algo == STV0900_WARM_START)
679 (*demod_timeout) /= 2;
682 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
683 enum fe_stv0900_demod_num demod)
688 dprintk("%s\n", __func__);
690 stv0900_write_reg(intp, vth_reg++, 0xd0);
691 stv0900_write_reg(intp, vth_reg++, 0x7d);
692 stv0900_write_reg(intp, vth_reg++, 0x53);
693 stv0900_write_reg(intp, vth_reg++, 0x2f);
694 stv0900_write_reg(intp, vth_reg++, 0x24);
695 stv0900_write_reg(intp, vth_reg++, 0x1f);
698 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
699 enum fe_stv0900_search_standard standard,
700 enum fe_stv0900_fec fec,
701 enum fe_stv0900_demod_num demod)
703 dprintk("%s: ViterbiStandard = ", __func__);
706 case STV0900_AUTO_SEARCH:
708 stv0900_write_reg(intp, FECM, 0x10);
709 stv0900_write_reg(intp, PRVIT, 0x3f);
711 case STV0900_SEARCH_DVBS1:
713 stv0900_write_reg(intp, FECM, 0x00);
715 case STV0900_FEC_UNKNOWN:
717 stv0900_write_reg(intp, PRVIT, 0x2f);
719 case STV0900_FEC_1_2:
720 stv0900_write_reg(intp, PRVIT, 0x01);
722 case STV0900_FEC_2_3:
723 stv0900_write_reg(intp, PRVIT, 0x02);
725 case STV0900_FEC_3_4:
726 stv0900_write_reg(intp, PRVIT, 0x04);
728 case STV0900_FEC_5_6:
729 stv0900_write_reg(intp, PRVIT, 0x08);
731 case STV0900_FEC_7_8:
732 stv0900_write_reg(intp, PRVIT, 0x20);
737 case STV0900_SEARCH_DSS:
739 stv0900_write_reg(intp, FECM, 0x80);
741 case STV0900_FEC_UNKNOWN:
743 stv0900_write_reg(intp, PRVIT, 0x13);
745 case STV0900_FEC_1_2:
746 stv0900_write_reg(intp, PRVIT, 0x01);
748 case STV0900_FEC_2_3:
749 stv0900_write_reg(intp, PRVIT, 0x02);
751 case STV0900_FEC_6_7:
752 stv0900_write_reg(intp, PRVIT, 0x10);
761 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
762 enum fe_stv0900_demod_num demod)
764 enum fe_stv0900_fec prate;
765 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
769 prate = STV0900_FEC_1_2;
772 prate = STV0900_FEC_2_3;
775 prate = STV0900_FEC_3_4;
778 prate = STV0900_FEC_5_6;
781 prate = STV0900_FEC_6_7;
784 prate = STV0900_FEC_7_8;
787 prate = STV0900_FEC_UNKNOWN;
794 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
795 enum fe_stv0900_demod_num demod,
798 if (intp->chip_id >= 0x30) {
799 if (srate >= 15000000) {
800 stv0900_write_reg(intp, ACLC, 0x2b);
801 stv0900_write_reg(intp, BCLC, 0x1a);
802 } else if ((srate >= 7000000) && (15000000 > srate)) {
803 stv0900_write_reg(intp, ACLC, 0x0c);
804 stv0900_write_reg(intp, BCLC, 0x1b);
805 } else if (srate < 7000000) {
806 stv0900_write_reg(intp, ACLC, 0x2c);
807 stv0900_write_reg(intp, BCLC, 0x1c);
810 } else { /*cut 2.0 and 1.x*/
811 stv0900_write_reg(intp, ACLC, 0x1a);
812 stv0900_write_reg(intp, BCLC, 0x09);
817 static void stv0900_track_optimization(struct dvb_frontend *fe)
819 struct stv0900_state *state = fe->demodulator_priv;
820 struct stv0900_internal *intp = state->internal;
821 enum fe_stv0900_demod_num demod = state->demod;
834 enum fe_stv0900_modcode foundModcod;
836 dprintk("%s\n", __func__);
838 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
839 srate += stv0900_get_timing_offst(intp, srate, demod);
841 switch (intp->result[demod].standard) {
842 case STV0900_DVBS1_STANDARD:
843 case STV0900_DSS_STANDARD:
844 dprintk("%s: found DVB-S or DSS\n", __func__);
845 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
846 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
847 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
850 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
851 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
853 if (intp->chip_id < 0x30) {
854 stv0900_write_reg(intp, ERRCTRL1, 0x75);
858 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
859 stv0900_write_reg(intp, GAUSSR0, 0x98);
860 stv0900_write_reg(intp, CCIR0, 0x18);
862 stv0900_write_reg(intp, GAUSSR0, 0x18);
863 stv0900_write_reg(intp, CCIR0, 0x18);
866 stv0900_write_reg(intp, ERRCTRL1, 0x75);
868 case STV0900_DVBS2_STANDARD:
869 dprintk("%s: found DVB-S2\n", __func__);
870 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
871 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
872 stv0900_write_reg(intp, ACLC, 0);
873 stv0900_write_reg(intp, BCLC, 0);
874 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
875 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
876 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
877 aclc = stv0900_get_optim_carr_loop(srate,
881 if (foundModcod <= STV0900_QPSK_910)
882 stv0900_write_reg(intp, ACLC2S2Q, aclc);
883 else if (foundModcod <= STV0900_8PSK_910) {
884 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
885 stv0900_write_reg(intp, ACLC2S28, aclc);
888 if ((intp->demod_mode == STV0900_SINGLE) &&
889 (foundModcod > STV0900_8PSK_910)) {
890 if (foundModcod <= STV0900_16APSK_910) {
891 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
892 stv0900_write_reg(intp, ACLC2S216A,
894 } else if (foundModcod <= STV0900_32APSK_910) {
895 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
896 stv0900_write_reg(intp, ACLC2S232A,
902 modulation = intp->result[demod].modulation;
903 aclc = stv0900_get_optim_short_carr_loop(srate,
904 modulation, intp->chip_id);
905 if (modulation == STV0900_QPSK)
906 stv0900_write_reg(intp, ACLC2S2Q, aclc);
907 else if (modulation == STV0900_8PSK) {
908 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
909 stv0900_write_reg(intp, ACLC2S28, aclc);
910 } else if (modulation == STV0900_16APSK) {
911 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
912 stv0900_write_reg(intp, ACLC2S216A, aclc);
913 } else if (modulation == STV0900_32APSK) {
914 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
915 stv0900_write_reg(intp, ACLC2S232A, aclc);
920 if (intp->chip_id <= 0x11) {
921 if (intp->demod_mode != STV0900_SINGLE)
922 stv0900_activate_s2_modcod(intp, demod);
926 stv0900_write_reg(intp, ERRCTRL1, 0x67);
928 case STV0900_UNKNOWN_STANDARD:
930 dprintk("%s: found unknown standard\n", __func__);
931 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
932 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
936 freq1 = stv0900_read_reg(intp, CFR2);
937 freq0 = stv0900_read_reg(intp, CFR1);
938 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
939 stv0900_write_reg(intp, SFRSTEP, 0x00);
940 stv0900_write_bits(intp, SCAN_ENABLE, 0);
941 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
942 stv0900_write_reg(intp, TMGCFG2, 0xc1);
943 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
945 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
946 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
950 if (intp->chip_id >= 0x20) {
951 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
952 (intp->srch_standard[demod] ==
953 STV0900_SEARCH_DSS) ||
954 (intp->srch_standard[demod] ==
955 STV0900_AUTO_SEARCH)) {
956 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
957 stv0900_write_reg(intp, VITSCALE, 0x0);
961 if (intp->chip_id < 0x20)
962 stv0900_write_reg(intp, CARHDR, 0x08);
964 if (intp->chip_id == 0x10)
965 stv0900_write_reg(intp, CORRELEXP, 0x0a);
967 stv0900_write_reg(intp, AGC2REF, 0x38);
969 if ((intp->chip_id >= 0x20) ||
970 (blind_tun_sw == 1) ||
971 (intp->symbol_rate[demod] < 10000000)) {
972 stv0900_write_reg(intp, CFRINIT1, freq1);
973 stv0900_write_reg(intp, CFRINIT0, freq0);
974 intp->bw[demod] = stv0900_carrier_width(srate,
975 intp->rolloff) + 10000000;
977 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
978 if (intp->srch_algo[demod] != STV0900_WARM_START) {
979 if (intp->tuner_type[demod] == 3)
980 stv0900_set_tuner_auto(intp,
985 stv0900_set_bandwidth(fe,
990 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
991 (intp->symbol_rate[demod] < 10000000))
996 stv0900_get_lock_timeout(&timed, &timef, srate,
999 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
1000 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1001 stv0900_write_reg(intp, CFRINIT1, freq1);
1002 stv0900_write_reg(intp, CFRINIT0, freq0);
1003 stv0900_write_reg(intp, DMDISTATE, 0x18);
1005 while ((stv0900_get_demod_lock(intp,
1007 timed / 2) == FALSE) &&
1009 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1010 stv0900_write_reg(intp, CFRINIT1, freq1);
1011 stv0900_write_reg(intp, CFRINIT0, freq0);
1012 stv0900_write_reg(intp, DMDISTATE, 0x18);
1019 if (intp->chip_id >= 0x20)
1020 stv0900_write_reg(intp, CARFREQ, 0x49);
1022 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1023 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1024 stv0900_set_viterbi_tracq(intp, demod);
1028 static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1029 enum fe_stv0900_demod_num demod, s32 time_out)
1031 s32 timer = 0, lock = 0;
1033 enum fe_stv0900_search_state dmd_state;
1035 dprintk("%s\n", __func__);
1037 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1039 while ((timer < time_out) && (lock == 0)) {
1040 switch (dmd_state) {
1041 case STV0900_SEARCH:
1042 case STV0900_PLH_DETECTED:
1046 case STV0900_DVBS2_FOUND:
1047 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1049 case STV0900_DVBS_FOUND:
1050 lock = stv0900_get_bits(intp, LOCKEDVIT);
1061 dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1063 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1068 static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1069 enum fe_stv0900_demod_num demod,
1070 s32 dmd_timeout, s32 fec_timeout)
1073 s32 timer = 0, lock = 0;
1075 dprintk("%s\n", __func__);
1077 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1080 lock = stv0900_get_fec_lock(intp, demod, fec_timeout);
1085 dprintk("%s: Timer = %d, time_out = %d\n",
1086 __func__, timer, fec_timeout);
1088 while ((timer < fec_timeout) && (lock == 0)) {
1089 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1096 dprintk("%s: DEMOD LOCK OK\n", __func__);
1098 dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1106 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1107 enum fe_stv0900_demod_num demod)
1109 struct stv0900_state *state = fe->demodulator_priv;
1110 struct stv0900_internal *intp = state->internal;
1111 enum fe_stv0900_tracking_standard fnd_standard;
1113 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1117 fnd_standard = STV0900_DVBS2_STANDARD;
1120 if (stv0900_get_bits(intp, DSS_DVB) == 1)
1121 fnd_standard = STV0900_DSS_STANDARD;
1123 fnd_standard = STV0900_DVBS1_STANDARD;
1127 fnd_standard = STV0900_UNKNOWN_STANDARD;
1130 dprintk("%s: standard %d\n", __func__, fnd_standard);
1132 return fnd_standard;
1135 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1136 enum fe_stv0900_demod_num demod)
1144 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1145 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1146 (stv0900_get_bits(intp, CAR_FREQ0));
1148 derot = ge2comp(derot, 24);
1149 intval1 = mclk >> 12;
1150 intval2 = derot >> 12;
1151 rem1 = mclk % 0x1000;
1152 rem2 = derot % 0x1000;
1153 derot = (intval1 * intval2) +
1154 ((intval1 * rem2) >> 12) +
1155 ((intval2 * rem1) >> 12);
1160 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1162 struct dvb_frontend_ops *frontend_ops = NULL;
1163 struct dvb_tuner_ops *tuner_ops = NULL;
1166 frontend_ops = &fe->ops;
1167 tuner_ops = &frontend_ops->tuner_ops;
1169 if (tuner_ops->get_frequency) {
1170 if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1171 dprintk("%s: Invalid parameter\n", __func__);
1173 dprintk("%s: Frequency=%d\n", __func__, freq);
1181 fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1183 struct stv0900_state *state = fe->demodulator_priv;
1184 struct stv0900_internal *intp = state->internal;
1185 enum fe_stv0900_demod_num demod = state->demod;
1186 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1187 struct stv0900_signal_info *result = &intp->result[demod];
1196 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1197 timing = stv0900_read_reg(intp, TMGREG2);
1199 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1201 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1202 timing = stv0900_read_reg(intp, TMGREG2);
1208 result->standard = stv0900_get_standard(fe, d);
1209 if (intp->tuner_type[demod] == 3)
1210 result->frequency = stv0900_get_freq_auto(intp, d);
1212 result->frequency = stv0900_get_tuner_freq(fe);
1214 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1215 result->frequency += offsetFreq;
1216 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1217 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1218 result->symbol_rate += srate_offset;
1219 result->fec = stv0900_get_vit_fec(intp, d);
1220 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1221 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1222 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1223 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1225 dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
1227 switch (result->standard) {
1228 case STV0900_DVBS2_STANDARD:
1229 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1230 if (result->modcode <= STV0900_QPSK_910)
1231 result->modulation = STV0900_QPSK;
1232 else if (result->modcode <= STV0900_8PSK_910)
1233 result->modulation = STV0900_8PSK;
1234 else if (result->modcode <= STV0900_16APSK_910)
1235 result->modulation = STV0900_16APSK;
1236 else if (result->modcode <= STV0900_32APSK_910)
1237 result->modulation = STV0900_32APSK;
1239 result->modulation = STV0900_UNKNOWN;
1241 case STV0900_DVBS1_STANDARD:
1242 case STV0900_DSS_STANDARD:
1243 result->spectrum = stv0900_get_bits(intp, IQINV);
1244 result->modulation = STV0900_QPSK;
1250 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1251 (intp->symbol_rate[d] < 10000000)) {
1252 offsetFreq = result->frequency - intp->freq[d];
1253 if (intp->tuner_type[demod] == 3)
1254 intp->freq[d] = stv0900_get_freq_auto(intp, d);
1256 intp->freq[d] = stv0900_get_tuner_freq(fe);
1258 if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1259 range = STV0900_RANGEOK;
1260 else if (ABS(offsetFreq) <=
1261 (stv0900_carrier_width(result->symbol_rate,
1262 result->rolloff) / 2000))
1263 range = STV0900_RANGEOK;
1265 } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1266 range = STV0900_RANGEOK;
1268 dprintk("%s: range %d\n", __func__, range);
1274 fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1276 struct stv0900_state *state = fe->demodulator_priv;
1277 struct stv0900_internal *intp = state->internal;
1278 enum fe_stv0900_demod_num demod = state->demod;
1279 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1287 intp->result[demod].locked = FALSE;
1289 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1290 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1291 srate += stv0900_get_timing_offst(intp, srate, demod);
1292 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1293 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1295 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1296 srate, STV0900_WARM_START);
1297 freq1 = stv0900_read_reg(intp, CFR2);
1298 freq0 = stv0900_read_reg(intp, CFR1);
1299 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1300 stv0900_write_bits(intp, SPECINV_CONTROL,
1301 STV0900_IQ_FORCE_SWAPPED);
1302 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1303 stv0900_write_reg(intp, CFRINIT1, freq1);
1304 stv0900_write_reg(intp, CFRINIT0, freq0);
1305 stv0900_write_reg(intp, DMDISTATE, 0x18);
1306 if (stv0900_wait_for_lock(intp, demod,
1307 demod_timeout, fec_timeout) == TRUE) {
1308 intp->result[demod].locked = TRUE;
1309 signal_type = stv0900_get_signal_params(fe);
1310 stv0900_track_optimization(fe);
1312 stv0900_write_bits(intp, SPECINV_CONTROL,
1313 STV0900_IQ_FORCE_NORMAL);
1314 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1315 stv0900_write_reg(intp, CFRINIT1, freq1);
1316 stv0900_write_reg(intp, CFRINIT0, freq0);
1317 stv0900_write_reg(intp, DMDISTATE, 0x18);
1318 if (stv0900_wait_for_lock(intp, demod,
1319 demod_timeout, fec_timeout) == TRUE) {
1320 intp->result[demod].locked = TRUE;
1321 signal_type = stv0900_get_signal_params(fe);
1322 stv0900_track_optimization(fe);
1328 intp->result[demod].locked = FALSE;
1333 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1334 enum fe_stv0900_demod_num demod)
1336 u32 minagc2level = 0xffff,
1338 init_freq, freq_step;
1340 s32 i, j, nb_steps, direction;
1342 dprintk("%s\n", __func__);
1344 stv0900_write_reg(intp, AGC2REF, 0x38);
1345 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1346 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1348 stv0900_write_bits(intp, AUTO_GUP, 1);
1349 stv0900_write_bits(intp, AUTO_GLOW, 1);
1351 stv0900_write_reg(intp, DMDT0M, 0x0);
1353 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1354 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1356 nb_steps = (2 * nb_steps) + 1;
1363 freq_step = (1000000 << 8) / (intp->mclk >> 8);
1367 for (i = 0; i < nb_steps; i++) {
1369 init_freq = init_freq + (freq_step * i);
1371 init_freq = init_freq - (freq_step * i);
1374 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1375 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1376 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1377 stv0900_write_reg(intp, DMDISTATE, 0x58);
1381 for (j = 0; j < 10; j++)
1382 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1383 | stv0900_read_reg(intp, AGC2I0);
1387 if (agc2level < minagc2level)
1388 minagc2level = agc2level;
1392 return (u16)minagc2level;
1395 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1397 struct stv0900_state *state = fe->demodulator_priv;
1398 struct stv0900_internal *intp = state->internal;
1399 enum fe_stv0900_demod_num demod = state->demod;
1400 int timing_lck = FALSE;
1401 s32 i, timingcpt = 0,
1409 currier_step = 1200;
1411 if (intp->chip_id >= 0x30)
1416 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1417 stv0900_write_reg(intp, TMGCFG, 0x12);
1418 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1419 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1420 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1421 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1422 stv0900_write_reg(intp, SFRUP1, 0x83);
1423 stv0900_write_reg(intp, SFRUP0, 0xc0);
1424 stv0900_write_reg(intp, SFRLOW1, 0x82);
1425 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1426 stv0900_write_reg(intp, DMDT0M, 0x0);
1427 stv0900_write_reg(intp, AGC2REF, 0x50);
1429 if (intp->chip_id >= 0x30) {
1430 stv0900_write_reg(intp, CARFREQ, 0x99);
1431 stv0900_write_reg(intp, SFRSTEP, 0x98);
1432 } else if (intp->chip_id >= 0x20) {
1433 stv0900_write_reg(intp, CARFREQ, 0x6a);
1434 stv0900_write_reg(intp, SFRSTEP, 0x95);
1436 stv0900_write_reg(intp, CARFREQ, 0xed);
1437 stv0900_write_reg(intp, SFRSTEP, 0x73);
1440 if (intp->symbol_rate[demod] <= 2000000)
1441 currier_step = 1000;
1442 else if (intp->symbol_rate[demod] <= 5000000)
1443 currier_step = 2000;
1444 else if (intp->symbol_rate[demod] <= 12000000)
1445 currier_step = 3000;
1447 currier_step = 5000;
1449 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1451 nb_steps = (2 * nb_steps) + 1;
1455 else if (nb_steps > 10) {
1457 currier_step = (intp->srch_range[demod] / 1000) / 10;
1463 tuner_freq = intp->freq[demod];
1465 while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1466 stv0900_write_reg(intp, DMDISTATE, 0x5f);
1467 stv0900_write_bits(intp, DEMOD_MODE, 0);
1471 for (i = 0; i < 10; i++) {
1472 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1475 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1476 stv0900_read_reg(intp, AGC2I0);
1480 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1484 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1485 tuner_freq, agc2_integr, coarse_srate, timingcpt);
1487 if ((timingcpt >= 5) &&
1488 (agc2_integr < agc2_th) &&
1489 (coarse_srate < 55000000) &&
1490 (coarse_srate > 850000))
1492 else if (current_step < nb_steps) {
1494 tuner_freq += (current_step * currier_step);
1496 tuner_freq -= (current_step * currier_step);
1498 if (intp->tuner_type[demod] == 3)
1499 stv0900_set_tuner_auto(intp, tuner_freq,
1500 intp->bw[demod], demod);
1502 stv0900_set_tuner(fe, tuner_freq,
1507 if (timing_lck == FALSE)
1510 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1512 return coarse_srate;
1515 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1517 struct stv0900_state *state = fe->demodulator_priv;
1518 struct stv0900_internal *intp = state->internal;
1519 enum fe_stv0900_demod_num demod = state->demod;
1527 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1529 if (coarse_srate > 3000000) {
1530 symbmax = 13 * (coarse_srate / 10);
1531 symbmax = (symbmax / 1000) * 65536;
1532 symbmax /= (intp->mclk / 1000);
1534 symbmin = 10 * (coarse_srate / 13);
1535 symbmin = (symbmin / 1000)*65536;
1536 symbmin /= (intp->mclk / 1000);
1538 symb = (coarse_srate / 1000) * 65536;
1539 symb /= (intp->mclk / 1000);
1541 symbmax = 13 * (coarse_srate / 10);
1542 symbmax = (symbmax / 100) * 65536;
1543 symbmax /= (intp->mclk / 100);
1545 symbmin = 10 * (coarse_srate / 14);
1546 symbmin = (symbmin / 100) * 65536;
1547 symbmin /= (intp->mclk / 100);
1549 symb = (coarse_srate / 100) * 65536;
1550 symb /= (intp->mclk / 100);
1553 symbcomp = 13 * (coarse_srate / 10);
1554 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1555 | stv0900_read_reg(intp, CFR1);
1557 if (symbcomp < intp->symbol_rate[demod])
1560 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1561 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1562 stv0900_write_reg(intp, TMGTHRISE, 0x20);
1563 stv0900_write_reg(intp, TMGTHFALL, 0x00);
1564 stv0900_write_reg(intp, TMGCFG, 0xd2);
1565 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1566 stv0900_write_reg(intp, AGC2REF, 0x38);
1568 if (intp->chip_id >= 0x30)
1569 stv0900_write_reg(intp, CARFREQ, 0x79);
1570 else if (intp->chip_id >= 0x20)
1571 stv0900_write_reg(intp, CARFREQ, 0x49);
1573 stv0900_write_reg(intp, CARFREQ, 0xed);
1575 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1576 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1578 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1579 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1581 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1582 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1584 stv0900_write_reg(intp, DMDT0M, 0x20);
1585 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1586 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1587 stv0900_write_reg(intp, DMDISTATE, 0x15);
1590 return coarse_srate;
1593 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1595 struct stv0900_state *state = fe->demodulator_priv;
1596 struct stv0900_internal *intp = state->internal;
1597 enum fe_stv0900_demod_num demod = state->demod;
1604 coarse_fail = FALSE;
1605 s32 demod_timeout = 500,
1613 dprintk("%s\n", __func__);
1615 if (intp->chip_id < 0x20) {
1616 k_ref_tmg_max = 233;
1617 k_ref_tmg_min = 143;
1619 k_ref_tmg_max = 110;
1623 if (intp->chip_id <= 0x20)
1624 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1626 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
1628 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1630 dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
1631 if (agc2_int > agc2_th)
1634 if (intp->chip_id == 0x10)
1635 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1637 if (intp->chip_id < 0x20)
1638 stv0900_write_reg(intp, CARHDR, 0x55);
1640 stv0900_write_reg(intp, CARHDR, 0x20);
1642 if (intp->chip_id <= 0x20)
1643 stv0900_write_reg(intp, CARCFG, 0xc4);
1645 stv0900_write_reg(intp, CARCFG, 0x6);
1647 stv0900_write_reg(intp, RTCS2, 0x44);
1649 if (intp->chip_id >= 0x20) {
1650 stv0900_write_reg(intp, EQUALCFG, 0x41);
1651 stv0900_write_reg(intp, FFECFG, 0x41);
1652 stv0900_write_reg(intp, VITSCALE, 0x82);
1653 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1656 k_ref_tmg = k_ref_tmg_max;
1659 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1660 if (stv0900_search_srate_coarse(fe) != 0) {
1661 coarse_srate = stv0900_search_srate_fine(fe);
1663 if (coarse_srate != 0) {
1664 stv0900_get_lock_timeout(&demod_timeout,
1667 STV0900_BLIND_SEARCH);
1668 lock = stv0900_get_demod_lock(intp,
1677 for (i = 0; i < 10; i++) {
1678 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1679 | stv0900_read_reg(intp, AGC2I0);
1681 if (agc2_int >= 0xff00)
1684 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1686 if (((dstatus2 & 0x1) == 0x1) &&
1687 ((dstatus2 >> 7) == 1))
1691 if ((fail_cpt > 7) || (agc2_overflow > 7))
1697 } while ((k_ref_tmg >= k_ref_tmg_min) &&
1699 (coarse_fail == FALSE));
1704 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1705 enum fe_stv0900_demod_num demod)
1707 s32 vth_reg = VTH12;
1709 dprintk("%s\n", __func__);
1711 stv0900_write_reg(intp, vth_reg++, 0x96);
1712 stv0900_write_reg(intp, vth_reg++, 0x64);
1713 stv0900_write_reg(intp, vth_reg++, 0x36);
1714 stv0900_write_reg(intp, vth_reg++, 0x23);
1715 stv0900_write_reg(intp, vth_reg++, 0x1e);
1716 stv0900_write_reg(intp, vth_reg++, 0x19);
1719 static void stv0900_set_search_standard(struct stv0900_internal *intp,
1720 enum fe_stv0900_demod_num demod)
1723 dprintk("%s\n", __func__);
1725 switch (intp->srch_standard[demod]) {
1726 case STV0900_SEARCH_DVBS1:
1727 dprintk("Search Standard = DVBS1\n");
1729 case STV0900_SEARCH_DSS:
1730 dprintk("Search Standard = DSS\n");
1732 case STV0900_SEARCH_DVBS2:
1733 dprintk("Search Standard = DVBS2\n");
1735 case STV0900_AUTO_SEARCH:
1737 dprintk("Search Standard = AUTO\n");
1741 switch (intp->srch_standard[demod]) {
1742 case STV0900_SEARCH_DVBS1:
1743 case STV0900_SEARCH_DSS:
1744 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1745 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1746 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1747 stv0900_set_dvbs1_track_car_loop(intp,
1749 intp->symbol_rate[demod]);
1750 stv0900_write_reg(intp, CAR2CFG, 0x22);
1752 stv0900_set_viterbi_acq(intp, demod);
1753 stv0900_set_viterbi_standard(intp,
1754 intp->srch_standard[demod],
1755 intp->fec[demod], demod);
1758 case STV0900_SEARCH_DVBS2:
1759 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1760 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1761 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1762 stv0900_write_reg(intp, ACLC, 0x1a);
1763 stv0900_write_reg(intp, BCLC, 0x09);
1764 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1765 stv0900_write_reg(intp, CAR2CFG, 0x26);
1767 stv0900_write_reg(intp, CAR2CFG, 0x66);
1769 if (intp->demod_mode != STV0900_SINGLE) {
1770 if (intp->chip_id <= 0x11)
1771 stv0900_stop_all_s2_modcod(intp, demod);
1773 stv0900_activate_s2_modcod(intp, demod);
1776 stv0900_activate_s2_modcod_single(intp, demod);
1778 stv0900_set_viterbi_tracq(intp, demod);
1781 case STV0900_AUTO_SEARCH:
1783 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1784 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1785 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1786 stv0900_write_reg(intp, ACLC, 0x1a);
1787 stv0900_write_reg(intp, BCLC, 0x09);
1788 stv0900_set_dvbs1_track_car_loop(intp,
1790 intp->symbol_rate[demod]);
1791 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1792 stv0900_write_reg(intp, CAR2CFG, 0x26);
1794 stv0900_write_reg(intp, CAR2CFG, 0x66);
1796 if (intp->demod_mode != STV0900_SINGLE) {
1797 if (intp->chip_id <= 0x11)
1798 stv0900_stop_all_s2_modcod(intp, demod);
1800 stv0900_activate_s2_modcod(intp, demod);
1803 stv0900_activate_s2_modcod_single(intp, demod);
1805 stv0900_set_viterbi_tracq(intp, demod);
1806 stv0900_set_viterbi_standard(intp,
1807 intp->srch_standard[demod],
1808 intp->fec[demod], demod);
1814 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1816 struct stv0900_state *state = fe->demodulator_priv;
1817 struct stv0900_internal *intp = state->internal;
1818 enum fe_stv0900_demod_num demod = state->demod;
1820 s32 demod_timeout = 500, fec_timeout = 50;
1821 s32 aq_power, agc1_power, i;
1823 int lock = FALSE, low_sr = FALSE;
1825 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1826 enum fe_stv0900_search_algo algo;
1827 int no_signal = FALSE;
1829 dprintk("%s\n", __func__);
1831 algo = intp->srch_algo[demod];
1832 stv0900_write_bits(intp, RST_HWARE, 1);
1833 stv0900_write_reg(intp, DMDISTATE, 0x5c);
1834 if (intp->chip_id >= 0x20) {
1835 if (intp->symbol_rate[demod] > 5000000)
1836 stv0900_write_reg(intp, CORRELABS, 0x9e);
1838 stv0900_write_reg(intp, CORRELABS, 0x82);
1840 stv0900_write_reg(intp, CORRELABS, 0x88);
1842 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1843 intp->symbol_rate[demod],
1844 intp->srch_algo[demod]);
1846 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1847 intp->bw[demod] = 2 * 36000000;
1849 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1850 stv0900_write_reg(intp, CORRELMANT, 0x70);
1852 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1854 stv0900_write_reg(intp, DMDT0M, 0x20);
1855 stv0900_write_reg(intp, TMGCFG, 0xd2);
1857 if (intp->symbol_rate[demod] < 2000000)
1858 stv0900_write_reg(intp, CORRELMANT, 0x63);
1860 stv0900_write_reg(intp, CORRELMANT, 0x70);
1862 stv0900_write_reg(intp, AGC2REF, 0x38);
1865 stv0900_carrier_width(intp->symbol_rate[demod],
1867 if (intp->chip_id >= 0x20) {
1868 stv0900_write_reg(intp, KREFTMG, 0x5a);
1870 if (intp->srch_algo[demod] == STV0900_COLD_START) {
1871 intp->bw[demod] += 10000000;
1872 intp->bw[demod] *= 15;
1873 intp->bw[demod] /= 10;
1874 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1875 intp->bw[demod] += 10000000;
1878 stv0900_write_reg(intp, KREFTMG, 0xc1);
1879 intp->bw[demod] += 10000000;
1880 intp->bw[demod] *= 15;
1881 intp->bw[demod] /= 10;
1884 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1886 stv0900_set_symbol_rate(intp, intp->mclk,
1887 intp->symbol_rate[demod], demod);
1888 stv0900_set_max_symbol_rate(intp, intp->mclk,
1889 intp->symbol_rate[demod], demod);
1890 stv0900_set_min_symbol_rate(intp, intp->mclk,
1891 intp->symbol_rate[demod], demod);
1892 if (intp->symbol_rate[demod] >= 10000000)
1899 if (intp->tuner_type[demod] == 3)
1900 stv0900_set_tuner_auto(intp, intp->freq[demod],
1901 intp->bw[demod], demod);
1903 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1905 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1906 stv0900_get_bits(intp, AGCIQ_VALUE0));
1910 if (agc1_power == 0) {
1911 for (i = 0; i < 5; i++)
1912 aq_power += (stv0900_get_bits(intp, POWER_I) +
1913 stv0900_get_bits(intp, POWER_Q)) / 2;
1918 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1919 intp->result[demod].locked = FALSE;
1920 signal_type = STV0900_NOAGC1;
1921 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1923 stv0900_write_bits(intp, SPECINV_CONTROL,
1924 intp->srch_iq_inv[demod]);
1925 if (intp->chip_id <= 0x20) /*cut 2.0*/
1926 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1928 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1930 stv0900_set_search_standard(intp, demod);
1932 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1933 stv0900_start_search(intp, demod);
1936 if (signal_type == STV0900_NOAGC1)
1939 if (intp->chip_id == 0x12) {
1940 stv0900_write_bits(intp, RST_HWARE, 0);
1942 stv0900_write_bits(intp, RST_HWARE, 1);
1943 stv0900_write_bits(intp, RST_HWARE, 0);
1946 if (algo == STV0900_BLIND_SEARCH)
1947 lock = stv0900_blind_search_algo(fe);
1948 else if (algo == STV0900_COLD_START)
1949 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1950 else if (algo == STV0900_WARM_START)
1951 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1953 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1954 if (low_sr == FALSE) {
1955 if (stv0900_check_timing_lock(intp, demod) == TRUE)
1956 lock = stv0900_sw_algo(intp, demod);
1961 signal_type = stv0900_get_signal_params(fe);
1963 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1964 stv0900_track_optimization(fe);
1965 if (intp->chip_id <= 0x11) {
1966 if ((stv0900_get_standard(fe, 0) ==
1967 STV0900_DVBS1_STANDARD) &&
1968 (stv0900_get_standard(fe, 1) ==
1969 STV0900_DVBS1_STANDARD)) {
1971 stv0900_write_bits(intp, RST_HWARE, 0);
1973 stv0900_write_bits(intp, RST_HWARE, 0);
1975 stv0900_write_bits(intp, RST_HWARE, 1);
1976 stv0900_write_bits(intp, RST_HWARE, 0);
1979 } else if (intp->chip_id >= 0x20) {
1980 stv0900_write_bits(intp, RST_HWARE, 0);
1982 stv0900_write_bits(intp, RST_HWARE, 1);
1983 stv0900_write_bits(intp, RST_HWARE, 0);
1986 if (stv0900_wait_for_lock(intp, demod,
1987 fec_timeout, fec_timeout) == TRUE) {
1989 intp->result[demod].locked = TRUE;
1990 if (intp->result[demod].standard ==
1991 STV0900_DVBS2_STANDARD) {
1992 stv0900_set_dvbs2_rolloff(intp, demod);
1993 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
1994 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
1995 stv0900_write_reg(intp, ERRCTRL1, 0x67);
1997 stv0900_write_reg(intp, ERRCTRL1, 0x75);
2000 stv0900_write_reg(intp, FBERCPT4, 0);
2001 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
2004 signal_type = STV0900_NODATA;
2005 no_signal = stv0900_check_signal_presence(intp, demod);
2007 intp->result[demod].locked = FALSE;
2011 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2014 if (intp->chip_id > 0x11) {
2015 intp->result[demod].locked = FALSE;
2019 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
2020 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
2021 signal_type = stv0900_dvbs1_acq_workaround(fe);