2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
29 #include <linux/dvb/frontend.h>
30 #include "dvb_frontend.h"
32 #include "stv6110x.h" /* for demodulator internal modes */
34 #include "stv090x_reg.h"
36 #include "stv090x_priv.h"
38 /* Max transfer size done by I2C transfer functions */
39 #define MAX_XFER_SIZE 64
41 static unsigned int verbose;
42 module_param(verbose, int, 0644);
44 /* internal params node */
46 /* pointer for internal params, one for each pair of demods */
47 struct stv090x_internal *internal;
48 struct stv090x_dev *next_dev;
51 /* first internal params */
52 static struct stv090x_dev *stv090x_first_dev;
54 /* find chip by i2c adapter and i2c address */
55 static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
58 struct stv090x_dev *temp_dev = stv090x_first_dev;
61 Search of the last stv0900 chip or
62 find it by i2c adapter and i2c address */
63 while ((temp_dev != NULL) &&
64 ((temp_dev->internal->i2c_adap != i2c_adap) ||
65 (temp_dev->internal->i2c_addr != i2c_addr))) {
67 temp_dev = temp_dev->next_dev;
73 /* deallocating chip */
74 static void remove_dev(struct stv090x_internal *internal)
76 struct stv090x_dev *prev_dev = stv090x_first_dev;
77 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
80 if (del_dev != NULL) {
81 if (del_dev == stv090x_first_dev) {
82 stv090x_first_dev = del_dev->next_dev;
84 while (prev_dev->next_dev != del_dev)
85 prev_dev = prev_dev->next_dev;
87 prev_dev->next_dev = del_dev->next_dev;
94 /* allocating new chip */
95 static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
97 struct stv090x_dev *new_dev;
98 struct stv090x_dev *temp_dev;
100 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
101 if (new_dev != NULL) {
102 new_dev->internal = internal;
103 new_dev->next_dev = NULL;
106 if (stv090x_first_dev == NULL) {
107 stv090x_first_dev = new_dev;
109 temp_dev = stv090x_first_dev;
110 while (temp_dev->next_dev != NULL)
111 temp_dev = temp_dev->next_dev;
113 temp_dev->next_dev = new_dev;
121 /* DVBS1 and DSS C/N Lookup table */
122 static const struct stv090x_tab stv090x_s1cn_tab[] = {
123 { 0, 8917 }, /* 0.0dB */
124 { 5, 8801 }, /* 0.5dB */
125 { 10, 8667 }, /* 1.0dB */
126 { 15, 8522 }, /* 1.5dB */
127 { 20, 8355 }, /* 2.0dB */
128 { 25, 8175 }, /* 2.5dB */
129 { 30, 7979 }, /* 3.0dB */
130 { 35, 7763 }, /* 3.5dB */
131 { 40, 7530 }, /* 4.0dB */
132 { 45, 7282 }, /* 4.5dB */
133 { 50, 7026 }, /* 5.0dB */
134 { 55, 6781 }, /* 5.5dB */
135 { 60, 6514 }, /* 6.0dB */
136 { 65, 6241 }, /* 6.5dB */
137 { 70, 5965 }, /* 7.0dB */
138 { 75, 5690 }, /* 7.5dB */
139 { 80, 5424 }, /* 8.0dB */
140 { 85, 5161 }, /* 8.5dB */
141 { 90, 4902 }, /* 9.0dB */
142 { 95, 4654 }, /* 9.5dB */
143 { 100, 4417 }, /* 10.0dB */
144 { 105, 4186 }, /* 10.5dB */
145 { 110, 3968 }, /* 11.0dB */
146 { 115, 3757 }, /* 11.5dB */
147 { 120, 3558 }, /* 12.0dB */
148 { 125, 3366 }, /* 12.5dB */
149 { 130, 3185 }, /* 13.0dB */
150 { 135, 3012 }, /* 13.5dB */
151 { 140, 2850 }, /* 14.0dB */
152 { 145, 2698 }, /* 14.5dB */
153 { 150, 2550 }, /* 15.0dB */
154 { 160, 2283 }, /* 16.0dB */
155 { 170, 2042 }, /* 17.0dB */
156 { 180, 1827 }, /* 18.0dB */
157 { 190, 1636 }, /* 19.0dB */
158 { 200, 1466 }, /* 20.0dB */
159 { 210, 1315 }, /* 21.0dB */
160 { 220, 1181 }, /* 22.0dB */
161 { 230, 1064 }, /* 23.0dB */
162 { 240, 960 }, /* 24.0dB */
163 { 250, 869 }, /* 25.0dB */
164 { 260, 792 }, /* 26.0dB */
165 { 270, 724 }, /* 27.0dB */
166 { 280, 665 }, /* 28.0dB */
167 { 290, 616 }, /* 29.0dB */
168 { 300, 573 }, /* 30.0dB */
169 { 310, 537 }, /* 31.0dB */
170 { 320, 507 }, /* 32.0dB */
171 { 330, 483 }, /* 33.0dB */
172 { 400, 398 }, /* 40.0dB */
173 { 450, 381 }, /* 45.0dB */
174 { 500, 377 } /* 50.0dB */
177 /* DVBS2 C/N Lookup table */
178 static const struct stv090x_tab stv090x_s2cn_tab[] = {
179 { -30, 13348 }, /* -3.0dB */
180 { -20, 12640 }, /* -2d.0B */
181 { -10, 11883 }, /* -1.0dB */
182 { 0, 11101 }, /* -0.0dB */
183 { 5, 10718 }, /* 0.5dB */
184 { 10, 10339 }, /* 1.0dB */
185 { 15, 9947 }, /* 1.5dB */
186 { 20, 9552 }, /* 2.0dB */
187 { 25, 9183 }, /* 2.5dB */
188 { 30, 8799 }, /* 3.0dB */
189 { 35, 8422 }, /* 3.5dB */
190 { 40, 8062 }, /* 4.0dB */
191 { 45, 7707 }, /* 4.5dB */
192 { 50, 7353 }, /* 5.0dB */
193 { 55, 7025 }, /* 5.5dB */
194 { 60, 6684 }, /* 6.0dB */
195 { 65, 6331 }, /* 6.5dB */
196 { 70, 6036 }, /* 7.0dB */
197 { 75, 5727 }, /* 7.5dB */
198 { 80, 5437 }, /* 8.0dB */
199 { 85, 5164 }, /* 8.5dB */
200 { 90, 4902 }, /* 9.0dB */
201 { 95, 4653 }, /* 9.5dB */
202 { 100, 4408 }, /* 10.0dB */
203 { 105, 4187 }, /* 10.5dB */
204 { 110, 3961 }, /* 11.0dB */
205 { 115, 3751 }, /* 11.5dB */
206 { 120, 3558 }, /* 12.0dB */
207 { 125, 3368 }, /* 12.5dB */
208 { 130, 3191 }, /* 13.0dB */
209 { 135, 3017 }, /* 13.5dB */
210 { 140, 2862 }, /* 14.0dB */
211 { 145, 2710 }, /* 14.5dB */
212 { 150, 2565 }, /* 15.0dB */
213 { 160, 2300 }, /* 16.0dB */
214 { 170, 2058 }, /* 17.0dB */
215 { 180, 1849 }, /* 18.0dB */
216 { 190, 1663 }, /* 19.0dB */
217 { 200, 1495 }, /* 20.0dB */
218 { 210, 1349 }, /* 21.0dB */
219 { 220, 1222 }, /* 22.0dB */
220 { 230, 1110 }, /* 23.0dB */
221 { 240, 1011 }, /* 24.0dB */
222 { 250, 925 }, /* 25.0dB */
223 { 260, 853 }, /* 26.0dB */
224 { 270, 789 }, /* 27.0dB */
225 { 280, 734 }, /* 28.0dB */
226 { 290, 690 }, /* 29.0dB */
227 { 300, 650 }, /* 30.0dB */
228 { 310, 619 }, /* 31.0dB */
229 { 320, 593 }, /* 32.0dB */
230 { 330, 571 }, /* 33.0dB */
231 { 400, 498 }, /* 40.0dB */
232 { 450, 484 }, /* 45.0dB */
233 { 500, 481 } /* 50.0dB */
236 /* RF level C/N lookup table */
237 static const struct stv090x_tab stv090x_rf_tab[] = {
238 { -5, 0xcaa1 }, /* -5dBm */
239 { -10, 0xc229 }, /* -10dBm */
240 { -15, 0xbb08 }, /* -15dBm */
241 { -20, 0xb4bc }, /* -20dBm */
242 { -25, 0xad5a }, /* -25dBm */
243 { -30, 0xa298 }, /* -30dBm */
244 { -35, 0x98a8 }, /* -35dBm */
245 { -40, 0x8389 }, /* -40dBm */
246 { -45, 0x59be }, /* -45dBm */
247 { -50, 0x3a14 }, /* -50dBm */
248 { -55, 0x2d11 }, /* -55dBm */
249 { -60, 0x210d }, /* -60dBm */
250 { -65, 0xa14f }, /* -65dBm */
251 { -70, 0x07aa } /* -70dBm */
255 static struct stv090x_reg stv0900_initval[] = {
257 { STV090x_OUTCFG, 0x00 },
258 { STV090x_MODECFG, 0xff },
259 { STV090x_AGCRF1CFG, 0x11 },
260 { STV090x_AGCRF2CFG, 0x13 },
261 { STV090x_TSGENERAL1X, 0x14 },
262 { STV090x_TSTTNR2, 0x21 },
263 { STV090x_TSTTNR4, 0x21 },
264 { STV090x_P2_DISTXCTL, 0x22 },
265 { STV090x_P2_F22TX, 0xc0 },
266 { STV090x_P2_F22RX, 0xc0 },
267 { STV090x_P2_DISRXCTL, 0x00 },
268 { STV090x_P2_DMDCFGMD, 0xF9 },
269 { STV090x_P2_DEMOD, 0x08 },
270 { STV090x_P2_DMDCFG3, 0xc4 },
271 { STV090x_P2_CARFREQ, 0xed },
272 { STV090x_P2_LDT, 0xd0 },
273 { STV090x_P2_LDT2, 0xb8 },
274 { STV090x_P2_TMGCFG, 0xd2 },
275 { STV090x_P2_TMGTHRISE, 0x20 },
276 { STV090x_P1_TMGCFG, 0xd2 },
278 { STV090x_P2_TMGTHFALL, 0x00 },
279 { STV090x_P2_FECSPY, 0x88 },
280 { STV090x_P2_FSPYDATA, 0x3a },
281 { STV090x_P2_FBERCPT4, 0x00 },
282 { STV090x_P2_FSPYBER, 0x10 },
283 { STV090x_P2_ERRCTRL1, 0x35 },
284 { STV090x_P2_ERRCTRL2, 0xc1 },
285 { STV090x_P2_CFRICFG, 0xf8 },
286 { STV090x_P2_NOSCFG, 0x1c },
287 { STV090x_P2_DMDTOM, 0x20 },
288 { STV090x_P2_CORRELMANT, 0x70 },
289 { STV090x_P2_CORRELABS, 0x88 },
290 { STV090x_P2_AGC2O, 0x5b },
291 { STV090x_P2_AGC2REF, 0x38 },
292 { STV090x_P2_CARCFG, 0xe4 },
293 { STV090x_P2_ACLC, 0x1A },
294 { STV090x_P2_BCLC, 0x09 },
295 { STV090x_P2_CARHDR, 0x08 },
296 { STV090x_P2_KREFTMG, 0xc1 },
297 { STV090x_P2_SFRUPRATIO, 0xf0 },
298 { STV090x_P2_SFRLOWRATIO, 0x70 },
299 { STV090x_P2_SFRSTEP, 0x58 },
300 { STV090x_P2_TMGCFG2, 0x01 },
301 { STV090x_P2_CAR2CFG, 0x26 },
302 { STV090x_P2_BCLC2S2Q, 0x86 },
303 { STV090x_P2_BCLC2S28, 0x86 },
304 { STV090x_P2_SMAPCOEF7, 0x77 },
305 { STV090x_P2_SMAPCOEF6, 0x85 },
306 { STV090x_P2_SMAPCOEF5, 0x77 },
307 { STV090x_P2_TSCFGL, 0x20 },
308 { STV090x_P2_DMDCFG2, 0x3b },
309 { STV090x_P2_MODCODLST0, 0xff },
310 { STV090x_P2_MODCODLST1, 0xff },
311 { STV090x_P2_MODCODLST2, 0xff },
312 { STV090x_P2_MODCODLST3, 0xff },
313 { STV090x_P2_MODCODLST4, 0xff },
314 { STV090x_P2_MODCODLST5, 0xff },
315 { STV090x_P2_MODCODLST6, 0xff },
316 { STV090x_P2_MODCODLST7, 0xcc },
317 { STV090x_P2_MODCODLST8, 0xcc },
318 { STV090x_P2_MODCODLST9, 0xcc },
319 { STV090x_P2_MODCODLSTA, 0xcc },
320 { STV090x_P2_MODCODLSTB, 0xcc },
321 { STV090x_P2_MODCODLSTC, 0xcc },
322 { STV090x_P2_MODCODLSTD, 0xcc },
323 { STV090x_P2_MODCODLSTE, 0xcc },
324 { STV090x_P2_MODCODLSTF, 0xcf },
325 { STV090x_P1_DISTXCTL, 0x22 },
326 { STV090x_P1_F22TX, 0xc0 },
327 { STV090x_P1_F22RX, 0xc0 },
328 { STV090x_P1_DISRXCTL, 0x00 },
329 { STV090x_P1_DMDCFGMD, 0xf9 },
330 { STV090x_P1_DEMOD, 0x08 },
331 { STV090x_P1_DMDCFG3, 0xc4 },
332 { STV090x_P1_DMDTOM, 0x20 },
333 { STV090x_P1_CARFREQ, 0xed },
334 { STV090x_P1_LDT, 0xd0 },
335 { STV090x_P1_LDT2, 0xb8 },
336 { STV090x_P1_TMGCFG, 0xd2 },
337 { STV090x_P1_TMGTHRISE, 0x20 },
338 { STV090x_P1_TMGTHFALL, 0x00 },
339 { STV090x_P1_SFRUPRATIO, 0xf0 },
340 { STV090x_P1_SFRLOWRATIO, 0x70 },
341 { STV090x_P1_TSCFGL, 0x20 },
342 { STV090x_P1_FECSPY, 0x88 },
343 { STV090x_P1_FSPYDATA, 0x3a },
344 { STV090x_P1_FBERCPT4, 0x00 },
345 { STV090x_P1_FSPYBER, 0x10 },
346 { STV090x_P1_ERRCTRL1, 0x35 },
347 { STV090x_P1_ERRCTRL2, 0xc1 },
348 { STV090x_P1_CFRICFG, 0xf8 },
349 { STV090x_P1_NOSCFG, 0x1c },
350 { STV090x_P1_CORRELMANT, 0x70 },
351 { STV090x_P1_CORRELABS, 0x88 },
352 { STV090x_P1_AGC2O, 0x5b },
353 { STV090x_P1_AGC2REF, 0x38 },
354 { STV090x_P1_CARCFG, 0xe4 },
355 { STV090x_P1_ACLC, 0x1A },
356 { STV090x_P1_BCLC, 0x09 },
357 { STV090x_P1_CARHDR, 0x08 },
358 { STV090x_P1_KREFTMG, 0xc1 },
359 { STV090x_P1_SFRSTEP, 0x58 },
360 { STV090x_P1_TMGCFG2, 0x01 },
361 { STV090x_P1_CAR2CFG, 0x26 },
362 { STV090x_P1_BCLC2S2Q, 0x86 },
363 { STV090x_P1_BCLC2S28, 0x86 },
364 { STV090x_P1_SMAPCOEF7, 0x77 },
365 { STV090x_P1_SMAPCOEF6, 0x85 },
366 { STV090x_P1_SMAPCOEF5, 0x77 },
367 { STV090x_P1_DMDCFG2, 0x3b },
368 { STV090x_P1_MODCODLST0, 0xff },
369 { STV090x_P1_MODCODLST1, 0xff },
370 { STV090x_P1_MODCODLST2, 0xff },
371 { STV090x_P1_MODCODLST3, 0xff },
372 { STV090x_P1_MODCODLST4, 0xff },
373 { STV090x_P1_MODCODLST5, 0xff },
374 { STV090x_P1_MODCODLST6, 0xff },
375 { STV090x_P1_MODCODLST7, 0xcc },
376 { STV090x_P1_MODCODLST8, 0xcc },
377 { STV090x_P1_MODCODLST9, 0xcc },
378 { STV090x_P1_MODCODLSTA, 0xcc },
379 { STV090x_P1_MODCODLSTB, 0xcc },
380 { STV090x_P1_MODCODLSTC, 0xcc },
381 { STV090x_P1_MODCODLSTD, 0xcc },
382 { STV090x_P1_MODCODLSTE, 0xcc },
383 { STV090x_P1_MODCODLSTF, 0xcf },
384 { STV090x_GENCFG, 0x1d },
385 { STV090x_NBITER_NF4, 0x37 },
386 { STV090x_NBITER_NF5, 0x29 },
387 { STV090x_NBITER_NF6, 0x37 },
388 { STV090x_NBITER_NF7, 0x33 },
389 { STV090x_NBITER_NF8, 0x31 },
390 { STV090x_NBITER_NF9, 0x2f },
391 { STV090x_NBITER_NF10, 0x39 },
392 { STV090x_NBITER_NF11, 0x3a },
393 { STV090x_NBITER_NF12, 0x29 },
394 { STV090x_NBITER_NF13, 0x37 },
395 { STV090x_NBITER_NF14, 0x33 },
396 { STV090x_NBITER_NF15, 0x2f },
397 { STV090x_NBITER_NF16, 0x39 },
398 { STV090x_NBITER_NF17, 0x3a },
399 { STV090x_NBITERNOERR, 0x04 },
400 { STV090x_GAINLLR_NF4, 0x0C },
401 { STV090x_GAINLLR_NF5, 0x0F },
402 { STV090x_GAINLLR_NF6, 0x11 },
403 { STV090x_GAINLLR_NF7, 0x14 },
404 { STV090x_GAINLLR_NF8, 0x17 },
405 { STV090x_GAINLLR_NF9, 0x19 },
406 { STV090x_GAINLLR_NF10, 0x20 },
407 { STV090x_GAINLLR_NF11, 0x21 },
408 { STV090x_GAINLLR_NF12, 0x0D },
409 { STV090x_GAINLLR_NF13, 0x0F },
410 { STV090x_GAINLLR_NF14, 0x13 },
411 { STV090x_GAINLLR_NF15, 0x1A },
412 { STV090x_GAINLLR_NF16, 0x1F },
413 { STV090x_GAINLLR_NF17, 0x21 },
414 { STV090x_RCCFGH, 0x20 },
415 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
416 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
417 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
418 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
421 static struct stv090x_reg stv0903_initval[] = {
422 { STV090x_OUTCFG, 0x00 },
423 { STV090x_AGCRF1CFG, 0x11 },
424 { STV090x_STOPCLK1, 0x48 },
425 { STV090x_STOPCLK2, 0x14 },
426 { STV090x_TSTTNR1, 0x27 },
427 { STV090x_TSTTNR2, 0x21 },
428 { STV090x_P1_DISTXCTL, 0x22 },
429 { STV090x_P1_F22TX, 0xc0 },
430 { STV090x_P1_F22RX, 0xc0 },
431 { STV090x_P1_DISRXCTL, 0x00 },
432 { STV090x_P1_DMDCFGMD, 0xF9 },
433 { STV090x_P1_DEMOD, 0x08 },
434 { STV090x_P1_DMDCFG3, 0xc4 },
435 { STV090x_P1_CARFREQ, 0xed },
436 { STV090x_P1_TNRCFG2, 0x82 },
437 { STV090x_P1_LDT, 0xd0 },
438 { STV090x_P1_LDT2, 0xb8 },
439 { STV090x_P1_TMGCFG, 0xd2 },
440 { STV090x_P1_TMGTHRISE, 0x20 },
441 { STV090x_P1_TMGTHFALL, 0x00 },
442 { STV090x_P1_SFRUPRATIO, 0xf0 },
443 { STV090x_P1_SFRLOWRATIO, 0x70 },
444 { STV090x_P1_TSCFGL, 0x20 },
445 { STV090x_P1_FECSPY, 0x88 },
446 { STV090x_P1_FSPYDATA, 0x3a },
447 { STV090x_P1_FBERCPT4, 0x00 },
448 { STV090x_P1_FSPYBER, 0x10 },
449 { STV090x_P1_ERRCTRL1, 0x35 },
450 { STV090x_P1_ERRCTRL2, 0xc1 },
451 { STV090x_P1_CFRICFG, 0xf8 },
452 { STV090x_P1_NOSCFG, 0x1c },
453 { STV090x_P1_DMDTOM, 0x20 },
454 { STV090x_P1_CORRELMANT, 0x70 },
455 { STV090x_P1_CORRELABS, 0x88 },
456 { STV090x_P1_AGC2O, 0x5b },
457 { STV090x_P1_AGC2REF, 0x38 },
458 { STV090x_P1_CARCFG, 0xe4 },
459 { STV090x_P1_ACLC, 0x1A },
460 { STV090x_P1_BCLC, 0x09 },
461 { STV090x_P1_CARHDR, 0x08 },
462 { STV090x_P1_KREFTMG, 0xc1 },
463 { STV090x_P1_SFRSTEP, 0x58 },
464 { STV090x_P1_TMGCFG2, 0x01 },
465 { STV090x_P1_CAR2CFG, 0x26 },
466 { STV090x_P1_BCLC2S2Q, 0x86 },
467 { STV090x_P1_BCLC2S28, 0x86 },
468 { STV090x_P1_SMAPCOEF7, 0x77 },
469 { STV090x_P1_SMAPCOEF6, 0x85 },
470 { STV090x_P1_SMAPCOEF5, 0x77 },
471 { STV090x_P1_DMDCFG2, 0x3b },
472 { STV090x_P1_MODCODLST0, 0xff },
473 { STV090x_P1_MODCODLST1, 0xff },
474 { STV090x_P1_MODCODLST2, 0xff },
475 { STV090x_P1_MODCODLST3, 0xff },
476 { STV090x_P1_MODCODLST4, 0xff },
477 { STV090x_P1_MODCODLST5, 0xff },
478 { STV090x_P1_MODCODLST6, 0xff },
479 { STV090x_P1_MODCODLST7, 0xcc },
480 { STV090x_P1_MODCODLST8, 0xcc },
481 { STV090x_P1_MODCODLST9, 0xcc },
482 { STV090x_P1_MODCODLSTA, 0xcc },
483 { STV090x_P1_MODCODLSTB, 0xcc },
484 { STV090x_P1_MODCODLSTC, 0xcc },
485 { STV090x_P1_MODCODLSTD, 0xcc },
486 { STV090x_P1_MODCODLSTE, 0xcc },
487 { STV090x_P1_MODCODLSTF, 0xcf },
488 { STV090x_GENCFG, 0x1c },
489 { STV090x_NBITER_NF4, 0x37 },
490 { STV090x_NBITER_NF5, 0x29 },
491 { STV090x_NBITER_NF6, 0x37 },
492 { STV090x_NBITER_NF7, 0x33 },
493 { STV090x_NBITER_NF8, 0x31 },
494 { STV090x_NBITER_NF9, 0x2f },
495 { STV090x_NBITER_NF10, 0x39 },
496 { STV090x_NBITER_NF11, 0x3a },
497 { STV090x_NBITER_NF12, 0x29 },
498 { STV090x_NBITER_NF13, 0x37 },
499 { STV090x_NBITER_NF14, 0x33 },
500 { STV090x_NBITER_NF15, 0x2f },
501 { STV090x_NBITER_NF16, 0x39 },
502 { STV090x_NBITER_NF17, 0x3a },
503 { STV090x_NBITERNOERR, 0x04 },
504 { STV090x_GAINLLR_NF4, 0x0C },
505 { STV090x_GAINLLR_NF5, 0x0F },
506 { STV090x_GAINLLR_NF6, 0x11 },
507 { STV090x_GAINLLR_NF7, 0x14 },
508 { STV090x_GAINLLR_NF8, 0x17 },
509 { STV090x_GAINLLR_NF9, 0x19 },
510 { STV090x_GAINLLR_NF10, 0x20 },
511 { STV090x_GAINLLR_NF11, 0x21 },
512 { STV090x_GAINLLR_NF12, 0x0D },
513 { STV090x_GAINLLR_NF13, 0x0F },
514 { STV090x_GAINLLR_NF14, 0x13 },
515 { STV090x_GAINLLR_NF15, 0x1A },
516 { STV090x_GAINLLR_NF16, 0x1F },
517 { STV090x_GAINLLR_NF17, 0x21 },
518 { STV090x_RCCFGH, 0x20 },
519 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
520 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
523 static struct stv090x_reg stv0900_cut20_val[] = {
525 { STV090x_P2_DMDCFG3, 0xe8 },
526 { STV090x_P2_DMDCFG4, 0x10 },
527 { STV090x_P2_CARFREQ, 0x38 },
528 { STV090x_P2_CARHDR, 0x20 },
529 { STV090x_P2_KREFTMG, 0x5a },
530 { STV090x_P2_SMAPCOEF7, 0x06 },
531 { STV090x_P2_SMAPCOEF6, 0x00 },
532 { STV090x_P2_SMAPCOEF5, 0x04 },
533 { STV090x_P2_NOSCFG, 0x0c },
534 { STV090x_P1_DMDCFG3, 0xe8 },
535 { STV090x_P1_DMDCFG4, 0x10 },
536 { STV090x_P1_CARFREQ, 0x38 },
537 { STV090x_P1_CARHDR, 0x20 },
538 { STV090x_P1_KREFTMG, 0x5a },
539 { STV090x_P1_SMAPCOEF7, 0x06 },
540 { STV090x_P1_SMAPCOEF6, 0x00 },
541 { STV090x_P1_SMAPCOEF5, 0x04 },
542 { STV090x_P1_NOSCFG, 0x0c },
543 { STV090x_GAINLLR_NF4, 0x21 },
544 { STV090x_GAINLLR_NF5, 0x21 },
545 { STV090x_GAINLLR_NF6, 0x20 },
546 { STV090x_GAINLLR_NF7, 0x1F },
547 { STV090x_GAINLLR_NF8, 0x1E },
548 { STV090x_GAINLLR_NF9, 0x1E },
549 { STV090x_GAINLLR_NF10, 0x1D },
550 { STV090x_GAINLLR_NF11, 0x1B },
551 { STV090x_GAINLLR_NF12, 0x20 },
552 { STV090x_GAINLLR_NF13, 0x20 },
553 { STV090x_GAINLLR_NF14, 0x20 },
554 { STV090x_GAINLLR_NF15, 0x20 },
555 { STV090x_GAINLLR_NF16, 0x20 },
556 { STV090x_GAINLLR_NF17, 0x21 },
559 static struct stv090x_reg stv0903_cut20_val[] = {
560 { STV090x_P1_DMDCFG3, 0xe8 },
561 { STV090x_P1_DMDCFG4, 0x10 },
562 { STV090x_P1_CARFREQ, 0x38 },
563 { STV090x_P1_CARHDR, 0x20 },
564 { STV090x_P1_KREFTMG, 0x5a },
565 { STV090x_P1_SMAPCOEF7, 0x06 },
566 { STV090x_P1_SMAPCOEF6, 0x00 },
567 { STV090x_P1_SMAPCOEF5, 0x04 },
568 { STV090x_P1_NOSCFG, 0x0c },
569 { STV090x_GAINLLR_NF4, 0x21 },
570 { STV090x_GAINLLR_NF5, 0x21 },
571 { STV090x_GAINLLR_NF6, 0x20 },
572 { STV090x_GAINLLR_NF7, 0x1F },
573 { STV090x_GAINLLR_NF8, 0x1E },
574 { STV090x_GAINLLR_NF9, 0x1E },
575 { STV090x_GAINLLR_NF10, 0x1D },
576 { STV090x_GAINLLR_NF11, 0x1B },
577 { STV090x_GAINLLR_NF12, 0x20 },
578 { STV090x_GAINLLR_NF13, 0x20 },
579 { STV090x_GAINLLR_NF14, 0x20 },
580 { STV090x_GAINLLR_NF15, 0x20 },
581 { STV090x_GAINLLR_NF16, 0x20 },
582 { STV090x_GAINLLR_NF17, 0x21 }
585 /* Cut 2.0 Long Frame Tracking CR loop */
586 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
587 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
588 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
589 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
590 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
591 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
592 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
593 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
594 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
595 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
596 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
597 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
598 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
599 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
600 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
601 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
604 /* Cut 3.0 Long Frame Tracking CR loop */
605 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
606 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
607 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
608 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
609 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
610 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
611 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
612 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
613 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
614 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
615 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
616 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
617 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
618 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
619 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
620 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
623 /* Cut 2.0 Long Frame Tracking CR Loop */
624 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
625 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
626 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
627 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
628 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
629 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
630 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
631 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
632 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
633 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
634 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
635 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
636 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
639 /* Cut 3.0 Long Frame Tracking CR Loop */
640 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
641 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
642 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
643 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
644 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
645 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
646 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
647 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
648 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
649 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
650 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
651 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
652 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
655 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
656 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
657 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
658 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
659 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
662 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
663 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
664 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
665 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
666 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
669 /* Cut 2.0 Short Frame Tracking CR Loop */
670 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
671 /* MODCOD 2M 5M 10M 20M 30M */
672 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
673 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
674 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
675 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
678 /* Cut 3.0 Short Frame Tracking CR Loop */
679 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
680 /* MODCOD 2M 5M 10M 20M 30M */
681 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
682 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
683 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
684 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
687 static inline s32 comp2(s32 __x, s32 __width)
692 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
695 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
697 const struct stv090x_config *config = state->config;
700 u8 b0[] = { reg >> 8, reg & 0xff };
703 struct i2c_msg msg[] = {
704 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
705 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
708 ret = i2c_transfer(state->i2c, msg, 2);
710 if (ret != -ERESTARTSYS)
712 "Read error, Reg=[0x%02x], Status=%d",
715 return ret < 0 ? ret : -EREMOTEIO;
717 if (unlikely(*state->verbose >= FE_DEBUGREG))
718 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
721 return (unsigned int) buf;
724 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
726 const struct stv090x_config *config = state->config;
728 u8 buf[MAX_XFER_SIZE];
729 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
731 if (2 + count > sizeof(buf)) {
733 "%s: i2c wr reg=%04x: len=%d is too big!\n",
734 KBUILD_MODNAME, reg, count);
740 memcpy(&buf[2], data, count);
742 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
745 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
746 for (i = 0; i < count; i++)
747 printk(" %02x", data[i]);
751 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
753 if (ret != -ERESTARTSYS)
754 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
755 reg, data[0], count, ret);
756 return ret < 0 ? ret : -EREMOTEIO;
762 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
764 return stv090x_write_regs(state, reg, &data, 1);
767 static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
772 * NOTE! A lock is used as a FSM to control the state in which
773 * access is serialized between two tuners on the same demod.
774 * This has nothing to do with a lock to protect a critical section
775 * which may in some other cases be confused with protecting I/O
776 * access to the demodulator gate.
777 * In case of any error, the lock is unlocked and exit within the
778 * relevant operations themselves.
781 if (state->config->tuner_i2c_lock)
782 state->config->tuner_i2c_lock(&state->frontend, 1);
784 mutex_lock(&state->internal->tuner_lock);
787 reg = STV090x_READ_DEMOD(state, I2CRPT);
789 dprintk(FE_DEBUG, 1, "Enable Gate");
790 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
791 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
795 dprintk(FE_DEBUG, 1, "Disable Gate");
796 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
797 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
802 if (state->config->tuner_i2c_lock)
803 state->config->tuner_i2c_lock(&state->frontend, 0);
805 mutex_unlock(&state->internal->tuner_lock);
810 dprintk(FE_ERROR, 1, "I/O error");
811 if (state->config->tuner_i2c_lock)
812 state->config->tuner_i2c_lock(&state->frontend, 0);
814 mutex_unlock(&state->internal->tuner_lock);
818 static void stv090x_get_lock_tmg(struct stv090x_state *state)
820 switch (state->algo) {
821 case STV090x_BLIND_SEARCH:
822 dprintk(FE_DEBUG, 1, "Blind Search");
823 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
824 state->DemodTimeout = 1500;
825 state->FecTimeout = 400;
826 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
827 state->DemodTimeout = 1000;
828 state->FecTimeout = 300;
829 } else { /*SR >20Msps*/
830 state->DemodTimeout = 700;
831 state->FecTimeout = 100;
835 case STV090x_COLD_SEARCH:
836 case STV090x_WARM_SEARCH:
838 dprintk(FE_DEBUG, 1, "Normal Search");
839 if (state->srate <= 1000000) { /*SR <=1Msps*/
840 state->DemodTimeout = 4500;
841 state->FecTimeout = 1700;
842 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
843 state->DemodTimeout = 2500;
844 state->FecTimeout = 1100;
845 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
846 state->DemodTimeout = 1000;
847 state->FecTimeout = 550;
848 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
849 state->DemodTimeout = 700;
850 state->FecTimeout = 250;
851 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
852 state->DemodTimeout = 400;
853 state->FecTimeout = 130;
854 } else { /*SR >20Msps*/
855 state->DemodTimeout = 300;
856 state->FecTimeout = 100;
861 if (state->algo == STV090x_WARM_SEARCH)
862 state->DemodTimeout /= 2;
865 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
869 if (srate > 60000000) {
870 sym = (srate << 4); /* SR * 2^16 / master_clk */
871 sym /= (state->internal->mclk >> 12);
872 } else if (srate > 6000000) {
874 sym /= (state->internal->mclk >> 10);
877 sym /= (state->internal->mclk >> 7);
880 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
882 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
887 dprintk(FE_ERROR, 1, "I/O error");
891 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
895 srate = 105 * (srate / 100);
896 if (srate > 60000000) {
897 sym = (srate << 4); /* SR * 2^16 / master_clk */
898 sym /= (state->internal->mclk >> 12);
899 } else if (srate > 6000000) {
901 sym /= (state->internal->mclk >> 10);
904 sym /= (state->internal->mclk >> 7);
908 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
910 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
913 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
915 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
921 dprintk(FE_ERROR, 1, "I/O error");
925 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
929 srate = 95 * (srate / 100);
930 if (srate > 60000000) {
931 sym = (srate << 4); /* SR * 2^16 / master_clk */
932 sym /= (state->internal->mclk >> 12);
933 } else if (srate > 6000000) {
935 sym /= (state->internal->mclk >> 10);
938 sym /= (state->internal->mclk >> 7);
941 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
943 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
947 dprintk(FE_ERROR, 1, "I/O error");
951 static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
968 return srate + (srate * ro) / 100;
971 static int stv090x_set_vit_thacq(struct stv090x_state *state)
973 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
975 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
977 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
979 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
981 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
983 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
987 dprintk(FE_ERROR, 1, "I/O error");
991 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
993 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
995 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
997 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
999 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
1001 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
1003 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
1007 dprintk(FE_ERROR, 1, "I/O error");
1011 static int stv090x_set_viterbi(struct stv090x_state *state)
1013 switch (state->search_mode) {
1014 case STV090x_SEARCH_AUTO:
1015 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
1017 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
1020 case STV090x_SEARCH_DVBS1:
1021 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
1023 switch (state->fec) {
1025 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1030 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1035 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1040 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1045 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1050 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1055 case STV090x_SEARCH_DSS:
1056 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1058 switch (state->fec) {
1060 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1065 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1070 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1075 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1085 dprintk(FE_ERROR, 1, "I/O error");
1089 static int stv090x_stop_modcod(struct stv090x_state *state)
1091 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1093 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1095 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1097 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1099 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1101 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1103 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1105 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1107 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1109 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1111 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1113 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1115 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1117 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1119 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1121 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1125 dprintk(FE_ERROR, 1, "I/O error");
1129 static int stv090x_activate_modcod(struct stv090x_state *state)
1131 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1133 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1135 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1137 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1139 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1141 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1143 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1145 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1147 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1149 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1151 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1153 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1155 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1157 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1159 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1161 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1166 dprintk(FE_ERROR, 1, "I/O error");
1170 static int stv090x_activate_modcod_single(struct stv090x_state *state)
1173 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1175 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1177 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1179 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1181 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1183 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1185 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1187 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1189 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1191 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1193 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1195 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1197 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1199 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1201 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1203 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1209 dprintk(FE_ERROR, 1, "I/O error");
1213 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1217 switch (state->demod) {
1218 case STV090x_DEMODULATOR_0:
1219 mutex_lock(&state->internal->demod_lock);
1220 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1221 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1222 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1224 mutex_unlock(&state->internal->demod_lock);
1227 case STV090x_DEMODULATOR_1:
1228 mutex_lock(&state->internal->demod_lock);
1229 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1230 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1231 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1233 mutex_unlock(&state->internal->demod_lock);
1237 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1242 mutex_unlock(&state->internal->demod_lock);
1243 dprintk(FE_ERROR, 1, "I/O error");
1247 static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1249 if (state->internal->dev_ver >= 0x30) {
1250 /* Set ACLC BCLC optimised value vs SR */
1251 if (state->srate >= 15000000) {
1252 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1254 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1256 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1257 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1259 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1261 } else if (state->srate < 7000000) {
1262 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1264 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1270 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1272 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1277 dprintk(FE_ERROR, 1, "I/O error");
1281 static int stv090x_delivery_search(struct stv090x_state *state)
1285 switch (state->search_mode) {
1286 case STV090x_SEARCH_DVBS1:
1287 case STV090x_SEARCH_DSS:
1288 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1289 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1290 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1291 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1294 /* Activate Viterbi decoder in legacy search,
1295 * do not use FRESVIT1, might impact VITERBI2
1297 if (stv090x_vitclk_ctl(state, 0) < 0)
1300 if (stv090x_dvbs_track_crl(state) < 0)
1303 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1306 if (stv090x_set_vit_thacq(state) < 0)
1308 if (stv090x_set_viterbi(state) < 0)
1312 case STV090x_SEARCH_DVBS2:
1313 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1314 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1315 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1316 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1318 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1319 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1320 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1323 if (stv090x_vitclk_ctl(state, 1) < 0)
1326 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1328 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1331 if (state->internal->dev_ver <= 0x20) {
1332 /* enable S2 carrier loop */
1333 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1336 /* > Cut 3: Stop carrier 3 */
1337 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1341 if (state->demod_mode != STV090x_SINGLE) {
1342 /* Cut 2: enable link during search */
1343 if (stv090x_activate_modcod(state) < 0)
1346 /* Single demodulator
1347 * Authorize SHORT and LONG frames,
1348 * QPSK, 8PSK, 16APSK and 32APSK
1350 if (stv090x_activate_modcod_single(state) < 0)
1354 if (stv090x_set_vit_thtracq(state) < 0)
1358 case STV090x_SEARCH_AUTO:
1360 /* enable DVB-S2 and DVB-S2 in Auto MODE */
1361 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1362 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1363 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1364 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1366 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1367 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1368 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1371 if (stv090x_vitclk_ctl(state, 0) < 0)
1374 if (stv090x_dvbs_track_crl(state) < 0)
1377 if (state->internal->dev_ver <= 0x20) {
1378 /* enable S2 carrier loop */
1379 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1382 /* > Cut 3: Stop carrier 3 */
1383 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1387 if (state->demod_mode != STV090x_SINGLE) {
1388 /* Cut 2: enable link during search */
1389 if (stv090x_activate_modcod(state) < 0)
1392 /* Single demodulator
1393 * Authorize SHORT and LONG frames,
1394 * QPSK, 8PSK, 16APSK and 32APSK
1396 if (stv090x_activate_modcod_single(state) < 0)
1400 if (stv090x_set_vit_thacq(state) < 0)
1403 if (stv090x_set_viterbi(state) < 0)
1409 dprintk(FE_ERROR, 1, "I/O error");
1413 static int stv090x_start_search(struct stv090x_state *state)
1418 /* Reset demodulator */
1419 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1420 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1421 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1424 if (state->internal->dev_ver <= 0x20) {
1425 if (state->srate <= 5000000) {
1426 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1428 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1430 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1432 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1434 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1437 /*enlarge the timing bandwidth for Low SR*/
1438 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1441 /* If the symbol rate is >5 Msps
1442 Set The carrier search up and low to auto mode */
1443 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1445 /*reduce the timing bandwidth for high SR*/
1446 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1451 if (state->srate <= 5000000) {
1452 /* enlarge the timing bandwidth for Low SR */
1453 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1455 /* reduce timing bandwidth for high SR */
1456 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1459 /* Set CFR min and max to manual mode */
1460 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1462 if (state->algo == STV090x_WARM_SEARCH) {
1467 freq_abs = 1000 << 16;
1468 freq_abs /= (state->internal->mclk / 1000);
1469 freq = (s16) freq_abs;
1472 * CFR min =- (SearchRange / 2 + 600KHz)
1473 * CFR max = +(SearchRange / 2 + 600KHz)
1474 * (600KHz for the tuner step size)
1476 freq_abs = (state->search_range / 2000) + 600;
1477 freq_abs = freq_abs << 16;
1478 freq_abs /= (state->internal->mclk / 1000);
1479 freq = (s16) freq_abs;
1482 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1484 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1489 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1491 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1496 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1498 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1501 if (state->internal->dev_ver >= 0x20) {
1502 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1504 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1507 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
1508 (state->search_mode == STV090x_SEARCH_DSS) ||
1509 (state->search_mode == STV090x_SEARCH_AUTO)) {
1511 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1513 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1518 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1520 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1522 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1525 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1526 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1527 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1528 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1530 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1531 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1532 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1535 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1538 if (state->internal->dev_ver >= 0x20) {
1539 /*Frequency offset detector setting*/
1540 if (state->srate < 2000000) {
1541 if (state->internal->dev_ver <= 0x20) {
1543 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1547 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1550 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1552 } else if (state->srate < 10000000) {
1553 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1555 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1558 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1560 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1564 if (state->srate < 10000000) {
1565 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1568 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1573 switch (state->algo) {
1574 case STV090x_WARM_SEARCH:
1575 /* The symbol rate and the exact
1576 * carrier Frequency are known
1578 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1580 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1584 case STV090x_COLD_SEARCH:
1585 /* The symbol rate is known */
1586 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1588 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1597 dprintk(FE_ERROR, 1, "I/O error");
1601 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1603 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1604 s32 i, j, steps, dir;
1606 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1608 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1609 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1610 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1611 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1614 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1616 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1618 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1620 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1622 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1624 if (stv090x_set_srate(state, 1000000) < 0)
1627 steps = state->search_range / 1000000;
1632 freq_step = (1000000 * 256) / (state->internal->mclk / 256);
1635 for (i = 0; i < steps; i++) {
1637 freq_init = freq_init + (freq_step * i);
1639 freq_init = freq_init - (freq_step * i);
1643 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1645 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1647 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1649 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1654 for (j = 0; j < 10; j++) {
1655 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1656 STV090x_READ_DEMOD(state, AGC2I0);
1659 if (agc2 < agc2_min)
1665 dprintk(FE_ERROR, 1, "I/O error");
1669 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1672 s32 srate, int_1, int_2, tmp_1, tmp_2;
1674 r3 = STV090x_READ_DEMOD(state, SFR3);
1675 r2 = STV090x_READ_DEMOD(state, SFR2);
1676 r1 = STV090x_READ_DEMOD(state, SFR1);
1677 r0 = STV090x_READ_DEMOD(state, SFR0);
1679 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1682 int_2 = srate >> 16;
1684 tmp_1 = clk % 0x10000;
1685 tmp_2 = srate % 0x10000;
1687 srate = (int_1 * int_2) +
1688 ((int_1 * tmp_2) >> 16) +
1689 ((int_2 * tmp_1) >> 16);
1694 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1696 struct dvb_frontend *fe = &state->frontend;
1698 int tmg_lock = 0, i;
1699 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1700 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1703 if (state->internal->dev_ver >= 0x30)
1708 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1709 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1710 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1712 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1714 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1716 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1718 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1720 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1721 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1722 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1723 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1726 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1728 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1730 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1732 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1734 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1736 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1739 if (state->internal->dev_ver >= 0x30) {
1740 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1742 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1745 } else if (state->internal->dev_ver >= 0x20) {
1746 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1748 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1752 if (state->srate <= 2000000)
1754 else if (state->srate <= 5000000)
1756 else if (state->srate <= 12000000)
1761 steps = -1 + ((state->search_range / 1000) / car_step);
1763 steps = (2 * steps) + 1;
1766 else if (steps > 10) {
1768 car_step = (state->search_range / 1000) / 10;
1772 freq = state->frequency;
1774 while ((!tmg_lock) && (cur_step < steps)) {
1775 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1777 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1779 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1781 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1783 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1785 /* trigger acquisition */
1786 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1789 for (i = 0; i < 10; i++) {
1790 reg = STV090x_READ_DEMOD(state, DSTATUS);
1791 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1793 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1794 STV090x_READ_DEMOD(state, AGC2I0);
1797 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1800 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1801 (srate_coarse < 50000000) && (srate_coarse > 850000))
1803 else if (cur_step < steps) {
1805 freq += cur_step * car_step;
1807 freq -= cur_step * car_step;
1810 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1813 if (state->config->tuner_set_frequency) {
1814 if (state->config->tuner_set_frequency(fe, freq) < 0)
1818 if (state->config->tuner_set_bandwidth) {
1819 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1823 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1828 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1831 if (state->config->tuner_get_status) {
1832 if (state->config->tuner_get_status(fe, ®) < 0)
1837 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1839 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1841 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1849 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1851 return srate_coarse;
1854 stv090x_i2c_gate_ctrl(state, 0);
1856 dprintk(FE_ERROR, 1, "I/O error");
1860 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1862 u32 srate_coarse, freq_coarse, sym, reg;
1864 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1865 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1866 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1867 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1869 if (sym < state->srate)
1872 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1874 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1876 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1878 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1880 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1882 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1883 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1884 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1887 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1890 if (state->internal->dev_ver >= 0x30) {
1891 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1893 } else if (state->internal->dev_ver >= 0x20) {
1894 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1898 if (srate_coarse > 3000000) {
1899 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1900 sym = (sym / 1000) * 65536;
1901 sym /= (state->internal->mclk / 1000);
1902 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1904 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1906 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1907 sym = (sym / 1000) * 65536;
1908 sym /= (state->internal->mclk / 1000);
1909 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1911 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1913 sym = (srate_coarse / 1000) * 65536;
1914 sym /= (state->internal->mclk / 1000);
1915 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1917 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1920 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1921 sym = (sym / 100) * 65536;
1922 sym /= (state->internal->mclk / 100);
1923 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1925 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1927 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1928 sym = (sym / 100) * 65536;
1929 sym /= (state->internal->mclk / 100);
1930 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1932 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1934 sym = (srate_coarse / 100) * 65536;
1935 sym /= (state->internal->mclk / 100);
1936 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1938 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1941 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1943 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1945 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1947 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1951 return srate_coarse;
1954 dprintk(FE_ERROR, 1, "I/O error");
1958 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1960 s32 timer = 0, lock = 0;
1964 while ((timer < timeout) && (!lock)) {
1965 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1966 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1969 case 0: /* searching */
1970 case 1: /* first PLH detected */
1972 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1975 case 2: /* DVB-S2 mode */
1976 case 3: /* DVB-S1/legacy mode */
1977 reg = STV090x_READ_DEMOD(state, DSTATUS);
1978 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1985 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1992 static int stv090x_blind_search(struct stv090x_state *state)
1994 u32 agc2, reg, srate_coarse;
1995 s32 cpt_fail, agc2_ovflw, i;
1996 u8 k_ref, k_max, k_min;
1997 int coarse_fail = 0;
2003 agc2 = stv090x_get_agc2_min_level(state);
2005 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
2009 if (state->internal->dev_ver <= 0x20) {
2010 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
2014 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
2018 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
2021 if (state->internal->dev_ver >= 0x20) {
2022 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
2024 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
2026 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
2028 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
2034 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2036 if (stv090x_srate_srch_coarse(state) != 0) {
2037 srate_coarse = stv090x_srate_srch_fine(state);
2038 if (srate_coarse != 0) {
2039 stv090x_get_lock_tmg(state);
2040 lock = stv090x_get_dmdlock(state,
2041 state->DemodTimeout);
2048 for (i = 0; i < 10; i++) {
2049 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2050 STV090x_READ_DEMOD(state, AGC2I0);
2053 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2054 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2055 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2059 if ((cpt_fail > 7) || (agc2_ovflw > 7))
2065 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
2071 dprintk(FE_ERROR, 1, "I/O error");
2075 static int stv090x_chk_tmg(struct stv090x_state *state)
2079 u8 freq, tmg_thh, tmg_thl;
2082 freq = STV090x_READ_DEMOD(state, CARFREQ);
2083 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2084 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2085 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2087 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2090 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2091 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2092 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2094 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2097 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2099 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2102 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2104 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2106 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2109 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2113 for (i = 0; i < 10; i++) {
2114 reg = STV090x_READ_DEMOD(state, DSTATUS);
2115 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2122 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2124 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2126 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2129 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2131 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2133 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2139 dprintk(FE_ERROR, 1, "I/O error");
2143 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2145 struct dvb_frontend *fe = &state->frontend;
2148 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2151 if (state->srate >= 10000000)
2152 timeout_lock = timeout_dmd / 3;
2154 timeout_lock = timeout_dmd / 2;
2156 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2160 if (state->srate >= 10000000) {
2161 if (stv090x_chk_tmg(state)) {
2162 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2164 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2166 return stv090x_get_dmdlock(state, timeout_dmd);
2171 if (state->srate <= 4000000)
2173 else if (state->srate <= 7000000)
2175 else if (state->srate <= 10000000)
2180 steps = (state->search_range / 1000) / car_step;
2182 steps = 2 * (steps + 1);
2185 else if (steps > 12)
2191 freq = state->frequency;
2192 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2193 while ((cur_step <= steps) && (!lock)) {
2195 freq += cur_step * car_step;
2197 freq -= cur_step * car_step;
2200 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2203 if (state->config->tuner_set_frequency) {
2204 if (state->config->tuner_set_frequency(fe, freq) < 0)
2208 if (state->config->tuner_set_bandwidth) {
2209 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2213 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2218 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2221 if (state->config->tuner_get_status) {
2222 if (state->config->tuner_get_status(fe, ®) < 0)
2227 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2229 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2231 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2234 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2235 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2237 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2239 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2241 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2243 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2252 stv090x_i2c_gate_ctrl(state, 0);
2254 dprintk(FE_ERROR, 1, "I/O error");
2258 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2260 s32 timeout, inc, steps_max, srate, car_max;
2262 srate = state->srate;
2263 car_max = state->search_range / 1000;
2264 car_max += car_max / 10;
2265 car_max = 65536 * (car_max / 2);
2266 car_max /= (state->internal->mclk / 1000);
2268 if (car_max > 0x4000)
2269 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2272 inc /= state->internal->mclk / 1000;
2277 switch (state->search_mode) {
2278 case STV090x_SEARCH_DVBS1:
2279 case STV090x_SEARCH_DSS:
2280 inc *= 3; /* freq step = 3% of srate */
2284 case STV090x_SEARCH_DVBS2:
2289 case STV090x_SEARCH_AUTO:
2296 if ((inc > car_max) || (inc < 0))
2297 inc = car_max / 2; /* increment <= 1/8 Mclk */
2299 timeout *= 27500; /* 27.5 Msps reference */
2301 timeout /= (srate / 1000);
2303 if ((timeout > 100) || (timeout < 0))
2306 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2307 if ((steps_max > 100) || (steps_max < 0)) {
2308 steps_max = 100; /* max steps <= 100 */
2309 inc = car_max / steps_max;
2312 *timeout_sw = timeout;
2318 static int stv090x_chk_signal(struct stv090x_state *state)
2320 s32 offst_car, agc2, car_max;
2323 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2324 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2325 offst_car = comp2(offst_car, 16);
2327 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2328 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2329 car_max = state->search_range / 1000;
2331 car_max += (car_max / 10); /* 10% margin */
2332 car_max = (65536 * car_max / 2);
2333 car_max /= state->internal->mclk / 1000;
2335 if (car_max > 0x4000)
2338 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2340 dprintk(FE_DEBUG, 1, "No Signal");
2343 dprintk(FE_DEBUG, 1, "Found Signal");
2349 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2351 int no_signal, lock = 0;
2352 s32 cpt_step = 0, offst_freq, car_max;
2355 car_max = state->search_range / 1000;
2356 car_max += (car_max / 10);
2357 car_max = (65536 * car_max / 2);
2358 car_max /= (state->internal->mclk / 1000);
2359 if (car_max > 0x4000)
2365 offst_freq = -car_max + inc;
2368 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2370 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2372 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2374 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2377 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2378 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2379 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2383 if (offst_freq >= 0)
2384 offst_freq = -offst_freq - 2 * inc;
2386 offst_freq = -offst_freq;
2388 offst_freq += 2 * inc;
2393 lock = stv090x_get_dmdlock(state, timeout);
2394 no_signal = stv090x_chk_signal(state);
2398 ((offst_freq - inc) < car_max) &&
2399 ((offst_freq + inc) > -car_max) &&
2400 (cpt_step < steps_max));
2402 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2403 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2404 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2409 dprintk(FE_ERROR, 1, "I/O error");
2413 static int stv090x_sw_algo(struct stv090x_state *state)
2415 int no_signal, zigzag, lock = 0;
2418 s32 dvbs2_fly_wheel;
2419 s32 inc, timeout_step, trials, steps_max;
2422 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2424 switch (state->search_mode) {
2425 case STV090x_SEARCH_DVBS1:
2426 case STV090x_SEARCH_DSS:
2427 /* accelerate the frequency detector */
2428 if (state->internal->dev_ver >= 0x20) {
2429 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2433 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2438 case STV090x_SEARCH_DVBS2:
2439 if (state->internal->dev_ver >= 0x20) {
2440 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2444 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2449 case STV090x_SEARCH_AUTO:
2451 /* accelerate the frequency detector */
2452 if (state->internal->dev_ver >= 0x20) {
2453 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2455 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2459 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2467 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2468 no_signal = stv090x_chk_signal(state);
2471 /*run the SW search 2 times maximum*/
2472 if (lock || no_signal || (trials == 2)) {
2473 /*Check if the demod is not losing lock in DVBS2*/
2474 if (state->internal->dev_ver >= 0x20) {
2475 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2477 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2481 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2482 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2483 /*Check if the demod is not losing lock in DVBS2*/
2484 msleep(timeout_step);
2485 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2486 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2487 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2488 msleep(timeout_step);
2489 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2490 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2492 if (dvbs2_fly_wheel < 0xd) {
2493 /*FALSE lock, The demod is losing lock */
2496 if (state->internal->dev_ver >= 0x20) {
2497 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2501 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2507 } while ((!lock) && (trials < 2) && (!no_signal));
2511 dprintk(FE_ERROR, 1, "I/O error");
2515 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2518 enum stv090x_delsys delsys;
2520 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2521 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2522 delsys = STV090x_DVBS2;
2523 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2524 reg = STV090x_READ_DEMOD(state, FECM);
2525 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2526 delsys = STV090x_DSS;
2528 delsys = STV090x_DVBS1;
2530 delsys = STV090x_ERROR;
2537 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2539 s32 derot, int_1, int_2, tmp_1, tmp_2;
2541 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2542 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2543 derot |= STV090x_READ_DEMOD(state, CFR0);
2545 derot = comp2(derot, 24);
2547 int_2 = derot >> 12;
2549 /* carrier_frequency = MasterClock * Reg / 2^24 */
2550 tmp_1 = mclk % 0x1000;
2551 tmp_2 = derot % 0x1000;
2553 derot = (int_1 * int_2) +
2554 ((int_1 * tmp_2) >> 12) +
2555 ((int_2 * tmp_1) >> 12);
2560 static int stv090x_get_viterbi(struct stv090x_state *state)
2564 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2565 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2569 state->fec = STV090x_PR12;
2573 state->fec = STV090x_PR23;
2577 state->fec = STV090x_PR34;
2581 state->fec = STV090x_PR56;
2585 state->fec = STV090x_PR67;
2589 state->fec = STV090x_PR78;
2593 state->fec = STV090x_PRERR;
2600 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2602 struct dvb_frontend *fe = &state->frontend;
2606 s32 i = 0, offst_freq;
2610 if (state->algo == STV090x_BLIND_SEARCH) {
2611 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2612 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2613 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
2614 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2619 state->delsys = stv090x_get_std(state);
2621 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2624 if (state->config->tuner_get_frequency) {
2625 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2629 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2632 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
2633 state->frequency += offst_freq;
2635 if (stv090x_get_viterbi(state) < 0)
2638 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2639 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2640 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2641 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2642 reg = STV090x_READ_DEMOD(state, TMGOBS);
2643 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2644 reg = STV090x_READ_DEMOD(state, FECM);
2645 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2647 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2649 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2652 if (state->config->tuner_get_frequency) {
2653 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2657 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2660 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2661 return STV090x_RANGEOK;
2662 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2663 return STV090x_RANGEOK;
2665 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2666 return STV090x_RANGEOK;
2669 return STV090x_OUTOFRANGE;
2672 stv090x_i2c_gate_ctrl(state, 0);
2674 dprintk(FE_ERROR, 1, "I/O error");
2678 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2682 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2683 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2684 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2686 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2690 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
2696 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2700 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
2702 if (state->internal->dev_ver == 0x20) {
2703 car_loop = stv090x_s2_crl_cut20;
2704 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2705 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2708 car_loop = stv090x_s2_crl_cut30;
2709 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2710 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2713 if (modcod < STV090x_QPSK_12) {
2715 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
2723 while ((i < 14) && (modcod != car_loop[i].modcod))
2728 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
2736 if (modcod <= STV090x_QPSK_25) {
2738 if (state->srate <= 3000000)
2739 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
2740 else if (state->srate <= 7000000)
2741 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
2742 else if (state->srate <= 15000000)
2743 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
2744 else if (state->srate <= 25000000)
2745 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
2747 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
2749 if (state->srate <= 3000000)
2750 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
2751 else if (state->srate <= 7000000)
2752 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
2753 else if (state->srate <= 15000000)
2754 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
2755 else if (state->srate <= 25000000)
2756 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
2758 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
2761 } else if (modcod <= STV090x_8PSK_910) {
2763 if (state->srate <= 3000000)
2764 aclc = car_loop[i].crl_pilots_on_2;
2765 else if (state->srate <= 7000000)
2766 aclc = car_loop[i].crl_pilots_on_5;
2767 else if (state->srate <= 15000000)
2768 aclc = car_loop[i].crl_pilots_on_10;
2769 else if (state->srate <= 25000000)
2770 aclc = car_loop[i].crl_pilots_on_20;
2772 aclc = car_loop[i].crl_pilots_on_30;
2774 if (state->srate <= 3000000)
2775 aclc = car_loop[i].crl_pilots_off_2;
2776 else if (state->srate <= 7000000)
2777 aclc = car_loop[i].crl_pilots_off_5;
2778 else if (state->srate <= 15000000)
2779 aclc = car_loop[i].crl_pilots_off_10;
2780 else if (state->srate <= 25000000)
2781 aclc = car_loop[i].crl_pilots_off_20;
2783 aclc = car_loop[i].crl_pilots_off_30;
2785 } else { /* 16APSK and 32APSK */
2787 * This should never happen in practice, except if
2788 * something is really wrong at the car_loop table.
2792 if (state->srate <= 3000000)
2793 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
2794 else if (state->srate <= 7000000)
2795 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
2796 else if (state->srate <= 15000000)
2797 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
2798 else if (state->srate <= 25000000)
2799 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
2801 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
2807 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2809 struct stv090x_short_frame_crloop *short_crl = NULL;
2813 switch (state->modulation) {
2821 case STV090x_16APSK:
2824 case STV090x_32APSK:
2829 if (state->internal->dev_ver >= 0x30) {
2830 /* Cut 3.0 and up */
2831 short_crl = stv090x_s2_short_crl_cut30;
2833 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2834 short_crl = stv090x_s2_short_crl_cut20;
2837 if (state->srate <= 3000000)
2838 aclc = short_crl[index].crl_2;
2839 else if (state->srate <= 7000000)
2840 aclc = short_crl[index].crl_5;
2841 else if (state->srate <= 15000000)
2842 aclc = short_crl[index].crl_10;
2843 else if (state->srate <= 25000000)
2844 aclc = short_crl[index].crl_20;
2846 aclc = short_crl[index].crl_30;
2851 static int stv090x_optimize_track(struct stv090x_state *state)
2853 struct dvb_frontend *fe = &state->frontend;
2855 enum stv090x_modcod modcod;
2857 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2860 srate = stv090x_get_srate(state, state->internal->mclk);
2861 srate += stv090x_get_tmgoffst(state, srate);
2863 switch (state->delsys) {
2866 if (state->search_mode == STV090x_SEARCH_AUTO) {
2867 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2868 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2869 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2870 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2873 reg = STV090x_READ_DEMOD(state, DEMOD);
2874 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2875 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2876 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2879 if (state->internal->dev_ver >= 0x30) {
2880 if (stv090x_get_viterbi(state) < 0)
2883 if (state->fec == STV090x_PR12) {
2884 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2886 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2889 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2891 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2896 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2901 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2902 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2903 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2904 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2906 if (state->internal->dev_ver >= 0x30) {
2907 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2909 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2912 if (state->frame_len == STV090x_LONG_FRAME) {
2913 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2914 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2915 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2916 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2917 if (modcod <= STV090x_QPSK_910) {
2918 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2919 } else if (modcod <= STV090x_8PSK_910) {
2920 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2922 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2925 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2926 if (modcod <= STV090x_16APSK_910) {
2927 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2929 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2932 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2934 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2939 /*Carrier loop setting for short frame*/
2940 aclc = stv090x_optimize_carloop_short(state);
2941 if (state->modulation == STV090x_QPSK) {
2942 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2944 } else if (state->modulation == STV090x_8PSK) {
2945 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2947 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2949 } else if (state->modulation == STV090x_16APSK) {
2950 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2952 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2954 } else if (state->modulation == STV090x_32APSK) {
2955 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2957 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2962 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2967 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2968 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2969 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2970 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2975 f_1 = STV090x_READ_DEMOD(state, CFR2);
2976 f_0 = STV090x_READ_DEMOD(state, CFR1);
2977 reg = STV090x_READ_DEMOD(state, TMGOBS);
2979 if (state->algo == STV090x_BLIND_SEARCH) {
2980 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2981 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2982 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2983 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2984 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2986 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2989 if (stv090x_set_srate(state, srate) < 0)
2993 if (stv090x_dvbs_track_crl(state) < 0)
2997 if (state->internal->dev_ver >= 0x20) {
2998 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2999 (state->search_mode == STV090x_SEARCH_DSS) ||
3000 (state->search_mode == STV090x_SEARCH_AUTO)) {
3002 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
3004 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
3009 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3012 /* AUTO tracking MODE */
3013 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
3015 /* AUTO tracking MODE */
3016 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
3019 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
3020 (state->srate < 10000000)) {
3021 /* update initial carrier freq with the found freq offset */
3022 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3024 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3026 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
3028 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
3030 if (state->algo != STV090x_WARM_SEARCH) {
3032 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3035 if (state->config->tuner_set_bandwidth) {
3036 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3040 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3045 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3046 msleep(50); /* blind search: wait 50ms for SR stabilization */
3050 stv090x_get_lock_tmg(state);
3052 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3053 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3055 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3057 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3059 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3064 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3066 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3068 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3070 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3072 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3080 if (state->internal->dev_ver >= 0x20) {
3081 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3085 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3086 stv090x_set_vit_thtracq(state);
3091 stv090x_i2c_gate_ctrl(state, 0);
3093 dprintk(FE_ERROR, 1, "I/O error");
3097 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3099 s32 timer = 0, lock = 0, stat;
3102 while ((timer < timeout) && (!lock)) {
3103 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3104 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3107 case 0: /* searching */
3108 case 1: /* first PLH detected */
3113 case 2: /* DVB-S2 mode */
3114 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3115 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3118 case 3: /* DVB-S1/legacy mode */
3119 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3120 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3131 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3137 lock = stv090x_get_dmdlock(state, timeout_dmd);
3139 lock = stv090x_get_feclock(state, timeout_fec);
3144 while ((timer < timeout_fec) && (!lock)) {
3145 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3146 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3155 static int stv090x_set_s2rolloff(struct stv090x_state *state)
3159 if (state->internal->dev_ver <= 0x20) {
3160 /* rolloff to auto mode if DVBS2 */
3161 reg = STV090x_READ_DEMOD(state, DEMOD);
3162 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3163 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3166 /* DVB-S2 rolloff to auto mode if DVBS2 */
3167 reg = STV090x_READ_DEMOD(state, DEMOD);
3168 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3169 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3174 dprintk(FE_ERROR, 1, "I/O error");
3179 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3181 struct dvb_frontend *fe = &state->frontend;
3182 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3184 s32 agc1_power, power_iq = 0, i;
3185 int lock = 0, low_sr = 0;
3187 reg = STV090x_READ_DEMOD(state, TSCFGH);
3188 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3189 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3192 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3195 if (state->internal->dev_ver >= 0x20) {
3196 if (state->srate > 5000000) {
3197 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3200 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3205 stv090x_get_lock_tmg(state);
3207 if (state->algo == STV090x_BLIND_SEARCH) {
3208 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3209 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3211 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3213 if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */
3217 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3219 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3222 if (state->srate < 2000000) {
3224 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3228 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3232 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3235 if (state->internal->dev_ver >= 0x20) {
3236 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3238 if (state->algo == STV090x_COLD_SEARCH)
3239 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3240 else if (state->algo == STV090x_WARM_SEARCH)
3241 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3244 /* if cold start or warm (Symbolrate is known)
3245 * use a Narrow symbol rate scan range
3247 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3250 if (stv090x_set_srate(state, state->srate) < 0)
3253 if (stv090x_set_max_srate(state, state->internal->mclk,
3256 if (stv090x_set_min_srate(state, state->internal->mclk,
3260 if (state->srate >= 10000000)
3267 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3270 if (state->config->tuner_set_bbgain) {
3271 reg = state->config->tuner_bbgain;
3273 reg = 10; /* default: 10dB */
3274 if (state->config->tuner_set_bbgain(fe, reg) < 0)
3278 if (state->config->tuner_set_frequency) {
3279 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3283 if (state->config->tuner_set_bandwidth) {
3284 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3288 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3293 if (state->config->tuner_get_status) {
3294 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3296 if (state->config->tuner_get_status(fe, ®) < 0)
3298 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3302 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3304 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3305 return STV090x_NOCARRIER;
3310 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3311 STV090x_READ_DEMOD(state, AGCIQIN0));
3313 if (agc1_power == 0) {
3314 /* If AGC1 integrator value is 0
3315 * then read POWERI, POWERQ
3317 for (i = 0; i < 5; i++) {
3318 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3319 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3324 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3325 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3327 signal_state = STV090x_NOAGC1;
3329 reg = STV090x_READ_DEMOD(state, DEMOD);
3330 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3332 if (state->internal->dev_ver <= 0x20) {
3333 /* rolloff to auto mode if DVBS2 */
3334 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3336 /* DVB-S2 rolloff to auto mode if DVBS2 */
3337 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3339 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3342 if (stv090x_delivery_search(state) < 0)
3345 if (state->algo != STV090x_BLIND_SEARCH) {
3346 if (stv090x_start_search(state) < 0)
3351 if (signal_state == STV090x_NOAGC1)
3352 return signal_state;
3354 if (state->algo == STV090x_BLIND_SEARCH)
3355 lock = stv090x_blind_search(state);
3357 else if (state->algo == STV090x_COLD_SEARCH)
3358 lock = stv090x_get_coldlock(state, state->DemodTimeout);
3360 else if (state->algo == STV090x_WARM_SEARCH)
3361 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3363 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3365 if (stv090x_chk_tmg(state))
3366 lock = stv090x_sw_algo(state);
3371 signal_state = stv090x_get_sig_params(state);
3373 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3374 stv090x_optimize_track(state);
3376 if (state->internal->dev_ver >= 0x20) {
3377 /* >= Cut 2.0 :release TS reset after
3378 * demod lock and optimized Tracking
3380 reg = STV090x_READ_DEMOD(state, TSCFGH);
3381 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3382 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3387 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3388 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3391 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3392 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3396 lock = stv090x_get_lock(state, state->FecTimeout,
3399 if (state->delsys == STV090x_DVBS2) {
3400 stv090x_set_s2rolloff(state);
3402 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3403 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3404 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3406 /* Reset DVBS2 packet delinator error counter */
3407 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3408 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3409 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3412 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3415 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3418 /* Reset the Total packet counter */
3419 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3421 /* Reset the packet Error counter2 */
3422 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3425 signal_state = STV090x_NODATA;
3426 stv090x_chk_signal(state);
3429 return signal_state;
3432 stv090x_i2c_gate_ctrl(state, 0);
3434 dprintk(FE_ERROR, 1, "I/O error");
3438 static int stv090x_set_mis(struct stv090x_state *state, int mis)
3442 if (mis < 0 || mis > 255) {
3443 dprintk(FE_DEBUG, 1, "Disable MIS filtering");
3444 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3445 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00);
3446 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3449 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis);
3450 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3451 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01);
3452 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3454 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0)
3456 if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0)
3461 dprintk(FE_ERROR, 1, "I/O error");
3465 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe)
3467 struct stv090x_state *state = fe->demodulator_priv;
3468 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3470 if (props->frequency == 0)
3471 return DVBFE_ALGO_SEARCH_INVALID;
3473 switch (props->delivery_system) {
3475 state->delsys = STV090x_DSS;
3478 state->delsys = STV090x_DVBS1;
3481 state->delsys = STV090x_DVBS2;
3484 return DVBFE_ALGO_SEARCH_INVALID;
3487 state->frequency = props->frequency;
3488 state->srate = props->symbol_rate;
3489 state->search_mode = STV090x_SEARCH_AUTO;
3490 state->algo = STV090x_COLD_SEARCH;
3491 state->fec = STV090x_PRERR;
3492 if (state->srate > 10000000) {
3493 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3494 state->search_range = 10000000;
3496 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3497 state->search_range = 5000000;
3500 stv090x_set_mis(state, props->stream_id);
3502 if (stv090x_algo(state) == STV090x_RANGEOK) {
3503 dprintk(FE_DEBUG, 1, "Search success!");
3504 return DVBFE_ALGO_SEARCH_SUCCESS;
3506 dprintk(FE_DEBUG, 1, "Search failed!");
3507 return DVBFE_ALGO_SEARCH_FAILED;
3510 return DVBFE_ALGO_SEARCH_ERROR;
3513 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3515 struct stv090x_state *state = fe->demodulator_priv;
3521 dstatus = STV090x_READ_DEMOD(state, DSTATUS);
3522 if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD))
3523 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
3525 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3526 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3528 switch (search_state) {
3529 case 0: /* searching */
3530 case 1: /* first PLH detected */
3532 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3535 case 2: /* DVB-S2 mode */
3536 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3537 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
3538 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3539 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3540 *status |= FE_HAS_VITERBI;
3541 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3542 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3543 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
3548 case 3: /* DVB-S1/legacy mode */
3549 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3550 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
3551 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3552 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3553 *status |= FE_HAS_VITERBI;
3554 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3555 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3556 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
3565 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3567 struct stv090x_state *state = fe->demodulator_priv;
3569 s32 count_4, count_3, count_2, count_1, count_0, count;
3571 enum fe_status status;
3573 stv090x_read_status(fe, &status);
3574 if (!(status & FE_HAS_LOCK)) {
3575 *per = 1 << 23; /* Max PER */
3578 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3579 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3581 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3582 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3584 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3585 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3587 *per = ((h << 16) | (m << 8) | l);
3589 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3590 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3591 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3592 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3593 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3595 if ((!count_4) && (!count_3)) {
3596 count = (count_2 & 0xff) << 16;
3597 count |= (count_1 & 0xff) << 8;
3598 count |= count_0 & 0xff;
3605 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3607 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3612 dprintk(FE_ERROR, 1, "I/O error");
3616 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3621 if ((val >= tab[min].read && val < tab[max].read) ||
3622 (val >= tab[max].read && val < tab[min].read)) {
3623 while ((max - min) > 1) {
3624 med = (max + min) / 2;
3625 if ((val >= tab[min].read && val < tab[med].read) ||
3626 (val >= tab[med].read && val < tab[min].read))
3631 res = ((val - tab[min].read) *
3632 (tab[max].real - tab[min].real) /
3633 (tab[max].read - tab[min].read)) +
3636 if (tab[min].read < tab[max].read) {
3637 if (val < tab[min].read)
3638 res = tab[min].real;
3639 else if (val >= tab[max].read)
3640 res = tab[max].real;
3642 if (val >= tab[min].read)
3643 res = tab[min].real;
3644 else if (val < tab[max].read)
3645 res = tab[max].real;
3652 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3654 struct stv090x_state *state = fe->demodulator_priv;
3656 s32 agc_0, agc_1, agc;
3659 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3660 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3661 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3662 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3663 agc = MAKEWORD16(agc_1, agc_0);
3665 str = stv090x_table_lookup(stv090x_rf_tab,
3666 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3667 if (agc > stv090x_rf_tab[0].read)
3669 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3671 *strength = (str + 100) * 0xFFFF / 100;
3676 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3678 struct stv090x_state *state = fe->demodulator_priv;
3679 u32 reg_0, reg_1, reg, i;
3680 s32 val_0, val_1, val = 0;
3685 switch (state->delsys) {
3687 reg = STV090x_READ_DEMOD(state, DSTATUS);
3688 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3691 for (i = 0; i < 16; i++) {
3692 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3693 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3694 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3695 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3696 val += MAKEWORD16(val_1, val_0);
3700 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3701 div = stv090x_s2cn_tab[0].read -
3702 stv090x_s2cn_tab[last].read;
3703 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3709 reg = STV090x_READ_DEMOD(state, DSTATUS);
3710 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3713 for (i = 0; i < 16; i++) {
3714 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3715 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3716 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3717 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3718 val += MAKEWORD16(val_1, val_0);
3722 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3723 div = stv090x_s1cn_tab[0].read -
3724 stv090x_s1cn_tab[last].read;
3725 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3735 static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
3737 struct stv090x_state *state = fe->demodulator_priv;
3740 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3743 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3744 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3745 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3747 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3748 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3753 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3754 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3755 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3764 dprintk(FE_ERROR, 1, "I/O error");
3769 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3771 return DVBFE_ALGO_CUSTOM;
3774 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3776 struct stv090x_state *state = fe->demodulator_priv;
3777 u32 reg, idle = 0, fifo_full = 1;
3780 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3782 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3783 (state->config->diseqc_envelope_mode) ? 4 : 2);
3784 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3785 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3787 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3788 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3791 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3792 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3795 for (i = 0; i < cmd->msg_len; i++) {
3798 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3799 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3802 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3805 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3806 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3807 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3812 while ((!idle) && (i < 10)) {
3813 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3814 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3821 dprintk(FE_ERROR, 1, "I/O error");
3825 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe,
3826 enum fe_sec_mini_cmd burst)
3828 struct stv090x_state *state = fe->demodulator_priv;
3829 u32 reg, idle = 0, fifo_full = 1;
3833 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3835 if (burst == SEC_MINI_A) {
3836 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
3839 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
3843 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3844 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3845 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3847 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3848 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3851 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3852 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3856 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3857 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3860 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3863 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3864 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3865 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3870 while ((!idle) && (i < 10)) {
3871 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3872 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3879 dprintk(FE_ERROR, 1, "I/O error");
3883 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3885 struct stv090x_state *state = fe->demodulator_priv;
3886 u32 reg = 0, i = 0, rx_end = 0;
3888 while ((rx_end != 1) && (i < 10)) {
3891 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3892 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3896 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3897 for (i = 0; i < reply->msg_len; i++)
3898 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3904 static int stv090x_sleep(struct dvb_frontend *fe)
3906 struct stv090x_state *state = fe->demodulator_priv;
3908 u8 full_standby = 0;
3910 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3913 if (state->config->tuner_sleep) {
3914 if (state->config->tuner_sleep(fe) < 0)
3918 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3921 dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep",
3922 state->device == STV0900 ? "STV0900" : "STV0903",
3925 mutex_lock(&state->internal->demod_lock);
3927 switch (state->demod) {
3928 case STV090x_DEMODULATOR_0:
3929 /* power off ADC 1 */
3930 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3931 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3932 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3934 /* power off DiSEqC 1 */
3935 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
3936 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
3937 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
3940 /* check whether path 2 is already sleeping, that is when
3942 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3943 if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
3947 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3948 /* packet delineator 1 clock */
3949 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
3951 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
3952 /* FEC clock is shared between the two paths, only stop it
3953 when full standby is possible */
3955 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3956 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3958 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
3959 /* sampling 1 clock */
3960 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
3961 /* viterbi 1 clock */
3962 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
3963 /* TS clock is shared between the two paths, only stop it
3964 when full standby is possible */
3966 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
3967 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3971 case STV090x_DEMODULATOR_1:
3972 /* power off ADC 2 */
3973 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3974 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
3975 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
3977 /* power off DiSEqC 2 */
3978 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
3979 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
3980 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
3983 /* check whether path 1 is already sleeping, that is when
3985 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3986 if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
3990 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3991 /* packet delineator 2 clock */
3992 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
3994 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
3995 /* FEC clock is shared between the two paths, only stop it
3996 when full standby is possible */
3998 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3999 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4001 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4002 /* sampling 2 clock */
4003 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
4004 /* viterbi 2 clock */
4005 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
4006 /* TS clock is shared between the two paths, only stop it
4007 when full standby is possible */
4009 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
4010 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4015 dprintk(FE_ERROR, 1, "Wrong demodulator!");
4020 /* general power off */
4021 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4022 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
4023 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4027 mutex_unlock(&state->internal->demod_lock);
4031 stv090x_i2c_gate_ctrl(state, 0);
4034 mutex_unlock(&state->internal->demod_lock);
4036 dprintk(FE_ERROR, 1, "I/O error");
4040 static int stv090x_wakeup(struct dvb_frontend *fe)
4042 struct stv090x_state *state = fe->demodulator_priv;
4045 dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby",
4046 state->device == STV0900 ? "STV0900" : "STV0903",
4049 mutex_lock(&state->internal->demod_lock);
4051 /* general power on */
4052 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4053 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
4054 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4057 switch (state->demod) {
4058 case STV090x_DEMODULATOR_0:
4059 /* power on ADC 1 */
4060 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4061 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
4062 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4064 /* power on DiSEqC 1 */
4065 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
4066 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
4067 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
4070 /* activate clocks */
4071 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4072 /* packet delineator 1 clock */
4073 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
4075 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
4077 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4078 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4080 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4081 /* sampling 1 clock */
4082 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
4083 /* viterbi 1 clock */
4084 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
4086 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4087 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4091 case STV090x_DEMODULATOR_1:
4092 /* power on ADC 2 */
4093 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4094 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
4095 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4097 /* power on DiSEqC 2 */
4098 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
4099 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
4100 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4103 /* activate clocks */
4104 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4105 /* packet delineator 2 clock */
4106 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
4108 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
4110 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4111 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4113 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4114 /* sampling 2 clock */
4115 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
4116 /* viterbi 2 clock */
4117 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
4119 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4120 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4125 dprintk(FE_ERROR, 1, "Wrong demodulator!");
4129 mutex_unlock(&state->internal->demod_lock);
4132 mutex_unlock(&state->internal->demod_lock);
4133 dprintk(FE_ERROR, 1, "I/O error");
4137 static void stv090x_release(struct dvb_frontend *fe)
4139 struct stv090x_state *state = fe->demodulator_priv;
4141 state->internal->num_used--;
4142 if (state->internal->num_used <= 0) {
4144 dprintk(FE_ERROR, 1, "Actually removing");
4146 remove_dev(state->internal);
4147 kfree(state->internal);
4153 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
4157 reg = stv090x_read_reg(state, STV090x_GENCFG);
4159 switch (ldpc_mode) {
4162 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
4163 /* set LDPC to dual mode */
4164 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
4167 state->demod_mode = STV090x_DUAL;
4169 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4170 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4171 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4173 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4174 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4177 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
4179 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
4181 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
4183 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
4185 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
4187 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
4189 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
4192 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
4194 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
4196 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
4198 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
4200 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
4202 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
4204 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
4207 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
4209 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
4214 case STV090x_SINGLE:
4215 if (stv090x_stop_modcod(state) < 0)
4217 if (stv090x_activate_modcod_single(state) < 0)
4220 if (state->demod == STV090x_DEMODULATOR_1) {
4221 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
4224 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
4228 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4229 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4230 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4232 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4233 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4236 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
4237 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
4238 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4240 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
4241 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4248 dprintk(FE_ERROR, 1, "I/O error");
4252 /* return (Hz), clk in Hz*/
4253 static u32 stv090x_get_mclk(struct stv090x_state *state)
4255 const struct stv090x_config *config = state->config;
4259 div = stv090x_read_reg(state, STV090x_NCOARSE);
4260 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4261 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4263 return (div + 1) * config->xtal / ratio; /* kHz */
4266 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4268 const struct stv090x_config *config = state->config;
4269 u32 reg, div, clk_sel;
4271 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4272 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4274 div = ((clk_sel * mclk) / config->xtal) - 1;
4276 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4277 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4278 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4281 state->internal->mclk = stv090x_get_mclk(state);
4283 /*Set the DiseqC frequency to 22KHz */
4284 div = state->internal->mclk / 704000;
4285 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4287 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4292 dprintk(FE_ERROR, 1, "I/O error");
4296 static int stv0900_set_tspath(struct stv090x_state *state)
4300 if (state->internal->dev_ver >= 0x20) {
4301 switch (state->config->ts1_mode) {
4302 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4303 case STV090x_TSMODE_DVBCI:
4304 switch (state->config->ts2_mode) {
4305 case STV090x_TSMODE_SERIAL_PUNCTURED:
4306 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4308 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4311 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4312 case STV090x_TSMODE_DVBCI:
4313 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4315 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4316 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4317 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4319 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4320 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4321 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4323 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4325 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4331 case STV090x_TSMODE_SERIAL_PUNCTURED:
4332 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4334 switch (state->config->ts2_mode) {
4335 case STV090x_TSMODE_SERIAL_PUNCTURED:
4336 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4338 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4342 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4343 case STV090x_TSMODE_DVBCI:
4344 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4351 switch (state->config->ts1_mode) {
4352 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4353 case STV090x_TSMODE_DVBCI:
4354 switch (state->config->ts2_mode) {
4355 case STV090x_TSMODE_SERIAL_PUNCTURED:
4356 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4358 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4361 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4362 case STV090x_TSMODE_DVBCI:
4363 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
4364 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4365 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4366 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4368 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4369 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4370 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4372 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4374 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4380 case STV090x_TSMODE_SERIAL_PUNCTURED:
4381 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4383 switch (state->config->ts2_mode) {
4384 case STV090x_TSMODE_SERIAL_PUNCTURED:
4385 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4387 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4390 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4391 case STV090x_TSMODE_DVBCI:
4392 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4399 switch (state->config->ts1_mode) {
4400 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4401 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4402 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4403 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4404 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4405 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4409 case STV090x_TSMODE_DVBCI:
4410 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4411 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4412 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4413 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4414 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4418 case STV090x_TSMODE_SERIAL_PUNCTURED:
4419 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4420 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4421 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4422 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4423 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4427 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4428 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4429 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4430 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4431 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4432 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4440 switch (state->config->ts2_mode) {
4441 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4442 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4443 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4444 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4445 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4446 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4450 case STV090x_TSMODE_DVBCI:
4451 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4452 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4453 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4454 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4455 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4459 case STV090x_TSMODE_SERIAL_PUNCTURED:
4460 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4461 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4462 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4463 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4464 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4468 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4469 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4470 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4471 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4472 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4473 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4481 if (state->config->ts1_clk > 0) {
4484 switch (state->config->ts1_mode) {
4485 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4486 case STV090x_TSMODE_DVBCI:
4488 speed = state->internal->mclk /
4489 (state->config->ts1_clk / 4);
4495 case STV090x_TSMODE_SERIAL_PUNCTURED:
4496 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4497 speed = state->internal->mclk /
4498 (state->config->ts1_clk / 32);
4505 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4506 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4507 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4509 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4513 if (state->config->ts2_clk > 0) {
4516 switch (state->config->ts2_mode) {
4517 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4518 case STV090x_TSMODE_DVBCI:
4520 speed = state->internal->mclk /
4521 (state->config->ts2_clk / 4);
4527 case STV090x_TSMODE_SERIAL_PUNCTURED:
4528 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4529 speed = state->internal->mclk /
4530 (state->config->ts2_clk / 32);
4537 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4538 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4539 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4541 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4545 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4546 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4547 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4549 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4550 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4553 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4554 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4555 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4557 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4558 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4563 dprintk(FE_ERROR, 1, "I/O error");
4567 static int stv0903_set_tspath(struct stv090x_state *state)
4571 if (state->internal->dev_ver >= 0x20) {
4572 switch (state->config->ts1_mode) {
4573 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4574 case STV090x_TSMODE_DVBCI:
4575 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4578 case STV090x_TSMODE_SERIAL_PUNCTURED:
4579 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4581 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c);
4585 switch (state->config->ts1_mode) {
4586 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4587 case STV090x_TSMODE_DVBCI:
4588 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4591 case STV090x_TSMODE_SERIAL_PUNCTURED:
4592 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4594 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4599 switch (state->config->ts1_mode) {
4600 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4601 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4602 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4603 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4604 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4608 case STV090x_TSMODE_DVBCI:
4609 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4610 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4611 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4612 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4616 case STV090x_TSMODE_SERIAL_PUNCTURED:
4617 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4618 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4619 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4620 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4624 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4625 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4626 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4627 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4628 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4636 if (state->config->ts1_clk > 0) {
4639 switch (state->config->ts1_mode) {
4640 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4641 case STV090x_TSMODE_DVBCI:
4643 speed = state->internal->mclk /
4644 (state->config->ts1_clk / 4);
4650 case STV090x_TSMODE_SERIAL_PUNCTURED:
4651 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4652 speed = state->internal->mclk /
4653 (state->config->ts1_clk / 32);
4660 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4661 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4662 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4664 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4668 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4669 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4670 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4672 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4673 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4678 dprintk(FE_ERROR, 1, "I/O error");
4682 static int stv090x_init(struct dvb_frontend *fe)
4684 struct stv090x_state *state = fe->demodulator_priv;
4685 const struct stv090x_config *config = state->config;
4688 if (state->internal->mclk == 0) {
4689 /* call tuner init to configure the tuner's clock output
4690 divider directly before setting up the master clock of
4692 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4695 if (config->tuner_init) {
4696 if (config->tuner_init(fe) < 0)
4700 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4703 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4705 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4706 0x20 | config->clk_mode) < 0)
4708 stv090x_get_mclk(state);
4711 if (stv090x_wakeup(fe) < 0) {
4712 dprintk(FE_ERROR, 1, "Error waking device");
4716 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4719 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4720 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4721 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4723 reg = STV090x_READ_DEMOD(state, DEMOD);
4724 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4725 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4728 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4731 if (config->tuner_set_mode) {
4732 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
4736 if (config->tuner_init) {
4737 if (config->tuner_init(fe) < 0)
4741 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4744 if (state->device == STV0900) {
4745 if (stv0900_set_tspath(state) < 0)
4748 if (stv0903_set_tspath(state) < 0)
4755 stv090x_i2c_gate_ctrl(state, 0);
4757 dprintk(FE_ERROR, 1, "I/O error");
4761 static int stv090x_setup(struct dvb_frontend *fe)
4763 struct stv090x_state *state = fe->demodulator_priv;
4764 const struct stv090x_config *config = state->config;
4765 const struct stv090x_reg *stv090x_initval = NULL;
4766 const struct stv090x_reg *stv090x_cut20_val = NULL;
4767 unsigned long t1_size = 0, t2_size = 0;
4772 if (state->device == STV0900) {
4773 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4774 stv090x_initval = stv0900_initval;
4775 t1_size = ARRAY_SIZE(stv0900_initval);
4776 stv090x_cut20_val = stv0900_cut20_val;
4777 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4778 } else if (state->device == STV0903) {
4779 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4780 stv090x_initval = stv0903_initval;
4781 t1_size = ARRAY_SIZE(stv0903_initval);
4782 stv090x_cut20_val = stv0903_cut20_val;
4783 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4789 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4791 if (state->device == STV0900)
4792 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
4797 /* Set No Tuner Mode */
4798 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4800 if (state->device == STV0900)
4801 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
4804 /* I2C repeater OFF */
4805 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4806 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4808 if (state->device == STV0900)
4809 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4812 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4815 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4817 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4822 dprintk(FE_DEBUG, 1, "Setting up initial values");
4823 for (i = 0; i < t1_size; i++) {
4824 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4828 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4829 if (state->internal->dev_ver >= 0x20) {
4830 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4833 /* write cut20_val*/
4834 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4835 for (i = 0; i < t2_size; i++) {
4836 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4840 } else if (state->internal->dev_ver < 0x20) {
4841 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
4842 state->internal->dev_ver);
4845 } else if (state->internal->dev_ver > 0x30) {
4846 /* we shouldn't bail out from here */
4847 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
4848 state->internal->dev_ver);
4852 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4853 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
4854 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
4855 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4859 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4860 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
4861 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
4862 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4865 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4867 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4872 dprintk(FE_ERROR, 1, "I/O error");
4876 static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir,
4877 u8 value, u8 xor_value)
4879 struct stv090x_state *state = fe->demodulator_priv;
4882 STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
4883 STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
4884 STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
4886 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
4889 static struct dvb_frontend_ops stv090x_ops = {
4890 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
4892 .name = "STV090x Multistandard",
4893 .frequency_min = 950000,
4894 .frequency_max = 2150000,
4895 .frequency_stepsize = 0,
4896 .frequency_tolerance = 0,
4897 .symbol_rate_min = 1000000,
4898 .symbol_rate_max = 45000000,
4899 .caps = FE_CAN_INVERSION_AUTO |
4902 FE_CAN_2G_MODULATION
4905 .release = stv090x_release,
4906 .init = stv090x_init,
4908 .sleep = stv090x_sleep,
4909 .get_frontend_algo = stv090x_frontend_algo,
4911 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
4912 .diseqc_send_burst = stv090x_send_diseqc_burst,
4913 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4914 .set_tone = stv090x_set_tone,
4916 .search = stv090x_search,
4917 .read_status = stv090x_read_status,
4918 .read_ber = stv090x_read_per,
4919 .read_signal_strength = stv090x_read_signal_strength,
4920 .read_snr = stv090x_read_cnr,
4924 struct dvb_frontend *stv090x_attach(struct stv090x_config *config,
4925 struct i2c_adapter *i2c,
4926 enum stv090x_demodulator demod)
4928 struct stv090x_state *state = NULL;
4929 struct stv090x_dev *temp_int;
4931 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4935 state->verbose = &verbose;
4936 state->config = config;
4938 state->frontend.ops = stv090x_ops;
4939 state->frontend.demodulator_priv = state;
4940 state->demod = demod;
4941 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4942 state->device = config->device;
4943 state->rolloff = STV090x_RO_35; /* default */
4945 temp_int = find_dev(state->i2c,
4946 state->config->address);
4948 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
4949 state->internal = temp_int->internal;
4950 state->internal->num_used++;
4951 dprintk(FE_INFO, 1, "Found Internal Structure!");
4953 state->internal = kmalloc(sizeof(struct stv090x_internal),
4955 if (!state->internal)
4957 temp_int = append_internal(state->internal);
4959 kfree(state->internal);
4962 state->internal->num_used = 1;
4963 state->internal->mclk = 0;
4964 state->internal->dev_ver = 0;
4965 state->internal->i2c_adap = state->i2c;
4966 state->internal->i2c_addr = state->config->address;
4967 dprintk(FE_INFO, 1, "Create New Internal Structure!");
4969 mutex_init(&state->internal->demod_lock);
4970 mutex_init(&state->internal->tuner_lock);
4972 if (stv090x_setup(&state->frontend) < 0) {
4973 dprintk(FE_ERROR, 1, "Error setting up device");
4978 if (state->internal->dev_ver >= 0x30)
4979 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
4981 /* workaround for stuck DiSEqC output */
4982 if (config->diseqc_envelope_mode)
4983 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
4985 config->set_gpio = stv090x_set_gpio;
4987 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4988 state->device == STV0900 ? "STV0900" : "STV0903",
4990 state->internal->dev_ver);
4992 return &state->frontend;
4995 remove_dev(state->internal);
4996 kfree(state->internal);
5001 EXPORT_SYMBOL(stv090x_attach);
5002 MODULE_PARM_DESC(verbose, "Set Verbosity level");
5003 MODULE_AUTHOR("Manu Abraham");
5004 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
5005 MODULE_LICENSE("GPL");