drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/i2c.h>
  35 #include <linux/delay.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <media/v4l2-device.h>
  40 #include <media/v4l2-ctrls.h>
  41 #include <media/v4l2-dv-timings.h>
  42 #include <media/adv7604.h>
  43
  44 static int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "debug level (0-2)");
  47
  48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  51 MODULE_LICENSE("GPL");
  52
  53 /* ADV7604 system clock frequency */
  54 #define ADV7604_fsc (28636360)
  55
  56 /*
  57  **********************************************************************
  58  *
  59  *  Arrays with configuration parameters for the ADV7604
  60  *
  61  **********************************************************************
  62  */
  63 struct adv7604_state {
  64         struct adv7604_platform_data pdata;
  65         struct v4l2_subdev sd;
  66         struct media_pad pad;
  67         struct v4l2_ctrl_handler hdl;
  68         enum adv7604_input_port selected_input;
  69         struct v4l2_dv_timings timings;
  70         struct {
  71                 u8 edid[256];
  72                 u32 present;
  73                 unsigned blocks;
  74         } edid;
  75         u16 spa_port_a[2];
  76         struct v4l2_fract aspect_ratio;
  77         u32 rgb_quantization_range;
  78         struct workqueue_struct *work_queues;
  79         struct delayed_work delayed_work_enable_hotplug;
  80         bool restart_stdi_once;
  81
  82         /* i2c clients */
  83         struct i2c_client *i2c_avlink;
  84         struct i2c_client *i2c_cec;
  85         struct i2c_client *i2c_infoframe;
  86         struct i2c_client *i2c_esdp;
  87         struct i2c_client *i2c_dpp;
  88         struct i2c_client *i2c_afe;
  89         struct i2c_client *i2c_repeater;
  90         struct i2c_client *i2c_edid;
  91         struct i2c_client *i2c_hdmi;
  92         struct i2c_client *i2c_test;
  93         struct i2c_client *i2c_cp;
  94         struct i2c_client *i2c_vdp;
  95
  96         /* controls */
  97         struct v4l2_ctrl *detect_tx_5v_ctrl;
  98         struct v4l2_ctrl *analog_sampling_phase_ctrl;
  99         struct v4l2_ctrl *free_run_color_manual_ctrl;
 100         struct v4l2_ctrl *free_run_color_ctrl;
 101         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 102 };
 103
 104 /* Supported CEA and DMT timings */
 105 static const struct v4l2_dv_timings adv7604_timings[] = {
 106         V4L2_DV_BT_CEA_720X480P59_94,
 107         V4L2_DV_BT_CEA_720X576P50,
 108         V4L2_DV_BT_CEA_1280X720P24,
 109         V4L2_DV_BT_CEA_1280X720P25,
 110         V4L2_DV_BT_CEA_1280X720P50,
 111         V4L2_DV_BT_CEA_1280X720P60,
 112         V4L2_DV_BT_CEA_1920X1080P24,
 113         V4L2_DV_BT_CEA_1920X1080P25,
 114         V4L2_DV_BT_CEA_1920X1080P30,
 115         V4L2_DV_BT_CEA_1920X1080P50,
 116         V4L2_DV_BT_CEA_1920X1080P60,
 117
 118         /* sorted by DMT ID */
 119         V4L2_DV_BT_DMT_640X350P85,
 120         V4L2_DV_BT_DMT_640X400P85,
 121         V4L2_DV_BT_DMT_720X400P85,
 122         V4L2_DV_BT_DMT_640X480P60,
 123         V4L2_DV_BT_DMT_640X480P72,
 124         V4L2_DV_BT_DMT_640X480P75,
 125         V4L2_DV_BT_DMT_640X480P85,
 126         V4L2_DV_BT_DMT_800X600P56,
 127         V4L2_DV_BT_DMT_800X600P60,
 128         V4L2_DV_BT_DMT_800X600P72,
 129         V4L2_DV_BT_DMT_800X600P75,
 130         V4L2_DV_BT_DMT_800X600P85,
 131         V4L2_DV_BT_DMT_848X480P60,
 132         V4L2_DV_BT_DMT_1024X768P60,
 133         V4L2_DV_BT_DMT_1024X768P70,
 134         V4L2_DV_BT_DMT_1024X768P75,
 135         V4L2_DV_BT_DMT_1024X768P85,
 136         V4L2_DV_BT_DMT_1152X864P75,
 137         V4L2_DV_BT_DMT_1280X768P60_RB,
 138         V4L2_DV_BT_DMT_1280X768P60,
 139         V4L2_DV_BT_DMT_1280X768P75,
 140         V4L2_DV_BT_DMT_1280X768P85,
 141         V4L2_DV_BT_DMT_1280X800P60_RB,
 142         V4L2_DV_BT_DMT_1280X800P60,
 143         V4L2_DV_BT_DMT_1280X800P75,
 144         V4L2_DV_BT_DMT_1280X800P85,
 145         V4L2_DV_BT_DMT_1280X960P60,
 146         V4L2_DV_BT_DMT_1280X960P85,
 147         V4L2_DV_BT_DMT_1280X1024P60,
 148         V4L2_DV_BT_DMT_1280X1024P75,
 149         V4L2_DV_BT_DMT_1280X1024P85,
 150         V4L2_DV_BT_DMT_1360X768P60,
 151         V4L2_DV_BT_DMT_1400X1050P60_RB,
 152         V4L2_DV_BT_DMT_1400X1050P60,
 153         V4L2_DV_BT_DMT_1400X1050P75,
 154         V4L2_DV_BT_DMT_1400X1050P85,
 155         V4L2_DV_BT_DMT_1440X900P60_RB,
 156         V4L2_DV_BT_DMT_1440X900P60,
 157         V4L2_DV_BT_DMT_1600X1200P60,
 158         V4L2_DV_BT_DMT_1680X1050P60_RB,
 159         V4L2_DV_BT_DMT_1680X1050P60,
 160         V4L2_DV_BT_DMT_1792X1344P60,
 161         V4L2_DV_BT_DMT_1856X1392P60,
 162         V4L2_DV_BT_DMT_1920X1200P60_RB,
 163         V4L2_DV_BT_DMT_1366X768P60_RB,
 164         V4L2_DV_BT_DMT_1366X768P60,
 165         V4L2_DV_BT_DMT_1920X1080P60,
 166         { },
 167 };
 168
 169 struct adv7604_video_standards {
 170         struct v4l2_dv_timings timings;
 171         u8 vid_std;
 172         u8 v_freq;
 173 };
 174
 175 /* sorted by number of lines */
 176 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
 177         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 178         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 179         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 180         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 181         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 182         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 183         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 184         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 185         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 186         /* TODO add 1920x1080P60_RB (CVT timing) */
 187         { },
 188 };
 189
 190 /* sorted by number of lines */
 191 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
 192         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 193         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 194         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 195         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 196         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 199         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 200         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 201         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 203         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 204         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 205         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 206         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 207         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 208         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 209         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 210         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 211         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 212         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 213         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 214         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 215         { },
 216 };
 217
 218 /* sorted by number of lines */
 219 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
 220         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 221         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 222         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 223         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 224         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 225         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 226         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 227         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 228         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 229         { },
 230 };
 231
 232 /* sorted by number of lines */
 233 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
 234         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 235         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 236         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 237         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 238         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 239         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 240         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 241         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 242         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 243         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 244         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 245         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 246         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 247         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 248         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 249         { },
 250 };
 251
 252 /* ----------------------------------------------------------------------- */
 253
 254 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
 255 {
 256         return container_of(sd, struct adv7604_state, sd);
 257 }
 258
 259 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 260 {
 261         return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
 262 }
 263
 264 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 265 {
 266         return V4L2_DV_BT_BLANKING_WIDTH(t);
 267 }
 268
 269 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 270 {
 271         return V4L2_DV_BT_FRAME_WIDTH(t);
 272 }
 273
 274 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 275 {
 276         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 277 }
 278
 279 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 280 {
 281         return V4L2_DV_BT_FRAME_HEIGHT(t);
 282 }
 283
 284 /* ----------------------------------------------------------------------- */
 285
 286 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 287                 u8 command, bool check)
 288 {
 289         union i2c_smbus_data data;
 290
 291         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 292                         I2C_SMBUS_READ, command,
 293                         I2C_SMBUS_BYTE_DATA, &data))
 294                 return data.byte;
 295         if (check)
 296                 v4l_err(client, "error reading %02x, %02x\n",
 297                                 client->addr, command);
 298         return -EIO;
 299 }
 300
 301 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 302 {
 303         return adv_smbus_read_byte_data_check(client, command, true);
 304 }
 305
 306 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 307                                         u8 command, u8 value)
 308 {
 309         union i2c_smbus_data data;
 310         int err;
 311         int i;
 312
 313         data.byte = value;
 314         for (i = 0; i < 3; i++) {
 315                 err = i2c_smbus_xfer(client->adapter, client->addr,
 316                                 client->flags,
 317                                 I2C_SMBUS_WRITE, command,
 318                                 I2C_SMBUS_BYTE_DATA, &data);
 319                 if (!err)
 320                         break;
 321         }
 322         if (err < 0)
 323                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 324                                 client->addr, command, value);
 325         return err;
 326 }
 327
 328 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 329                u8 command, unsigned length, const u8 *values)
 330 {
 331         union i2c_smbus_data data;
 332
 333         if (length > I2C_SMBUS_BLOCK_MAX)
 334                 length = I2C_SMBUS_BLOCK_MAX;
 335         data.block[0] = length;
 336         memcpy(data.block + 1, values, length);
 337         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 338                               I2C_SMBUS_WRITE, command,
 339                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 340 }
 341
 342 /* ----------------------------------------------------------------------- */
 343
 344 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 345 {
 346         struct i2c_client *client = v4l2_get_subdevdata(sd);
 347
 348         return adv_smbus_read_byte_data(client, reg);
 349 }
 350
 351 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 352 {
 353         struct i2c_client *client = v4l2_get_subdevdata(sd);
 354
 355         return adv_smbus_write_byte_data(client, reg, val);
 356 }
 357
 358 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 359 {
 360         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 361 }
 362
 363 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 364 {
 365         struct adv7604_state *state = to_state(sd);
 366
 367         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 368 }
 369
 370 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 371 {
 372         struct adv7604_state *state = to_state(sd);
 373
 374         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 375 }
 376
 377 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 378 {
 379         struct adv7604_state *state = to_state(sd);
 380
 381         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 382 }
 383
 384 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 385 {
 386         struct adv7604_state *state = to_state(sd);
 387
 388         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 389 }
 390
 391 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 392 {
 393         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 394 }
 395
 396 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 397 {
 398         struct adv7604_state *state = to_state(sd);
 399
 400         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 401 }
 402
 403 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 404 {
 405         struct adv7604_state *state = to_state(sd);
 406
 407         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 408 }
 409
 410 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
 411 {
 412         struct adv7604_state *state = to_state(sd);
 413
 414         return adv_smbus_read_byte_data(state->i2c_esdp, reg);
 415 }
 416
 417 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 418 {
 419         struct adv7604_state *state = to_state(sd);
 420
 421         return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
 422 }
 423
 424 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
 425 {
 426         struct adv7604_state *state = to_state(sd);
 427
 428         return adv_smbus_read_byte_data(state->i2c_dpp, reg);
 429 }
 430
 431 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 432 {
 433         struct adv7604_state *state = to_state(sd);
 434
 435         return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
 436 }
 437
 438 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 439 {
 440         struct adv7604_state *state = to_state(sd);
 441
 442         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 443 }
 444
 445 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 446 {
 447         struct adv7604_state *state = to_state(sd);
 448
 449         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 450 }
 451
 452 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 453 {
 454         struct adv7604_state *state = to_state(sd);
 455
 456         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 457 }
 458
 459 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 460 {
 461         struct adv7604_state *state = to_state(sd);
 462
 463         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 464 }
 465
 466 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 467 {
 468         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 469 }
 470
 471 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 472 {
 473         struct adv7604_state *state = to_state(sd);
 474
 475         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 476 }
 477
 478 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 479 {
 480         struct adv7604_state *state = to_state(sd);
 481
 482         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 483 }
 484
 485 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
 486 {
 487         struct adv7604_state *state = to_state(sd);
 488         struct i2c_client *client = state->i2c_edid;
 489         u8 msgbuf0[1] = { 0 };
 490         u8 msgbuf1[256];
 491         struct i2c_msg msg[2] = {
 492                 {
 493                         .addr = client->addr,
 494                         .len = 1,
 495                         .buf = msgbuf0
 496                 },
 497                 {
 498                         .addr = client->addr,
 499                         .flags = I2C_M_RD,
 500                         .len = len,
 501                         .buf = msgbuf1
 502                 },
 503         };
 504
 505         if (i2c_transfer(client->adapter, msg, 2) < 0)
 506                 return -EIO;
 507         memcpy(val, msgbuf1, len);
 508         return 0;
 509 }
 510
 511 static inline int edid_write_block(struct v4l2_subdev *sd,
 512                                         unsigned len, const u8 *val)
 513 {
 514         struct adv7604_state *state = to_state(sd);
 515         int err = 0;
 516         int i;
 517
 518         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 519
 520         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 521                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 522                                 I2C_SMBUS_BLOCK_MAX, val + i);
 523         return err;
 524 }
 525
 526 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
 527 {
 528         struct delayed_work *dwork = to_delayed_work(work);
 529         struct adv7604_state *state = container_of(dwork, struct adv7604_state,
 530                                                 delayed_work_enable_hotplug);
 531         struct v4l2_subdev *sd = &state->sd;
 532
 533         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 534
 535         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
 536 }
 537
 538 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 539 {
 540         struct adv7604_state *state = to_state(sd);
 541
 542         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 543 }
 544
 545 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 546 {
 547         struct adv7604_state *state = to_state(sd);
 548
 549         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 550 }
 551
 552 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 553 {
 554         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
 555 }
 556
 557 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
 558 {
 559         struct adv7604_state *state = to_state(sd);
 560
 561         return adv_smbus_read_byte_data(state->i2c_test, reg);
 562 }
 563
 564 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 565 {
 566         struct adv7604_state *state = to_state(sd);
 567
 568         return adv_smbus_write_byte_data(state->i2c_test, reg, val);
 569 }
 570
 571 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 572 {
 573         struct adv7604_state *state = to_state(sd);
 574
 575         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 576 }
 577
 578 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 579 {
 580         struct adv7604_state *state = to_state(sd);
 581
 582         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 583 }
 584
 585 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 586 {
 587         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 588 }
 589
 590 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 591 {
 592         struct adv7604_state *state = to_state(sd);
 593
 594         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 595 }
 596
 597 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 598 {
 599         struct adv7604_state *state = to_state(sd);
 600
 601         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 602 }
 603
 604 /* ----------------------------------------------------------------------- */
 605
 606 static inline bool is_analog_input(struct v4l2_subdev *sd)
 607 {
 608         struct adv7604_state *state = to_state(sd);
 609
 610         return state->selected_input == ADV7604_INPUT_VGA_RGB ||
 611                state->selected_input == ADV7604_INPUT_VGA_COMP;
 612 }
 613
 614 static inline bool is_digital_input(struct v4l2_subdev *sd)
 615 {
 616         struct adv7604_state *state = to_state(sd);
 617
 618         return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
 619                state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
 620                state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
 621                state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
 622 }
 623
 624 /* ----------------------------------------------------------------------- */
 625
 626 #ifdef CONFIG_VIDEO_ADV_DEBUG
 627 static void adv7604_inv_register(struct v4l2_subdev *sd)
 628 {
 629         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 630         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 631         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 632         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 633         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 634         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 635         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 636         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 637         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 638         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 639         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 640         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 641         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 642 }
 643
 644 static int adv7604_g_register(struct v4l2_subdev *sd,
 645                                         struct v4l2_dbg_register *reg)
 646 {
 647         reg->size = 1;
 648         switch (reg->reg >> 8) {
 649         case 0:
 650                 reg->val = io_read(sd, reg->reg & 0xff);
 651                 break;
 652         case 1:
 653                 reg->val = avlink_read(sd, reg->reg & 0xff);
 654                 break;
 655         case 2:
 656                 reg->val = cec_read(sd, reg->reg & 0xff);
 657                 break;
 658         case 3:
 659                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 660                 break;
 661         case 4:
 662                 reg->val = esdp_read(sd, reg->reg & 0xff);
 663                 break;
 664         case 5:
 665                 reg->val = dpp_read(sd, reg->reg & 0xff);
 666                 break;
 667         case 6:
 668                 reg->val = afe_read(sd, reg->reg & 0xff);
 669                 break;
 670         case 7:
 671                 reg->val = rep_read(sd, reg->reg & 0xff);
 672                 break;
 673         case 8:
 674                 reg->val = edid_read(sd, reg->reg & 0xff);
 675                 break;
 676         case 9:
 677                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 678                 break;
 679         case 0xa:
 680                 reg->val = test_read(sd, reg->reg & 0xff);
 681                 break;
 682         case 0xb:
 683                 reg->val = cp_read(sd, reg->reg & 0xff);
 684                 break;
 685         case 0xc:
 686                 reg->val = vdp_read(sd, reg->reg & 0xff);
 687                 break;
 688         default:
 689                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 690                 adv7604_inv_register(sd);
 691                 break;
 692         }
 693         return 0;
 694 }
 695
 696 static int adv7604_s_register(struct v4l2_subdev *sd,
 697                                         const struct v4l2_dbg_register *reg)
 698 {
 699         u8 val = reg->val & 0xff;
 700
 701         switch (reg->reg >> 8) {
 702         case 0:
 703                 io_write(sd, reg->reg & 0xff, val);
 704                 break;
 705         case 1:
 706                 avlink_write(sd, reg->reg & 0xff, val);
 707                 break;
 708         case 2:
 709                 cec_write(sd, reg->reg & 0xff, val);
 710                 break;
 711         case 3:
 712                 infoframe_write(sd, reg->reg & 0xff, val);
 713                 break;
 714         case 4:
 715                 esdp_write(sd, reg->reg & 0xff, val);
 716                 break;
 717         case 5:
 718                 dpp_write(sd, reg->reg & 0xff, val);
 719                 break;
 720         case 6:
 721                 afe_write(sd, reg->reg & 0xff, val);
 722                 break;
 723         case 7:
 724                 rep_write(sd, reg->reg & 0xff, val);
 725                 break;
 726         case 8:
 727                 edid_write(sd, reg->reg & 0xff, val);
 728                 break;
 729         case 9:
 730                 hdmi_write(sd, reg->reg & 0xff, val);
 731                 break;
 732         case 0xa:
 733                 test_write(sd, reg->reg & 0xff, val);
 734                 break;
 735         case 0xb:
 736                 cp_write(sd, reg->reg & 0xff, val);
 737                 break;
 738         case 0xc:
 739                 vdp_write(sd, reg->reg & 0xff, val);
 740                 break;
 741         default:
 742                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 743                 adv7604_inv_register(sd);
 744                 break;
 745         }
 746         return 0;
 747 }
 748 #endif
 749
 750 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 751 {
 752         struct adv7604_state *state = to_state(sd);
 753         u8 reg_io_6f = io_read(sd, 0x6f);
 754
 755         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 756                         ((reg_io_6f & 0x10) >> 4) |
 757                         ((reg_io_6f & 0x08) >> 2) |
 758                         (reg_io_6f & 0x04) |
 759                         ((reg_io_6f & 0x02) << 2));
 760 }
 761
 762 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 763                 u8 prim_mode,
 764                 const struct adv7604_video_standards *predef_vid_timings,
 765                 const struct v4l2_dv_timings *timings)
 766 {
 767         int i;
 768
 769         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 770                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 771                                         is_digital_input(sd) ? 250000 : 1000000))
 772                         continue;
 773                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 774                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 775                                 prim_mode); /* v_freq and prim mode */
 776                 return 0;
 777         }
 778
 779         return -1;
 780 }
 781
 782 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 783                 struct v4l2_dv_timings *timings)
 784 {
 785         struct adv7604_state *state = to_state(sd);
 786         int err;
 787
 788         v4l2_dbg(1, debug, sd, "%s", __func__);
 789
 790         /* reset to default values */
 791         io_write(sd, 0x16, 0x43);
 792         io_write(sd, 0x17, 0x5a);
 793         /* disable embedded syncs for auto graphics mode */
 794         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 795         cp_write(sd, 0x8f, 0x00);
 796         cp_write(sd, 0x90, 0x00);
 797         cp_write(sd, 0xa2, 0x00);
 798         cp_write(sd, 0xa3, 0x00);
 799         cp_write(sd, 0xa4, 0x00);
 800         cp_write(sd, 0xa5, 0x00);
 801         cp_write(sd, 0xa6, 0x00);
 802         cp_write(sd, 0xa7, 0x00);
 803         cp_write(sd, 0xab, 0x00);
 804         cp_write(sd, 0xac, 0x00);
 805
 806         if (is_analog_input(sd)) {
 807                 err = find_and_set_predefined_video_timings(sd,
 808                                 0x01, adv7604_prim_mode_comp, timings);
 809                 if (err)
 810                         err = find_and_set_predefined_video_timings(sd,
 811                                         0x02, adv7604_prim_mode_gr, timings);
 812         } else if (is_digital_input(sd)) {
 813                 err = find_and_set_predefined_video_timings(sd,
 814                                 0x05, adv7604_prim_mode_hdmi_comp, timings);
 815                 if (err)
 816                         err = find_and_set_predefined_video_timings(sd,
 817                                         0x06, adv7604_prim_mode_hdmi_gr, timings);
 818         } else {
 819                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 820                                 __func__, state->selected_input);
 821                 err = -1;
 822         }
 823
 824
 825         return err;
 826 }
 827
 828 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 829                 const struct v4l2_bt_timings *bt)
 830 {
 831         struct adv7604_state *state = to_state(sd);
 832         struct i2c_client *client = v4l2_get_subdevdata(sd);
 833         u32 width = htotal(bt);
 834         u32 height = vtotal(bt);
 835         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 836         u16 cp_start_eav = width - bt->hfrontporch;
 837         u16 cp_start_vbi = height - bt->vfrontporch;
 838         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 839         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 840                 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 841         const u8 pll[2] = {
 842                 0xc0 | ((width >> 8) & 0x1f),
 843                 width & 0xff
 844         };
 845
 846         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 847
 848         if (is_analog_input(sd)) {
 849                 /* auto graphics */
 850                 io_write(sd, 0x00, 0x07); /* video std */
 851                 io_write(sd, 0x01, 0x02); /* prim mode */
 852                 /* enable embedded syncs for auto graphics mode */
 853                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 854
 855                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 856                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 857                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 858                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
 859                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 860
 861                 /* active video - horizontal timing */
 862                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
 863                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
 864                                    ((cp_start_eav >> 8) & 0x0f));
 865                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
 866
 867                 /* active video - vertical timing */
 868                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 869                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 870                                    ((cp_end_vbi >> 8) & 0xf));
 871                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 872         } else if (is_digital_input(sd)) {
 873                 /* set default prim_mode/vid_std for HDMI
 874                    according to [REF_03, c. 4.2] */
 875                 io_write(sd, 0x00, 0x02); /* video std */
 876                 io_write(sd, 0x01, 0x06); /* prim mode */
 877         } else {
 878                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 879                                 __func__, state->selected_input);
 880         }
 881
 882         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
 883         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
 884         cp_write(sd, 0xab, (height >> 4) & 0xff);
 885         cp_write(sd, 0xac, (height & 0x0f) << 4);
 886 }
 887
 888 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
 889 {
 890         struct adv7604_state *state = to_state(sd);
 891
 892         v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
 893                        __func__, state->rgb_quantization_range);
 894
 895         switch (state->rgb_quantization_range) {
 896         case V4L2_DV_RGB_RANGE_AUTO:
 897                 if (state->selected_input == ADV7604_INPUT_VGA_RGB) {
 898                         /* Receiving analog RGB signal
 899                          * Set RGB full range (0-255) */
 900                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
 901                         break;
 902                 }
 903
 904                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
 905                         /* Receiving analog YPbPr signal
 906                          * Set automode */
 907                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 908                         break;
 909                 }
 910
 911                 if (hdmi_read(sd, 0x05) & 0x80) {
 912                         /* Receiving HDMI signal
 913                          * Set automode */
 914                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 915                         break;
 916                 }
 917
 918                 /* Receiving DVI-D signal
 919                  * ADV7604 selects RGB limited range regardless of
 920                  * input format (CE/IT) in automatic mode */
 921                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 922                         /* RGB limited range (16-235) */
 923                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
 924                 } else {
 925                         /* RGB full range (0-255) */
 926                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
 927                 }
 928                 break;
 929         case V4L2_DV_RGB_RANGE_LIMITED:
 930                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
 931                         /* YCrCb limited range (16-235) */
 932                         io_write_and_or(sd, 0x02, 0x0f, 0x20);
 933                 } else {
 934                         /* RGB limited range (16-235) */
 935                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
 936                 }
 937                 break;
 938         case V4L2_DV_RGB_RANGE_FULL:
 939                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
 940                         /* YCrCb full range (0-255) */
 941                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
 942                 } else {
 943                         /* RGB full range (0-255) */
 944                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
 945                 }
 946                 break;
 947         }
 948 }
 949
 950 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
 951 {
 952         struct v4l2_subdev *sd = to_sd(ctrl);
 953         struct adv7604_state *state = to_state(sd);
 954
 955         switch (ctrl->id) {
 956         case V4L2_CID_BRIGHTNESS:
 957                 cp_write(sd, 0x3c, ctrl->val);
 958                 return 0;
 959         case V4L2_CID_CONTRAST:
 960                 cp_write(sd, 0x3a, ctrl->val);
 961                 return 0;
 962         case V4L2_CID_SATURATION:
 963                 cp_write(sd, 0x3b, ctrl->val);
 964                 return 0;
 965         case V4L2_CID_HUE:
 966                 cp_write(sd, 0x3d, ctrl->val);
 967                 return 0;
 968         case  V4L2_CID_DV_RX_RGB_RANGE:
 969                 state->rgb_quantization_range = ctrl->val;
 970                 set_rgb_quantization_range(sd);
 971                 return 0;
 972         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
 973                 /* Set the analog sampling phase. This is needed to find the
 974                    best sampling phase for analog video: an application or
 975                    driver has to try a number of phases and analyze the picture
 976                    quality before settling on the best performing phase. */
 977                 afe_write(sd, 0xc8, ctrl->val);
 978                 return 0;
 979         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
 980                 /* Use the default blue color for free running mode,
 981                    or supply your own. */
 982                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
 983                 return 0;
 984         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
 985                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
 986                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
 987                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
 988                 return 0;
 989         }
 990         return -EINVAL;
 991 }
 992
 993 /* ----------------------------------------------------------------------- */
 994
 995 static inline bool no_power(struct v4l2_subdev *sd)
 996 {
 997         /* Entire chip or CP powered off */
 998         return io_read(sd, 0x0c) & 0x24;
 999 }
1000
1001 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1002 {
1003         struct adv7604_state *state = to_state(sd);
1004
1005         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1006 }
1007
1008 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1009 {
1010         return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1011 }
1012
1013 static inline bool is_hdmi(struct v4l2_subdev *sd)
1014 {
1015         return hdmi_read(sd, 0x05) & 0x80;
1016 }
1017
1018 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1019 {
1020         /* TODO channel 2 */
1021         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1022 }
1023
1024 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1025 {
1026         /* TODO channel 2 */
1027         return !(cp_read(sd, 0xb1) & 0x80);
1028 }
1029
1030 static inline bool no_signal(struct v4l2_subdev *sd)
1031 {
1032         bool ret;
1033
1034         ret = no_power(sd);
1035
1036         ret |= no_lock_stdi(sd);
1037         ret |= no_lock_sspd(sd);
1038
1039         if (is_digital_input(sd)) {
1040                 ret |= no_lock_tmds(sd);
1041                 ret |= no_signal_tmds(sd);
1042         }
1043
1044         return ret;
1045 }
1046
1047 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1048 {
1049         /* CP has detected a non standard number of lines on the incoming
1050            video compared to what it is configured to receive by s_dv_timings */
1051         return io_read(sd, 0x12) & 0x01;
1052 }
1053
1054 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1055 {
1056         *status = 0;
1057         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1058         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1059         if (no_lock_cp(sd))
1060                 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1061
1062         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1063
1064         return 0;
1065 }
1066
1067 /* ----------------------------------------------------------------------- */
1068
1069 struct stdi_readback {
1070         u16 bl, lcf, lcvs;
1071         u8 hs_pol, vs_pol;
1072         bool interlaced;
1073 };
1074
1075 static int stdi2dv_timings(struct v4l2_subdev *sd,
1076                 struct stdi_readback *stdi,
1077                 struct v4l2_dv_timings *timings)
1078 {
1079         struct adv7604_state *state = to_state(sd);
1080         u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1081         u32 pix_clk;
1082         int i;
1083
1084         for (i = 0; adv7604_timings[i].bt.height; i++) {
1085                 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1086                         continue;
1087                 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1088                         continue;
1089
1090                 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1091
1092                 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1093                     (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1094                         *timings = adv7604_timings[i];
1095                         return 0;
1096                 }
1097         }
1098
1099         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1100                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1101                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1102                         timings))
1103                 return 0;
1104         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1105                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1106                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1107                         state->aspect_ratio, timings))
1108                 return 0;
1109
1110         v4l2_dbg(2, debug, sd,
1111                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1112                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1113                 stdi->hs_pol, stdi->vs_pol);
1114         return -1;
1115 }
1116
1117 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1118 {
1119         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1120                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1121                 return -1;
1122         }
1123
1124         /* read STDI */
1125         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1126         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1127         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1128         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1129
1130         /* read SSPD */
1131         if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1132                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1133                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1134                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1135                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1136         } else {
1137                 stdi->hs_pol = 'x';
1138                 stdi->vs_pol = 'x';
1139         }
1140
1141         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1142                 v4l2_dbg(2, debug, sd,
1143                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1144                 return -1;
1145         }
1146
1147         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1148                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1149                 memset(stdi, 0, sizeof(struct stdi_readback));
1150                 return -1;
1151         }
1152
1153         v4l2_dbg(2, debug, sd,
1154                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1155                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1156                 stdi->hs_pol, stdi->vs_pol,
1157                 stdi->interlaced ? "interlaced" : "progressive");
1158
1159         return 0;
1160 }
1161
1162 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1163                         struct v4l2_enum_dv_timings *timings)
1164 {
1165         if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1166                 return -EINVAL;
1167         memset(timings->reserved, 0, sizeof(timings->reserved));
1168         timings->timings = adv7604_timings[timings->index];
1169         return 0;
1170 }
1171
1172 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1173                         struct v4l2_dv_timings_cap *cap)
1174 {
1175         cap->type = V4L2_DV_BT_656_1120;
1176         cap->bt.max_width = 1920;
1177         cap->bt.max_height = 1200;
1178         cap->bt.min_pixelclock = 25000000;
1179         if (is_digital_input(sd))
1180                 cap->bt.max_pixelclock = 225000000;
1181         else
1182                 cap->bt.max_pixelclock = 170000000;
1183         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1184                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1185         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1186                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1187         return 0;
1188 }
1189
1190 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1191    if the format is listed in adv7604_timings[] */
1192 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1193                 struct v4l2_dv_timings *timings)
1194 {
1195         int i;
1196
1197         for (i = 0; adv7604_timings[i].bt.width; i++) {
1198                 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
1199                                         is_digital_input(sd) ? 250000 : 1000000)) {
1200                         *timings = adv7604_timings[i];
1201                         break;
1202                 }
1203         }
1204 }
1205
1206 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1207                         struct v4l2_dv_timings *timings)
1208 {
1209         struct adv7604_state *state = to_state(sd);
1210         struct v4l2_bt_timings *bt = &timings->bt;
1211         struct stdi_readback stdi;
1212
1213         if (!timings)
1214                 return -EINVAL;
1215
1216         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1217
1218         if (no_signal(sd)) {
1219                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1220                 return -ENOLINK;
1221         }
1222
1223         /* read STDI */
1224         if (read_stdi(sd, &stdi)) {
1225                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1226                 return -ENOLINK;
1227         }
1228         bt->interlaced = stdi.interlaced ?
1229                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1230
1231         if (is_digital_input(sd)) {
1232                 uint32_t freq;
1233
1234                 timings->type = V4L2_DV_BT_656_1120;
1235
1236                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1237                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1238                 freq = (hdmi_read(sd, 0x06) * 1000000) +
1239                         ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1240                 if (is_hdmi(sd)) {
1241                         /* adjust for deep color mode */
1242                         unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1243
1244                         freq = freq * 8 / bits_per_channel;
1245                 }
1246                 bt->pixelclock = freq;
1247                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1248                         hdmi_read(sd, 0x21);
1249                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1250                         hdmi_read(sd, 0x23);
1251                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1252                         hdmi_read(sd, 0x25);
1253                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1254                         hdmi_read(sd, 0x2b)) / 2;
1255                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1256                         hdmi_read(sd, 0x2f)) / 2;
1257                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1258                         hdmi_read(sd, 0x33)) / 2;
1259                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1260                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1261                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1262                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1263                                         hdmi_read(sd, 0x0c);
1264                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1265                                         hdmi_read(sd, 0x2d)) / 2;
1266                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1267                                         hdmi_read(sd, 0x31)) / 2;
1268                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1269                                         hdmi_read(sd, 0x35)) / 2;
1270                 }
1271                 adv7604_fill_optional_dv_timings_fields(sd, timings);
1272         } else {
1273                 /* find format
1274                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1275                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1276                  */
1277                 if (!stdi2dv_timings(sd, &stdi, timings))
1278                         goto found;
1279                 stdi.lcvs += 1;
1280                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1281                 if (!stdi2dv_timings(sd, &stdi, timings))
1282                         goto found;
1283                 stdi.lcvs -= 2;
1284                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1285                 if (stdi2dv_timings(sd, &stdi, timings)) {
1286                         /*
1287                          * The STDI block may measure wrong values, especially
1288                          * for lcvs and lcf. If the driver can not find any
1289                          * valid timing, the STDI block is restarted to measure
1290                          * the video timings again. The function will return an
1291                          * error, but the restart of STDI will generate a new
1292                          * STDI interrupt and the format detection process will
1293                          * restart.
1294                          */
1295                         if (state->restart_stdi_once) {
1296                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1297                                 /* TODO restart STDI for Sync Channel 2 */
1298                                 /* enter one-shot mode */
1299                                 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1300                                 /* trigger STDI restart */
1301                                 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1302                                 /* reset to continuous mode */
1303                                 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1304                                 state->restart_stdi_once = false;
1305                                 return -ENOLINK;
1306                         }
1307                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1308                         return -ERANGE;
1309                 }
1310                 state->restart_stdi_once = true;
1311         }
1312 found:
1313
1314         if (no_signal(sd)) {
1315                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1316                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1317                 return -ENOLINK;
1318         }
1319
1320         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1321                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1322                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1323                                 __func__, (u32)bt->pixelclock);
1324                 return -ERANGE;
1325         }
1326
1327         if (debug > 1)
1328                 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1329                                       timings, true);
1330
1331         return 0;
1332 }
1333
1334 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1335                 struct v4l2_dv_timings *timings)
1336 {
1337         struct adv7604_state *state = to_state(sd);
1338         struct v4l2_bt_timings *bt;
1339         int err;
1340
1341         if (!timings)
1342                 return -EINVAL;
1343
1344         bt = &timings->bt;
1345
1346         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1347                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1348                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1349                                 __func__, (u32)bt->pixelclock);
1350                 return -ERANGE;
1351         }
1352
1353         adv7604_fill_optional_dv_timings_fields(sd, timings);
1354
1355         state->timings = *timings;
1356
1357         cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1358
1359         /* Use prim_mode and vid_std when available */
1360         err = configure_predefined_video_timings(sd, timings);
1361         if (err) {
1362                 /* custom settings when the video format
1363                  does not have prim_mode/vid_std */
1364                 configure_custom_video_timings(sd, bt);
1365         }
1366
1367         set_rgb_quantization_range(sd);
1368
1369
1370         if (debug > 1)
1371                 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1372                                       timings, true);
1373         return 0;
1374 }
1375
1376 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1377                 struct v4l2_dv_timings *timings)
1378 {
1379         struct adv7604_state *state = to_state(sd);
1380
1381         *timings = state->timings;
1382         return 0;
1383 }
1384
1385 static void enable_input(struct v4l2_subdev *sd)
1386 {
1387         struct adv7604_state *state = to_state(sd);
1388
1389         if (is_analog_input(sd)) {
1390                 /* enable */
1391                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1392         } else if (is_digital_input(sd)) {
1393                 /* enable */
1394                 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
1395                 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1396                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1397                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1398         } else {
1399                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1400                                 __func__, state->selected_input);
1401         }
1402 }
1403
1404 static void disable_input(struct v4l2_subdev *sd)
1405 {
1406         /* disable */
1407         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1408         hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1409         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1410 }
1411
1412 static void select_input(struct v4l2_subdev *sd)
1413 {
1414         struct adv7604_state *state = to_state(sd);
1415
1416         if (is_analog_input(sd)) {
1417                 /* reset ADI recommended settings for HDMI: */
1418                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1419                 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1420                 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1421                 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1422                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1423                 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1424                 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1425                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1426                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1427                 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1428                 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1429                 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1430
1431                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1432                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1433                 afe_write(sd, 0xc8, 0x00); /* phase control */
1434
1435                 /* set ADI recommended settings for digitizer */
1436                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1437                 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1438                 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1439                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1440                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1441                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1442         } else if (is_digital_input(sd)) {
1443                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1444
1445                 /* set ADI recommended settings for HDMI: */
1446                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1447                 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1448                 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1449                 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1450                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1451                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1452                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1453                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1454                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1455                 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1456                 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1457                 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1458
1459                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1460                 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1461                 afe_write(sd, 0xc8, 0x40); /* phase control */
1462
1463                 /* reset ADI recommended settings for digitizer */
1464                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1465                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1466                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1467                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1468                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1469                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1470         } else {
1471                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1472                                 __func__, state->selected_input);
1473         }
1474 }
1475
1476 static int adv7604_s_routing(struct v4l2_subdev *sd,
1477                 u32 input, u32 output, u32 config)
1478 {
1479         struct adv7604_state *state = to_state(sd);
1480
1481         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1482                         __func__, input, state->selected_input);
1483
1484         if (input == state->selected_input)
1485                 return 0;
1486
1487         state->selected_input = input;
1488
1489         disable_input(sd);
1490
1491         select_input(sd);
1492
1493         enable_input(sd);
1494
1495         return 0;
1496 }
1497
1498 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1499                              enum v4l2_mbus_pixelcode *code)
1500 {
1501         if (index)
1502                 return -EINVAL;
1503         /* Good enough for now */
1504         *code = V4L2_MBUS_FMT_FIXED;
1505         return 0;
1506 }
1507
1508 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1509                 struct v4l2_mbus_framefmt *fmt)
1510 {
1511         struct adv7604_state *state = to_state(sd);
1512
1513         fmt->width = state->timings.bt.width;
1514         fmt->height = state->timings.bt.height;
1515         fmt->code = V4L2_MBUS_FMT_FIXED;
1516         fmt->field = V4L2_FIELD_NONE;
1517         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1518                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1519                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1520         }
1521         return 0;
1522 }
1523
1524 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1525 {
1526         u8 fmt_change, fmt_change_digital, tx_5v;
1527
1528         v4l2_dbg(2, debug, sd, "%s: ", __func__);
1529
1530         /* format change */
1531         fmt_change = io_read(sd, 0x43) & 0x98;
1532         if (fmt_change)
1533                 io_write(sd, 0x44, fmt_change);
1534
1535         fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0;
1536         if (fmt_change_digital)
1537                 io_write(sd, 0x6c, fmt_change_digital);
1538
1539         if (fmt_change || fmt_change_digital) {
1540                 v4l2_dbg(1, debug, sd,
1541                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1542                         __func__, fmt_change, fmt_change_digital);
1543
1544                 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1545
1546                 if (handled)
1547                         *handled = true;
1548         }
1549         /* tx 5v detect */
1550         tx_5v = io_read(sd, 0x70) & 0x1e;
1551         if (tx_5v) {
1552                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1553                 io_write(sd, 0x71, tx_5v);
1554                 adv7604_s_detect_tx_5v_ctrl(sd);
1555                 if (handled)
1556                         *handled = true;
1557         }
1558         return 0;
1559 }
1560
1561 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1562 {
1563         struct adv7604_state *state = to_state(sd);
1564         u8 *data = NULL;
1565
1566         if (edid->pad > ADV7604_EDID_PORT_D)
1567                 return -EINVAL;
1568         if (edid->blocks == 0)
1569                 return -EINVAL;
1570         if (edid->blocks > 2)
1571                 return -EINVAL;
1572         if (edid->start_block > 1)
1573                 return -EINVAL;
1574         if (edid->start_block == 1)
1575                 edid->blocks = 1;
1576         if (!edid->edid)
1577                 return -EINVAL;
1578
1579         if (edid->blocks > state->edid.blocks)
1580                 edid->blocks = state->edid.blocks;
1581
1582         switch (edid->pad) {
1583         case ADV7604_EDID_PORT_A:
1584         case ADV7604_EDID_PORT_B:
1585         case ADV7604_EDID_PORT_C:
1586         case ADV7604_EDID_PORT_D:
1587                 if (state->edid.present & (1 << edid->pad))
1588                         data = state->edid.edid;
1589                 break;
1590         default:
1591                 return -EINVAL;
1592                 break;
1593         }
1594         if (!data)
1595                 return -ENODATA;
1596
1597         memcpy(edid->edid,
1598                data + edid->start_block * 128,
1599                edid->blocks * 128);
1600         return 0;
1601 }
1602
1603 static int get_edid_spa_location(const u8 *edid)
1604 {
1605         u8 d;
1606
1607         if ((edid[0x7e] != 1) ||
1608             (edid[0x80] != 0x02) ||
1609             (edid[0x81] != 0x03)) {
1610                 return -1;
1611         }
1612
1613         /* search Vendor Specific Data Block (tag 3) */
1614         d = edid[0x82] & 0x7f;
1615         if (d > 4) {
1616                 int i = 0x84;
1617                 int end = 0x80 + d;
1618
1619                 do {
1620                         u8 tag = edid[i] >> 5;
1621                         u8 len = edid[i] & 0x1f;
1622
1623                         if ((tag == 3) && (len >= 5))
1624                                 return i + 4;
1625                         i += len + 1;
1626                 } while (i < end);
1627         }
1628         return -1;
1629 }
1630
1631 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1632 {
1633         struct adv7604_state *state = to_state(sd);
1634         int spa_loc;
1635         int tmp = 0;
1636         int err;
1637         int i;
1638
1639         if (edid->pad > ADV7604_EDID_PORT_D)
1640                 return -EINVAL;
1641         if (edid->start_block != 0)
1642                 return -EINVAL;
1643         if (edid->blocks == 0) {
1644                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
1645                 state->edid.present &= ~(1 << edid->pad);
1646                 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
1647                 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1648
1649                 /* Fall back to a 16:9 aspect ratio */
1650                 state->aspect_ratio.numerator = 16;
1651                 state->aspect_ratio.denominator = 9;
1652
1653                 if (!state->edid.present)
1654                         state->edid.blocks = 0;
1655
1656                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
1657                                 __func__, edid->pad, state->edid.present);
1658                 return 0;
1659         }
1660         if (edid->blocks > 2) {
1661                 edid->blocks = 2;
1662                 return -E2BIG;
1663         }
1664         if (!edid->edid)
1665                 return -EINVAL;
1666
1667         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
1668                         __func__, edid->pad, state->edid.present);
1669
1670         /* Disable hotplug and I2C access to EDID RAM from DDC port */
1671         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
1672         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
1673         rep_write_and_or(sd, 0x77, 0xf0, 0x00);
1674
1675         spa_loc = get_edid_spa_location(edid->edid);
1676         if (spa_loc < 0)
1677                 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
1678
1679         switch (edid->pad) {
1680         case ADV7604_EDID_PORT_A:
1681                 state->spa_port_a[0] = edid->edid[spa_loc];
1682                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
1683                 break;
1684         case ADV7604_EDID_PORT_B:
1685                 rep_write(sd, 0x70, edid->edid[spa_loc]);
1686                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
1687                 break;
1688         case ADV7604_EDID_PORT_C:
1689                 rep_write(sd, 0x72, edid->edid[spa_loc]);
1690                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
1691                 break;
1692         case ADV7604_EDID_PORT_D:
1693                 rep_write(sd, 0x74, edid->edid[spa_loc]);
1694                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
1695                 break;
1696         default:
1697                 return -EINVAL;
1698         }
1699         rep_write(sd, 0x76, spa_loc & 0xff);
1700         rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
1701
1702         edid->edid[spa_loc] = state->spa_port_a[0];
1703         edid->edid[spa_loc + 1] = state->spa_port_a[1];
1704
1705         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1706         state->edid.blocks = edid->blocks;
1707         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1708                         edid->edid[0x16]);
1709         state->edid.present |= 1 << edid->pad;
1710
1711         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1712         if (err < 0) {
1713                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
1714                 return err;
1715         }
1716
1717         /* adv7604 calculates the checksums and enables I2C access to internal
1718            EDID RAM from DDC port. */
1719         rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1720
1721         for (i = 0; i < 1000; i++) {
1722                 if (rep_read(sd, 0x7d) & state->edid.present)
1723                         break;
1724                 mdelay(1);
1725         }
1726         if (i == 1000) {
1727                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
1728                 return -EIO;
1729         }
1730
1731
1732         /* enable hotplug after 100 ms */
1733         queue_delayed_work(state->work_queues,
1734                         &state->delayed_work_enable_hotplug, HZ / 10);
1735         return 0;
1736 }
1737
1738 /*********** avi info frame CEA-861-E **************/
1739
1740 static void print_avi_infoframe(struct v4l2_subdev *sd)
1741 {
1742         int i;
1743         u8 buf[14];
1744         u8 avi_len;
1745         u8 avi_ver;
1746
1747         if (!is_hdmi(sd)) {
1748                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1749                 return;
1750         }
1751         if (!(io_read(sd, 0x60) & 0x01)) {
1752                 v4l2_info(sd, "AVI infoframe not received\n");
1753                 return;
1754         }
1755
1756         if (io_read(sd, 0x83) & 0x01) {
1757                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1758                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1759                 if (io_read(sd, 0x83) & 0x01) {
1760                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
1761                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1762                 }
1763         }
1764
1765         avi_len = infoframe_read(sd, 0xe2);
1766         avi_ver = infoframe_read(sd, 0xe1);
1767         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1768                         avi_ver, avi_len);
1769
1770         if (avi_ver != 0x02)
1771                 return;
1772
1773         for (i = 0; i < 14; i++)
1774                 buf[i] = infoframe_read(sd, i);
1775
1776         v4l2_info(sd,
1777                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1778                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1779                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1780 }
1781
1782 static int adv7604_log_status(struct v4l2_subdev *sd)
1783 {
1784         struct adv7604_state *state = to_state(sd);
1785         struct v4l2_dv_timings timings;
1786         struct stdi_readback stdi;
1787         u8 reg_io_0x02 = io_read(sd, 0x02);
1788
1789         char *csc_coeff_sel_rb[16] = {
1790                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1791                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1792                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1793                 "reserved", "reserved", "reserved", "reserved", "manual"
1794         };
1795         char *input_color_space_txt[16] = {
1796                 "RGB limited range (16-235)", "RGB full range (0-255)",
1797                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1798                 "xvYCC Bt.601", "xvYCC Bt.709",
1799                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1800                 "invalid", "invalid", "invalid", "invalid", "invalid",
1801                 "invalid", "invalid", "automatic"
1802         };
1803         char *rgb_quantization_range_txt[] = {
1804                 "Automatic",
1805                 "RGB limited range (16-235)",
1806                 "RGB full range (0-255)",
1807         };
1808         char *deep_color_mode_txt[4] = {
1809                 "8-bits per channel",
1810                 "10-bits per channel",
1811                 "12-bits per channel",
1812                 "16-bits per channel (not supported)"
1813         };
1814
1815         v4l2_info(sd, "-----Chip status-----\n");
1816         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1817         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1818                         ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1819                         ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1820                         ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1821                         ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
1822         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1823                         "enabled" : "disabled");
1824
1825         v4l2_info(sd, "-----Signal status-----\n");
1826         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1827                         ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1828                         ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1829                         ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1830                         ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
1831         v4l2_info(sd, "TMDS signal detected: %s\n",
1832                         no_signal_tmds(sd) ? "false" : "true");
1833         v4l2_info(sd, "TMDS signal locked: %s\n",
1834                         no_lock_tmds(sd) ? "false" : "true");
1835         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1836         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1837         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1838         v4l2_info(sd, "CP free run: %s\n",
1839                         (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1840         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1841                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1842                         (io_read(sd, 0x01) & 0x70) >> 4);
1843
1844         v4l2_info(sd, "-----Video Timings-----\n");
1845         if (read_stdi(sd, &stdi))
1846                 v4l2_info(sd, "STDI: not locked\n");
1847         else
1848                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1849                                 stdi.lcf, stdi.bl, stdi.lcvs,
1850                                 stdi.interlaced ? "interlaced" : "progressive",
1851                                 stdi.hs_pol, stdi.vs_pol);
1852         if (adv7604_query_dv_timings(sd, &timings))
1853                 v4l2_info(sd, "No video detected\n");
1854         else
1855                 v4l2_print_dv_timings(sd->name, "Detected format: ",
1856                                       &timings, true);
1857         v4l2_print_dv_timings(sd->name, "Configured format: ",
1858                               &state->timings, true);
1859
1860         if (no_signal(sd))
1861                 return 0;
1862
1863         v4l2_info(sd, "-----Color space-----\n");
1864         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1865                         rgb_quantization_range_txt[state->rgb_quantization_range]);
1866         v4l2_info(sd, "Input color space: %s\n",
1867                         input_color_space_txt[reg_io_0x02 >> 4]);
1868         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1869                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1870                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1871                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1872                                 "enabled" : "disabled");
1873         v4l2_info(sd, "Color space conversion: %s\n",
1874                         csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1875
1876         if (!is_digital_input(sd))
1877                 return 0;
1878
1879         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1880         v4l2_info(sd, "Digital video port selected: %c\n",
1881                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
1882         v4l2_info(sd, "HDCP encrypted content: %s\n",
1883                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
1884         v4l2_info(sd, "HDCP keys read: %s%s\n",
1885                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1886                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1887         if (!is_hdmi(sd)) {
1888                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1889                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1890                 bool audio_mute = io_read(sd, 0x65) & 0x40;
1891
1892                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1893                                 audio_pll_locked ? "locked" : "not locked",
1894                                 audio_sample_packet_detect ? "detected" : "not detected",
1895                                 audio_mute ? "muted" : "enabled");
1896                 if (audio_pll_locked && audio_sample_packet_detect) {
1897                         v4l2_info(sd, "Audio format: %s\n",
1898                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1899                 }
1900                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1901                                 (hdmi_read(sd, 0x5c) << 8) +
1902                                 (hdmi_read(sd, 0x5d) & 0xf0));
1903                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
1904                                 (hdmi_read(sd, 0x5e) << 8) +
1905                                 hdmi_read(sd, 0x5f));
1906                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
1907
1908                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
1909
1910                 print_avi_infoframe(sd);
1911         }
1912
1913         return 0;
1914 }
1915
1916 /* ----------------------------------------------------------------------- */
1917
1918 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1919         .s_ctrl = adv7604_s_ctrl,
1920 };
1921
1922 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1923         .log_status = adv7604_log_status,
1924         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1925         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1926         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1927         .g_ctrl = v4l2_subdev_g_ctrl,
1928         .s_ctrl = v4l2_subdev_s_ctrl,
1929         .queryctrl = v4l2_subdev_queryctrl,
1930         .querymenu = v4l2_subdev_querymenu,
1931         .interrupt_service_routine = adv7604_isr,
1932 #ifdef CONFIG_VIDEO_ADV_DEBUG
1933         .g_register = adv7604_g_register,
1934         .s_register = adv7604_s_register,
1935 #endif
1936 };
1937
1938 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1939         .s_routing = adv7604_s_routing,
1940         .g_input_status = adv7604_g_input_status,
1941         .s_dv_timings = adv7604_s_dv_timings,
1942         .g_dv_timings = adv7604_g_dv_timings,
1943         .query_dv_timings = adv7604_query_dv_timings,
1944         .enum_dv_timings = adv7604_enum_dv_timings,
1945         .dv_timings_cap = adv7604_dv_timings_cap,
1946         .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1947         .g_mbus_fmt = adv7604_g_mbus_fmt,
1948         .try_mbus_fmt = adv7604_g_mbus_fmt,
1949         .s_mbus_fmt = adv7604_g_mbus_fmt,
1950 };
1951
1952 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1953         .get_edid = adv7604_get_edid,
1954         .set_edid = adv7604_set_edid,
1955 };
1956
1957 static const struct v4l2_subdev_ops adv7604_ops = {
1958         .core = &adv7604_core_ops,
1959         .video = &adv7604_video_ops,
1960         .pad = &adv7604_pad_ops,
1961 };
1962
1963 /* -------------------------- custom ctrls ---------------------------------- */
1964
1965 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1966         .ops = &adv7604_ctrl_ops,
1967         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1968         .name = "Analog Sampling Phase",
1969         .type = V4L2_CTRL_TYPE_INTEGER,
1970         .min = 0,
1971         .max = 0x1f,
1972         .step = 1,
1973         .def = 0,
1974 };
1975
1976 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1977         .ops = &adv7604_ctrl_ops,
1978         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1979         .name = "Free Running Color, Manual",
1980         .type = V4L2_CTRL_TYPE_BOOLEAN,
1981         .min = false,
1982         .max = true,
1983         .step = 1,
1984         .def = false,
1985 };
1986
1987 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1988         .ops = &adv7604_ctrl_ops,
1989         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1990         .name = "Free Running Color",
1991         .type = V4L2_CTRL_TYPE_INTEGER,
1992         .min = 0x0,
1993         .max = 0xffffff,
1994         .step = 0x1,
1995         .def = 0x0,
1996 };
1997
1998 /* ----------------------------------------------------------------------- */
1999
2000 static int adv7604_core_init(struct v4l2_subdev *sd)
2001 {
2002         struct adv7604_state *state = to_state(sd);
2003         struct adv7604_platform_data *pdata = &state->pdata;
2004
2005         hdmi_write(sd, 0x48,
2006                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2007                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2008
2009         disable_input(sd);
2010
2011         /* power */
2012         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2013         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2014         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2015
2016         /* video format */
2017         io_write_and_or(sd, 0x02, 0xf0,
2018                         pdata->alt_gamma << 3 |
2019                         pdata->op_656_range << 2 |
2020                         pdata->rgb_out << 1 |
2021                         pdata->alt_data_sat << 0);
2022         io_write(sd, 0x03, pdata->op_format_sel);
2023         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2024         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2025                                         pdata->insert_av_codes << 2 |
2026                                         pdata->replicate_av_codes << 1 |
2027                                         pdata->invert_cbcr << 0);
2028
2029         /* TODO from platform data */
2030         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2031         io_write(sd, 0x06, 0xa6);   /* positive VS and HS */
2032
2033         /* Adjust drive strength */
2034         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2035                                 pdata->dr_str_clk << 2 |
2036                                 pdata->dr_str_sync);
2037
2038         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2039         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2040         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2041                                       ADI recommended setting [REF_01, c. 2.3.3] */
2042         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2043                                       ADI recommended setting [REF_01, c. 2.3.3] */
2044         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2045                                      for digital formats */
2046
2047         /* TODO from platform data */
2048         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2049
2050         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2051         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2052
2053         /* interrupts */
2054         io_write(sd, 0x40, 0xc2); /* Configure INT1 */
2055         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2056         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2057         io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2058         io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
2059
2060         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2061 }
2062
2063 static void adv7604_unregister_clients(struct adv7604_state *state)
2064 {
2065         if (state->i2c_avlink)
2066                 i2c_unregister_device(state->i2c_avlink);
2067         if (state->i2c_cec)
2068                 i2c_unregister_device(state->i2c_cec);
2069         if (state->i2c_infoframe)
2070                 i2c_unregister_device(state->i2c_infoframe);
2071         if (state->i2c_esdp)
2072                 i2c_unregister_device(state->i2c_esdp);
2073         if (state->i2c_dpp)
2074                 i2c_unregister_device(state->i2c_dpp);
2075         if (state->i2c_afe)
2076                 i2c_unregister_device(state->i2c_afe);
2077         if (state->i2c_repeater)
2078                 i2c_unregister_device(state->i2c_repeater);
2079         if (state->i2c_edid)
2080                 i2c_unregister_device(state->i2c_edid);
2081         if (state->i2c_hdmi)
2082                 i2c_unregister_device(state->i2c_hdmi);
2083         if (state->i2c_test)
2084                 i2c_unregister_device(state->i2c_test);
2085         if (state->i2c_cp)
2086                 i2c_unregister_device(state->i2c_cp);
2087         if (state->i2c_vdp)
2088                 i2c_unregister_device(state->i2c_vdp);
2089 }
2090
2091 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2092                                                         u8 addr, u8 io_reg)
2093 {
2094         struct i2c_client *client = v4l2_get_subdevdata(sd);
2095
2096         if (addr)
2097                 io_write(sd, io_reg, addr << 1);
2098         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2099 }
2100
2101 static int adv7604_probe(struct i2c_client *client,
2102                          const struct i2c_device_id *id)
2103 {
2104         struct adv7604_state *state;
2105         struct adv7604_platform_data *pdata = client->dev.platform_data;
2106         struct v4l2_ctrl_handler *hdl;
2107         struct v4l2_subdev *sd;
2108         int err;
2109
2110         /* Check if the adapter supports the needed features */
2111         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2112                 return -EIO;
2113         v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2114                         client->addr << 1);
2115
2116         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2117         if (!state) {
2118                 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2119                 return -ENOMEM;
2120         }
2121
2122         /* initialize variables */
2123         state->restart_stdi_once = true;
2124         state->selected_input = ~0;
2125
2126         /* platform data */
2127         if (!pdata) {
2128                 v4l_err(client, "No platform data!\n");
2129                 return -ENODEV;
2130         }
2131         memcpy(&state->pdata, pdata, sizeof(state->pdata));
2132
2133         sd = &state->sd;
2134         v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2135         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2136
2137         /* i2c access to adv7604? */
2138         if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2139                 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2140                                 client->addr << 1);
2141                 return -ENODEV;
2142         }
2143
2144         /* control handlers */
2145         hdl = &state->hdl;
2146         v4l2_ctrl_handler_init(hdl, 9);
2147
2148         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2149                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2150         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2151                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
2152         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2153                         V4L2_CID_SATURATION, 0, 255, 1, 128);
2154         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2155                         V4L2_CID_HUE, 0, 128, 1, 0);
2156
2157         /* private controls */
2158         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2159                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
2160         state->rgb_quantization_range_ctrl =
2161                 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2162                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2163                         0, V4L2_DV_RGB_RANGE_AUTO);
2164
2165         /* custom controls */
2166         state->analog_sampling_phase_ctrl =
2167                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2168         state->free_run_color_manual_ctrl =
2169                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2170         state->free_run_color_ctrl =
2171                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2172
2173         sd->ctrl_handler = hdl;
2174         if (hdl->error) {
2175                 err = hdl->error;
2176                 goto err_hdl;
2177         }
2178         state->detect_tx_5v_ctrl->is_private = true;
2179         state->rgb_quantization_range_ctrl->is_private = true;
2180         state->analog_sampling_phase_ctrl->is_private = true;
2181         state->free_run_color_manual_ctrl->is_private = true;
2182         state->free_run_color_ctrl->is_private = true;
2183
2184         if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2185                 err = -ENODEV;
2186                 goto err_hdl;
2187         }
2188
2189         state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2190         state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2191         state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2192         state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2193         state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2194         state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2195         state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2196         state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2197         state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2198         state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2199         state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2200         state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2201         if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2202             !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2203             !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2204             !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2205                 err = -ENOMEM;
2206                 v4l2_err(sd, "failed to create all i2c clients\n");
2207                 goto err_i2c;
2208         }
2209
2210         /* work queues */
2211         state->work_queues = create_singlethread_workqueue(client->name);
2212         if (!state->work_queues) {
2213                 v4l2_err(sd, "Could not create work queue\n");
2214                 err = -ENOMEM;
2215                 goto err_i2c;
2216         }
2217
2218         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2219                         adv7604_delayed_work_enable_hotplug);
2220
2221         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2222         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2223         if (err)
2224                 goto err_work_queues;
2225
2226         err = adv7604_core_init(sd);
2227         if (err)
2228                 goto err_entity;
2229         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2230                         client->addr << 1, client->adapter->name);
2231         return 0;
2232
2233 err_entity:
2234         media_entity_cleanup(&sd->entity);
2235 err_work_queues:
2236         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2237         destroy_workqueue(state->work_queues);
2238 err_i2c:
2239         adv7604_unregister_clients(state);
2240 err_hdl:
2241         v4l2_ctrl_handler_free(hdl);
2242         return err;
2243 }
2244
2245 /* ----------------------------------------------------------------------- */
2246
2247 static int adv7604_remove(struct i2c_client *client)
2248 {
2249         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2250         struct adv7604_state *state = to_state(sd);
2251
2252         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2253         destroy_workqueue(state->work_queues);
2254         v4l2_device_unregister_subdev(sd);
2255         media_entity_cleanup(&sd->entity);
2256         adv7604_unregister_clients(to_state(sd));
2257         v4l2_ctrl_handler_free(sd->ctrl_handler);
2258         return 0;
2259 }
2260
2261 /* ----------------------------------------------------------------------- */
2262
2263 static struct i2c_device_id adv7604_id[] = {
2264         { "adv7604", 0 },
2265         { }
2266 };
2267 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2268
2269 static struct i2c_driver adv7604_driver = {
2270         .driver = {
2271                 .owner = THIS_MODULE,
2272                 .name = "adv7604",
2273         },
2274         .probe = adv7604_probe,
2275         .remove = adv7604_remove,
2276         .id_table = adv7604_id,
2277 };
2278
2279 module_i2c_driver(adv7604_driver);