drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/i2c.h>
  35 #include <linux/delay.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <media/v4l2-device.h>
  40 #include <media/v4l2-ctrls.h>
  41 #include <media/v4l2-dv-timings.h>
  42 #include <media/adv7604.h>
  43
  44 static int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "debug level (0-2)");
  47
  48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  51 MODULE_LICENSE("GPL");
  52
  53 /* ADV7604 system clock frequency */
  54 #define ADV7604_fsc (28636360)
  55
  56 /*
  57  **********************************************************************
  58  *
  59  *  Arrays with configuration parameters for the ADV7604
  60  *
  61  **********************************************************************
  62  */
  63 struct adv7604_state {
  64         struct adv7604_platform_data pdata;
  65         struct v4l2_subdev sd;
  66         struct media_pad pad;
  67         struct v4l2_ctrl_handler hdl;
  68         enum adv7604_input_port selected_input;
  69         struct v4l2_dv_timings timings;
  70         struct {
  71                 u8 edid[256];
  72                 u32 present;
  73                 unsigned blocks;
  74         } edid;
  75         u16 spa_port_a[2];
  76         struct v4l2_fract aspect_ratio;
  77         u32 rgb_quantization_range;
  78         struct workqueue_struct *work_queues;
  79         struct delayed_work delayed_work_enable_hotplug;
  80         bool restart_stdi_once;
  81         u32 prev_input_status;
  82
  83         /* i2c clients */
  84         struct i2c_client *i2c_avlink;
  85         struct i2c_client *i2c_cec;
  86         struct i2c_client *i2c_infoframe;
  87         struct i2c_client *i2c_esdp;
  88         struct i2c_client *i2c_dpp;
  89         struct i2c_client *i2c_afe;
  90         struct i2c_client *i2c_repeater;
  91         struct i2c_client *i2c_edid;
  92         struct i2c_client *i2c_hdmi;
  93         struct i2c_client *i2c_test;
  94         struct i2c_client *i2c_cp;
  95         struct i2c_client *i2c_vdp;
  96
  97         /* controls */
  98         struct v4l2_ctrl *detect_tx_5v_ctrl;
  99         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 100         struct v4l2_ctrl *free_run_color_manual_ctrl;
 101         struct v4l2_ctrl *free_run_color_ctrl;
 102         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 103 };
 104
 105 /* Supported CEA and DMT timings */
 106 static const struct v4l2_dv_timings adv7604_timings[] = {
 107         V4L2_DV_BT_CEA_720X480P59_94,
 108         V4L2_DV_BT_CEA_720X576P50,
 109         V4L2_DV_BT_CEA_1280X720P24,
 110         V4L2_DV_BT_CEA_1280X720P25,
 111         V4L2_DV_BT_CEA_1280X720P50,
 112         V4L2_DV_BT_CEA_1280X720P60,
 113         V4L2_DV_BT_CEA_1920X1080P24,
 114         V4L2_DV_BT_CEA_1920X1080P25,
 115         V4L2_DV_BT_CEA_1920X1080P30,
 116         V4L2_DV_BT_CEA_1920X1080P50,
 117         V4L2_DV_BT_CEA_1920X1080P60,
 118
 119         /* sorted by DMT ID */
 120         V4L2_DV_BT_DMT_640X350P85,
 121         V4L2_DV_BT_DMT_640X400P85,
 122         V4L2_DV_BT_DMT_720X400P85,
 123         V4L2_DV_BT_DMT_640X480P60,
 124         V4L2_DV_BT_DMT_640X480P72,
 125         V4L2_DV_BT_DMT_640X480P75,
 126         V4L2_DV_BT_DMT_640X480P85,
 127         V4L2_DV_BT_DMT_800X600P56,
 128         V4L2_DV_BT_DMT_800X600P60,
 129         V4L2_DV_BT_DMT_800X600P72,
 130         V4L2_DV_BT_DMT_800X600P75,
 131         V4L2_DV_BT_DMT_800X600P85,
 132         V4L2_DV_BT_DMT_848X480P60,
 133         V4L2_DV_BT_DMT_1024X768P60,
 134         V4L2_DV_BT_DMT_1024X768P70,
 135         V4L2_DV_BT_DMT_1024X768P75,
 136         V4L2_DV_BT_DMT_1024X768P85,
 137         V4L2_DV_BT_DMT_1152X864P75,
 138         V4L2_DV_BT_DMT_1280X768P60_RB,
 139         V4L2_DV_BT_DMT_1280X768P60,
 140         V4L2_DV_BT_DMT_1280X768P75,
 141         V4L2_DV_BT_DMT_1280X768P85,
 142         V4L2_DV_BT_DMT_1280X800P60_RB,
 143         V4L2_DV_BT_DMT_1280X800P60,
 144         V4L2_DV_BT_DMT_1280X800P75,
 145         V4L2_DV_BT_DMT_1280X800P85,
 146         V4L2_DV_BT_DMT_1280X960P60,
 147         V4L2_DV_BT_DMT_1280X960P85,
 148         V4L2_DV_BT_DMT_1280X1024P60,
 149         V4L2_DV_BT_DMT_1280X1024P75,
 150         V4L2_DV_BT_DMT_1280X1024P85,
 151         V4L2_DV_BT_DMT_1360X768P60,
 152         V4L2_DV_BT_DMT_1400X1050P60_RB,
 153         V4L2_DV_BT_DMT_1400X1050P60,
 154         V4L2_DV_BT_DMT_1400X1050P75,
 155         V4L2_DV_BT_DMT_1400X1050P85,
 156         V4L2_DV_BT_DMT_1440X900P60_RB,
 157         V4L2_DV_BT_DMT_1440X900P60,
 158         V4L2_DV_BT_DMT_1600X1200P60,
 159         V4L2_DV_BT_DMT_1680X1050P60_RB,
 160         V4L2_DV_BT_DMT_1680X1050P60,
 161         V4L2_DV_BT_DMT_1792X1344P60,
 162         V4L2_DV_BT_DMT_1856X1392P60,
 163         V4L2_DV_BT_DMT_1920X1200P60_RB,
 164         V4L2_DV_BT_DMT_1366X768P60_RB,
 165         V4L2_DV_BT_DMT_1366X768P60,
 166         V4L2_DV_BT_DMT_1920X1080P60,
 167         { },
 168 };
 169
 170 struct adv7604_video_standards {
 171         struct v4l2_dv_timings timings;
 172         u8 vid_std;
 173         u8 v_freq;
 174 };
 175
 176 /* sorted by number of lines */
 177 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
 178         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 179         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 180         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 181         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 182         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 183         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 184         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 185         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 186         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 187         /* TODO add 1920x1080P60_RB (CVT timing) */
 188         { },
 189 };
 190
 191 /* sorted by number of lines */
 192 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
 193         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 194         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 195         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 196         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 199         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 200         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 201         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 203         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 204         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 205         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 206         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 207         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 208         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 209         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 210         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 211         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 212         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 213         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 214         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 215         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 216         { },
 217 };
 218
 219 /* sorted by number of lines */
 220 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
 221         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 222         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 223         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 224         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 225         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 226         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 227         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 228         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 229         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 230         { },
 231 };
 232
 233 /* sorted by number of lines */
 234 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
 235         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 236         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 237         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 238         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 239         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 240         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 241         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 242         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 243         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 244         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 245         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 246         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 247         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 248         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 249         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 250         { },
 251 };
 252
 253 /* ----------------------------------------------------------------------- */
 254
 255 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
 256 {
 257         return container_of(sd, struct adv7604_state, sd);
 258 }
 259
 260 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 261 {
 262         return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
 263 }
 264
 265 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 266 {
 267         return V4L2_DV_BT_BLANKING_WIDTH(t);
 268 }
 269
 270 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 271 {
 272         return V4L2_DV_BT_FRAME_WIDTH(t);
 273 }
 274
 275 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 276 {
 277         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 278 }
 279
 280 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 281 {
 282         return V4L2_DV_BT_FRAME_HEIGHT(t);
 283 }
 284
 285 /* ----------------------------------------------------------------------- */
 286
 287 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 288                 u8 command, bool check)
 289 {
 290         union i2c_smbus_data data;
 291
 292         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 293                         I2C_SMBUS_READ, command,
 294                         I2C_SMBUS_BYTE_DATA, &data))
 295                 return data.byte;
 296         if (check)
 297                 v4l_err(client, "error reading %02x, %02x\n",
 298                                 client->addr, command);
 299         return -EIO;
 300 }
 301
 302 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 303 {
 304         return adv_smbus_read_byte_data_check(client, command, true);
 305 }
 306
 307 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 308                                         u8 command, u8 value)
 309 {
 310         union i2c_smbus_data data;
 311         int err;
 312         int i;
 313
 314         data.byte = value;
 315         for (i = 0; i < 3; i++) {
 316                 err = i2c_smbus_xfer(client->adapter, client->addr,
 317                                 client->flags,
 318                                 I2C_SMBUS_WRITE, command,
 319                                 I2C_SMBUS_BYTE_DATA, &data);
 320                 if (!err)
 321                         break;
 322         }
 323         if (err < 0)
 324                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 325                                 client->addr, command, value);
 326         return err;
 327 }
 328
 329 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 330                u8 command, unsigned length, const u8 *values)
 331 {
 332         union i2c_smbus_data data;
 333
 334         if (length > I2C_SMBUS_BLOCK_MAX)
 335                 length = I2C_SMBUS_BLOCK_MAX;
 336         data.block[0] = length;
 337         memcpy(data.block + 1, values, length);
 338         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 339                               I2C_SMBUS_WRITE, command,
 340                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 341 }
 342
 343 /* ----------------------------------------------------------------------- */
 344
 345 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 346 {
 347         struct i2c_client *client = v4l2_get_subdevdata(sd);
 348
 349         return adv_smbus_read_byte_data(client, reg);
 350 }
 351
 352 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 353 {
 354         struct i2c_client *client = v4l2_get_subdevdata(sd);
 355
 356         return adv_smbus_write_byte_data(client, reg, val);
 357 }
 358
 359 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 360 {
 361         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 362 }
 363
 364 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 365 {
 366         struct adv7604_state *state = to_state(sd);
 367
 368         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 369 }
 370
 371 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 372 {
 373         struct adv7604_state *state = to_state(sd);
 374
 375         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 376 }
 377
 378 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 379 {
 380         struct adv7604_state *state = to_state(sd);
 381
 382         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 383 }
 384
 385 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 386 {
 387         struct adv7604_state *state = to_state(sd);
 388
 389         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 390 }
 391
 392 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 393 {
 394         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 395 }
 396
 397 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 398 {
 399         struct adv7604_state *state = to_state(sd);
 400
 401         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 402 }
 403
 404 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 405 {
 406         struct adv7604_state *state = to_state(sd);
 407
 408         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 409 }
 410
 411 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
 412 {
 413         struct adv7604_state *state = to_state(sd);
 414
 415         return adv_smbus_read_byte_data(state->i2c_esdp, reg);
 416 }
 417
 418 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 419 {
 420         struct adv7604_state *state = to_state(sd);
 421
 422         return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
 423 }
 424
 425 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
 426 {
 427         struct adv7604_state *state = to_state(sd);
 428
 429         return adv_smbus_read_byte_data(state->i2c_dpp, reg);
 430 }
 431
 432 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 433 {
 434         struct adv7604_state *state = to_state(sd);
 435
 436         return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
 437 }
 438
 439 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 440 {
 441         struct adv7604_state *state = to_state(sd);
 442
 443         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 444 }
 445
 446 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 447 {
 448         struct adv7604_state *state = to_state(sd);
 449
 450         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 451 }
 452
 453 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 454 {
 455         struct adv7604_state *state = to_state(sd);
 456
 457         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 458 }
 459
 460 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 461 {
 462         struct adv7604_state *state = to_state(sd);
 463
 464         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 465 }
 466
 467 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 468 {
 469         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 470 }
 471
 472 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 473 {
 474         struct adv7604_state *state = to_state(sd);
 475
 476         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 477 }
 478
 479 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 480 {
 481         struct adv7604_state *state = to_state(sd);
 482
 483         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 484 }
 485
 486 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
 487 {
 488         struct adv7604_state *state = to_state(sd);
 489         struct i2c_client *client = state->i2c_edid;
 490         u8 msgbuf0[1] = { 0 };
 491         u8 msgbuf1[256];
 492         struct i2c_msg msg[2] = {
 493                 {
 494                         .addr = client->addr,
 495                         .len = 1,
 496                         .buf = msgbuf0
 497                 },
 498                 {
 499                         .addr = client->addr,
 500                         .flags = I2C_M_RD,
 501                         .len = len,
 502                         .buf = msgbuf1
 503                 },
 504         };
 505
 506         if (i2c_transfer(client->adapter, msg, 2) < 0)
 507                 return -EIO;
 508         memcpy(val, msgbuf1, len);
 509         return 0;
 510 }
 511
 512 static inline int edid_write_block(struct v4l2_subdev *sd,
 513                                         unsigned len, const u8 *val)
 514 {
 515         struct adv7604_state *state = to_state(sd);
 516         int err = 0;
 517         int i;
 518
 519         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 520
 521         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 522                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 523                                 I2C_SMBUS_BLOCK_MAX, val + i);
 524         return err;
 525 }
 526
 527 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
 528 {
 529         struct delayed_work *dwork = to_delayed_work(work);
 530         struct adv7604_state *state = container_of(dwork, struct adv7604_state,
 531                                                 delayed_work_enable_hotplug);
 532         struct v4l2_subdev *sd = &state->sd;
 533
 534         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 535
 536         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
 537 }
 538
 539 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 540 {
 541         struct adv7604_state *state = to_state(sd);
 542
 543         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 544 }
 545
 546 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 547 {
 548         struct adv7604_state *state = to_state(sd);
 549
 550         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 551 }
 552
 553 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 554 {
 555         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
 556 }
 557
 558 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
 559 {
 560         struct adv7604_state *state = to_state(sd);
 561
 562         return adv_smbus_read_byte_data(state->i2c_test, reg);
 563 }
 564
 565 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 566 {
 567         struct adv7604_state *state = to_state(sd);
 568
 569         return adv_smbus_write_byte_data(state->i2c_test, reg, val);
 570 }
 571
 572 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 573 {
 574         struct adv7604_state *state = to_state(sd);
 575
 576         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 577 }
 578
 579 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 580 {
 581         struct adv7604_state *state = to_state(sd);
 582
 583         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 584 }
 585
 586 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 587 {
 588         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 589 }
 590
 591 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 592 {
 593         struct adv7604_state *state = to_state(sd);
 594
 595         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 596 }
 597
 598 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 599 {
 600         struct adv7604_state *state = to_state(sd);
 601
 602         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 603 }
 604
 605 /* ----------------------------------------------------------------------- */
 606
 607 static inline bool is_analog_input(struct v4l2_subdev *sd)
 608 {
 609         struct adv7604_state *state = to_state(sd);
 610
 611         return state->selected_input == ADV7604_INPUT_VGA_RGB ||
 612                state->selected_input == ADV7604_INPUT_VGA_COMP;
 613 }
 614
 615 static inline bool is_digital_input(struct v4l2_subdev *sd)
 616 {
 617         struct adv7604_state *state = to_state(sd);
 618
 619         return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
 620                state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
 621                state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
 622                state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
 623 }
 624
 625 /* ----------------------------------------------------------------------- */
 626
 627 #ifdef CONFIG_VIDEO_ADV_DEBUG
 628 static void adv7604_inv_register(struct v4l2_subdev *sd)
 629 {
 630         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 631         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 632         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 633         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 634         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 635         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 636         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 637         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 638         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 639         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 640         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 641         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 642         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 643 }
 644
 645 static int adv7604_g_register(struct v4l2_subdev *sd,
 646                                         struct v4l2_dbg_register *reg)
 647 {
 648         reg->size = 1;
 649         switch (reg->reg >> 8) {
 650         case 0:
 651                 reg->val = io_read(sd, reg->reg & 0xff);
 652                 break;
 653         case 1:
 654                 reg->val = avlink_read(sd, reg->reg & 0xff);
 655                 break;
 656         case 2:
 657                 reg->val = cec_read(sd, reg->reg & 0xff);
 658                 break;
 659         case 3:
 660                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 661                 break;
 662         case 4:
 663                 reg->val = esdp_read(sd, reg->reg & 0xff);
 664                 break;
 665         case 5:
 666                 reg->val = dpp_read(sd, reg->reg & 0xff);
 667                 break;
 668         case 6:
 669                 reg->val = afe_read(sd, reg->reg & 0xff);
 670                 break;
 671         case 7:
 672                 reg->val = rep_read(sd, reg->reg & 0xff);
 673                 break;
 674         case 8:
 675                 reg->val = edid_read(sd, reg->reg & 0xff);
 676                 break;
 677         case 9:
 678                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 679                 break;
 680         case 0xa:
 681                 reg->val = test_read(sd, reg->reg & 0xff);
 682                 break;
 683         case 0xb:
 684                 reg->val = cp_read(sd, reg->reg & 0xff);
 685                 break;
 686         case 0xc:
 687                 reg->val = vdp_read(sd, reg->reg & 0xff);
 688                 break;
 689         default:
 690                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 691                 adv7604_inv_register(sd);
 692                 break;
 693         }
 694         return 0;
 695 }
 696
 697 static int adv7604_s_register(struct v4l2_subdev *sd,
 698                                         const struct v4l2_dbg_register *reg)
 699 {
 700         u8 val = reg->val & 0xff;
 701
 702         switch (reg->reg >> 8) {
 703         case 0:
 704                 io_write(sd, reg->reg & 0xff, val);
 705                 break;
 706         case 1:
 707                 avlink_write(sd, reg->reg & 0xff, val);
 708                 break;
 709         case 2:
 710                 cec_write(sd, reg->reg & 0xff, val);
 711                 break;
 712         case 3:
 713                 infoframe_write(sd, reg->reg & 0xff, val);
 714                 break;
 715         case 4:
 716                 esdp_write(sd, reg->reg & 0xff, val);
 717                 break;
 718         case 5:
 719                 dpp_write(sd, reg->reg & 0xff, val);
 720                 break;
 721         case 6:
 722                 afe_write(sd, reg->reg & 0xff, val);
 723                 break;
 724         case 7:
 725                 rep_write(sd, reg->reg & 0xff, val);
 726                 break;
 727         case 8:
 728                 edid_write(sd, reg->reg & 0xff, val);
 729                 break;
 730         case 9:
 731                 hdmi_write(sd, reg->reg & 0xff, val);
 732                 break;
 733         case 0xa:
 734                 test_write(sd, reg->reg & 0xff, val);
 735                 break;
 736         case 0xb:
 737                 cp_write(sd, reg->reg & 0xff, val);
 738                 break;
 739         case 0xc:
 740                 vdp_write(sd, reg->reg & 0xff, val);
 741                 break;
 742         default:
 743                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 744                 adv7604_inv_register(sd);
 745                 break;
 746         }
 747         return 0;
 748 }
 749 #endif
 750
 751 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 752 {
 753         struct adv7604_state *state = to_state(sd);
 754         u8 reg_io_6f = io_read(sd, 0x6f);
 755
 756         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 757                         ((reg_io_6f & 0x10) >> 4) |
 758                         ((reg_io_6f & 0x08) >> 2) |
 759                         (reg_io_6f & 0x04) |
 760                         ((reg_io_6f & 0x02) << 2));
 761 }
 762
 763 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 764                 u8 prim_mode,
 765                 const struct adv7604_video_standards *predef_vid_timings,
 766                 const struct v4l2_dv_timings *timings)
 767 {
 768         int i;
 769
 770         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 771                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 772                                         is_digital_input(sd) ? 250000 : 1000000))
 773                         continue;
 774                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 775                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 776                                 prim_mode); /* v_freq and prim mode */
 777                 return 0;
 778         }
 779
 780         return -1;
 781 }
 782
 783 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 784                 struct v4l2_dv_timings *timings)
 785 {
 786         struct adv7604_state *state = to_state(sd);
 787         int err;
 788
 789         v4l2_dbg(1, debug, sd, "%s", __func__);
 790
 791         /* reset to default values */
 792         io_write(sd, 0x16, 0x43);
 793         io_write(sd, 0x17, 0x5a);
 794         /* disable embedded syncs for auto graphics mode */
 795         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 796         cp_write(sd, 0x8f, 0x00);
 797         cp_write(sd, 0x90, 0x00);
 798         cp_write(sd, 0xa2, 0x00);
 799         cp_write(sd, 0xa3, 0x00);
 800         cp_write(sd, 0xa4, 0x00);
 801         cp_write(sd, 0xa5, 0x00);
 802         cp_write(sd, 0xa6, 0x00);
 803         cp_write(sd, 0xa7, 0x00);
 804         cp_write(sd, 0xab, 0x00);
 805         cp_write(sd, 0xac, 0x00);
 806
 807         if (is_analog_input(sd)) {
 808                 err = find_and_set_predefined_video_timings(sd,
 809                                 0x01, adv7604_prim_mode_comp, timings);
 810                 if (err)
 811                         err = find_and_set_predefined_video_timings(sd,
 812                                         0x02, adv7604_prim_mode_gr, timings);
 813         } else if (is_digital_input(sd)) {
 814                 err = find_and_set_predefined_video_timings(sd,
 815                                 0x05, adv7604_prim_mode_hdmi_comp, timings);
 816                 if (err)
 817                         err = find_and_set_predefined_video_timings(sd,
 818                                         0x06, adv7604_prim_mode_hdmi_gr, timings);
 819         } else {
 820                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 821                                 __func__, state->selected_input);
 822                 err = -1;
 823         }
 824
 825
 826         return err;
 827 }
 828
 829 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 830                 const struct v4l2_bt_timings *bt)
 831 {
 832         struct adv7604_state *state = to_state(sd);
 833         struct i2c_client *client = v4l2_get_subdevdata(sd);
 834         u32 width = htotal(bt);
 835         u32 height = vtotal(bt);
 836         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 837         u16 cp_start_eav = width - bt->hfrontporch;
 838         u16 cp_start_vbi = height - bt->vfrontporch;
 839         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 840         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 841                 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 842         const u8 pll[2] = {
 843                 0xc0 | ((width >> 8) & 0x1f),
 844                 width & 0xff
 845         };
 846
 847         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 848
 849         if (is_analog_input(sd)) {
 850                 /* auto graphics */
 851                 io_write(sd, 0x00, 0x07); /* video std */
 852                 io_write(sd, 0x01, 0x02); /* prim mode */
 853                 /* enable embedded syncs for auto graphics mode */
 854                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 855
 856                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 857                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 858                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 859                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
 860                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 861
 862                 /* active video - horizontal timing */
 863                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
 864                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
 865                                    ((cp_start_eav >> 8) & 0x0f));
 866                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
 867
 868                 /* active video - vertical timing */
 869                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 870                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 871                                    ((cp_end_vbi >> 8) & 0xf));
 872                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 873         } else if (is_digital_input(sd)) {
 874                 /* set default prim_mode/vid_std for HDMI
 875                    according to [REF_03, c. 4.2] */
 876                 io_write(sd, 0x00, 0x02); /* video std */
 877                 io_write(sd, 0x01, 0x06); /* prim mode */
 878         } else {
 879                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 880                                 __func__, state->selected_input);
 881         }
 882
 883         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
 884         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
 885         cp_write(sd, 0xab, (height >> 4) & 0xff);
 886         cp_write(sd, 0xac, (height & 0x0f) << 4);
 887 }
 888
 889 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
 890 {
 891         struct adv7604_state *state = to_state(sd);
 892
 893         v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
 894                        __func__, state->rgb_quantization_range);
 895
 896         switch (state->rgb_quantization_range) {
 897         case V4L2_DV_RGB_RANGE_AUTO:
 898                 if (state->selected_input == ADV7604_INPUT_VGA_RGB) {
 899                         /* Receiving analog RGB signal
 900                          * Set RGB full range (0-255) */
 901                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
 902                         break;
 903                 }
 904
 905                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
 906                         /* Receiving analog YPbPr signal
 907                          * Set automode */
 908                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 909                         break;
 910                 }
 911
 912                 if (hdmi_read(sd, 0x05) & 0x80) {
 913                         /* Receiving HDMI signal
 914                          * Set automode */
 915                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 916                         break;
 917                 }
 918
 919                 /* Receiving DVI-D signal
 920                  * ADV7604 selects RGB limited range regardless of
 921                  * input format (CE/IT) in automatic mode */
 922                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 923                         /* RGB limited range (16-235) */
 924                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
 925                 } else {
 926                         /* RGB full range (0-255) */
 927                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
 928                 }
 929                 break;
 930         case V4L2_DV_RGB_RANGE_LIMITED:
 931                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
 932                         /* YCrCb limited range (16-235) */
 933                         io_write_and_or(sd, 0x02, 0x0f, 0x20);
 934                 } else {
 935                         /* RGB limited range (16-235) */
 936                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
 937                 }
 938                 break;
 939         case V4L2_DV_RGB_RANGE_FULL:
 940                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
 941                         /* YCrCb full range (0-255) */
 942                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
 943                 } else {
 944                         /* RGB full range (0-255) */
 945                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
 946                 }
 947                 break;
 948         }
 949 }
 950
 951 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
 952 {
 953         struct v4l2_subdev *sd = to_sd(ctrl);
 954         struct adv7604_state *state = to_state(sd);
 955
 956         switch (ctrl->id) {
 957         case V4L2_CID_BRIGHTNESS:
 958                 cp_write(sd, 0x3c, ctrl->val);
 959                 return 0;
 960         case V4L2_CID_CONTRAST:
 961                 cp_write(sd, 0x3a, ctrl->val);
 962                 return 0;
 963         case V4L2_CID_SATURATION:
 964                 cp_write(sd, 0x3b, ctrl->val);
 965                 return 0;
 966         case V4L2_CID_HUE:
 967                 cp_write(sd, 0x3d, ctrl->val);
 968                 return 0;
 969         case  V4L2_CID_DV_RX_RGB_RANGE:
 970                 state->rgb_quantization_range = ctrl->val;
 971                 set_rgb_quantization_range(sd);
 972                 return 0;
 973         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
 974                 /* Set the analog sampling phase. This is needed to find the
 975                    best sampling phase for analog video: an application or
 976                    driver has to try a number of phases and analyze the picture
 977                    quality before settling on the best performing phase. */
 978                 afe_write(sd, 0xc8, ctrl->val);
 979                 return 0;
 980         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
 981                 /* Use the default blue color for free running mode,
 982                    or supply your own. */
 983                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
 984                 return 0;
 985         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
 986                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
 987                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
 988                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
 989                 return 0;
 990         }
 991         return -EINVAL;
 992 }
 993
 994 /* ----------------------------------------------------------------------- */
 995
 996 static inline bool no_power(struct v4l2_subdev *sd)
 997 {
 998         /* Entire chip or CP powered off */
 999         return io_read(sd, 0x0c) & 0x24;
1000 }
1001
1002 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1003 {
1004         struct adv7604_state *state = to_state(sd);
1005
1006         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1007 }
1008
1009 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1010 {
1011         return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1012 }
1013
1014 static inline bool is_hdmi(struct v4l2_subdev *sd)
1015 {
1016         return hdmi_read(sd, 0x05) & 0x80;
1017 }
1018
1019 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1020 {
1021         /* TODO channel 2 */
1022         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1023 }
1024
1025 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1026 {
1027         /* TODO channel 2 */
1028         return !(cp_read(sd, 0xb1) & 0x80);
1029 }
1030
1031 static inline bool no_signal(struct v4l2_subdev *sd)
1032 {
1033         bool ret;
1034
1035         ret = no_power(sd);
1036
1037         ret |= no_lock_stdi(sd);
1038         ret |= no_lock_sspd(sd);
1039
1040         if (is_digital_input(sd)) {
1041                 ret |= no_lock_tmds(sd);
1042                 ret |= no_signal_tmds(sd);
1043         }
1044
1045         return ret;
1046 }
1047
1048 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1049 {
1050         /* CP has detected a non standard number of lines on the incoming
1051            video compared to what it is configured to receive by s_dv_timings */
1052         return io_read(sd, 0x12) & 0x01;
1053 }
1054
1055 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1056 {
1057         *status = 0;
1058         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1059         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1060         if (no_lock_cp(sd))
1061                 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1062
1063         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1064
1065         return 0;
1066 }
1067
1068 /* ----------------------------------------------------------------------- */
1069
1070 struct stdi_readback {
1071         u16 bl, lcf, lcvs;
1072         u8 hs_pol, vs_pol;
1073         bool interlaced;
1074 };
1075
1076 static int stdi2dv_timings(struct v4l2_subdev *sd,
1077                 struct stdi_readback *stdi,
1078                 struct v4l2_dv_timings *timings)
1079 {
1080         struct adv7604_state *state = to_state(sd);
1081         u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1082         u32 pix_clk;
1083         int i;
1084
1085         for (i = 0; adv7604_timings[i].bt.height; i++) {
1086                 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1087                         continue;
1088                 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1089                         continue;
1090
1091                 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1092
1093                 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1094                     (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1095                         *timings = adv7604_timings[i];
1096                         return 0;
1097                 }
1098         }
1099
1100         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1101                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1102                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1103                         timings))
1104                 return 0;
1105         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1106                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1107                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1108                         state->aspect_ratio, timings))
1109                 return 0;
1110
1111         v4l2_dbg(2, debug, sd,
1112                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1113                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1114                 stdi->hs_pol, stdi->vs_pol);
1115         return -1;
1116 }
1117
1118 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1119 {
1120         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1121                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1122                 return -1;
1123         }
1124
1125         /* read STDI */
1126         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1127         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1128         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1129         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1130
1131         /* read SSPD */
1132         if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1133                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1134                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1135                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1136                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1137         } else {
1138                 stdi->hs_pol = 'x';
1139                 stdi->vs_pol = 'x';
1140         }
1141
1142         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1143                 v4l2_dbg(2, debug, sd,
1144                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1145                 return -1;
1146         }
1147
1148         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1149                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1150                 memset(stdi, 0, sizeof(struct stdi_readback));
1151                 return -1;
1152         }
1153
1154         v4l2_dbg(2, debug, sd,
1155                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1156                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1157                 stdi->hs_pol, stdi->vs_pol,
1158                 stdi->interlaced ? "interlaced" : "progressive");
1159
1160         return 0;
1161 }
1162
1163 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1164                         struct v4l2_enum_dv_timings *timings)
1165 {
1166         if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1167                 return -EINVAL;
1168         memset(timings->reserved, 0, sizeof(timings->reserved));
1169         timings->timings = adv7604_timings[timings->index];
1170         return 0;
1171 }
1172
1173 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1174                         struct v4l2_dv_timings_cap *cap)
1175 {
1176         cap->type = V4L2_DV_BT_656_1120;
1177         cap->bt.max_width = 1920;
1178         cap->bt.max_height = 1200;
1179         cap->bt.min_pixelclock = 25000000;
1180         if (is_digital_input(sd))
1181                 cap->bt.max_pixelclock = 225000000;
1182         else
1183                 cap->bt.max_pixelclock = 170000000;
1184         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1185                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1186         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1187                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1188         return 0;
1189 }
1190
1191 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1192    if the format is listed in adv7604_timings[] */
1193 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1194                 struct v4l2_dv_timings *timings)
1195 {
1196         int i;
1197
1198         for (i = 0; adv7604_timings[i].bt.width; i++) {
1199                 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
1200                                         is_digital_input(sd) ? 250000 : 1000000)) {
1201                         *timings = adv7604_timings[i];
1202                         break;
1203                 }
1204         }
1205 }
1206
1207 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1208                         struct v4l2_dv_timings *timings)
1209 {
1210         struct adv7604_state *state = to_state(sd);
1211         struct v4l2_bt_timings *bt = &timings->bt;
1212         struct stdi_readback stdi;
1213
1214         if (!timings)
1215                 return -EINVAL;
1216
1217         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1218
1219         if (no_signal(sd)) {
1220                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1221                 return -ENOLINK;
1222         }
1223
1224         /* read STDI */
1225         if (read_stdi(sd, &stdi)) {
1226                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1227                 return -ENOLINK;
1228         }
1229         bt->interlaced = stdi.interlaced ?
1230                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1231
1232         if (is_digital_input(sd)) {
1233                 uint32_t freq;
1234
1235                 timings->type = V4L2_DV_BT_656_1120;
1236
1237                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1238                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1239                 freq = (hdmi_read(sd, 0x06) * 1000000) +
1240                         ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1241                 if (is_hdmi(sd)) {
1242                         /* adjust for deep color mode */
1243                         unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1244
1245                         freq = freq * 8 / bits_per_channel;
1246                 }
1247                 bt->pixelclock = freq;
1248                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1249                         hdmi_read(sd, 0x21);
1250                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1251                         hdmi_read(sd, 0x23);
1252                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1253                         hdmi_read(sd, 0x25);
1254                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1255                         hdmi_read(sd, 0x2b)) / 2;
1256                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1257                         hdmi_read(sd, 0x2f)) / 2;
1258                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1259                         hdmi_read(sd, 0x33)) / 2;
1260                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1261                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1262                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1263                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1264                                         hdmi_read(sd, 0x0c);
1265                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1266                                         hdmi_read(sd, 0x2d)) / 2;
1267                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1268                                         hdmi_read(sd, 0x31)) / 2;
1269                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1270                                         hdmi_read(sd, 0x35)) / 2;
1271                 }
1272                 adv7604_fill_optional_dv_timings_fields(sd, timings);
1273         } else {
1274                 /* find format
1275                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1276                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1277                  */
1278                 if (!stdi2dv_timings(sd, &stdi, timings))
1279                         goto found;
1280                 stdi.lcvs += 1;
1281                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1282                 if (!stdi2dv_timings(sd, &stdi, timings))
1283                         goto found;
1284                 stdi.lcvs -= 2;
1285                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1286                 if (stdi2dv_timings(sd, &stdi, timings)) {
1287                         /*
1288                          * The STDI block may measure wrong values, especially
1289                          * for lcvs and lcf. If the driver can not find any
1290                          * valid timing, the STDI block is restarted to measure
1291                          * the video timings again. The function will return an
1292                          * error, but the restart of STDI will generate a new
1293                          * STDI interrupt and the format detection process will
1294                          * restart.
1295                          */
1296                         if (state->restart_stdi_once) {
1297                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1298                                 /* TODO restart STDI for Sync Channel 2 */
1299                                 /* enter one-shot mode */
1300                                 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1301                                 /* trigger STDI restart */
1302                                 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1303                                 /* reset to continuous mode */
1304                                 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1305                                 state->restart_stdi_once = false;
1306                                 return -ENOLINK;
1307                         }
1308                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1309                         return -ERANGE;
1310                 }
1311                 state->restart_stdi_once = true;
1312         }
1313 found:
1314
1315         if (no_signal(sd)) {
1316                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1317                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1318                 return -ENOLINK;
1319         }
1320
1321         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1322                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1323                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1324                                 __func__, (u32)bt->pixelclock);
1325                 return -ERANGE;
1326         }
1327
1328         if (debug > 1)
1329                 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1330                                       timings, true);
1331
1332         return 0;
1333 }
1334
1335 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1336                 struct v4l2_dv_timings *timings)
1337 {
1338         struct adv7604_state *state = to_state(sd);
1339         struct v4l2_bt_timings *bt;
1340         int err;
1341
1342         if (!timings)
1343                 return -EINVAL;
1344
1345         bt = &timings->bt;
1346
1347         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1348                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1349                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1350                                 __func__, (u32)bt->pixelclock);
1351                 return -ERANGE;
1352         }
1353
1354         adv7604_fill_optional_dv_timings_fields(sd, timings);
1355
1356         state->timings = *timings;
1357
1358         cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1359
1360         /* Use prim_mode and vid_std when available */
1361         err = configure_predefined_video_timings(sd, timings);
1362         if (err) {
1363                 /* custom settings when the video format
1364                  does not have prim_mode/vid_std */
1365                 configure_custom_video_timings(sd, bt);
1366         }
1367
1368         set_rgb_quantization_range(sd);
1369
1370
1371         if (debug > 1)
1372                 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1373                                       timings, true);
1374         return 0;
1375 }
1376
1377 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1378                 struct v4l2_dv_timings *timings)
1379 {
1380         struct adv7604_state *state = to_state(sd);
1381
1382         *timings = state->timings;
1383         return 0;
1384 }
1385
1386 static void enable_input(struct v4l2_subdev *sd)
1387 {
1388         struct adv7604_state *state = to_state(sd);
1389
1390         if (is_analog_input(sd)) {
1391                 /* enable */
1392                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1393         } else if (is_digital_input(sd)) {
1394                 /* enable */
1395                 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
1396                 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1397                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1398                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1399         } else {
1400                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1401                                 __func__, state->selected_input);
1402         }
1403 }
1404
1405 static void disable_input(struct v4l2_subdev *sd)
1406 {
1407         /* disable */
1408         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1409         hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1410         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1411 }
1412
1413 static void select_input(struct v4l2_subdev *sd)
1414 {
1415         struct adv7604_state *state = to_state(sd);
1416
1417         if (is_analog_input(sd)) {
1418                 /* reset ADI recommended settings for HDMI: */
1419                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1420                 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1421                 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1422                 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1423                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1424                 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1425                 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1426                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1427                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1428                 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1429                 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1430                 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1431
1432                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1433                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1434                 afe_write(sd, 0xc8, 0x00); /* phase control */
1435
1436                 /* set ADI recommended settings for digitizer */
1437                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1438                 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1439                 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1440                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1441                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1442                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1443         } else if (is_digital_input(sd)) {
1444                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1445
1446                 /* set ADI recommended settings for HDMI: */
1447                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1448                 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1449                 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1450                 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1451                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1452                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1453                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1454                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1455                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1456                 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1457                 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1458                 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1459
1460                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1461                 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1462                 afe_write(sd, 0xc8, 0x40); /* phase control */
1463
1464                 /* reset ADI recommended settings for digitizer */
1465                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1466                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1467                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1468                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1469                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1470                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1471         } else {
1472                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1473                                 __func__, state->selected_input);
1474         }
1475 }
1476
1477 static int adv7604_s_routing(struct v4l2_subdev *sd,
1478                 u32 input, u32 output, u32 config)
1479 {
1480         struct adv7604_state *state = to_state(sd);
1481
1482         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1483                         __func__, input, state->selected_input);
1484
1485         if (input == state->selected_input)
1486                 return 0;
1487
1488         state->selected_input = input;
1489
1490         disable_input(sd);
1491
1492         select_input(sd);
1493
1494         enable_input(sd);
1495
1496         return 0;
1497 }
1498
1499 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1500                              enum v4l2_mbus_pixelcode *code)
1501 {
1502         if (index)
1503                 return -EINVAL;
1504         /* Good enough for now */
1505         *code = V4L2_MBUS_FMT_FIXED;
1506         return 0;
1507 }
1508
1509 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1510                 struct v4l2_mbus_framefmt *fmt)
1511 {
1512         struct adv7604_state *state = to_state(sd);
1513
1514         fmt->width = state->timings.bt.width;
1515         fmt->height = state->timings.bt.height;
1516         fmt->code = V4L2_MBUS_FMT_FIXED;
1517         fmt->field = V4L2_FIELD_NONE;
1518         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1519                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1520                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1521         }
1522         return 0;
1523 }
1524
1525 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1526 {
1527         struct adv7604_state *state = to_state(sd);
1528         u8 fmt_change, fmt_change_digital, tx_5v;
1529         u32 input_status;
1530
1531         v4l2_dbg(2, debug, sd, "%s: ", __func__);
1532
1533         /* format change */
1534         fmt_change = io_read(sd, 0x43) & 0x98;
1535         if (fmt_change)
1536                 io_write(sd, 0x44, fmt_change);
1537         fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0;
1538         if (fmt_change_digital)
1539                 io_write(sd, 0x6c, fmt_change_digital);
1540         if (fmt_change || fmt_change_digital) {
1541                 v4l2_dbg(1, debug, sd,
1542                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1543                         __func__, fmt_change, fmt_change_digital);
1544
1545                 adv7604_g_input_status(sd, &input_status);
1546                 if (input_status != state->prev_input_status) {
1547                         v4l2_dbg(1, debug, sd,
1548                                 "%s: input_status = 0x%x, prev_input_status = 0x%x\n",
1549                                 __func__, input_status, state->prev_input_status);
1550                         state->prev_input_status = input_status;
1551                         v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1552                 }
1553
1554                 if (handled)
1555                         *handled = true;
1556         }
1557         /* tx 5v detect */
1558         tx_5v = io_read(sd, 0x70) & 0x1e;
1559         if (tx_5v) {
1560                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1561                 io_write(sd, 0x71, tx_5v);
1562                 adv7604_s_detect_tx_5v_ctrl(sd);
1563                 if (handled)
1564                         *handled = true;
1565         }
1566         return 0;
1567 }
1568
1569 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1570 {
1571         struct adv7604_state *state = to_state(sd);
1572         u8 *data = NULL;
1573
1574         if (edid->pad > ADV7604_EDID_PORT_D)
1575                 return -EINVAL;
1576         if (edid->blocks == 0)
1577                 return -EINVAL;
1578         if (edid->blocks > 2)
1579                 return -EINVAL;
1580         if (edid->start_block > 1)
1581                 return -EINVAL;
1582         if (edid->start_block == 1)
1583                 edid->blocks = 1;
1584         if (!edid->edid)
1585                 return -EINVAL;
1586
1587         if (edid->blocks > state->edid.blocks)
1588                 edid->blocks = state->edid.blocks;
1589
1590         switch (edid->pad) {
1591         case ADV7604_EDID_PORT_A:
1592         case ADV7604_EDID_PORT_B:
1593         case ADV7604_EDID_PORT_C:
1594         case ADV7604_EDID_PORT_D:
1595                 if (state->edid.present & (1 << edid->pad))
1596                         data = state->edid.edid;
1597                 break;
1598         default:
1599                 return -EINVAL;
1600                 break;
1601         }
1602         if (!data)
1603                 return -ENODATA;
1604
1605         memcpy(edid->edid,
1606                data + edid->start_block * 128,
1607                edid->blocks * 128);
1608         return 0;
1609 }
1610
1611 static int get_edid_spa_location(const u8 *edid)
1612 {
1613         u8 d;
1614
1615         if ((edid[0x7e] != 1) ||
1616             (edid[0x80] != 0x02) ||
1617             (edid[0x81] != 0x03)) {
1618                 return -1;
1619         }
1620
1621         /* search Vendor Specific Data Block (tag 3) */
1622         d = edid[0x82] & 0x7f;
1623         if (d > 4) {
1624                 int i = 0x84;
1625                 int end = 0x80 + d;
1626
1627                 do {
1628                         u8 tag = edid[i] >> 5;
1629                         u8 len = edid[i] & 0x1f;
1630
1631                         if ((tag == 3) && (len >= 5))
1632                                 return i + 4;
1633                         i += len + 1;
1634                 } while (i < end);
1635         }
1636         return -1;
1637 }
1638
1639 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1640 {
1641         struct adv7604_state *state = to_state(sd);
1642         int spa_loc;
1643         int tmp = 0;
1644         int err;
1645         int i;
1646
1647         if (edid->pad > ADV7604_EDID_PORT_D)
1648                 return -EINVAL;
1649         if (edid->start_block != 0)
1650                 return -EINVAL;
1651         if (edid->blocks == 0) {
1652                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
1653                 state->edid.present &= ~(1 << edid->pad);
1654                 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
1655                 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1656
1657                 /* Fall back to a 16:9 aspect ratio */
1658                 state->aspect_ratio.numerator = 16;
1659                 state->aspect_ratio.denominator = 9;
1660
1661                 if (!state->edid.present)
1662                         state->edid.blocks = 0;
1663
1664                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
1665                                 __func__, edid->pad, state->edid.present);
1666                 return 0;
1667         }
1668         if (edid->blocks > 2) {
1669                 edid->blocks = 2;
1670                 return -E2BIG;
1671         }
1672         if (!edid->edid)
1673                 return -EINVAL;
1674
1675         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
1676                         __func__, edid->pad, state->edid.present);
1677
1678         /* Disable hotplug and I2C access to EDID RAM from DDC port */
1679         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
1680         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
1681         rep_write_and_or(sd, 0x77, 0xf0, 0x00);
1682
1683         spa_loc = get_edid_spa_location(edid->edid);
1684         if (spa_loc < 0)
1685                 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
1686
1687         switch (edid->pad) {
1688         case ADV7604_EDID_PORT_A:
1689                 state->spa_port_a[0] = edid->edid[spa_loc];
1690                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
1691                 break;
1692         case ADV7604_EDID_PORT_B:
1693                 rep_write(sd, 0x70, edid->edid[spa_loc]);
1694                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
1695                 break;
1696         case ADV7604_EDID_PORT_C:
1697                 rep_write(sd, 0x72, edid->edid[spa_loc]);
1698                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
1699                 break;
1700         case ADV7604_EDID_PORT_D:
1701                 rep_write(sd, 0x74, edid->edid[spa_loc]);
1702                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
1703                 break;
1704         default:
1705                 return -EINVAL;
1706         }
1707         rep_write(sd, 0x76, spa_loc & 0xff);
1708         rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
1709
1710         edid->edid[spa_loc] = state->spa_port_a[0];
1711         edid->edid[spa_loc + 1] = state->spa_port_a[1];
1712
1713         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1714         state->edid.blocks = edid->blocks;
1715         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1716                         edid->edid[0x16]);
1717         state->edid.present |= 1 << edid->pad;
1718
1719         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1720         if (err < 0) {
1721                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
1722                 return err;
1723         }
1724
1725         /* adv7604 calculates the checksums and enables I2C access to internal
1726            EDID RAM from DDC port. */
1727         rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1728
1729         for (i = 0; i < 1000; i++) {
1730                 if (rep_read(sd, 0x7d) & state->edid.present)
1731                         break;
1732                 mdelay(1);
1733         }
1734         if (i == 1000) {
1735                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
1736                 return -EIO;
1737         }
1738
1739
1740         /* enable hotplug after 100 ms */
1741         queue_delayed_work(state->work_queues,
1742                         &state->delayed_work_enable_hotplug, HZ / 10);
1743         return 0;
1744 }
1745
1746 /*********** avi info frame CEA-861-E **************/
1747
1748 static void print_avi_infoframe(struct v4l2_subdev *sd)
1749 {
1750         int i;
1751         u8 buf[14];
1752         u8 avi_len;
1753         u8 avi_ver;
1754
1755         if (!is_hdmi(sd)) {
1756                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1757                 return;
1758         }
1759         if (!(io_read(sd, 0x60) & 0x01)) {
1760                 v4l2_info(sd, "AVI infoframe not received\n");
1761                 return;
1762         }
1763
1764         if (io_read(sd, 0x83) & 0x01) {
1765                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1766                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1767                 if (io_read(sd, 0x83) & 0x01) {
1768                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
1769                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1770                 }
1771         }
1772
1773         avi_len = infoframe_read(sd, 0xe2);
1774         avi_ver = infoframe_read(sd, 0xe1);
1775         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1776                         avi_ver, avi_len);
1777
1778         if (avi_ver != 0x02)
1779                 return;
1780
1781         for (i = 0; i < 14; i++)
1782                 buf[i] = infoframe_read(sd, i);
1783
1784         v4l2_info(sd,
1785                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1786                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1787                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1788 }
1789
1790 static int adv7604_log_status(struct v4l2_subdev *sd)
1791 {
1792         struct adv7604_state *state = to_state(sd);
1793         struct v4l2_dv_timings timings;
1794         struct stdi_readback stdi;
1795         u8 reg_io_0x02 = io_read(sd, 0x02);
1796
1797         char *csc_coeff_sel_rb[16] = {
1798                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1799                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1800                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1801                 "reserved", "reserved", "reserved", "reserved", "manual"
1802         };
1803         char *input_color_space_txt[16] = {
1804                 "RGB limited range (16-235)", "RGB full range (0-255)",
1805                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1806                 "xvYCC Bt.601", "xvYCC Bt.709",
1807                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1808                 "invalid", "invalid", "invalid", "invalid", "invalid",
1809                 "invalid", "invalid", "automatic"
1810         };
1811         char *rgb_quantization_range_txt[] = {
1812                 "Automatic",
1813                 "RGB limited range (16-235)",
1814                 "RGB full range (0-255)",
1815         };
1816         char *deep_color_mode_txt[4] = {
1817                 "8-bits per channel",
1818                 "10-bits per channel",
1819                 "12-bits per channel",
1820                 "16-bits per channel (not supported)"
1821         };
1822
1823         v4l2_info(sd, "-----Chip status-----\n");
1824         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1825         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1826                         ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1827                         ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1828                         ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1829                         ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
1830         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1831                         "enabled" : "disabled");
1832
1833         v4l2_info(sd, "-----Signal status-----\n");
1834         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1835                         ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1836                         ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1837                         ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1838                         ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
1839         v4l2_info(sd, "TMDS signal detected: %s\n",
1840                         no_signal_tmds(sd) ? "false" : "true");
1841         v4l2_info(sd, "TMDS signal locked: %s\n",
1842                         no_lock_tmds(sd) ? "false" : "true");
1843         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1844         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1845         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1846         v4l2_info(sd, "CP free run: %s\n",
1847                         (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1848         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1849                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1850                         (io_read(sd, 0x01) & 0x70) >> 4);
1851
1852         v4l2_info(sd, "-----Video Timings-----\n");
1853         if (read_stdi(sd, &stdi))
1854                 v4l2_info(sd, "STDI: not locked\n");
1855         else
1856                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1857                                 stdi.lcf, stdi.bl, stdi.lcvs,
1858                                 stdi.interlaced ? "interlaced" : "progressive",
1859                                 stdi.hs_pol, stdi.vs_pol);
1860         if (adv7604_query_dv_timings(sd, &timings))
1861                 v4l2_info(sd, "No video detected\n");
1862         else
1863                 v4l2_print_dv_timings(sd->name, "Detected format: ",
1864                                       &timings, true);
1865         v4l2_print_dv_timings(sd->name, "Configured format: ",
1866                               &state->timings, true);
1867
1868         if (no_signal(sd))
1869                 return 0;
1870
1871         v4l2_info(sd, "-----Color space-----\n");
1872         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1873                         rgb_quantization_range_txt[state->rgb_quantization_range]);
1874         v4l2_info(sd, "Input color space: %s\n",
1875                         input_color_space_txt[reg_io_0x02 >> 4]);
1876         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1877                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1878                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1879                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1880                                 "enabled" : "disabled");
1881         v4l2_info(sd, "Color space conversion: %s\n",
1882                         csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1883
1884         if (!is_digital_input(sd))
1885                 return 0;
1886
1887         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1888         v4l2_info(sd, "Digital video port selected: %c\n",
1889                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
1890         v4l2_info(sd, "HDCP encrypted content: %s\n",
1891                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
1892         v4l2_info(sd, "HDCP keys read: %s%s\n",
1893                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1894                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1895         if (!is_hdmi(sd)) {
1896                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1897                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1898                 bool audio_mute = io_read(sd, 0x65) & 0x40;
1899
1900                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1901                                 audio_pll_locked ? "locked" : "not locked",
1902                                 audio_sample_packet_detect ? "detected" : "not detected",
1903                                 audio_mute ? "muted" : "enabled");
1904                 if (audio_pll_locked && audio_sample_packet_detect) {
1905                         v4l2_info(sd, "Audio format: %s\n",
1906                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1907                 }
1908                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1909                                 (hdmi_read(sd, 0x5c) << 8) +
1910                                 (hdmi_read(sd, 0x5d) & 0xf0));
1911                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
1912                                 (hdmi_read(sd, 0x5e) << 8) +
1913                                 hdmi_read(sd, 0x5f));
1914                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
1915
1916                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
1917
1918                 print_avi_infoframe(sd);
1919         }
1920
1921         return 0;
1922 }
1923
1924 /* ----------------------------------------------------------------------- */
1925
1926 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1927         .s_ctrl = adv7604_s_ctrl,
1928 };
1929
1930 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1931         .log_status = adv7604_log_status,
1932         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1933         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1934         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1935         .g_ctrl = v4l2_subdev_g_ctrl,
1936         .s_ctrl = v4l2_subdev_s_ctrl,
1937         .queryctrl = v4l2_subdev_queryctrl,
1938         .querymenu = v4l2_subdev_querymenu,
1939         .interrupt_service_routine = adv7604_isr,
1940 #ifdef CONFIG_VIDEO_ADV_DEBUG
1941         .g_register = adv7604_g_register,
1942         .s_register = adv7604_s_register,
1943 #endif
1944 };
1945
1946 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1947         .s_routing = adv7604_s_routing,
1948         .g_input_status = adv7604_g_input_status,
1949         .s_dv_timings = adv7604_s_dv_timings,
1950         .g_dv_timings = adv7604_g_dv_timings,
1951         .query_dv_timings = adv7604_query_dv_timings,
1952         .enum_dv_timings = adv7604_enum_dv_timings,
1953         .dv_timings_cap = adv7604_dv_timings_cap,
1954         .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1955         .g_mbus_fmt = adv7604_g_mbus_fmt,
1956         .try_mbus_fmt = adv7604_g_mbus_fmt,
1957         .s_mbus_fmt = adv7604_g_mbus_fmt,
1958 };
1959
1960 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1961         .get_edid = adv7604_get_edid,
1962         .set_edid = adv7604_set_edid,
1963 };
1964
1965 static const struct v4l2_subdev_ops adv7604_ops = {
1966         .core = &adv7604_core_ops,
1967         .video = &adv7604_video_ops,
1968         .pad = &adv7604_pad_ops,
1969 };
1970
1971 /* -------------------------- custom ctrls ---------------------------------- */
1972
1973 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1974         .ops = &adv7604_ctrl_ops,
1975         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1976         .name = "Analog Sampling Phase",
1977         .type = V4L2_CTRL_TYPE_INTEGER,
1978         .min = 0,
1979         .max = 0x1f,
1980         .step = 1,
1981         .def = 0,
1982 };
1983
1984 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1985         .ops = &adv7604_ctrl_ops,
1986         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1987         .name = "Free Running Color, Manual",
1988         .type = V4L2_CTRL_TYPE_BOOLEAN,
1989         .min = false,
1990         .max = true,
1991         .step = 1,
1992         .def = false,
1993 };
1994
1995 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1996         .ops = &adv7604_ctrl_ops,
1997         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1998         .name = "Free Running Color",
1999         .type = V4L2_CTRL_TYPE_INTEGER,
2000         .min = 0x0,
2001         .max = 0xffffff,
2002         .step = 0x1,
2003         .def = 0x0,
2004 };
2005
2006 /* ----------------------------------------------------------------------- */
2007
2008 static int adv7604_core_init(struct v4l2_subdev *sd)
2009 {
2010         struct adv7604_state *state = to_state(sd);
2011         struct adv7604_platform_data *pdata = &state->pdata;
2012
2013         hdmi_write(sd, 0x48,
2014                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2015                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2016
2017         disable_input(sd);
2018
2019         /* power */
2020         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2021         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2022         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2023
2024         /* video format */
2025         io_write_and_or(sd, 0x02, 0xf0,
2026                         pdata->alt_gamma << 3 |
2027                         pdata->op_656_range << 2 |
2028                         pdata->rgb_out << 1 |
2029                         pdata->alt_data_sat << 0);
2030         io_write(sd, 0x03, pdata->op_format_sel);
2031         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2032         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2033                                         pdata->insert_av_codes << 2 |
2034                                         pdata->replicate_av_codes << 1 |
2035                                         pdata->invert_cbcr << 0);
2036
2037         /* TODO from platform data */
2038         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2039         io_write(sd, 0x06, 0xa6);   /* positive VS and HS */
2040
2041         /* Adjust drive strength */
2042         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2043                                 pdata->dr_str_clk << 2 |
2044                                 pdata->dr_str_sync);
2045
2046         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2047         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2048         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2049                                       ADI recommended setting [REF_01, c. 2.3.3] */
2050         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2051                                       ADI recommended setting [REF_01, c. 2.3.3] */
2052         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2053                                      for digital formats */
2054
2055         /* TODO from platform data */
2056         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2057
2058         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2059         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2060
2061         /* interrupts */
2062         io_write(sd, 0x40, 0xc2); /* Configure INT1 */
2063         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2064         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2065         io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2066         io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
2067
2068         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2069 }
2070
2071 static void adv7604_unregister_clients(struct adv7604_state *state)
2072 {
2073         if (state->i2c_avlink)
2074                 i2c_unregister_device(state->i2c_avlink);
2075         if (state->i2c_cec)
2076                 i2c_unregister_device(state->i2c_cec);
2077         if (state->i2c_infoframe)
2078                 i2c_unregister_device(state->i2c_infoframe);
2079         if (state->i2c_esdp)
2080                 i2c_unregister_device(state->i2c_esdp);
2081         if (state->i2c_dpp)
2082                 i2c_unregister_device(state->i2c_dpp);
2083         if (state->i2c_afe)
2084                 i2c_unregister_device(state->i2c_afe);
2085         if (state->i2c_repeater)
2086                 i2c_unregister_device(state->i2c_repeater);
2087         if (state->i2c_edid)
2088                 i2c_unregister_device(state->i2c_edid);
2089         if (state->i2c_hdmi)
2090                 i2c_unregister_device(state->i2c_hdmi);
2091         if (state->i2c_test)
2092                 i2c_unregister_device(state->i2c_test);
2093         if (state->i2c_cp)
2094                 i2c_unregister_device(state->i2c_cp);
2095         if (state->i2c_vdp)
2096                 i2c_unregister_device(state->i2c_vdp);
2097 }
2098
2099 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2100                                                         u8 addr, u8 io_reg)
2101 {
2102         struct i2c_client *client = v4l2_get_subdevdata(sd);
2103
2104         if (addr)
2105                 io_write(sd, io_reg, addr << 1);
2106         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2107 }
2108
2109 static int adv7604_probe(struct i2c_client *client,
2110                          const struct i2c_device_id *id)
2111 {
2112         struct adv7604_state *state;
2113         struct adv7604_platform_data *pdata = client->dev.platform_data;
2114         struct v4l2_ctrl_handler *hdl;
2115         struct v4l2_subdev *sd;
2116         int err;
2117
2118         /* Check if the adapter supports the needed features */
2119         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2120                 return -EIO;
2121         v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2122                         client->addr << 1);
2123
2124         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2125         if (!state) {
2126                 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2127                 return -ENOMEM;
2128         }
2129
2130         /* initialize variables */
2131         state->restart_stdi_once = true;
2132         state->prev_input_status = ~0;
2133         state->selected_input = ~0;
2134
2135         /* platform data */
2136         if (!pdata) {
2137                 v4l_err(client, "No platform data!\n");
2138                 return -ENODEV;
2139         }
2140         memcpy(&state->pdata, pdata, sizeof(state->pdata));
2141
2142         sd = &state->sd;
2143         v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2144         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2145
2146         /* i2c access to adv7604? */
2147         if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2148                 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2149                                 client->addr << 1);
2150                 return -ENODEV;
2151         }
2152
2153         /* control handlers */
2154         hdl = &state->hdl;
2155         v4l2_ctrl_handler_init(hdl, 9);
2156
2157         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2158                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2159         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2160                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
2161         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2162                         V4L2_CID_SATURATION, 0, 255, 1, 128);
2163         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2164                         V4L2_CID_HUE, 0, 128, 1, 0);
2165
2166         /* private controls */
2167         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2168                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
2169         state->rgb_quantization_range_ctrl =
2170                 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2171                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2172                         0, V4L2_DV_RGB_RANGE_AUTO);
2173
2174         /* custom controls */
2175         state->analog_sampling_phase_ctrl =
2176                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2177         state->free_run_color_manual_ctrl =
2178                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2179         state->free_run_color_ctrl =
2180                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2181
2182         sd->ctrl_handler = hdl;
2183         if (hdl->error) {
2184                 err = hdl->error;
2185                 goto err_hdl;
2186         }
2187         state->detect_tx_5v_ctrl->is_private = true;
2188         state->rgb_quantization_range_ctrl->is_private = true;
2189         state->analog_sampling_phase_ctrl->is_private = true;
2190         state->free_run_color_manual_ctrl->is_private = true;
2191         state->free_run_color_ctrl->is_private = true;
2192
2193         if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2194                 err = -ENODEV;
2195                 goto err_hdl;
2196         }
2197
2198         state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2199         state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2200         state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2201         state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2202         state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2203         state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2204         state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2205         state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2206         state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2207         state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2208         state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2209         state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2210         if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2211             !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2212             !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2213             !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2214                 err = -ENOMEM;
2215                 v4l2_err(sd, "failed to create all i2c clients\n");
2216                 goto err_i2c;
2217         }
2218
2219         /* work queues */
2220         state->work_queues = create_singlethread_workqueue(client->name);
2221         if (!state->work_queues) {
2222                 v4l2_err(sd, "Could not create work queue\n");
2223                 err = -ENOMEM;
2224                 goto err_i2c;
2225         }
2226
2227         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2228                         adv7604_delayed_work_enable_hotplug);
2229
2230         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2231         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2232         if (err)
2233                 goto err_work_queues;
2234
2235         err = adv7604_core_init(sd);
2236         if (err)
2237                 goto err_entity;
2238         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2239                         client->addr << 1, client->adapter->name);
2240         return 0;
2241
2242 err_entity:
2243         media_entity_cleanup(&sd->entity);
2244 err_work_queues:
2245         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2246         destroy_workqueue(state->work_queues);
2247 err_i2c:
2248         adv7604_unregister_clients(state);
2249 err_hdl:
2250         v4l2_ctrl_handler_free(hdl);
2251         return err;
2252 }
2253
2254 /* ----------------------------------------------------------------------- */
2255
2256 static int adv7604_remove(struct i2c_client *client)
2257 {
2258         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2259         struct adv7604_state *state = to_state(sd);
2260
2261         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2262         destroy_workqueue(state->work_queues);
2263         v4l2_device_unregister_subdev(sd);
2264         media_entity_cleanup(&sd->entity);
2265         adv7604_unregister_clients(to_state(sd));
2266         v4l2_ctrl_handler_free(sd->ctrl_handler);
2267         return 0;
2268 }
2269
2270 /* ----------------------------------------------------------------------- */
2271
2272 static struct i2c_device_id adv7604_id[] = {
2273         { "adv7604", 0 },
2274         { }
2275 };
2276 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2277
2278 static struct i2c_driver adv7604_driver = {
2279         .driver = {
2280                 .owner = THIS_MODULE,
2281                 .name = "adv7604",
2282         },
2283         .probe = adv7604_probe,
2284         .remove = adv7604_remove,
2285         .id_table = adv7604_id,
2286 };
2287
2288 module_i2c_driver(adv7604_driver);