drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/i2c.h>
  35 #include <linux/delay.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <media/v4l2-device.h>
  40 #include <media/v4l2-ctrls.h>
  41 #include <media/v4l2-dv-timings.h>
  42 #include <media/adv7604.h>
  43
  44 static int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "debug level (0-2)");
  47
  48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  51 MODULE_LICENSE("GPL");
  52
  53 /* ADV7604 system clock frequency */
  54 #define ADV7604_fsc (28636360)
  55
  56 /*
  57  **********************************************************************
  58  *
  59  *  Arrays with configuration parameters for the ADV7604
  60  *
  61  **********************************************************************
  62  */
  63 struct adv7604_state {
  64         struct adv7604_platform_data pdata;
  65         struct v4l2_subdev sd;
  66         struct media_pad pad;
  67         struct v4l2_ctrl_handler hdl;
  68         enum adv7604_input_port selected_input;
  69         struct v4l2_dv_timings timings;
  70         struct {
  71                 u8 edid[256];
  72                 u32 present;
  73                 unsigned blocks;
  74         } edid;
  75         struct v4l2_fract aspect_ratio;
  76         u32 rgb_quantization_range;
  77         struct workqueue_struct *work_queues;
  78         struct delayed_work delayed_work_enable_hotplug;
  79         bool connector_hdmi;
  80         bool restart_stdi_once;
  81         u32 prev_input_status;
  82
  83         /* i2c clients */
  84         struct i2c_client *i2c_avlink;
  85         struct i2c_client *i2c_cec;
  86         struct i2c_client *i2c_infoframe;
  87         struct i2c_client *i2c_esdp;
  88         struct i2c_client *i2c_dpp;
  89         struct i2c_client *i2c_afe;
  90         struct i2c_client *i2c_repeater;
  91         struct i2c_client *i2c_edid;
  92         struct i2c_client *i2c_hdmi;
  93         struct i2c_client *i2c_test;
  94         struct i2c_client *i2c_cp;
  95         struct i2c_client *i2c_vdp;
  96
  97         /* controls */
  98         struct v4l2_ctrl *detect_tx_5v_ctrl;
  99         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 100         struct v4l2_ctrl *free_run_color_manual_ctrl;
 101         struct v4l2_ctrl *free_run_color_ctrl;
 102         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 103 };
 104
 105 /* Supported CEA and DMT timings */
 106 static const struct v4l2_dv_timings adv7604_timings[] = {
 107         V4L2_DV_BT_CEA_720X480P59_94,
 108         V4L2_DV_BT_CEA_720X576P50,
 109         V4L2_DV_BT_CEA_1280X720P24,
 110         V4L2_DV_BT_CEA_1280X720P25,
 111         V4L2_DV_BT_CEA_1280X720P50,
 112         V4L2_DV_BT_CEA_1280X720P60,
 113         V4L2_DV_BT_CEA_1920X1080P24,
 114         V4L2_DV_BT_CEA_1920X1080P25,
 115         V4L2_DV_BT_CEA_1920X1080P30,
 116         V4L2_DV_BT_CEA_1920X1080P50,
 117         V4L2_DV_BT_CEA_1920X1080P60,
 118
 119         /* sorted by DMT ID */
 120         V4L2_DV_BT_DMT_640X350P85,
 121         V4L2_DV_BT_DMT_640X400P85,
 122         V4L2_DV_BT_DMT_720X400P85,
 123         V4L2_DV_BT_DMT_640X480P60,
 124         V4L2_DV_BT_DMT_640X480P72,
 125         V4L2_DV_BT_DMT_640X480P75,
 126         V4L2_DV_BT_DMT_640X480P85,
 127         V4L2_DV_BT_DMT_800X600P56,
 128         V4L2_DV_BT_DMT_800X600P60,
 129         V4L2_DV_BT_DMT_800X600P72,
 130         V4L2_DV_BT_DMT_800X600P75,
 131         V4L2_DV_BT_DMT_800X600P85,
 132         V4L2_DV_BT_DMT_848X480P60,
 133         V4L2_DV_BT_DMT_1024X768P60,
 134         V4L2_DV_BT_DMT_1024X768P70,
 135         V4L2_DV_BT_DMT_1024X768P75,
 136         V4L2_DV_BT_DMT_1024X768P85,
 137         V4L2_DV_BT_DMT_1152X864P75,
 138         V4L2_DV_BT_DMT_1280X768P60_RB,
 139         V4L2_DV_BT_DMT_1280X768P60,
 140         V4L2_DV_BT_DMT_1280X768P75,
 141         V4L2_DV_BT_DMT_1280X768P85,
 142         V4L2_DV_BT_DMT_1280X800P60_RB,
 143         V4L2_DV_BT_DMT_1280X800P60,
 144         V4L2_DV_BT_DMT_1280X800P75,
 145         V4L2_DV_BT_DMT_1280X800P85,
 146         V4L2_DV_BT_DMT_1280X960P60,
 147         V4L2_DV_BT_DMT_1280X960P85,
 148         V4L2_DV_BT_DMT_1280X1024P60,
 149         V4L2_DV_BT_DMT_1280X1024P75,
 150         V4L2_DV_BT_DMT_1280X1024P85,
 151         V4L2_DV_BT_DMT_1360X768P60,
 152         V4L2_DV_BT_DMT_1400X1050P60_RB,
 153         V4L2_DV_BT_DMT_1400X1050P60,
 154         V4L2_DV_BT_DMT_1400X1050P75,
 155         V4L2_DV_BT_DMT_1400X1050P85,
 156         V4L2_DV_BT_DMT_1440X900P60_RB,
 157         V4L2_DV_BT_DMT_1440X900P60,
 158         V4L2_DV_BT_DMT_1600X1200P60,
 159         V4L2_DV_BT_DMT_1680X1050P60_RB,
 160         V4L2_DV_BT_DMT_1680X1050P60,
 161         V4L2_DV_BT_DMT_1792X1344P60,
 162         V4L2_DV_BT_DMT_1856X1392P60,
 163         V4L2_DV_BT_DMT_1920X1200P60_RB,
 164         V4L2_DV_BT_DMT_1366X768P60,
 165         V4L2_DV_BT_DMT_1920X1080P60,
 166         { },
 167 };
 168
 169 struct adv7604_video_standards {
 170         struct v4l2_dv_timings timings;
 171         u8 vid_std;
 172         u8 v_freq;
 173 };
 174
 175 /* sorted by number of lines */
 176 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
 177         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 178         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 179         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 180         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 181         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 182         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 183         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 184         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 185         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 186         /* TODO add 1920x1080P60_RB (CVT timing) */
 187         { },
 188 };
 189
 190 /* sorted by number of lines */
 191 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
 192         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 193         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 194         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 195         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 196         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 199         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 200         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 201         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 203         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 204         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 205         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 206         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 207         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 208         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 209         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 210         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 211         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 212         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 213         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 214         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 215         { },
 216 };
 217
 218 /* sorted by number of lines */
 219 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
 220         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 221         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 222         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 223         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 224         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 225         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 226         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 227         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 228         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 229         { },
 230 };
 231
 232 /* sorted by number of lines */
 233 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
 234         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 235         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 236         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 237         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 238         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 239         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 240         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 241         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 242         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 243         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 244         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 245         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 246         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 247         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 248         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 249         { },
 250 };
 251
 252 /* ----------------------------------------------------------------------- */
 253
 254 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
 255 {
 256         return container_of(sd, struct adv7604_state, sd);
 257 }
 258
 259 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 260 {
 261         return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
 262 }
 263
 264 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 265 {
 266         return V4L2_DV_BT_BLANKING_WIDTH(t);
 267 }
 268
 269 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 270 {
 271         return V4L2_DV_BT_FRAME_WIDTH(t);
 272 }
 273
 274 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 275 {
 276         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 277 }
 278
 279 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 280 {
 281         return V4L2_DV_BT_FRAME_HEIGHT(t);
 282 }
 283
 284 /* ----------------------------------------------------------------------- */
 285
 286 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 287                 u8 command, bool check)
 288 {
 289         union i2c_smbus_data data;
 290
 291         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 292                         I2C_SMBUS_READ, command,
 293                         I2C_SMBUS_BYTE_DATA, &data))
 294                 return data.byte;
 295         if (check)
 296                 v4l_err(client, "error reading %02x, %02x\n",
 297                                 client->addr, command);
 298         return -EIO;
 299 }
 300
 301 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 302 {
 303         return adv_smbus_read_byte_data_check(client, command, true);
 304 }
 305
 306 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 307                                         u8 command, u8 value)
 308 {
 309         union i2c_smbus_data data;
 310         int err;
 311         int i;
 312
 313         data.byte = value;
 314         for (i = 0; i < 3; i++) {
 315                 err = i2c_smbus_xfer(client->adapter, client->addr,
 316                                 client->flags,
 317                                 I2C_SMBUS_WRITE, command,
 318                                 I2C_SMBUS_BYTE_DATA, &data);
 319                 if (!err)
 320                         break;
 321         }
 322         if (err < 0)
 323                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 324                                 client->addr, command, value);
 325         return err;
 326 }
 327
 328 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 329                u8 command, unsigned length, const u8 *values)
 330 {
 331         union i2c_smbus_data data;
 332
 333         if (length > I2C_SMBUS_BLOCK_MAX)
 334                 length = I2C_SMBUS_BLOCK_MAX;
 335         data.block[0] = length;
 336         memcpy(data.block + 1, values, length);
 337         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 338                               I2C_SMBUS_WRITE, command,
 339                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 340 }
 341
 342 /* ----------------------------------------------------------------------- */
 343
 344 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 345 {
 346         struct i2c_client *client = v4l2_get_subdevdata(sd);
 347
 348         return adv_smbus_read_byte_data(client, reg);
 349 }
 350
 351 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 352 {
 353         struct i2c_client *client = v4l2_get_subdevdata(sd);
 354
 355         return adv_smbus_write_byte_data(client, reg, val);
 356 }
 357
 358 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 359 {
 360         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 361 }
 362
 363 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 364 {
 365         struct adv7604_state *state = to_state(sd);
 366
 367         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 368 }
 369
 370 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 371 {
 372         struct adv7604_state *state = to_state(sd);
 373
 374         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 375 }
 376
 377 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 378 {
 379         struct adv7604_state *state = to_state(sd);
 380
 381         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 382 }
 383
 384 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 385 {
 386         struct adv7604_state *state = to_state(sd);
 387
 388         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 389 }
 390
 391 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 392 {
 393         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 394 }
 395
 396 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 397 {
 398         struct adv7604_state *state = to_state(sd);
 399
 400         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 401 }
 402
 403 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 404 {
 405         struct adv7604_state *state = to_state(sd);
 406
 407         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 408 }
 409
 410 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
 411 {
 412         struct adv7604_state *state = to_state(sd);
 413
 414         return adv_smbus_read_byte_data(state->i2c_esdp, reg);
 415 }
 416
 417 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 418 {
 419         struct adv7604_state *state = to_state(sd);
 420
 421         return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
 422 }
 423
 424 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
 425 {
 426         struct adv7604_state *state = to_state(sd);
 427
 428         return adv_smbus_read_byte_data(state->i2c_dpp, reg);
 429 }
 430
 431 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 432 {
 433         struct adv7604_state *state = to_state(sd);
 434
 435         return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
 436 }
 437
 438 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 439 {
 440         struct adv7604_state *state = to_state(sd);
 441
 442         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 443 }
 444
 445 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 446 {
 447         struct adv7604_state *state = to_state(sd);
 448
 449         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 450 }
 451
 452 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 453 {
 454         struct adv7604_state *state = to_state(sd);
 455
 456         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 457 }
 458
 459 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 460 {
 461         struct adv7604_state *state = to_state(sd);
 462
 463         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 464 }
 465
 466 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 467 {
 468         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 469 }
 470
 471 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 472 {
 473         struct adv7604_state *state = to_state(sd);
 474
 475         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 476 }
 477
 478 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 479 {
 480         struct adv7604_state *state = to_state(sd);
 481
 482         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 483 }
 484
 485 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
 486 {
 487         struct adv7604_state *state = to_state(sd);
 488         struct i2c_client *client = state->i2c_edid;
 489         u8 msgbuf0[1] = { 0 };
 490         u8 msgbuf1[256];
 491         struct i2c_msg msg[2] = {
 492                 {
 493                         .addr = client->addr,
 494                         .len = 1,
 495                         .buf = msgbuf0
 496                 },
 497                 {
 498                         .addr = client->addr,
 499                         .flags = I2C_M_RD,
 500                         .len = len,
 501                         .buf = msgbuf1
 502                 },
 503         };
 504
 505         if (i2c_transfer(client->adapter, msg, 2) < 0)
 506                 return -EIO;
 507         memcpy(val, msgbuf1, len);
 508         return 0;
 509 }
 510
 511 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
 512 {
 513         struct delayed_work *dwork = to_delayed_work(work);
 514         struct adv7604_state *state = container_of(dwork, struct adv7604_state,
 515                                                 delayed_work_enable_hotplug);
 516         struct v4l2_subdev *sd = &state->sd;
 517
 518         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 519
 520         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
 521 }
 522
 523 static inline int edid_write_block(struct v4l2_subdev *sd,
 524                                         unsigned len, const u8 *val)
 525 {
 526         struct i2c_client *client = v4l2_get_subdevdata(sd);
 527         struct adv7604_state *state = to_state(sd);
 528         int err = 0;
 529         int i;
 530
 531         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 532
 533         /* Disables I2C access to internal EDID ram from DDC port */
 534         rep_write_and_or(sd, 0x77, 0xf0, 0x0);
 535
 536         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 537                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 538                                 I2C_SMBUS_BLOCK_MAX, val + i);
 539         if (err)
 540                 return err;
 541
 542         /* adv7604 calculates the checksums and enables I2C access to internal
 543            EDID RAM from DDC port. */
 544         rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
 545
 546         for (i = 0; i < 1000; i++) {
 547                 if (rep_read(sd, 0x7d) & state->edid.present)
 548                         break;
 549                 mdelay(1);
 550         }
 551         if (i == 1000) {
 552                 v4l_err(client, "error enabling edid (0x%x)\n", state->edid.present);
 553                 return -EIO;
 554         }
 555
 556         return 0;
 557 }
 558
 559 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 560 {
 561         struct adv7604_state *state = to_state(sd);
 562
 563         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 564 }
 565
 566 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 567 {
 568         struct adv7604_state *state = to_state(sd);
 569
 570         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 571 }
 572
 573 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 574 {
 575         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
 576 }
 577
 578 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
 579 {
 580         struct adv7604_state *state = to_state(sd);
 581
 582         return adv_smbus_read_byte_data(state->i2c_test, reg);
 583 }
 584
 585 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 586 {
 587         struct adv7604_state *state = to_state(sd);
 588
 589         return adv_smbus_write_byte_data(state->i2c_test, reg, val);
 590 }
 591
 592 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 593 {
 594         struct adv7604_state *state = to_state(sd);
 595
 596         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 597 }
 598
 599 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 600 {
 601         struct adv7604_state *state = to_state(sd);
 602
 603         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 604 }
 605
 606 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 607 {
 608         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 609 }
 610
 611 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 612 {
 613         struct adv7604_state *state = to_state(sd);
 614
 615         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 616 }
 617
 618 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 619 {
 620         struct adv7604_state *state = to_state(sd);
 621
 622         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 623 }
 624
 625 /* ----------------------------------------------------------------------- */
 626
 627 static inline bool is_analog_input(struct v4l2_subdev *sd)
 628 {
 629         struct adv7604_state *state = to_state(sd);
 630
 631         return state->selected_input == ADV7604_INPUT_VGA_RGB ||
 632                state->selected_input == ADV7604_INPUT_VGA_COMP;
 633 }
 634
 635 static inline bool is_digital_input(struct v4l2_subdev *sd)
 636 {
 637         struct adv7604_state *state = to_state(sd);
 638
 639         return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
 640                state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
 641                state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
 642                state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
 643 }
 644
 645 /* ----------------------------------------------------------------------- */
 646
 647 #ifdef CONFIG_VIDEO_ADV_DEBUG
 648 static void adv7604_inv_register(struct v4l2_subdev *sd)
 649 {
 650         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 651         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 652         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 653         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 654         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 655         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 656         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 657         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 658         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 659         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 660         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 661         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 662         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 663 }
 664
 665 static int adv7604_g_register(struct v4l2_subdev *sd,
 666                                         struct v4l2_dbg_register *reg)
 667 {
 668         reg->size = 1;
 669         switch (reg->reg >> 8) {
 670         case 0:
 671                 reg->val = io_read(sd, reg->reg & 0xff);
 672                 break;
 673         case 1:
 674                 reg->val = avlink_read(sd, reg->reg & 0xff);
 675                 break;
 676         case 2:
 677                 reg->val = cec_read(sd, reg->reg & 0xff);
 678                 break;
 679         case 3:
 680                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 681                 break;
 682         case 4:
 683                 reg->val = esdp_read(sd, reg->reg & 0xff);
 684                 break;
 685         case 5:
 686                 reg->val = dpp_read(sd, reg->reg & 0xff);
 687                 break;
 688         case 6:
 689                 reg->val = afe_read(sd, reg->reg & 0xff);
 690                 break;
 691         case 7:
 692                 reg->val = rep_read(sd, reg->reg & 0xff);
 693                 break;
 694         case 8:
 695                 reg->val = edid_read(sd, reg->reg & 0xff);
 696                 break;
 697         case 9:
 698                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 699                 break;
 700         case 0xa:
 701                 reg->val = test_read(sd, reg->reg & 0xff);
 702                 break;
 703         case 0xb:
 704                 reg->val = cp_read(sd, reg->reg & 0xff);
 705                 break;
 706         case 0xc:
 707                 reg->val = vdp_read(sd, reg->reg & 0xff);
 708                 break;
 709         default:
 710                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 711                 adv7604_inv_register(sd);
 712                 break;
 713         }
 714         return 0;
 715 }
 716
 717 static int adv7604_s_register(struct v4l2_subdev *sd,
 718                                         const struct v4l2_dbg_register *reg)
 719 {
 720         switch (reg->reg >> 8) {
 721         case 0:
 722                 io_write(sd, reg->reg & 0xff, reg->val & 0xff);
 723                 break;
 724         case 1:
 725                 avlink_write(sd, reg->reg & 0xff, reg->val & 0xff);
 726                 break;
 727         case 2:
 728                 cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
 729                 break;
 730         case 3:
 731                 infoframe_write(sd, reg->reg & 0xff, reg->val & 0xff);
 732                 break;
 733         case 4:
 734                 esdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 735                 break;
 736         case 5:
 737                 dpp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 738                 break;
 739         case 6:
 740                 afe_write(sd, reg->reg & 0xff, reg->val & 0xff);
 741                 break;
 742         case 7:
 743                 rep_write(sd, reg->reg & 0xff, reg->val & 0xff);
 744                 break;
 745         case 8:
 746                 edid_write(sd, reg->reg & 0xff, reg->val & 0xff);
 747                 break;
 748         case 9:
 749                 hdmi_write(sd, reg->reg & 0xff, reg->val & 0xff);
 750                 break;
 751         case 0xa:
 752                 test_write(sd, reg->reg & 0xff, reg->val & 0xff);
 753                 break;
 754         case 0xb:
 755                 cp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 756                 break;
 757         case 0xc:
 758                 vdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 759                 break;
 760         default:
 761                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 762                 adv7604_inv_register(sd);
 763                 break;
 764         }
 765         return 0;
 766 }
 767 #endif
 768
 769 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 770 {
 771         struct adv7604_state *state = to_state(sd);
 772         u8 reg_io_6f = io_read(sd, 0x6f);
 773
 774         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 775                         ((reg_io_6f & 0x10) >> 4) |
 776                         ((reg_io_6f & 0x08) >> 2) |
 777                         (reg_io_6f & 0x04) |
 778                         ((reg_io_6f & 0x02) << 2));
 779 }
 780
 781 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 782                 u8 prim_mode,
 783                 const struct adv7604_video_standards *predef_vid_timings,
 784                 const struct v4l2_dv_timings *timings)
 785 {
 786         int i;
 787
 788         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 789                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 790                                         is_digital_input(sd) ? 250000 : 1000000))
 791                         continue;
 792                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 793                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 794                                 prim_mode); /* v_freq and prim mode */
 795                 return 0;
 796         }
 797
 798         return -1;
 799 }
 800
 801 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 802                 struct v4l2_dv_timings *timings)
 803 {
 804         struct adv7604_state *state = to_state(sd);
 805         int err;
 806
 807         v4l2_dbg(1, debug, sd, "%s", __func__);
 808
 809         /* reset to default values */
 810         io_write(sd, 0x16, 0x43);
 811         io_write(sd, 0x17, 0x5a);
 812         /* disable embedded syncs for auto graphics mode */
 813         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 814         cp_write(sd, 0x8f, 0x00);
 815         cp_write(sd, 0x90, 0x00);
 816         cp_write(sd, 0xa2, 0x00);
 817         cp_write(sd, 0xa3, 0x00);
 818         cp_write(sd, 0xa4, 0x00);
 819         cp_write(sd, 0xa5, 0x00);
 820         cp_write(sd, 0xa6, 0x00);
 821         cp_write(sd, 0xa7, 0x00);
 822         cp_write(sd, 0xab, 0x00);
 823         cp_write(sd, 0xac, 0x00);
 824
 825         if (is_analog_input(sd)) {
 826                 err = find_and_set_predefined_video_timings(sd,
 827                                 0x01, adv7604_prim_mode_comp, timings);
 828                 if (err)
 829                         err = find_and_set_predefined_video_timings(sd,
 830                                         0x02, adv7604_prim_mode_gr, timings);
 831         } else if (is_digital_input(sd)) {
 832                 err = find_and_set_predefined_video_timings(sd,
 833                                 0x05, adv7604_prim_mode_hdmi_comp, timings);
 834                 if (err)
 835                         err = find_and_set_predefined_video_timings(sd,
 836                                         0x06, adv7604_prim_mode_hdmi_gr, timings);
 837         } else {
 838                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 839                                 __func__, state->selected_input);
 840                 err = -1;
 841         }
 842
 843
 844         return err;
 845 }
 846
 847 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 848                 const struct v4l2_bt_timings *bt)
 849 {
 850         struct adv7604_state *state = to_state(sd);
 851         struct i2c_client *client = v4l2_get_subdevdata(sd);
 852         u32 width = htotal(bt);
 853         u32 height = vtotal(bt);
 854         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 855         u16 cp_start_eav = width - bt->hfrontporch;
 856         u16 cp_start_vbi = height - bt->vfrontporch;
 857         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 858         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 859                 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 860         const u8 pll[2] = {
 861                 0xc0 | ((width >> 8) & 0x1f),
 862                 width & 0xff
 863         };
 864
 865         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 866
 867         if (is_analog_input(sd)) {
 868                 /* auto graphics */
 869                 io_write(sd, 0x00, 0x07); /* video std */
 870                 io_write(sd, 0x01, 0x02); /* prim mode */
 871                 /* enable embedded syncs for auto graphics mode */
 872                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 873
 874                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 875                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 876                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 877                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
 878                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 879
 880                 /* active video - horizontal timing */
 881                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
 882                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
 883                                    ((cp_start_eav >> 8) & 0x0f));
 884                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
 885
 886                 /* active video - vertical timing */
 887                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 888                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 889                                    ((cp_end_vbi >> 8) & 0xf));
 890                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 891         } else if (is_digital_input(sd)) {
 892                 /* set default prim_mode/vid_std for HDMI
 893                    according to [REF_03, c. 4.2] */
 894                 io_write(sd, 0x00, 0x02); /* video std */
 895                 io_write(sd, 0x01, 0x06); /* prim mode */
 896         } else {
 897                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 898                                 __func__, state->selected_input);
 899         }
 900
 901         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
 902         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
 903         cp_write(sd, 0xab, (height >> 4) & 0xff);
 904         cp_write(sd, 0xac, (height & 0x0f) << 4);
 905 }
 906
 907 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
 908 {
 909         struct adv7604_state *state = to_state(sd);
 910
 911         switch (state->rgb_quantization_range) {
 912         case V4L2_DV_RGB_RANGE_AUTO:
 913                 /* automatic */
 914                 if (is_digital_input(sd) && !(hdmi_read(sd, 0x05) & 0x80)) {
 915                         /* receiving DVI-D signal */
 916
 917                         /* ADV7604 selects RGB limited range regardless of
 918                            input format (CE/IT) in automatic mode */
 919                         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 920                                 /* RGB limited range (16-235) */
 921                                 io_write_and_or(sd, 0x02, 0x0f, 0x00);
 922
 923                         } else {
 924                                 /* RGB full range (0-255) */
 925                                 io_write_and_or(sd, 0x02, 0x0f, 0x10);
 926                         }
 927                 } else {
 928                         /* receiving HDMI or analog signal, set automode */
 929                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 930                 }
 931                 break;
 932         case V4L2_DV_RGB_RANGE_LIMITED:
 933                 /* RGB limited range (16-235) */
 934                 io_write_and_or(sd, 0x02, 0x0f, 0x00);
 935                 break;
 936         case V4L2_DV_RGB_RANGE_FULL:
 937                 /* RGB full range (0-255) */
 938                 io_write_and_or(sd, 0x02, 0x0f, 0x10);
 939                 break;
 940         }
 941 }
 942
 943
 944 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
 945 {
 946         struct v4l2_subdev *sd = to_sd(ctrl);
 947         struct adv7604_state *state = to_state(sd);
 948
 949         switch (ctrl->id) {
 950         case V4L2_CID_BRIGHTNESS:
 951                 cp_write(sd, 0x3c, ctrl->val);
 952                 return 0;
 953         case V4L2_CID_CONTRAST:
 954                 cp_write(sd, 0x3a, ctrl->val);
 955                 return 0;
 956         case V4L2_CID_SATURATION:
 957                 cp_write(sd, 0x3b, ctrl->val);
 958                 return 0;
 959         case V4L2_CID_HUE:
 960                 cp_write(sd, 0x3d, ctrl->val);
 961                 return 0;
 962         case  V4L2_CID_DV_RX_RGB_RANGE:
 963                 state->rgb_quantization_range = ctrl->val;
 964                 set_rgb_quantization_range(sd);
 965                 return 0;
 966         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
 967                 /* Set the analog sampling phase. This is needed to find the
 968                    best sampling phase for analog video: an application or
 969                    driver has to try a number of phases and analyze the picture
 970                    quality before settling on the best performing phase. */
 971                 afe_write(sd, 0xc8, ctrl->val);
 972                 return 0;
 973         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
 974                 /* Use the default blue color for free running mode,
 975                    or supply your own. */
 976                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
 977                 return 0;
 978         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
 979                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
 980                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
 981                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
 982                 return 0;
 983         }
 984         return -EINVAL;
 985 }
 986
 987 /* ----------------------------------------------------------------------- */
 988
 989 static inline bool no_power(struct v4l2_subdev *sd)
 990 {
 991         /* Entire chip or CP powered off */
 992         return io_read(sd, 0x0c) & 0x24;
 993 }
 994
 995 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
 996 {
 997         struct adv7604_state *state = to_state(sd);
 998
 999         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1000 }
1001
1002 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1003 {
1004         return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1005 }
1006
1007 static inline bool is_hdmi(struct v4l2_subdev *sd)
1008 {
1009         return hdmi_read(sd, 0x05) & 0x80;
1010 }
1011
1012 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1013 {
1014         /* TODO channel 2 */
1015         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1016 }
1017
1018 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1019 {
1020         /* TODO channel 2 */
1021         return !(cp_read(sd, 0xb1) & 0x80);
1022 }
1023
1024 static inline bool no_signal(struct v4l2_subdev *sd)
1025 {
1026         bool ret;
1027
1028         ret = no_power(sd);
1029
1030         ret |= no_lock_stdi(sd);
1031         ret |= no_lock_sspd(sd);
1032
1033         if (is_digital_input(sd)) {
1034                 ret |= no_lock_tmds(sd);
1035                 ret |= no_signal_tmds(sd);
1036         }
1037
1038         return ret;
1039 }
1040
1041 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1042 {
1043         /* CP has detected a non standard number of lines on the incoming
1044            video compared to what it is configured to receive by s_dv_timings */
1045         return io_read(sd, 0x12) & 0x01;
1046 }
1047
1048 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1049 {
1050         *status = 0;
1051         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1052         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1053         if (no_lock_cp(sd))
1054                 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1055
1056         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1057
1058         return 0;
1059 }
1060
1061 /* ----------------------------------------------------------------------- */
1062
1063 struct stdi_readback {
1064         u16 bl, lcf, lcvs;
1065         u8 hs_pol, vs_pol;
1066         bool interlaced;
1067 };
1068
1069 static int stdi2dv_timings(struct v4l2_subdev *sd,
1070                 struct stdi_readback *stdi,
1071                 struct v4l2_dv_timings *timings)
1072 {
1073         struct adv7604_state *state = to_state(sd);
1074         u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1075         u32 pix_clk;
1076         int i;
1077
1078         for (i = 0; adv7604_timings[i].bt.height; i++) {
1079                 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1080                         continue;
1081                 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1082                         continue;
1083
1084                 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1085
1086                 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1087                     (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1088                         *timings = adv7604_timings[i];
1089                         return 0;
1090                 }
1091         }
1092
1093         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1094                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1095                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1096                         timings))
1097                 return 0;
1098         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1099                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1100                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1101                         state->aspect_ratio, timings))
1102                 return 0;
1103
1104         v4l2_dbg(2, debug, sd,
1105                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1106                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1107                 stdi->hs_pol, stdi->vs_pol);
1108         return -1;
1109 }
1110
1111 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1112 {
1113         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1114                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1115                 return -1;
1116         }
1117
1118         /* read STDI */
1119         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1120         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1121         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1122         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1123
1124         /* read SSPD */
1125         if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1126                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1127                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1128                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1129                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1130         } else {
1131                 stdi->hs_pol = 'x';
1132                 stdi->vs_pol = 'x';
1133         }
1134
1135         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1136                 v4l2_dbg(2, debug, sd,
1137                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1138                 return -1;
1139         }
1140
1141         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1142                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1143                 memset(stdi, 0, sizeof(struct stdi_readback));
1144                 return -1;
1145         }
1146
1147         v4l2_dbg(2, debug, sd,
1148                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1149                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1150                 stdi->hs_pol, stdi->vs_pol,
1151                 stdi->interlaced ? "interlaced" : "progressive");
1152
1153         return 0;
1154 }
1155
1156 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1157                         struct v4l2_enum_dv_timings *timings)
1158 {
1159         if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1160                 return -EINVAL;
1161         memset(timings->reserved, 0, sizeof(timings->reserved));
1162         timings->timings = adv7604_timings[timings->index];
1163         return 0;
1164 }
1165
1166 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1167                         struct v4l2_dv_timings_cap *cap)
1168 {
1169         cap->type = V4L2_DV_BT_656_1120;
1170         cap->bt.max_width = 1920;
1171         cap->bt.max_height = 1200;
1172         cap->bt.min_pixelclock = 25000000;
1173         if (is_digital_input(sd))
1174                 cap->bt.max_pixelclock = 225000000;
1175         else
1176                 cap->bt.max_pixelclock = 170000000;
1177         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1178                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1179         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1180                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1181         return 0;
1182 }
1183
1184 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1185    if the format is listed in adv7604_timings[] */
1186 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1187                 struct v4l2_dv_timings *timings)
1188 {
1189         int i;
1190
1191         for (i = 0; adv7604_timings[i].bt.width; i++) {
1192                 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
1193                                         is_digital_input(sd) ? 250000 : 1000000)) {
1194                         *timings = adv7604_timings[i];
1195                         break;
1196                 }
1197         }
1198 }
1199
1200 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1201                         struct v4l2_dv_timings *timings)
1202 {
1203         struct adv7604_state *state = to_state(sd);
1204         struct v4l2_bt_timings *bt = &timings->bt;
1205         struct stdi_readback stdi;
1206
1207         if (!timings)
1208                 return -EINVAL;
1209
1210         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1211
1212         if (no_signal(sd)) {
1213                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1214                 return -ENOLINK;
1215         }
1216
1217         /* read STDI */
1218         if (read_stdi(sd, &stdi)) {
1219                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1220                 return -ENOLINK;
1221         }
1222         bt->interlaced = stdi.interlaced ?
1223                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1224
1225         if (is_digital_input(sd)) {
1226                 uint32_t freq;
1227
1228                 timings->type = V4L2_DV_BT_656_1120;
1229
1230                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1231                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1232                 freq = (hdmi_read(sd, 0x06) * 1000000) +
1233                         ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1234                 if (is_hdmi(sd)) {
1235                         /* adjust for deep color mode */
1236                         unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1237
1238                         freq = freq * 8 / bits_per_channel;
1239                 }
1240                 bt->pixelclock = freq;
1241                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1242                         hdmi_read(sd, 0x21);
1243                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1244                         hdmi_read(sd, 0x23);
1245                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1246                         hdmi_read(sd, 0x25);
1247                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1248                         hdmi_read(sd, 0x2b)) / 2;
1249                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1250                         hdmi_read(sd, 0x2f)) / 2;
1251                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1252                         hdmi_read(sd, 0x33)) / 2;
1253                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1254                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1255                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1256                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1257                                         hdmi_read(sd, 0x0c);
1258                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1259                                         hdmi_read(sd, 0x2d)) / 2;
1260                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1261                                         hdmi_read(sd, 0x31)) / 2;
1262                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1263                                         hdmi_read(sd, 0x35)) / 2;
1264                 }
1265                 adv7604_fill_optional_dv_timings_fields(sd, timings);
1266         } else {
1267                 /* find format
1268                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1269                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1270                  */
1271                 if (!stdi2dv_timings(sd, &stdi, timings))
1272                         goto found;
1273                 stdi.lcvs += 1;
1274                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1275                 if (!stdi2dv_timings(sd, &stdi, timings))
1276                         goto found;
1277                 stdi.lcvs -= 2;
1278                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1279                 if (stdi2dv_timings(sd, &stdi, timings)) {
1280                         /*
1281                          * The STDI block may measure wrong values, especially
1282                          * for lcvs and lcf. If the driver can not find any
1283                          * valid timing, the STDI block is restarted to measure
1284                          * the video timings again. The function will return an
1285                          * error, but the restart of STDI will generate a new
1286                          * STDI interrupt and the format detection process will
1287                          * restart.
1288                          */
1289                         if (state->restart_stdi_once) {
1290                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1291                                 /* TODO restart STDI for Sync Channel 2 */
1292                                 /* enter one-shot mode */
1293                                 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1294                                 /* trigger STDI restart */
1295                                 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1296                                 /* reset to continuous mode */
1297                                 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1298                                 state->restart_stdi_once = false;
1299                                 return -ENOLINK;
1300                         }
1301                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1302                         return -ERANGE;
1303                 }
1304                 state->restart_stdi_once = true;
1305         }
1306 found:
1307
1308         if (no_signal(sd)) {
1309                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1310                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1311                 return -ENOLINK;
1312         }
1313
1314         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1315                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1316                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1317                                 __func__, (u32)bt->pixelclock);
1318                 return -ERANGE;
1319         }
1320
1321         if (debug > 1)
1322                 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1323                                       timings, true);
1324
1325         return 0;
1326 }
1327
1328 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1329                 struct v4l2_dv_timings *timings)
1330 {
1331         struct adv7604_state *state = to_state(sd);
1332         struct v4l2_bt_timings *bt;
1333         int err;
1334
1335         if (!timings)
1336                 return -EINVAL;
1337
1338         bt = &timings->bt;
1339
1340         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1341                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1342                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1343                                 __func__, (u32)bt->pixelclock);
1344                 return -ERANGE;
1345         }
1346
1347         adv7604_fill_optional_dv_timings_fields(sd, timings);
1348
1349         state->timings = *timings;
1350
1351         cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1352
1353         /* Use prim_mode and vid_std when available */
1354         err = configure_predefined_video_timings(sd, timings);
1355         if (err) {
1356                 /* custom settings when the video format
1357                  does not have prim_mode/vid_std */
1358                 configure_custom_video_timings(sd, bt);
1359         }
1360
1361         set_rgb_quantization_range(sd);
1362
1363
1364         if (debug > 1)
1365                 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1366                                       timings, true);
1367         return 0;
1368 }
1369
1370 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1371                 struct v4l2_dv_timings *timings)
1372 {
1373         struct adv7604_state *state = to_state(sd);
1374
1375         *timings = state->timings;
1376         return 0;
1377 }
1378
1379 static void enable_input(struct v4l2_subdev *sd)
1380 {
1381         struct adv7604_state *state = to_state(sd);
1382
1383         if (is_analog_input(sd)) {
1384                 /* enable */
1385                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1386         } else if (is_digital_input(sd)) {
1387                 /* enable */
1388                 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
1389                 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1390                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1391                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1392         } else {
1393                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1394                                 __func__, state->selected_input);
1395         }
1396 }
1397
1398 static void disable_input(struct v4l2_subdev *sd)
1399 {
1400         /* disable */
1401         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1402         hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1403         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1404 }
1405
1406 static void select_input(struct v4l2_subdev *sd)
1407 {
1408         struct adv7604_state *state = to_state(sd);
1409
1410         if (is_analog_input(sd)) {
1411                 /* reset ADI recommended settings for HDMI: */
1412                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1413                 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1414                 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1415                 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1416                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1417                 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1418                 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1419                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1420                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1421                 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1422                 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1423                 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1424
1425                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1426                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1427                 afe_write(sd, 0xc8, 0x00); /* phase control */
1428
1429                 /* set ADI recommended settings for digitizer */
1430                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1431                 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1432                 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1433                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1434                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1435                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1436         } else if (is_digital_input(sd)) {
1437                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1438
1439                 /* set ADI recommended settings for HDMI: */
1440                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1441                 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1442                 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1443                 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1444                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1445                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1446                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1447                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1448                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1449                 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1450                 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1451                 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1452
1453                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1454                 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1455                 afe_write(sd, 0xc8, 0x40); /* phase control */
1456
1457                 /* reset ADI recommended settings for digitizer */
1458                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1459                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1460                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1461                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1462                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1463                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1464         } else {
1465                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1466                                 __func__, state->selected_input);
1467         }
1468 }
1469
1470 static int adv7604_s_routing(struct v4l2_subdev *sd,
1471                 u32 input, u32 output, u32 config)
1472 {
1473         struct adv7604_state *state = to_state(sd);
1474
1475         v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1476
1477         state->selected_input = input;
1478
1479         disable_input(sd);
1480
1481         select_input(sd);
1482
1483         enable_input(sd);
1484
1485         return 0;
1486 }
1487
1488 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1489                              enum v4l2_mbus_pixelcode *code)
1490 {
1491         if (index)
1492                 return -EINVAL;
1493         /* Good enough for now */
1494         *code = V4L2_MBUS_FMT_FIXED;
1495         return 0;
1496 }
1497
1498 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1499                 struct v4l2_mbus_framefmt *fmt)
1500 {
1501         struct adv7604_state *state = to_state(sd);
1502
1503         fmt->width = state->timings.bt.width;
1504         fmt->height = state->timings.bt.height;
1505         fmt->code = V4L2_MBUS_FMT_FIXED;
1506         fmt->field = V4L2_FIELD_NONE;
1507         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1508                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1509                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1510         }
1511         return 0;
1512 }
1513
1514 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1515 {
1516         struct adv7604_state *state = to_state(sd);
1517         u8 fmt_change, fmt_change_digital, tx_5v;
1518         u32 input_status;
1519
1520         /* format change */
1521         fmt_change = io_read(sd, 0x43) & 0x98;
1522         if (fmt_change)
1523                 io_write(sd, 0x44, fmt_change);
1524         fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0;
1525         if (fmt_change_digital)
1526                 io_write(sd, 0x6c, fmt_change_digital);
1527         if (fmt_change || fmt_change_digital) {
1528                 v4l2_dbg(1, debug, sd,
1529                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1530                         __func__, fmt_change, fmt_change_digital);
1531
1532                 adv7604_g_input_status(sd, &input_status);
1533                 if (input_status != state->prev_input_status) {
1534                         v4l2_dbg(1, debug, sd,
1535                                 "%s: input_status = 0x%x, prev_input_status = 0x%x\n",
1536                                 __func__, input_status, state->prev_input_status);
1537                         state->prev_input_status = input_status;
1538                         v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1539                 }
1540
1541                 if (handled)
1542                         *handled = true;
1543         }
1544         /* tx 5v detect */
1545         tx_5v = io_read(sd, 0x70) & 0x1e;
1546         if (tx_5v) {
1547                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1548                 io_write(sd, 0x71, tx_5v);
1549                 adv7604_s_detect_tx_5v_ctrl(sd);
1550                 if (handled)
1551                         *handled = true;
1552         }
1553         return 0;
1554 }
1555
1556 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1557 {
1558         struct adv7604_state *state = to_state(sd);
1559         u8 *data = NULL;
1560
1561         if (edid->pad > ADV7604_EDID_PORT_D)
1562                 return -EINVAL;
1563         if (edid->blocks == 0)
1564                 return -EINVAL;
1565         if (edid->blocks > 2)
1566                 return -EINVAL;
1567         if (edid->start_block > 1)
1568                 return -EINVAL;
1569         if (edid->start_block == 1)
1570                 edid->blocks = 1;
1571         if (!edid->edid)
1572                 return -EINVAL;
1573
1574         if (edid->blocks > state->edid.blocks)
1575                 edid->blocks = state->edid.blocks;
1576
1577         switch (edid->pad) {
1578         case ADV7604_EDID_PORT_A:
1579         case ADV7604_EDID_PORT_B:
1580         case ADV7604_EDID_PORT_C:
1581         case ADV7604_EDID_PORT_D:
1582                 if (state->edid.present & (1 << edid->pad))
1583                         data = state->edid.edid;
1584                 break;
1585         default:
1586                 return -EINVAL;
1587                 break;
1588         }
1589         if (!data)
1590                 return -ENODATA;
1591
1592         memcpy(edid->edid,
1593                data + edid->start_block * 128,
1594                edid->blocks * 128);
1595         return 0;
1596 }
1597
1598 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1599 {
1600         struct adv7604_state *state = to_state(sd);
1601         int err;
1602
1603         if (edid->pad > ADV7604_EDID_PORT_D)
1604                 return -EINVAL;
1605         if (edid->start_block != 0)
1606                 return -EINVAL;
1607         if (edid->blocks == 0) {
1608                 /* Pull down the hotplug pin */
1609                 state->edid.present &= ~(1 << edid->pad);
1610                 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
1611                 /* Disables I2C access to internal EDID ram from DDC port */
1612                 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
1613                 state->edid.blocks = 0;
1614                 /* Fall back to a 16:9 aspect ratio */
1615                 state->aspect_ratio.numerator = 16;
1616                 state->aspect_ratio.denominator = 9;
1617                 v4l2_dbg(2, debug, sd, "%s: clear edid\n", __func__);
1618                 return 0;
1619         }
1620         if (edid->blocks > 2) {
1621                 edid->blocks = 2;
1622                 return -E2BIG;
1623         }
1624         if (!edid->edid)
1625                 return -EINVAL;
1626
1627         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
1628         state->edid.present &= ~(1 << edid->pad);
1629         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
1630
1631         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1632         state->edid.blocks = edid->blocks;
1633         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1634                         edid->edid[0x16]);
1635         state->edid.present |= edid->pad;
1636
1637         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1638         if (err < 0) {
1639                 v4l2_err(sd, "error %d writing edid\n", err);
1640                 return err;
1641         }
1642
1643         /* enable hotplug after 100 ms */
1644         queue_delayed_work(state->work_queues,
1645                         &state->delayed_work_enable_hotplug, HZ / 10);
1646         return 0;
1647 }
1648
1649 /*********** avi info frame CEA-861-E **************/
1650
1651 static void print_avi_infoframe(struct v4l2_subdev *sd)
1652 {
1653         int i;
1654         u8 buf[14];
1655         u8 avi_len;
1656         u8 avi_ver;
1657
1658         if (!is_hdmi(sd)) {
1659                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1660                 return;
1661         }
1662         if (!(io_read(sd, 0x60) & 0x01)) {
1663                 v4l2_info(sd, "AVI infoframe not received\n");
1664                 return;
1665         }
1666
1667         if (io_read(sd, 0x83) & 0x01) {
1668                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1669                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1670                 if (io_read(sd, 0x83) & 0x01) {
1671                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
1672                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1673                 }
1674         }
1675
1676         avi_len = infoframe_read(sd, 0xe2);
1677         avi_ver = infoframe_read(sd, 0xe1);
1678         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1679                         avi_ver, avi_len);
1680
1681         if (avi_ver != 0x02)
1682                 return;
1683
1684         for (i = 0; i < 14; i++)
1685                 buf[i] = infoframe_read(sd, i);
1686
1687         v4l2_info(sd,
1688                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1689                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1690                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1691 }
1692
1693 static int adv7604_log_status(struct v4l2_subdev *sd)
1694 {
1695         struct adv7604_state *state = to_state(sd);
1696         struct v4l2_dv_timings timings;
1697         struct stdi_readback stdi;
1698         u8 reg_io_0x02 = io_read(sd, 0x02);
1699
1700         char *csc_coeff_sel_rb[16] = {
1701                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1702                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1703                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1704                 "reserved", "reserved", "reserved", "reserved", "manual"
1705         };
1706         char *input_color_space_txt[16] = {
1707                 "RGB limited range (16-235)", "RGB full range (0-255)",
1708                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1709                 "XvYCC Bt.601", "XvYCC Bt.709",
1710                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1711                 "invalid", "invalid", "invalid", "invalid", "invalid",
1712                 "invalid", "invalid", "automatic"
1713         };
1714         char *rgb_quantization_range_txt[] = {
1715                 "Automatic",
1716                 "RGB limited range (16-235)",
1717                 "RGB full range (0-255)",
1718         };
1719         char *deep_color_mode_txt[4] = {
1720                 "8-bits per channel",
1721                 "10-bits per channel",
1722                 "12-bits per channel",
1723                 "16-bits per channel (not supported)"
1724         };
1725
1726         v4l2_info(sd, "-----Chip status-----\n");
1727         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1728         v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
1729                         "HDMI" : (is_digital_input(sd) ? "DVI-D" : "DVI-A"));
1730         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1731                         ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1732                         ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1733                         ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1734                         ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
1735         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1736                         "enabled" : "disabled");
1737
1738         v4l2_info(sd, "-----Signal status-----\n");
1739         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1740                         ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1741                         ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1742                         ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1743                         ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
1744         v4l2_info(sd, "TMDS signal detected: %s\n",
1745                         no_signal_tmds(sd) ? "false" : "true");
1746         v4l2_info(sd, "TMDS signal locked: %s\n",
1747                         no_lock_tmds(sd) ? "false" : "true");
1748         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1749         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1750         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1751         v4l2_info(sd, "CP free run: %s\n",
1752                         (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1753         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1754                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1755                         (io_read(sd, 0x01) & 0x70) >> 4);
1756
1757         v4l2_info(sd, "-----Video Timings-----\n");
1758         if (read_stdi(sd, &stdi))
1759                 v4l2_info(sd, "STDI: not locked\n");
1760         else
1761                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1762                                 stdi.lcf, stdi.bl, stdi.lcvs,
1763                                 stdi.interlaced ? "interlaced" : "progressive",
1764                                 stdi.hs_pol, stdi.vs_pol);
1765         if (adv7604_query_dv_timings(sd, &timings))
1766                 v4l2_info(sd, "No video detected\n");
1767         else
1768                 v4l2_print_dv_timings(sd->name, "Detected format: ",
1769                                       &timings, true);
1770         v4l2_print_dv_timings(sd->name, "Configured format: ",
1771                               &state->timings, true);
1772
1773         if (no_signal(sd))
1774                 return 0;
1775
1776         v4l2_info(sd, "-----Color space-----\n");
1777         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1778                         rgb_quantization_range_txt[state->rgb_quantization_range]);
1779         v4l2_info(sd, "Input color space: %s\n",
1780                         input_color_space_txt[reg_io_0x02 >> 4]);
1781         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1782                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1783                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1784                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1785                                 "enabled" : "disabled");
1786         v4l2_info(sd, "Color space conversion: %s\n",
1787                         csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1788
1789         if (!is_digital_input(sd))
1790                 return 0;
1791
1792         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1793         v4l2_info(sd, "Digital video port selected: %c\n",
1794                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
1795         v4l2_info(sd, "HDCP encrypted content: %s\n",
1796                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
1797         v4l2_info(sd, "HDCP keys read: %s%s\n",
1798                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1799                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1800         if (!is_hdmi(sd)) {
1801                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1802                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1803                 bool audio_mute = io_read(sd, 0x65) & 0x40;
1804
1805                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1806                                 audio_pll_locked ? "locked" : "not locked",
1807                                 audio_sample_packet_detect ? "detected" : "not detected",
1808                                 audio_mute ? "muted" : "enabled");
1809                 if (audio_pll_locked && audio_sample_packet_detect) {
1810                         v4l2_info(sd, "Audio format: %s\n",
1811                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1812                 }
1813                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1814                                 (hdmi_read(sd, 0x5c) << 8) +
1815                                 (hdmi_read(sd, 0x5d) & 0xf0));
1816                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
1817                                 (hdmi_read(sd, 0x5e) << 8) +
1818                                 hdmi_read(sd, 0x5f));
1819                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
1820
1821                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
1822
1823                 print_avi_infoframe(sd);
1824         }
1825
1826         return 0;
1827 }
1828
1829 /* ----------------------------------------------------------------------- */
1830
1831 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1832         .s_ctrl = adv7604_s_ctrl,
1833 };
1834
1835 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1836         .log_status = adv7604_log_status,
1837         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1838         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1839         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1840         .g_ctrl = v4l2_subdev_g_ctrl,
1841         .s_ctrl = v4l2_subdev_s_ctrl,
1842         .queryctrl = v4l2_subdev_queryctrl,
1843         .querymenu = v4l2_subdev_querymenu,
1844         .interrupt_service_routine = adv7604_isr,
1845 #ifdef CONFIG_VIDEO_ADV_DEBUG
1846         .g_register = adv7604_g_register,
1847         .s_register = adv7604_s_register,
1848 #endif
1849 };
1850
1851 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1852         .s_routing = adv7604_s_routing,
1853         .g_input_status = adv7604_g_input_status,
1854         .s_dv_timings = adv7604_s_dv_timings,
1855         .g_dv_timings = adv7604_g_dv_timings,
1856         .query_dv_timings = adv7604_query_dv_timings,
1857         .enum_dv_timings = adv7604_enum_dv_timings,
1858         .dv_timings_cap = adv7604_dv_timings_cap,
1859         .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1860         .g_mbus_fmt = adv7604_g_mbus_fmt,
1861         .try_mbus_fmt = adv7604_g_mbus_fmt,
1862         .s_mbus_fmt = adv7604_g_mbus_fmt,
1863 };
1864
1865 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1866         .get_edid = adv7604_get_edid,
1867         .set_edid = adv7604_set_edid,
1868 };
1869
1870 static const struct v4l2_subdev_ops adv7604_ops = {
1871         .core = &adv7604_core_ops,
1872         .video = &adv7604_video_ops,
1873         .pad = &adv7604_pad_ops,
1874 };
1875
1876 /* -------------------------- custom ctrls ---------------------------------- */
1877
1878 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1879         .ops = &adv7604_ctrl_ops,
1880         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1881         .name = "Analog Sampling Phase",
1882         .type = V4L2_CTRL_TYPE_INTEGER,
1883         .min = 0,
1884         .max = 0x1f,
1885         .step = 1,
1886         .def = 0,
1887 };
1888
1889 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1890         .ops = &adv7604_ctrl_ops,
1891         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1892         .name = "Free Running Color, Manual",
1893         .type = V4L2_CTRL_TYPE_BOOLEAN,
1894         .min = false,
1895         .max = true,
1896         .step = 1,
1897         .def = false,
1898 };
1899
1900 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1901         .ops = &adv7604_ctrl_ops,
1902         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1903         .name = "Free Running Color",
1904         .type = V4L2_CTRL_TYPE_INTEGER,
1905         .min = 0x0,
1906         .max = 0xffffff,
1907         .step = 0x1,
1908         .def = 0x0,
1909 };
1910
1911 /* ----------------------------------------------------------------------- */
1912
1913 static int adv7604_core_init(struct v4l2_subdev *sd)
1914 {
1915         struct adv7604_state *state = to_state(sd);
1916         struct adv7604_platform_data *pdata = &state->pdata;
1917
1918         hdmi_write(sd, 0x48,
1919                 (pdata->disable_pwrdnb ? 0x80 : 0) |
1920                 (pdata->disable_cable_det_rst ? 0x40 : 0));
1921
1922         disable_input(sd);
1923
1924         /* power */
1925         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
1926         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
1927         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
1928
1929         /* video format */
1930         io_write_and_or(sd, 0x02, 0xf0,
1931                         pdata->alt_gamma << 3 |
1932                         pdata->op_656_range << 2 |
1933                         pdata->rgb_out << 1 |
1934                         pdata->alt_data_sat << 0);
1935         io_write(sd, 0x03, pdata->op_format_sel);
1936         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1937         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1938                                         pdata->insert_av_codes << 2 |
1939                                         pdata->replicate_av_codes << 1 |
1940                                         pdata->invert_cbcr << 0);
1941
1942         /* TODO from platform data */
1943         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
1944         io_write(sd, 0x06, 0xa6);   /* positive VS and HS */
1945         io_write(sd, 0x14, 0x7f);   /* Drive strength adjusted to max */
1946         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1947         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1948         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
1949                                       ADI recommended setting [REF_01, c. 2.3.3] */
1950         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
1951                                       ADI recommended setting [REF_01, c. 2.3.3] */
1952         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1953                                      for digital formats */
1954         rep_write(sd, 0x76, 0xc0); /* SPA location for port B, C and D */
1955
1956         /* TODO from platform data */
1957         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
1958
1959         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1960         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1961
1962         /* interrupts */
1963         io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1964         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1965         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1966         io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1967         io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
1968
1969         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
1970 }
1971
1972 static void adv7604_unregister_clients(struct adv7604_state *state)
1973 {
1974         if (state->i2c_avlink)
1975                 i2c_unregister_device(state->i2c_avlink);
1976         if (state->i2c_cec)
1977                 i2c_unregister_device(state->i2c_cec);
1978         if (state->i2c_infoframe)
1979                 i2c_unregister_device(state->i2c_infoframe);
1980         if (state->i2c_esdp)
1981                 i2c_unregister_device(state->i2c_esdp);
1982         if (state->i2c_dpp)
1983                 i2c_unregister_device(state->i2c_dpp);
1984         if (state->i2c_afe)
1985                 i2c_unregister_device(state->i2c_afe);
1986         if (state->i2c_repeater)
1987                 i2c_unregister_device(state->i2c_repeater);
1988         if (state->i2c_edid)
1989                 i2c_unregister_device(state->i2c_edid);
1990         if (state->i2c_hdmi)
1991                 i2c_unregister_device(state->i2c_hdmi);
1992         if (state->i2c_test)
1993                 i2c_unregister_device(state->i2c_test);
1994         if (state->i2c_cp)
1995                 i2c_unregister_device(state->i2c_cp);
1996         if (state->i2c_vdp)
1997                 i2c_unregister_device(state->i2c_vdp);
1998 }
1999
2000 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2001                                                         u8 addr, u8 io_reg)
2002 {
2003         struct i2c_client *client = v4l2_get_subdevdata(sd);
2004
2005         if (addr)
2006                 io_write(sd, io_reg, addr << 1);
2007         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2008 }
2009
2010 static int adv7604_probe(struct i2c_client *client,
2011                          const struct i2c_device_id *id)
2012 {
2013         struct adv7604_state *state;
2014         struct adv7604_platform_data *pdata = client->dev.platform_data;
2015         struct v4l2_ctrl_handler *hdl;
2016         struct v4l2_subdev *sd;
2017         int err;
2018
2019         /* Check if the adapter supports the needed features */
2020         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2021                 return -EIO;
2022         v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2023                         client->addr << 1);
2024
2025         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2026         if (!state) {
2027                 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2028                 return -ENOMEM;
2029         }
2030
2031         /* initialize variables */
2032         state->restart_stdi_once = true;
2033         state->prev_input_status = ~0;
2034
2035         /* platform data */
2036         if (!pdata) {
2037                 v4l_err(client, "No platform data!\n");
2038                 return -ENODEV;
2039         }
2040         memcpy(&state->pdata, pdata, sizeof(state->pdata));
2041
2042         sd = &state->sd;
2043         v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2044         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2045         state->connector_hdmi = pdata->connector_hdmi;
2046
2047         /* i2c access to adv7604? */
2048         if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2049                 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2050                                 client->addr << 1);
2051                 return -ENODEV;
2052         }
2053
2054         /* control handlers */
2055         hdl = &state->hdl;
2056         v4l2_ctrl_handler_init(hdl, 9);
2057
2058         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2059                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2060         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2061                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
2062         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2063                         V4L2_CID_SATURATION, 0, 255, 1, 128);
2064         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2065                         V4L2_CID_HUE, 0, 128, 1, 0);
2066
2067         /* private controls */
2068         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2069                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
2070         state->rgb_quantization_range_ctrl =
2071                 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2072                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2073                         0, V4L2_DV_RGB_RANGE_AUTO);
2074
2075         /* custom controls */
2076         state->analog_sampling_phase_ctrl =
2077                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2078         state->free_run_color_manual_ctrl =
2079                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2080         state->free_run_color_ctrl =
2081                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2082
2083         sd->ctrl_handler = hdl;
2084         if (hdl->error) {
2085                 err = hdl->error;
2086                 goto err_hdl;
2087         }
2088         state->detect_tx_5v_ctrl->is_private = true;
2089         state->rgb_quantization_range_ctrl->is_private = true;
2090         state->analog_sampling_phase_ctrl->is_private = true;
2091         state->free_run_color_manual_ctrl->is_private = true;
2092         state->free_run_color_ctrl->is_private = true;
2093
2094         if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2095                 err = -ENODEV;
2096                 goto err_hdl;
2097         }
2098
2099         state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2100         state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2101         state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2102         state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2103         state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2104         state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2105         state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2106         state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2107         state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2108         state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2109         state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2110         state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2111         if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2112             !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2113             !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2114             !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2115                 err = -ENOMEM;
2116                 v4l2_err(sd, "failed to create all i2c clients\n");
2117                 goto err_i2c;
2118         }
2119
2120         /* work queues */
2121         state->work_queues = create_singlethread_workqueue(client->name);
2122         if (!state->work_queues) {
2123                 v4l2_err(sd, "Could not create work queue\n");
2124                 err = -ENOMEM;
2125                 goto err_i2c;
2126         }
2127
2128         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2129                         adv7604_delayed_work_enable_hotplug);
2130
2131         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2132         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2133         if (err)
2134                 goto err_work_queues;
2135
2136         err = adv7604_core_init(sd);
2137         if (err)
2138                 goto err_entity;
2139         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2140                         client->addr << 1, client->adapter->name);
2141         return 0;
2142
2143 err_entity:
2144         media_entity_cleanup(&sd->entity);
2145 err_work_queues:
2146         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2147         destroy_workqueue(state->work_queues);
2148 err_i2c:
2149         adv7604_unregister_clients(state);
2150 err_hdl:
2151         v4l2_ctrl_handler_free(hdl);
2152         return err;
2153 }
2154
2155 /* ----------------------------------------------------------------------- */
2156
2157 static int adv7604_remove(struct i2c_client *client)
2158 {
2159         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2160         struct adv7604_state *state = to_state(sd);
2161
2162         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2163         destroy_workqueue(state->work_queues);
2164         v4l2_device_unregister_subdev(sd);
2165         media_entity_cleanup(&sd->entity);
2166         adv7604_unregister_clients(to_state(sd));
2167         v4l2_ctrl_handler_free(sd->ctrl_handler);
2168         return 0;
2169 }
2170
2171 /* ----------------------------------------------------------------------- */
2172
2173 static struct i2c_device_id adv7604_id[] = {
2174         { "adv7604", 0 },
2175         { }
2176 };
2177 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2178
2179 static struct i2c_driver adv7604_driver = {
2180         .driver = {
2181                 .owner = THIS_MODULE,
2182                 .name = "adv7604",
2183         },
2184         .probe = adv7604_probe,
2185         .remove = adv7604_remove,
2186         .id_table = adv7604_id,
2187 };
2188
2189 module_i2c_driver(adv7604_driver);