drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/i2c.h>
  35 #include <linux/delay.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <media/v4l2-device.h>
  40 #include <media/v4l2-ctrls.h>
  41 #include <media/v4l2-dv-timings.h>
  42 #include <media/adv7604.h>
  43
  44 static int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "debug level (0-2)");
  47
  48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  51 MODULE_LICENSE("GPL");
  52
  53 /* ADV7604 system clock frequency */
  54 #define ADV7604_fsc (28636360)
  55
  56 #define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI)
  57
  58 /*
  59  **********************************************************************
  60  *
  61  *  Arrays with configuration parameters for the ADV7604
  62  *
  63  **********************************************************************
  64  */
  65 struct adv7604_state {
  66         struct adv7604_platform_data pdata;
  67         struct v4l2_subdev sd;
  68         struct media_pad pad;
  69         struct v4l2_ctrl_handler hdl;
  70         enum adv7604_mode mode;
  71         struct v4l2_dv_timings timings;
  72         u8 edid[256];
  73         unsigned edid_blocks;
  74         struct v4l2_fract aspect_ratio;
  75         u32 rgb_quantization_range;
  76         struct workqueue_struct *work_queues;
  77         struct delayed_work delayed_work_enable_hotplug;
  78         bool connector_hdmi;
  79         bool restart_stdi_once;
  80         u32 prev_input_status;
  81
  82         /* i2c clients */
  83         struct i2c_client *i2c_avlink;
  84         struct i2c_client *i2c_cec;
  85         struct i2c_client *i2c_infoframe;
  86         struct i2c_client *i2c_esdp;
  87         struct i2c_client *i2c_dpp;
  88         struct i2c_client *i2c_afe;
  89         struct i2c_client *i2c_repeater;
  90         struct i2c_client *i2c_edid;
  91         struct i2c_client *i2c_hdmi;
  92         struct i2c_client *i2c_test;
  93         struct i2c_client *i2c_cp;
  94         struct i2c_client *i2c_vdp;
  95
  96         /* controls */
  97         struct v4l2_ctrl *detect_tx_5v_ctrl;
  98         struct v4l2_ctrl *analog_sampling_phase_ctrl;
  99         struct v4l2_ctrl *free_run_color_manual_ctrl;
 100         struct v4l2_ctrl *free_run_color_ctrl;
 101         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 102 };
 103
 104 /* Supported CEA and DMT timings */
 105 static const struct v4l2_dv_timings adv7604_timings[] = {
 106         V4L2_DV_BT_CEA_720X480P59_94,
 107         V4L2_DV_BT_CEA_720X576P50,
 108         V4L2_DV_BT_CEA_1280X720P24,
 109         V4L2_DV_BT_CEA_1280X720P25,
 110         V4L2_DV_BT_CEA_1280X720P50,
 111         V4L2_DV_BT_CEA_1280X720P60,
 112         V4L2_DV_BT_CEA_1920X1080P24,
 113         V4L2_DV_BT_CEA_1920X1080P25,
 114         V4L2_DV_BT_CEA_1920X1080P30,
 115         V4L2_DV_BT_CEA_1920X1080P50,
 116         V4L2_DV_BT_CEA_1920X1080P60,
 117
 118         /* sorted by DMT ID */
 119         V4L2_DV_BT_DMT_640X350P85,
 120         V4L2_DV_BT_DMT_640X400P85,
 121         V4L2_DV_BT_DMT_720X400P85,
 122         V4L2_DV_BT_DMT_640X480P60,
 123         V4L2_DV_BT_DMT_640X480P72,
 124         V4L2_DV_BT_DMT_640X480P75,
 125         V4L2_DV_BT_DMT_640X480P85,
 126         V4L2_DV_BT_DMT_800X600P56,
 127         V4L2_DV_BT_DMT_800X600P60,
 128         V4L2_DV_BT_DMT_800X600P72,
 129         V4L2_DV_BT_DMT_800X600P75,
 130         V4L2_DV_BT_DMT_800X600P85,
 131         V4L2_DV_BT_DMT_848X480P60,
 132         V4L2_DV_BT_DMT_1024X768P60,
 133         V4L2_DV_BT_DMT_1024X768P70,
 134         V4L2_DV_BT_DMT_1024X768P75,
 135         V4L2_DV_BT_DMT_1024X768P85,
 136         V4L2_DV_BT_DMT_1152X864P75,
 137         V4L2_DV_BT_DMT_1280X768P60_RB,
 138         V4L2_DV_BT_DMT_1280X768P60,
 139         V4L2_DV_BT_DMT_1280X768P75,
 140         V4L2_DV_BT_DMT_1280X768P85,
 141         V4L2_DV_BT_DMT_1280X800P60_RB,
 142         V4L2_DV_BT_DMT_1280X800P60,
 143         V4L2_DV_BT_DMT_1280X800P75,
 144         V4L2_DV_BT_DMT_1280X800P85,
 145         V4L2_DV_BT_DMT_1280X960P60,
 146         V4L2_DV_BT_DMT_1280X960P85,
 147         V4L2_DV_BT_DMT_1280X1024P60,
 148         V4L2_DV_BT_DMT_1280X1024P75,
 149         V4L2_DV_BT_DMT_1280X1024P85,
 150         V4L2_DV_BT_DMT_1360X768P60,
 151         V4L2_DV_BT_DMT_1400X1050P60_RB,
 152         V4L2_DV_BT_DMT_1400X1050P60,
 153         V4L2_DV_BT_DMT_1400X1050P75,
 154         V4L2_DV_BT_DMT_1400X1050P85,
 155         V4L2_DV_BT_DMT_1440X900P60_RB,
 156         V4L2_DV_BT_DMT_1440X900P60,
 157         V4L2_DV_BT_DMT_1600X1200P60,
 158         V4L2_DV_BT_DMT_1680X1050P60_RB,
 159         V4L2_DV_BT_DMT_1680X1050P60,
 160         V4L2_DV_BT_DMT_1792X1344P60,
 161         V4L2_DV_BT_DMT_1856X1392P60,
 162         V4L2_DV_BT_DMT_1920X1200P60_RB,
 163         V4L2_DV_BT_DMT_1366X768P60,
 164         V4L2_DV_BT_DMT_1920X1080P60,
 165         { },
 166 };
 167
 168 struct adv7604_video_standards {
 169         struct v4l2_dv_timings timings;
 170         u8 vid_std;
 171         u8 v_freq;
 172 };
 173
 174 /* sorted by number of lines */
 175 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
 176         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 177         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 178         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 179         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 180         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 181         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 182         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 183         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 184         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 185         /* TODO add 1920x1080P60_RB (CVT timing) */
 186         { },
 187 };
 188
 189 /* sorted by number of lines */
 190 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
 191         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 192         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 193         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 194         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 195         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 196         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 199         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 200         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 201         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 203         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 204         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 205         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 206         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 207         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 208         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 209         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 210         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 211         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 212         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 213         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 214         { },
 215 };
 216
 217 /* sorted by number of lines */
 218 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
 219         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 220         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 221         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 222         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 223         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 224         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 225         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 226         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 227         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 228         { },
 229 };
 230
 231 /* sorted by number of lines */
 232 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
 233         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 234         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 235         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 236         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 237         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 238         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 239         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 240         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 241         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 242         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 243         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 244         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 245         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 246         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 247         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 248         { },
 249 };
 250
 251 /* ----------------------------------------------------------------------- */
 252
 253 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
 254 {
 255         return container_of(sd, struct adv7604_state, sd);
 256 }
 257
 258 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 259 {
 260         return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
 261 }
 262
 263 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 264 {
 265         return V4L2_DV_BT_BLANKING_WIDTH(t);
 266 }
 267
 268 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 269 {
 270         return V4L2_DV_BT_FRAME_WIDTH(t);
 271 }
 272
 273 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 274 {
 275         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 276 }
 277
 278 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 279 {
 280         return V4L2_DV_BT_FRAME_HEIGHT(t);
 281 }
 282
 283 /* ----------------------------------------------------------------------- */
 284
 285 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 286                 u8 command, bool check)
 287 {
 288         union i2c_smbus_data data;
 289
 290         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 291                         I2C_SMBUS_READ, command,
 292                         I2C_SMBUS_BYTE_DATA, &data))
 293                 return data.byte;
 294         if (check)
 295                 v4l_err(client, "error reading %02x, %02x\n",
 296                                 client->addr, command);
 297         return -EIO;
 298 }
 299
 300 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 301 {
 302         return adv_smbus_read_byte_data_check(client, command, true);
 303 }
 304
 305 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 306                                         u8 command, u8 value)
 307 {
 308         union i2c_smbus_data data;
 309         int err;
 310         int i;
 311
 312         data.byte = value;
 313         for (i = 0; i < 3; i++) {
 314                 err = i2c_smbus_xfer(client->adapter, client->addr,
 315                                 client->flags,
 316                                 I2C_SMBUS_WRITE, command,
 317                                 I2C_SMBUS_BYTE_DATA, &data);
 318                 if (!err)
 319                         break;
 320         }
 321         if (err < 0)
 322                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 323                                 client->addr, command, value);
 324         return err;
 325 }
 326
 327 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 328                u8 command, unsigned length, const u8 *values)
 329 {
 330         union i2c_smbus_data data;
 331
 332         if (length > I2C_SMBUS_BLOCK_MAX)
 333                 length = I2C_SMBUS_BLOCK_MAX;
 334         data.block[0] = length;
 335         memcpy(data.block + 1, values, length);
 336         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 337                               I2C_SMBUS_WRITE, command,
 338                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 339 }
 340
 341 /* ----------------------------------------------------------------------- */
 342
 343 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 344 {
 345         struct i2c_client *client = v4l2_get_subdevdata(sd);
 346
 347         return adv_smbus_read_byte_data(client, reg);
 348 }
 349
 350 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 351 {
 352         struct i2c_client *client = v4l2_get_subdevdata(sd);
 353
 354         return adv_smbus_write_byte_data(client, reg, val);
 355 }
 356
 357 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 358 {
 359         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 360 }
 361
 362 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 363 {
 364         struct adv7604_state *state = to_state(sd);
 365
 366         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 367 }
 368
 369 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 370 {
 371         struct adv7604_state *state = to_state(sd);
 372
 373         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 374 }
 375
 376 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 377 {
 378         struct adv7604_state *state = to_state(sd);
 379
 380         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 381 }
 382
 383 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 384 {
 385         struct adv7604_state *state = to_state(sd);
 386
 387         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 388 }
 389
 390 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 391 {
 392         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 393 }
 394
 395 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 396 {
 397         struct adv7604_state *state = to_state(sd);
 398
 399         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 400 }
 401
 402 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 403 {
 404         struct adv7604_state *state = to_state(sd);
 405
 406         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 407 }
 408
 409 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
 410 {
 411         struct adv7604_state *state = to_state(sd);
 412
 413         return adv_smbus_read_byte_data(state->i2c_esdp, reg);
 414 }
 415
 416 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 417 {
 418         struct adv7604_state *state = to_state(sd);
 419
 420         return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
 421 }
 422
 423 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
 424 {
 425         struct adv7604_state *state = to_state(sd);
 426
 427         return adv_smbus_read_byte_data(state->i2c_dpp, reg);
 428 }
 429
 430 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 431 {
 432         struct adv7604_state *state = to_state(sd);
 433
 434         return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
 435 }
 436
 437 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 438 {
 439         struct adv7604_state *state = to_state(sd);
 440
 441         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 442 }
 443
 444 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 445 {
 446         struct adv7604_state *state = to_state(sd);
 447
 448         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 449 }
 450
 451 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 452 {
 453         struct adv7604_state *state = to_state(sd);
 454
 455         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 456 }
 457
 458 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 459 {
 460         struct adv7604_state *state = to_state(sd);
 461
 462         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 463 }
 464
 465 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 466 {
 467         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 468 }
 469
 470 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 471 {
 472         struct adv7604_state *state = to_state(sd);
 473
 474         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 475 }
 476
 477 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 478 {
 479         struct adv7604_state *state = to_state(sd);
 480
 481         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 482 }
 483
 484 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
 485 {
 486         struct adv7604_state *state = to_state(sd);
 487         struct i2c_client *client = state->i2c_edid;
 488         u8 msgbuf0[1] = { 0 };
 489         u8 msgbuf1[256];
 490         struct i2c_msg msg[2] = {
 491                 {
 492                         .addr = client->addr,
 493                         .len = 1,
 494                         .buf = msgbuf0
 495                 },
 496                 {
 497                         .addr = client->addr,
 498                         .flags = I2C_M_RD,
 499                         .len = len,
 500                         .buf = msgbuf1
 501                 },
 502         };
 503
 504         if (i2c_transfer(client->adapter, msg, 2) < 0)
 505                 return -EIO;
 506         memcpy(val, msgbuf1, len);
 507         return 0;
 508 }
 509
 510 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
 511 {
 512         struct delayed_work *dwork = to_delayed_work(work);
 513         struct adv7604_state *state = container_of(dwork, struct adv7604_state,
 514                                                 delayed_work_enable_hotplug);
 515         struct v4l2_subdev *sd = &state->sd;
 516
 517         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 518
 519         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)1);
 520 }
 521
 522 static inline int edid_write_block(struct v4l2_subdev *sd,
 523                                         unsigned len, const u8 *val)
 524 {
 525         struct i2c_client *client = v4l2_get_subdevdata(sd);
 526         struct adv7604_state *state = to_state(sd);
 527         int err = 0;
 528         int i;
 529
 530         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 531
 532         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
 533
 534         /* Disables I2C access to internal EDID ram from DDC port */
 535         rep_write_and_or(sd, 0x77, 0xf0, 0x0);
 536
 537         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 538                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 539                                 I2C_SMBUS_BLOCK_MAX, val + i);
 540         if (err)
 541                 return err;
 542
 543         /* adv7604 calculates the checksums and enables I2C access to internal
 544            EDID ram from DDC port. */
 545         rep_write_and_or(sd, 0x77, 0xf0, 0x1);
 546
 547         for (i = 0; i < 1000; i++) {
 548                 if (rep_read(sd, 0x7d) & 1)
 549                         break;
 550                 mdelay(1);
 551         }
 552         if (i == 1000) {
 553                 v4l_err(client, "error enabling edid\n");
 554                 return -EIO;
 555         }
 556
 557         /* enable hotplug after 100 ms */
 558         queue_delayed_work(state->work_queues,
 559                         &state->delayed_work_enable_hotplug, HZ / 10);
 560         return 0;
 561 }
 562
 563 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 564 {
 565         struct adv7604_state *state = to_state(sd);
 566
 567         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 568 }
 569
 570 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 571 {
 572         struct adv7604_state *state = to_state(sd);
 573
 574         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 575 }
 576
 577 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
 578 {
 579         struct adv7604_state *state = to_state(sd);
 580
 581         return adv_smbus_read_byte_data(state->i2c_test, reg);
 582 }
 583
 584 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 585 {
 586         struct adv7604_state *state = to_state(sd);
 587
 588         return adv_smbus_write_byte_data(state->i2c_test, reg, val);
 589 }
 590
 591 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 592 {
 593         struct adv7604_state *state = to_state(sd);
 594
 595         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 596 }
 597
 598 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 599 {
 600         struct adv7604_state *state = to_state(sd);
 601
 602         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 603 }
 604
 605 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 606 {
 607         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 608 }
 609
 610 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 611 {
 612         struct adv7604_state *state = to_state(sd);
 613
 614         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 615 }
 616
 617 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 618 {
 619         struct adv7604_state *state = to_state(sd);
 620
 621         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 622 }
 623
 624 /* ----------------------------------------------------------------------- */
 625
 626 #ifdef CONFIG_VIDEO_ADV_DEBUG
 627 static void adv7604_inv_register(struct v4l2_subdev *sd)
 628 {
 629         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 630         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 631         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 632         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 633         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 634         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 635         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 636         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 637         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 638         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 639         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 640         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 641         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 642 }
 643
 644 static int adv7604_g_register(struct v4l2_subdev *sd,
 645                                         struct v4l2_dbg_register *reg)
 646 {
 647         reg->size = 1;
 648         switch (reg->reg >> 8) {
 649         case 0:
 650                 reg->val = io_read(sd, reg->reg & 0xff);
 651                 break;
 652         case 1:
 653                 reg->val = avlink_read(sd, reg->reg & 0xff);
 654                 break;
 655         case 2:
 656                 reg->val = cec_read(sd, reg->reg & 0xff);
 657                 break;
 658         case 3:
 659                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 660                 break;
 661         case 4:
 662                 reg->val = esdp_read(sd, reg->reg & 0xff);
 663                 break;
 664         case 5:
 665                 reg->val = dpp_read(sd, reg->reg & 0xff);
 666                 break;
 667         case 6:
 668                 reg->val = afe_read(sd, reg->reg & 0xff);
 669                 break;
 670         case 7:
 671                 reg->val = rep_read(sd, reg->reg & 0xff);
 672                 break;
 673         case 8:
 674                 reg->val = edid_read(sd, reg->reg & 0xff);
 675                 break;
 676         case 9:
 677                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 678                 break;
 679         case 0xa:
 680                 reg->val = test_read(sd, reg->reg & 0xff);
 681                 break;
 682         case 0xb:
 683                 reg->val = cp_read(sd, reg->reg & 0xff);
 684                 break;
 685         case 0xc:
 686                 reg->val = vdp_read(sd, reg->reg & 0xff);
 687                 break;
 688         default:
 689                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 690                 adv7604_inv_register(sd);
 691                 break;
 692         }
 693         return 0;
 694 }
 695
 696 static int adv7604_s_register(struct v4l2_subdev *sd,
 697                                         const struct v4l2_dbg_register *reg)
 698 {
 699         switch (reg->reg >> 8) {
 700         case 0:
 701                 io_write(sd, reg->reg & 0xff, reg->val & 0xff);
 702                 break;
 703         case 1:
 704                 avlink_write(sd, reg->reg & 0xff, reg->val & 0xff);
 705                 break;
 706         case 2:
 707                 cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
 708                 break;
 709         case 3:
 710                 infoframe_write(sd, reg->reg & 0xff, reg->val & 0xff);
 711                 break;
 712         case 4:
 713                 esdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 714                 break;
 715         case 5:
 716                 dpp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 717                 break;
 718         case 6:
 719                 afe_write(sd, reg->reg & 0xff, reg->val & 0xff);
 720                 break;
 721         case 7:
 722                 rep_write(sd, reg->reg & 0xff, reg->val & 0xff);
 723                 break;
 724         case 8:
 725                 edid_write(sd, reg->reg & 0xff, reg->val & 0xff);
 726                 break;
 727         case 9:
 728                 hdmi_write(sd, reg->reg & 0xff, reg->val & 0xff);
 729                 break;
 730         case 0xa:
 731                 test_write(sd, reg->reg & 0xff, reg->val & 0xff);
 732                 break;
 733         case 0xb:
 734                 cp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 735                 break;
 736         case 0xc:
 737                 vdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
 738                 break;
 739         default:
 740                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 741                 adv7604_inv_register(sd);
 742                 break;
 743         }
 744         return 0;
 745 }
 746 #endif
 747
 748 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 749 {
 750         struct adv7604_state *state = to_state(sd);
 751
 752         /* port A only */
 753         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 754                                 ((io_read(sd, 0x6f) & 0x10) >> 4));
 755 }
 756
 757 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 758                 u8 prim_mode,
 759                 const struct adv7604_video_standards *predef_vid_timings,
 760                 const struct v4l2_dv_timings *timings)
 761 {
 762         struct adv7604_state *state = to_state(sd);
 763         int i;
 764
 765         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 766                 if (!v4l_match_dv_timings(timings, &predef_vid_timings[i].timings,
 767                                         DIGITAL_INPUT ? 250000 : 1000000))
 768                         continue;
 769                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 770                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 771                                 prim_mode); /* v_freq and prim mode */
 772                 return 0;
 773         }
 774
 775         return -1;
 776 }
 777
 778 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 779                 struct v4l2_dv_timings *timings)
 780 {
 781         struct adv7604_state *state = to_state(sd);
 782         int err;
 783
 784         v4l2_dbg(1, debug, sd, "%s", __func__);
 785
 786         /* reset to default values */
 787         io_write(sd, 0x16, 0x43);
 788         io_write(sd, 0x17, 0x5a);
 789         /* disable embedded syncs for auto graphics mode */
 790         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 791         cp_write(sd, 0x8f, 0x00);
 792         cp_write(sd, 0x90, 0x00);
 793         cp_write(sd, 0xa2, 0x00);
 794         cp_write(sd, 0xa3, 0x00);
 795         cp_write(sd, 0xa4, 0x00);
 796         cp_write(sd, 0xa5, 0x00);
 797         cp_write(sd, 0xa6, 0x00);
 798         cp_write(sd, 0xa7, 0x00);
 799         cp_write(sd, 0xab, 0x00);
 800         cp_write(sd, 0xac, 0x00);
 801
 802         switch (state->mode) {
 803         case ADV7604_MODE_COMP:
 804         case ADV7604_MODE_GR:
 805                 err = find_and_set_predefined_video_timings(sd,
 806                                 0x01, adv7604_prim_mode_comp, timings);
 807                 if (err)
 808                         err = find_and_set_predefined_video_timings(sd,
 809                                         0x02, adv7604_prim_mode_gr, timings);
 810                 break;
 811         case ADV7604_MODE_HDMI:
 812                 err = find_and_set_predefined_video_timings(sd,
 813                                 0x05, adv7604_prim_mode_hdmi_comp, timings);
 814                 if (err)
 815                         err = find_and_set_predefined_video_timings(sd,
 816                                         0x06, adv7604_prim_mode_hdmi_gr, timings);
 817                 break;
 818         default:
 819                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
 820                                 __func__, state->mode);
 821                 err = -1;
 822                 break;
 823         }
 824
 825
 826         return err;
 827 }
 828
 829 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 830                 const struct v4l2_bt_timings *bt)
 831 {
 832         struct adv7604_state *state = to_state(sd);
 833         struct i2c_client *client = v4l2_get_subdevdata(sd);
 834         u32 width = htotal(bt);
 835         u32 height = vtotal(bt);
 836         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 837         u16 cp_start_eav = width - bt->hfrontporch;
 838         u16 cp_start_vbi = height - bt->vfrontporch;
 839         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 840         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 841                 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 842         const u8 pll[2] = {
 843                 0xc0 | ((width >> 8) & 0x1f),
 844                 width & 0xff
 845         };
 846
 847         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 848
 849         switch (state->mode) {
 850         case ADV7604_MODE_COMP:
 851         case ADV7604_MODE_GR:
 852                 /* auto graphics */
 853                 io_write(sd, 0x00, 0x07); /* video std */
 854                 io_write(sd, 0x01, 0x02); /* prim mode */
 855                 /* enable embedded syncs for auto graphics mode */
 856                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 857
 858                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 859                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 860                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 861                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
 862                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 863                         break;
 864                 }
 865
 866                 /* active video - horizontal timing */
 867                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
 868                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
 869                                         ((cp_start_eav >> 8) & 0x0f));
 870                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
 871
 872                 /* active video - vertical timing */
 873                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 874                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 875                                         ((cp_end_vbi >> 8) & 0xf));
 876                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 877                 break;
 878         case ADV7604_MODE_HDMI:
 879                 /* set default prim_mode/vid_std for HDMI
 880                    accoring to [REF_03, c. 4.2] */
 881                 io_write(sd, 0x00, 0x02); /* video std */
 882                 io_write(sd, 0x01, 0x06); /* prim mode */
 883                 break;
 884         default:
 885                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
 886                                 __func__, state->mode);
 887                 break;
 888         }
 889
 890         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
 891         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
 892         cp_write(sd, 0xab, (height >> 4) & 0xff);
 893         cp_write(sd, 0xac, (height & 0x0f) << 4);
 894 }
 895
 896 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
 897 {
 898         struct adv7604_state *state = to_state(sd);
 899
 900         switch (state->rgb_quantization_range) {
 901         case V4L2_DV_RGB_RANGE_AUTO:
 902                 /* automatic */
 903                 if (DIGITAL_INPUT && !(hdmi_read(sd, 0x05) & 0x80)) {
 904                         /* receiving DVI-D signal */
 905
 906                         /* ADV7604 selects RGB limited range regardless of
 907                            input format (CE/IT) in automatic mode */
 908                         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 909                                 /* RGB limited range (16-235) */
 910                                 io_write_and_or(sd, 0x02, 0x0f, 0x00);
 911
 912                         } else {
 913                                 /* RGB full range (0-255) */
 914                                 io_write_and_or(sd, 0x02, 0x0f, 0x10);
 915                         }
 916                 } else {
 917                         /* receiving HDMI or analog signal, set automode */
 918                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 919                 }
 920                 break;
 921         case V4L2_DV_RGB_RANGE_LIMITED:
 922                 /* RGB limited range (16-235) */
 923                 io_write_and_or(sd, 0x02, 0x0f, 0x00);
 924                 break;
 925         case V4L2_DV_RGB_RANGE_FULL:
 926                 /* RGB full range (0-255) */
 927                 io_write_and_or(sd, 0x02, 0x0f, 0x10);
 928                 break;
 929         }
 930 }
 931
 932
 933 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
 934 {
 935         struct v4l2_subdev *sd = to_sd(ctrl);
 936         struct adv7604_state *state = to_state(sd);
 937
 938         switch (ctrl->id) {
 939         case V4L2_CID_BRIGHTNESS:
 940                 cp_write(sd, 0x3c, ctrl->val);
 941                 return 0;
 942         case V4L2_CID_CONTRAST:
 943                 cp_write(sd, 0x3a, ctrl->val);
 944                 return 0;
 945         case V4L2_CID_SATURATION:
 946                 cp_write(sd, 0x3b, ctrl->val);
 947                 return 0;
 948         case V4L2_CID_HUE:
 949                 cp_write(sd, 0x3d, ctrl->val);
 950                 return 0;
 951         case  V4L2_CID_DV_RX_RGB_RANGE:
 952                 state->rgb_quantization_range = ctrl->val;
 953                 set_rgb_quantization_range(sd);
 954                 return 0;
 955         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
 956                 /* Set the analog sampling phase. This is needed to find the
 957                    best sampling phase for analog video: an application or
 958                    driver has to try a number of phases and analyze the picture
 959                    quality before settling on the best performing phase. */
 960                 afe_write(sd, 0xc8, ctrl->val);
 961                 return 0;
 962         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
 963                 /* Use the default blue color for free running mode,
 964                    or supply your own. */
 965                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
 966                 return 0;
 967         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
 968                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
 969                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
 970                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
 971                 return 0;
 972         }
 973         return -EINVAL;
 974 }
 975
 976 /* ----------------------------------------------------------------------- */
 977
 978 static inline bool no_power(struct v4l2_subdev *sd)
 979 {
 980         /* Entire chip or CP powered off */
 981         return io_read(sd, 0x0c) & 0x24;
 982 }
 983
 984 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
 985 {
 986         /* TODO port B, C and D */
 987         return !(io_read(sd, 0x6a) & 0x10);
 988 }
 989
 990 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
 991 {
 992         return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
 993 }
 994
 995 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
 996 {
 997         /* TODO channel 2 */
 998         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
 999 }
1000
1001 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1002 {
1003         /* TODO channel 2 */
1004         return !(cp_read(sd, 0xb1) & 0x80);
1005 }
1006
1007 static inline bool no_signal(struct v4l2_subdev *sd)
1008 {
1009         struct adv7604_state *state = to_state(sd);
1010         bool ret;
1011
1012         ret = no_power(sd);
1013
1014         ret |= no_lock_stdi(sd);
1015         ret |= no_lock_sspd(sd);
1016
1017         if (DIGITAL_INPUT) {
1018                 ret |= no_lock_tmds(sd);
1019                 ret |= no_signal_tmds(sd);
1020         }
1021
1022         return ret;
1023 }
1024
1025 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1026 {
1027         /* CP has detected a non standard number of lines on the incoming
1028            video compared to what it is configured to receive by s_dv_timings */
1029         return io_read(sd, 0x12) & 0x01;
1030 }
1031
1032 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1033 {
1034         struct adv7604_state *state = to_state(sd);
1035
1036         *status = 0;
1037         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1038         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1039         if (no_lock_cp(sd))
1040                 *status |= DIGITAL_INPUT ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1041
1042         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1043
1044         return 0;
1045 }
1046
1047 /* ----------------------------------------------------------------------- */
1048
1049 static void adv7604_print_timings(struct v4l2_subdev *sd,
1050         struct v4l2_dv_timings *timings, const char *txt, bool detailed)
1051 {
1052         struct v4l2_bt_timings *bt = &timings->bt;
1053         u32 htot, vtot;
1054
1055         if (timings->type != V4L2_DV_BT_656_1120)
1056                 return;
1057
1058         htot = htotal(bt);
1059         vtot = vtotal(bt);
1060
1061         v4l2_info(sd, "%s %dx%d%s%d (%dx%d)",
1062                         txt, bt->width, bt->height, bt->interlaced ? "i" : "p",
1063                         (htot * vtot) > 0 ? ((u32)bt->pixelclock /
1064                                 (htot * vtot)) : 0,
1065                         htot, vtot);
1066
1067         if (detailed) {
1068                 v4l2_info(sd, "    horizontal: fp = %d, %ssync = %d, bp = %d\n",
1069                                 bt->hfrontporch,
1070                                 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-",
1071                                 bt->hsync, bt->hbackporch);
1072                 v4l2_info(sd, "    vertical: fp = %d, %ssync = %d, bp = %d\n",
1073                                 bt->vfrontporch,
1074                                 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
1075                                 bt->vsync, bt->vbackporch);
1076                 v4l2_info(sd, "    pixelclock: %lld, flags: 0x%x, standards: 0x%x\n",
1077                                 bt->pixelclock, bt->flags, bt->standards);
1078         }
1079 }
1080
1081 struct stdi_readback {
1082         u16 bl, lcf, lcvs;
1083         u8 hs_pol, vs_pol;
1084         bool interlaced;
1085 };
1086
1087 static int stdi2dv_timings(struct v4l2_subdev *sd,
1088                 struct stdi_readback *stdi,
1089                 struct v4l2_dv_timings *timings)
1090 {
1091         struct adv7604_state *state = to_state(sd);
1092         u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1093         u32 pix_clk;
1094         int i;
1095
1096         for (i = 0; adv7604_timings[i].bt.height; i++) {
1097                 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1098                         continue;
1099                 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1100                         continue;
1101
1102                 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1103
1104                 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1105                     (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1106                         *timings = adv7604_timings[i];
1107                         return 0;
1108                 }
1109         }
1110
1111         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1112                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1113                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1114                         timings))
1115                 return 0;
1116         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1117                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1118                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1119                         state->aspect_ratio, timings))
1120                 return 0;
1121
1122         v4l2_dbg(2, debug, sd,
1123                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1124                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1125                 stdi->hs_pol, stdi->vs_pol);
1126         return -1;
1127 }
1128
1129 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1130 {
1131         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1132                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1133                 return -1;
1134         }
1135
1136         /* read STDI */
1137         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1138         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1139         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1140         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1141
1142         /* read SSPD */
1143         if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1144                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1145                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1146                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1147                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1148         } else {
1149                 stdi->hs_pol = 'x';
1150                 stdi->vs_pol = 'x';
1151         }
1152
1153         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1154                 v4l2_dbg(2, debug, sd,
1155                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1156                 return -1;
1157         }
1158
1159         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1160                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1161                 memset(stdi, 0, sizeof(struct stdi_readback));
1162                 return -1;
1163         }
1164
1165         v4l2_dbg(2, debug, sd,
1166                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1167                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1168                 stdi->hs_pol, stdi->vs_pol,
1169                 stdi->interlaced ? "interlaced" : "progressive");
1170
1171         return 0;
1172 }
1173
1174 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1175                         struct v4l2_enum_dv_timings *timings)
1176 {
1177         if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1178                 return -EINVAL;
1179         memset(timings->reserved, 0, sizeof(timings->reserved));
1180         timings->timings = adv7604_timings[timings->index];
1181         return 0;
1182 }
1183
1184 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1185                         struct v4l2_dv_timings_cap *cap)
1186 {
1187         struct adv7604_state *state = to_state(sd);
1188
1189         cap->type = V4L2_DV_BT_656_1120;
1190         cap->bt.max_width = 1920;
1191         cap->bt.max_height = 1200;
1192         cap->bt.min_pixelclock = 27000000;
1193         if (DIGITAL_INPUT)
1194                 cap->bt.max_pixelclock = 225000000;
1195         else
1196                 cap->bt.max_pixelclock = 170000000;
1197         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1198                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1199         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1200                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1201         return 0;
1202 }
1203
1204 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1205    if the format is listed in adv7604_timings[] */
1206 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1207                 struct v4l2_dv_timings *timings)
1208 {
1209         struct adv7604_state *state = to_state(sd);
1210         int i;
1211
1212         for (i = 0; adv7604_timings[i].bt.width; i++) {
1213                 if (v4l_match_dv_timings(timings, &adv7604_timings[i],
1214                                         DIGITAL_INPUT ? 250000 : 1000000)) {
1215                         *timings = adv7604_timings[i];
1216                         break;
1217                 }
1218         }
1219 }
1220
1221 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1222                         struct v4l2_dv_timings *timings)
1223 {
1224         struct adv7604_state *state = to_state(sd);
1225         struct v4l2_bt_timings *bt = &timings->bt;
1226         struct stdi_readback stdi;
1227
1228         if (!timings)
1229                 return -EINVAL;
1230
1231         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1232
1233         if (no_signal(sd)) {
1234                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1235                 return -ENOLINK;
1236         }
1237
1238         /* read STDI */
1239         if (read_stdi(sd, &stdi)) {
1240                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1241                 return -ENOLINK;
1242         }
1243         bt->interlaced = stdi.interlaced ?
1244                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1245
1246         if (DIGITAL_INPUT) {
1247                 timings->type = V4L2_DV_BT_656_1120;
1248
1249                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1250                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1251                 bt->pixelclock = (hdmi_read(sd, 0x06) * 1000000) +
1252                         ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1253                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1254                         hdmi_read(sd, 0x21);
1255                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1256                         hdmi_read(sd, 0x23);
1257                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1258                         hdmi_read(sd, 0x25);
1259                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1260                         hdmi_read(sd, 0x2b)) / 2;
1261                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1262                         hdmi_read(sd, 0x2f)) / 2;
1263                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1264                         hdmi_read(sd, 0x33)) / 2;
1265                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1266                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1267                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1268                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1269                                         hdmi_read(sd, 0x0c);
1270                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1271                                         hdmi_read(sd, 0x2d)) / 2;
1272                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1273                                         hdmi_read(sd, 0x31)) / 2;
1274                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1275                                         hdmi_read(sd, 0x35)) / 2;
1276                 }
1277                 adv7604_fill_optional_dv_timings_fields(sd, timings);
1278         } else {
1279                 /* find format
1280                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1281                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1282                  */
1283                 if (!stdi2dv_timings(sd, &stdi, timings))
1284                         goto found;
1285                 stdi.lcvs += 1;
1286                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1287                 if (!stdi2dv_timings(sd, &stdi, timings))
1288                         goto found;
1289                 stdi.lcvs -= 2;
1290                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1291                 if (stdi2dv_timings(sd, &stdi, timings)) {
1292                         /*
1293                          * The STDI block may measure wrong values, especially
1294                          * for lcvs and lcf. If the driver can not find any
1295                          * valid timing, the STDI block is restarted to measure
1296                          * the video timings again. The function will return an
1297                          * error, but the restart of STDI will generate a new
1298                          * STDI interrupt and the format detection process will
1299                          * restart.
1300                          */
1301                         if (state->restart_stdi_once) {
1302                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1303                                 /* TODO restart STDI for Sync Channel 2 */
1304                                 /* enter one-shot mode */
1305                                 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1306                                 /* trigger STDI restart */
1307                                 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1308                                 /* reset to continuous mode */
1309                                 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1310                                 state->restart_stdi_once = false;
1311                                 return -ENOLINK;
1312                         }
1313                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1314                         return -ERANGE;
1315                 }
1316                 state->restart_stdi_once = true;
1317         }
1318 found:
1319
1320         if (no_signal(sd)) {
1321                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1322                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1323                 return -ENOLINK;
1324         }
1325
1326         if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1327                         (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1328                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1329                                 __func__, (u32)bt->pixelclock);
1330                 return -ERANGE;
1331         }
1332
1333         if (debug > 1)
1334                 adv7604_print_timings(sd, timings,
1335                                 "adv7604_query_dv_timings:", true);
1336
1337         return 0;
1338 }
1339
1340 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1341                 struct v4l2_dv_timings *timings)
1342 {
1343         struct adv7604_state *state = to_state(sd);
1344         struct v4l2_bt_timings *bt;
1345         int err;
1346
1347         if (!timings)
1348                 return -EINVAL;
1349
1350         bt = &timings->bt;
1351
1352         if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1353                         (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1354                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1355                                 __func__, (u32)bt->pixelclock);
1356                 return -ERANGE;
1357         }
1358
1359         adv7604_fill_optional_dv_timings_fields(sd, timings);
1360
1361         state->timings = *timings;
1362
1363         cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1364
1365         /* Use prim_mode and vid_std when available */
1366         err = configure_predefined_video_timings(sd, timings);
1367         if (err) {
1368                 /* custom settings when the video format
1369                  does not have prim_mode/vid_std */
1370                 configure_custom_video_timings(sd, bt);
1371         }
1372
1373         set_rgb_quantization_range(sd);
1374
1375
1376         if (debug > 1)
1377                 adv7604_print_timings(sd, timings,
1378                                 "adv7604_s_dv_timings:", true);
1379         return 0;
1380 }
1381
1382 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1383                 struct v4l2_dv_timings *timings)
1384 {
1385         struct adv7604_state *state = to_state(sd);
1386
1387         *timings = state->timings;
1388         return 0;
1389 }
1390
1391 static void enable_input(struct v4l2_subdev *sd)
1392 {
1393         struct adv7604_state *state = to_state(sd);
1394
1395         switch (state->mode) {
1396         case ADV7604_MODE_COMP:
1397         case ADV7604_MODE_GR:
1398                 /* enable */
1399                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1400                 break;
1401         case ADV7604_MODE_HDMI:
1402                 /* enable */
1403                 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1404                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1405                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1406                 break;
1407         default:
1408                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1409                                 __func__, state->mode);
1410                 break;
1411         }
1412 }
1413
1414 static void disable_input(struct v4l2_subdev *sd)
1415 {
1416         /* disable */
1417         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1418         hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1419         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1420 }
1421
1422 static void select_input(struct v4l2_subdev *sd)
1423 {
1424         struct adv7604_state *state = to_state(sd);
1425
1426         switch (state->mode) {
1427         case ADV7604_MODE_COMP:
1428         case ADV7604_MODE_GR:
1429                 /* reset ADI recommended settings for HDMI: */
1430                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1431                 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1432                 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1433                 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1434                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1435                 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1436                 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1437                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1438                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1439                 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1440                 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1441                 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1442
1443                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1444                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1445                 afe_write(sd, 0xc8, 0x00); /* phase control */
1446
1447                 /* set ADI recommended settings for digitizer */
1448                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1449                 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1450                 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1451                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1452                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1453                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1454                 break;
1455
1456         case ADV7604_MODE_HDMI:
1457                 /* set ADI recommended settings for HDMI: */
1458                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1459                 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1460                 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1461                 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1462                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1463                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1464                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1465                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1466                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1467                 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1468                 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1469                 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1470
1471                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1472                 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1473                 afe_write(sd, 0xc8, 0x40); /* phase control */
1474
1475                 /* reset ADI recommended settings for digitizer */
1476                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1477                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1478                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1479                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1480                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1481                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1482
1483                 break;
1484         default:
1485                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1486                                 __func__, state->mode);
1487                 break;
1488         }
1489 }
1490
1491 static int adv7604_s_routing(struct v4l2_subdev *sd,
1492                 u32 input, u32 output, u32 config)
1493 {
1494         struct adv7604_state *state = to_state(sd);
1495
1496         v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1497
1498         state->mode = input;
1499
1500         disable_input(sd);
1501
1502         select_input(sd);
1503
1504         enable_input(sd);
1505
1506         return 0;
1507 }
1508
1509 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1510                              enum v4l2_mbus_pixelcode *code)
1511 {
1512         if (index)
1513                 return -EINVAL;
1514         /* Good enough for now */
1515         *code = V4L2_MBUS_FMT_FIXED;
1516         return 0;
1517 }
1518
1519 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1520                 struct v4l2_mbus_framefmt *fmt)
1521 {
1522         struct adv7604_state *state = to_state(sd);
1523
1524         fmt->width = state->timings.bt.width;
1525         fmt->height = state->timings.bt.height;
1526         fmt->code = V4L2_MBUS_FMT_FIXED;
1527         fmt->field = V4L2_FIELD_NONE;
1528         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1529                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1530                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1531         }
1532         return 0;
1533 }
1534
1535 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1536 {
1537         struct adv7604_state *state = to_state(sd);
1538         u8 fmt_change, fmt_change_digital, tx_5v;
1539         u32 input_status;
1540
1541         /* format change */
1542         fmt_change = io_read(sd, 0x43) & 0x98;
1543         if (fmt_change)
1544                 io_write(sd, 0x44, fmt_change);
1545         fmt_change_digital = DIGITAL_INPUT ? (io_read(sd, 0x6b) & 0xc0) : 0;
1546         if (fmt_change_digital)
1547                 io_write(sd, 0x6c, fmt_change_digital);
1548         if (fmt_change || fmt_change_digital) {
1549                 v4l2_dbg(1, debug, sd,
1550                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1551                         __func__, fmt_change, fmt_change_digital);
1552
1553                 adv7604_g_input_status(sd, &input_status);
1554                 if (input_status != state->prev_input_status) {
1555                         v4l2_dbg(1, debug, sd,
1556                                 "%s: input_status = 0x%x, prev_input_status = 0x%x\n",
1557                                 __func__, input_status, state->prev_input_status);
1558                         state->prev_input_status = input_status;
1559                         v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1560                 }
1561
1562                 if (handled)
1563                         *handled = true;
1564         }
1565         /* tx 5v detect */
1566         tx_5v = io_read(sd, 0x70) & 0x10;
1567         if (tx_5v) {
1568                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1569                 io_write(sd, 0x71, tx_5v);
1570                 adv7604_s_detect_tx_5v_ctrl(sd);
1571                 if (handled)
1572                         *handled = true;
1573         }
1574         return 0;
1575 }
1576
1577 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1578 {
1579         struct adv7604_state *state = to_state(sd);
1580
1581         if (edid->pad != 0)
1582                 return -EINVAL;
1583         if (edid->blocks == 0)
1584                 return -EINVAL;
1585         if (edid->start_block >= state->edid_blocks)
1586                 return -EINVAL;
1587         if (edid->start_block + edid->blocks > state->edid_blocks)
1588                 edid->blocks = state->edid_blocks - edid->start_block;
1589         if (!edid->edid)
1590                 return -EINVAL;
1591         memcpy(edid->edid + edid->start_block * 128,
1592                state->edid + edid->start_block * 128,
1593                edid->blocks * 128);
1594         return 0;
1595 }
1596
1597 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1598 {
1599         struct adv7604_state *state = to_state(sd);
1600         int err;
1601
1602         if (edid->pad != 0)
1603                 return -EINVAL;
1604         if (edid->start_block != 0)
1605                 return -EINVAL;
1606         if (edid->blocks == 0) {
1607                 /* Pull down the hotplug pin */
1608                 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
1609                 /* Disables I2C access to internal EDID ram from DDC port */
1610                 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
1611                 state->edid_blocks = 0;
1612                 /* Fall back to a 16:9 aspect ratio */
1613                 state->aspect_ratio.numerator = 16;
1614                 state->aspect_ratio.denominator = 9;
1615                 return 0;
1616         }
1617         if (edid->blocks > 2)
1618                 return -E2BIG;
1619         if (!edid->edid)
1620                 return -EINVAL;
1621         memcpy(state->edid, edid->edid, 128 * edid->blocks);
1622         state->edid_blocks = edid->blocks;
1623         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1624                         edid->edid[0x16]);
1625         err = edid_write_block(sd, 128 * edid->blocks, state->edid);
1626         if (err < 0)
1627                 v4l2_err(sd, "error %d writing edid\n", err);
1628         return err;
1629 }
1630
1631 /*********** avi info frame CEA-861-E **************/
1632
1633 static void print_avi_infoframe(struct v4l2_subdev *sd)
1634 {
1635         int i;
1636         u8 buf[14];
1637         u8 avi_len;
1638         u8 avi_ver;
1639
1640         if (!(hdmi_read(sd, 0x05) & 0x80)) {
1641                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1642                 return;
1643         }
1644         if (!(io_read(sd, 0x60) & 0x01)) {
1645                 v4l2_info(sd, "AVI infoframe not received\n");
1646                 return;
1647         }
1648
1649         if (io_read(sd, 0x83) & 0x01) {
1650                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1651                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1652                 if (io_read(sd, 0x83) & 0x01) {
1653                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
1654                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1655                 }
1656         }
1657
1658         avi_len = infoframe_read(sd, 0xe2);
1659         avi_ver = infoframe_read(sd, 0xe1);
1660         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1661                         avi_ver, avi_len);
1662
1663         if (avi_ver != 0x02)
1664                 return;
1665
1666         for (i = 0; i < 14; i++)
1667                 buf[i] = infoframe_read(sd, i);
1668
1669         v4l2_info(sd,
1670                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1671                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1672                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1673 }
1674
1675 static int adv7604_log_status(struct v4l2_subdev *sd)
1676 {
1677         struct adv7604_state *state = to_state(sd);
1678         struct v4l2_dv_timings timings;
1679         struct stdi_readback stdi;
1680         u8 reg_io_0x02 = io_read(sd, 0x02);
1681
1682         char *csc_coeff_sel_rb[16] = {
1683                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1684                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1685                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1686                 "reserved", "reserved", "reserved", "reserved", "manual"
1687         };
1688         char *input_color_space_txt[16] = {
1689                 "RGB limited range (16-235)", "RGB full range (0-255)",
1690                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1691                 "XvYCC Bt.601", "XvYCC Bt.709",
1692                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1693                 "invalid", "invalid", "invalid", "invalid", "invalid",
1694                 "invalid", "invalid", "automatic"
1695         };
1696         char *rgb_quantization_range_txt[] = {
1697                 "Automatic",
1698                 "RGB limited range (16-235)",
1699                 "RGB full range (0-255)",
1700         };
1701
1702         v4l2_info(sd, "-----Chip status-----\n");
1703         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1704         v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
1705                         "HDMI" : (DIGITAL_INPUT ? "DVI-D" : "DVI-A"));
1706         v4l2_info(sd, "EDID: %s\n", ((rep_read(sd, 0x7d) & 0x01) &&
1707                         (rep_read(sd, 0x77) & 0x01)) ? "enabled" : "disabled ");
1708         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1709                         "enabled" : "disabled");
1710
1711         v4l2_info(sd, "-----Signal status-----\n");
1712         v4l2_info(sd, "Cable detected (+5V power): %s\n",
1713                         (io_read(sd, 0x6f) & 0x10) ? "true" : "false");
1714         v4l2_info(sd, "TMDS signal detected: %s\n",
1715                         no_signal_tmds(sd) ? "false" : "true");
1716         v4l2_info(sd, "TMDS signal locked: %s\n",
1717                         no_lock_tmds(sd) ? "false" : "true");
1718         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1719         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1720         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1721         v4l2_info(sd, "CP free run: %s\n",
1722                         (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1723         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1724                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1725                         (io_read(sd, 0x01) & 0x70) >> 4);
1726
1727         v4l2_info(sd, "-----Video Timings-----\n");
1728         if (read_stdi(sd, &stdi))
1729                 v4l2_info(sd, "STDI: not locked\n");
1730         else
1731                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1732                                 stdi.lcf, stdi.bl, stdi.lcvs,
1733                                 stdi.interlaced ? "interlaced" : "progressive",
1734                                 stdi.hs_pol, stdi.vs_pol);
1735         if (adv7604_query_dv_timings(sd, &timings))
1736                 v4l2_info(sd, "No video detected\n");
1737         else
1738                 adv7604_print_timings(sd, &timings, "Detected format:", true);
1739         adv7604_print_timings(sd, &state->timings, "Configured format:", true);
1740
1741         v4l2_info(sd, "-----Color space-----\n");
1742         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1743                         rgb_quantization_range_txt[state->rgb_quantization_range]);
1744         v4l2_info(sd, "Input color space: %s\n",
1745                         input_color_space_txt[reg_io_0x02 >> 4]);
1746         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1747                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1748                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1749                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1750                                         "enabled" : "disabled");
1751         v4l2_info(sd, "Color space conversion: %s\n",
1752                         csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1753
1754         /* Digital video */
1755         if (DIGITAL_INPUT) {
1756                 v4l2_info(sd, "-----HDMI status-----\n");
1757                 v4l2_info(sd, "HDCP encrypted content: %s\n",
1758                                 hdmi_read(sd, 0x05) & 0x40 ? "true" : "false");
1759
1760                 print_avi_infoframe(sd);
1761         }
1762
1763         return 0;
1764 }
1765
1766 /* ----------------------------------------------------------------------- */
1767
1768 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1769         .s_ctrl = adv7604_s_ctrl,
1770 };
1771
1772 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1773         .log_status = adv7604_log_status,
1774         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1775         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1776         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1777         .g_ctrl = v4l2_subdev_g_ctrl,
1778         .s_ctrl = v4l2_subdev_s_ctrl,
1779         .queryctrl = v4l2_subdev_queryctrl,
1780         .querymenu = v4l2_subdev_querymenu,
1781         .interrupt_service_routine = adv7604_isr,
1782 #ifdef CONFIG_VIDEO_ADV_DEBUG
1783         .g_register = adv7604_g_register,
1784         .s_register = adv7604_s_register,
1785 #endif
1786 };
1787
1788 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1789         .s_routing = adv7604_s_routing,
1790         .g_input_status = adv7604_g_input_status,
1791         .s_dv_timings = adv7604_s_dv_timings,
1792         .g_dv_timings = adv7604_g_dv_timings,
1793         .query_dv_timings = adv7604_query_dv_timings,
1794         .enum_dv_timings = adv7604_enum_dv_timings,
1795         .dv_timings_cap = adv7604_dv_timings_cap,
1796         .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1797         .g_mbus_fmt = adv7604_g_mbus_fmt,
1798         .try_mbus_fmt = adv7604_g_mbus_fmt,
1799         .s_mbus_fmt = adv7604_g_mbus_fmt,
1800 };
1801
1802 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1803         .get_edid = adv7604_get_edid,
1804         .set_edid = adv7604_set_edid,
1805 };
1806
1807 static const struct v4l2_subdev_ops adv7604_ops = {
1808         .core = &adv7604_core_ops,
1809         .video = &adv7604_video_ops,
1810         .pad = &adv7604_pad_ops,
1811 };
1812
1813 /* -------------------------- custom ctrls ---------------------------------- */
1814
1815 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1816         .ops = &adv7604_ctrl_ops,
1817         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1818         .name = "Analog Sampling Phase",
1819         .type = V4L2_CTRL_TYPE_INTEGER,
1820         .min = 0,
1821         .max = 0x1f,
1822         .step = 1,
1823         .def = 0,
1824 };
1825
1826 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1827         .ops = &adv7604_ctrl_ops,
1828         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1829         .name = "Free Running Color, Manual",
1830         .type = V4L2_CTRL_TYPE_BOOLEAN,
1831         .min = false,
1832         .max = true,
1833         .step = 1,
1834         .def = false,
1835 };
1836
1837 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1838         .ops = &adv7604_ctrl_ops,
1839         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1840         .name = "Free Running Color",
1841         .type = V4L2_CTRL_TYPE_INTEGER,
1842         .min = 0x0,
1843         .max = 0xffffff,
1844         .step = 0x1,
1845         .def = 0x0,
1846 };
1847
1848 /* ----------------------------------------------------------------------- */
1849
1850 static int adv7604_core_init(struct v4l2_subdev *sd)
1851 {
1852         struct adv7604_state *state = to_state(sd);
1853         struct adv7604_platform_data *pdata = &state->pdata;
1854
1855         hdmi_write(sd, 0x48,
1856                 (pdata->disable_pwrdnb ? 0x80 : 0) |
1857                 (pdata->disable_cable_det_rst ? 0x40 : 0));
1858
1859         disable_input(sd);
1860
1861         /* power */
1862         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
1863         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
1864         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
1865
1866         /* video format */
1867         io_write_and_or(sd, 0x02, 0xf0,
1868                         pdata->alt_gamma << 3 |
1869                         pdata->op_656_range << 2 |
1870                         pdata->rgb_out << 1 |
1871                         pdata->alt_data_sat << 0);
1872         io_write(sd, 0x03, pdata->op_format_sel);
1873         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1874         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1875                                         pdata->insert_av_codes << 2 |
1876                                         pdata->replicate_av_codes << 1 |
1877                                         pdata->invert_cbcr << 0);
1878
1879         /* TODO from platform data */
1880         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
1881         io_write(sd, 0x06, 0xa6);   /* positive VS and HS */
1882         io_write(sd, 0x14, 0x7f);   /* Drive strength adjusted to max */
1883         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1884         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1885         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
1886                                       ADI recommended setting [REF_01, c. 2.3.3] */
1887         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
1888                                       ADI recommended setting [REF_01, c. 2.3.3] */
1889         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1890                                      for digital formats */
1891
1892         /* TODO from platform data */
1893         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
1894
1895         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1896         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1897
1898         /* interrupts */
1899         io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1900         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1901         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1902         io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1903         io_write(sd, 0x73, 0x10); /* Enable CABLE_DET_A_ST (+5v) interrupt */
1904
1905         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
1906 }
1907
1908 static void adv7604_unregister_clients(struct adv7604_state *state)
1909 {
1910         if (state->i2c_avlink)
1911                 i2c_unregister_device(state->i2c_avlink);
1912         if (state->i2c_cec)
1913                 i2c_unregister_device(state->i2c_cec);
1914         if (state->i2c_infoframe)
1915                 i2c_unregister_device(state->i2c_infoframe);
1916         if (state->i2c_esdp)
1917                 i2c_unregister_device(state->i2c_esdp);
1918         if (state->i2c_dpp)
1919                 i2c_unregister_device(state->i2c_dpp);
1920         if (state->i2c_afe)
1921                 i2c_unregister_device(state->i2c_afe);
1922         if (state->i2c_repeater)
1923                 i2c_unregister_device(state->i2c_repeater);
1924         if (state->i2c_edid)
1925                 i2c_unregister_device(state->i2c_edid);
1926         if (state->i2c_hdmi)
1927                 i2c_unregister_device(state->i2c_hdmi);
1928         if (state->i2c_test)
1929                 i2c_unregister_device(state->i2c_test);
1930         if (state->i2c_cp)
1931                 i2c_unregister_device(state->i2c_cp);
1932         if (state->i2c_vdp)
1933                 i2c_unregister_device(state->i2c_vdp);
1934 }
1935
1936 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
1937                                                         u8 addr, u8 io_reg)
1938 {
1939         struct i2c_client *client = v4l2_get_subdevdata(sd);
1940
1941         if (addr)
1942                 io_write(sd, io_reg, addr << 1);
1943         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
1944 }
1945
1946 static int adv7604_probe(struct i2c_client *client,
1947                          const struct i2c_device_id *id)
1948 {
1949         struct adv7604_state *state;
1950         struct adv7604_platform_data *pdata = client->dev.platform_data;
1951         struct v4l2_ctrl_handler *hdl;
1952         struct v4l2_subdev *sd;
1953         int err;
1954
1955         /* Check if the adapter supports the needed features */
1956         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1957                 return -EIO;
1958         v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
1959                         client->addr << 1);
1960
1961         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1962         if (!state) {
1963                 v4l_err(client, "Could not allocate adv7604_state memory!\n");
1964                 return -ENOMEM;
1965         }
1966
1967         /* initialize variables */
1968         state->restart_stdi_once = true;
1969         state->prev_input_status = ~0;
1970
1971         /* platform data */
1972         if (!pdata) {
1973                 v4l_err(client, "No platform data!\n");
1974                 return -ENODEV;
1975         }
1976         memcpy(&state->pdata, pdata, sizeof(state->pdata));
1977
1978         sd = &state->sd;
1979         v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
1980         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1981         state->connector_hdmi = pdata->connector_hdmi;
1982
1983         /* i2c access to adv7604? */
1984         if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
1985                 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
1986                                 client->addr << 1);
1987                 return -ENODEV;
1988         }
1989
1990         /* control handlers */
1991         hdl = &state->hdl;
1992         v4l2_ctrl_handler_init(hdl, 9);
1993
1994         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1995                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
1996         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1997                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
1998         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1999                         V4L2_CID_SATURATION, 0, 255, 1, 128);
2000         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2001                         V4L2_CID_HUE, 0, 128, 1, 0);
2002
2003         /* private controls */
2004         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2005                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2006         state->detect_tx_5v_ctrl->is_private = true;
2007         state->rgb_quantization_range_ctrl =
2008                 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2009                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2010                         0, V4L2_DV_RGB_RANGE_AUTO);
2011         state->rgb_quantization_range_ctrl->is_private = true;
2012
2013         /* custom controls */
2014         state->analog_sampling_phase_ctrl =
2015                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2016         state->analog_sampling_phase_ctrl->is_private = true;
2017         state->free_run_color_manual_ctrl =
2018                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2019         state->free_run_color_manual_ctrl->is_private = true;
2020         state->free_run_color_ctrl =
2021                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2022         state->free_run_color_ctrl->is_private = true;
2023
2024         sd->ctrl_handler = hdl;
2025         if (hdl->error) {
2026                 err = hdl->error;
2027                 goto err_hdl;
2028         }
2029         if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2030                 err = -ENODEV;
2031                 goto err_hdl;
2032         }
2033
2034         state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2035         state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2036         state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2037         state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2038         state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2039         state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2040         state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2041         state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2042         state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2043         state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2044         state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2045         state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2046         if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2047             !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2048             !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2049             !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2050                 err = -ENOMEM;
2051                 v4l2_err(sd, "failed to create all i2c clients\n");
2052                 goto err_i2c;
2053         }
2054
2055         /* work queues */
2056         state->work_queues = create_singlethread_workqueue(client->name);
2057         if (!state->work_queues) {
2058                 v4l2_err(sd, "Could not create work queue\n");
2059                 err = -ENOMEM;
2060                 goto err_i2c;
2061         }
2062
2063         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2064                         adv7604_delayed_work_enable_hotplug);
2065
2066         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2067         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2068         if (err)
2069                 goto err_work_queues;
2070
2071         err = adv7604_core_init(sd);
2072         if (err)
2073                 goto err_entity;
2074         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2075                         client->addr << 1, client->adapter->name);
2076         return 0;
2077
2078 err_entity:
2079         media_entity_cleanup(&sd->entity);
2080 err_work_queues:
2081         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2082         destroy_workqueue(state->work_queues);
2083 err_i2c:
2084         adv7604_unregister_clients(state);
2085 err_hdl:
2086         v4l2_ctrl_handler_free(hdl);
2087         return err;
2088 }
2089
2090 /* ----------------------------------------------------------------------- */
2091
2092 static int adv7604_remove(struct i2c_client *client)
2093 {
2094         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2095         struct adv7604_state *state = to_state(sd);
2096
2097         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2098         destroy_workqueue(state->work_queues);
2099         v4l2_device_unregister_subdev(sd);
2100         media_entity_cleanup(&sd->entity);
2101         adv7604_unregister_clients(to_state(sd));
2102         v4l2_ctrl_handler_free(sd->ctrl_handler);
2103         return 0;
2104 }
2105
2106 /* ----------------------------------------------------------------------- */
2107
2108 static struct i2c_device_id adv7604_id[] = {
2109         { "adv7604", 0 },
2110         { }
2111 };
2112 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2113
2114 static struct i2c_driver adv7604_driver = {
2115         .driver = {
2116                 .owner = THIS_MODULE,
2117                 .name = "adv7604",
2118         },
2119         .probe = adv7604_probe,
2120         .remove = adv7604_remove,
2121         .id_table = adv7604_id,
2122 };
2123
2124 module_i2c_driver(adv7604_driver);