2 * adv7604 - Analog Devices ADV7604 video decoder driver
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/i2c.h>
35 #include <linux/delay.h>
36 #include <linux/videodev2.h>
37 #include <linux/workqueue.h>
38 #include <linux/v4l2-dv-timings.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-ctrls.h>
41 #include <media/v4l2-dv-timings.h>
42 #include <media/adv7604.h>
45 module_param(debug, int, 0644);
46 MODULE_PARM_DESC(debug, "debug level (0-2)");
48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51 MODULE_LICENSE("GPL");
53 /* ADV7604 system clock frequency */
54 #define ADV7604_fsc (28636360)
57 **********************************************************************
59 * Arrays with configuration parameters for the ADV7604
61 **********************************************************************
63 struct adv7604_state {
64 struct adv7604_platform_data pdata;
65 struct v4l2_subdev sd;
67 struct v4l2_ctrl_handler hdl;
68 enum adv7604_input_port selected_input;
69 struct v4l2_dv_timings timings;
76 struct v4l2_fract aspect_ratio;
77 u32 rgb_quantization_range;
78 struct workqueue_struct *work_queues;
79 struct delayed_work delayed_work_enable_hotplug;
80 bool restart_stdi_once;
83 struct i2c_client *i2c_avlink;
84 struct i2c_client *i2c_cec;
85 struct i2c_client *i2c_infoframe;
86 struct i2c_client *i2c_esdp;
87 struct i2c_client *i2c_dpp;
88 struct i2c_client *i2c_afe;
89 struct i2c_client *i2c_repeater;
90 struct i2c_client *i2c_edid;
91 struct i2c_client *i2c_hdmi;
92 struct i2c_client *i2c_test;
93 struct i2c_client *i2c_cp;
94 struct i2c_client *i2c_vdp;
97 struct v4l2_ctrl *detect_tx_5v_ctrl;
98 struct v4l2_ctrl *analog_sampling_phase_ctrl;
99 struct v4l2_ctrl *free_run_color_manual_ctrl;
100 struct v4l2_ctrl *free_run_color_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
104 /* Supported CEA and DMT timings */
105 static const struct v4l2_dv_timings adv7604_timings[] = {
106 V4L2_DV_BT_CEA_720X480P59_94,
107 V4L2_DV_BT_CEA_720X576P50,
108 V4L2_DV_BT_CEA_1280X720P24,
109 V4L2_DV_BT_CEA_1280X720P25,
110 V4L2_DV_BT_CEA_1280X720P50,
111 V4L2_DV_BT_CEA_1280X720P60,
112 V4L2_DV_BT_CEA_1920X1080P24,
113 V4L2_DV_BT_CEA_1920X1080P25,
114 V4L2_DV_BT_CEA_1920X1080P30,
115 V4L2_DV_BT_CEA_1920X1080P50,
116 V4L2_DV_BT_CEA_1920X1080P60,
118 /* sorted by DMT ID */
119 V4L2_DV_BT_DMT_640X350P85,
120 V4L2_DV_BT_DMT_640X400P85,
121 V4L2_DV_BT_DMT_720X400P85,
122 V4L2_DV_BT_DMT_640X480P60,
123 V4L2_DV_BT_DMT_640X480P72,
124 V4L2_DV_BT_DMT_640X480P75,
125 V4L2_DV_BT_DMT_640X480P85,
126 V4L2_DV_BT_DMT_800X600P56,
127 V4L2_DV_BT_DMT_800X600P60,
128 V4L2_DV_BT_DMT_800X600P72,
129 V4L2_DV_BT_DMT_800X600P75,
130 V4L2_DV_BT_DMT_800X600P85,
131 V4L2_DV_BT_DMT_848X480P60,
132 V4L2_DV_BT_DMT_1024X768P60,
133 V4L2_DV_BT_DMT_1024X768P70,
134 V4L2_DV_BT_DMT_1024X768P75,
135 V4L2_DV_BT_DMT_1024X768P85,
136 V4L2_DV_BT_DMT_1152X864P75,
137 V4L2_DV_BT_DMT_1280X768P60_RB,
138 V4L2_DV_BT_DMT_1280X768P60,
139 V4L2_DV_BT_DMT_1280X768P75,
140 V4L2_DV_BT_DMT_1280X768P85,
141 V4L2_DV_BT_DMT_1280X800P60_RB,
142 V4L2_DV_BT_DMT_1280X800P60,
143 V4L2_DV_BT_DMT_1280X800P75,
144 V4L2_DV_BT_DMT_1280X800P85,
145 V4L2_DV_BT_DMT_1280X960P60,
146 V4L2_DV_BT_DMT_1280X960P85,
147 V4L2_DV_BT_DMT_1280X1024P60,
148 V4L2_DV_BT_DMT_1280X1024P75,
149 V4L2_DV_BT_DMT_1280X1024P85,
150 V4L2_DV_BT_DMT_1360X768P60,
151 V4L2_DV_BT_DMT_1400X1050P60_RB,
152 V4L2_DV_BT_DMT_1400X1050P60,
153 V4L2_DV_BT_DMT_1400X1050P75,
154 V4L2_DV_BT_DMT_1400X1050P85,
155 V4L2_DV_BT_DMT_1440X900P60_RB,
156 V4L2_DV_BT_DMT_1440X900P60,
157 V4L2_DV_BT_DMT_1600X1200P60,
158 V4L2_DV_BT_DMT_1680X1050P60_RB,
159 V4L2_DV_BT_DMT_1680X1050P60,
160 V4L2_DV_BT_DMT_1792X1344P60,
161 V4L2_DV_BT_DMT_1856X1392P60,
162 V4L2_DV_BT_DMT_1920X1200P60_RB,
163 V4L2_DV_BT_DMT_1366X768P60_RB,
164 V4L2_DV_BT_DMT_1366X768P60,
165 V4L2_DV_BT_DMT_1920X1080P60,
169 struct adv7604_video_standards {
170 struct v4l2_dv_timings timings;
175 /* sorted by number of lines */
176 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
177 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
178 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
179 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
180 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
181 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
182 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
183 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
184 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
185 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
186 /* TODO add 1920x1080P60_RB (CVT timing) */
190 /* sorted by number of lines */
191 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
192 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
205 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
207 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
208 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
209 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
211 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
212 /* TODO add 1600X1200P60_RB (not a DMT timing) */
213 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
214 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
218 /* sorted by number of lines */
219 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
220 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
221 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
222 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
223 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
224 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
225 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
226 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
227 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
228 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
232 /* sorted by number of lines */
233 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
234 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
247 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
252 /* ----------------------------------------------------------------------- */
254 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
256 return container_of(sd, struct adv7604_state, sd);
259 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
261 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
264 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
266 return V4L2_DV_BT_BLANKING_WIDTH(t);
269 static inline unsigned htotal(const struct v4l2_bt_timings *t)
271 return V4L2_DV_BT_FRAME_WIDTH(t);
274 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
276 return V4L2_DV_BT_BLANKING_HEIGHT(t);
279 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
281 return V4L2_DV_BT_FRAME_HEIGHT(t);
284 /* ----------------------------------------------------------------------- */
286 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
287 u8 command, bool check)
289 union i2c_smbus_data data;
291 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
292 I2C_SMBUS_READ, command,
293 I2C_SMBUS_BYTE_DATA, &data))
296 v4l_err(client, "error reading %02x, %02x\n",
297 client->addr, command);
301 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
303 return adv_smbus_read_byte_data_check(client, command, true);
306 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
307 u8 command, u8 value)
309 union i2c_smbus_data data;
314 for (i = 0; i < 3; i++) {
315 err = i2c_smbus_xfer(client->adapter, client->addr,
317 I2C_SMBUS_WRITE, command,
318 I2C_SMBUS_BYTE_DATA, &data);
323 v4l_err(client, "error writing %02x, %02x, %02x\n",
324 client->addr, command, value);
328 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
329 u8 command, unsigned length, const u8 *values)
331 union i2c_smbus_data data;
333 if (length > I2C_SMBUS_BLOCK_MAX)
334 length = I2C_SMBUS_BLOCK_MAX;
335 data.block[0] = length;
336 memcpy(data.block + 1, values, length);
337 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
338 I2C_SMBUS_WRITE, command,
339 I2C_SMBUS_I2C_BLOCK_DATA, &data);
342 /* ----------------------------------------------------------------------- */
344 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
346 struct i2c_client *client = v4l2_get_subdevdata(sd);
348 return adv_smbus_read_byte_data(client, reg);
351 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
353 struct i2c_client *client = v4l2_get_subdevdata(sd);
355 return adv_smbus_write_byte_data(client, reg, val);
358 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
360 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
363 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
365 struct adv7604_state *state = to_state(sd);
367 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
370 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
372 struct adv7604_state *state = to_state(sd);
374 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
377 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
379 struct adv7604_state *state = to_state(sd);
381 return adv_smbus_read_byte_data(state->i2c_cec, reg);
384 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
386 struct adv7604_state *state = to_state(sd);
388 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
391 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
393 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
396 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
398 struct adv7604_state *state = to_state(sd);
400 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
403 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
405 struct adv7604_state *state = to_state(sd);
407 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
410 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
412 struct adv7604_state *state = to_state(sd);
414 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
417 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
419 struct adv7604_state *state = to_state(sd);
421 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
424 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
426 struct adv7604_state *state = to_state(sd);
428 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
431 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
433 struct adv7604_state *state = to_state(sd);
435 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
438 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
440 struct adv7604_state *state = to_state(sd);
442 return adv_smbus_read_byte_data(state->i2c_afe, reg);
445 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
447 struct adv7604_state *state = to_state(sd);
449 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
452 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
454 struct adv7604_state *state = to_state(sd);
456 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
459 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
461 struct adv7604_state *state = to_state(sd);
463 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
466 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
468 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
471 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
473 struct adv7604_state *state = to_state(sd);
475 return adv_smbus_read_byte_data(state->i2c_edid, reg);
478 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
480 struct adv7604_state *state = to_state(sd);
482 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
485 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
487 struct adv7604_state *state = to_state(sd);
488 struct i2c_client *client = state->i2c_edid;
489 u8 msgbuf0[1] = { 0 };
491 struct i2c_msg msg[2] = {
493 .addr = client->addr,
498 .addr = client->addr,
505 if (i2c_transfer(client->adapter, msg, 2) < 0)
507 memcpy(val, msgbuf1, len);
511 static inline int edid_write_block(struct v4l2_subdev *sd,
512 unsigned len, const u8 *val)
514 struct adv7604_state *state = to_state(sd);
518 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
520 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
521 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
522 I2C_SMBUS_BLOCK_MAX, val + i);
526 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
528 struct delayed_work *dwork = to_delayed_work(work);
529 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
530 delayed_work_enable_hotplug);
531 struct v4l2_subdev *sd = &state->sd;
533 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
535 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
538 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
540 struct adv7604_state *state = to_state(sd);
542 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
545 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
547 struct adv7604_state *state = to_state(sd);
549 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
552 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
554 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
557 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
559 struct adv7604_state *state = to_state(sd);
561 return adv_smbus_read_byte_data(state->i2c_test, reg);
564 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
566 struct adv7604_state *state = to_state(sd);
568 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
571 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
573 struct adv7604_state *state = to_state(sd);
575 return adv_smbus_read_byte_data(state->i2c_cp, reg);
578 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
580 struct adv7604_state *state = to_state(sd);
582 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
585 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
587 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
590 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
592 struct adv7604_state *state = to_state(sd);
594 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
597 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
599 struct adv7604_state *state = to_state(sd);
601 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
604 /* ----------------------------------------------------------------------- */
606 static inline bool is_analog_input(struct v4l2_subdev *sd)
608 struct adv7604_state *state = to_state(sd);
610 return state->selected_input == ADV7604_INPUT_VGA_RGB ||
611 state->selected_input == ADV7604_INPUT_VGA_COMP;
614 static inline bool is_digital_input(struct v4l2_subdev *sd)
616 struct adv7604_state *state = to_state(sd);
618 return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
619 state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
620 state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
621 state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
624 /* ----------------------------------------------------------------------- */
626 #ifdef CONFIG_VIDEO_ADV_DEBUG
627 static void adv7604_inv_register(struct v4l2_subdev *sd)
629 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
630 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
631 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
632 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
633 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
634 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
635 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
636 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
637 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
638 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
639 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
640 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
641 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
644 static int adv7604_g_register(struct v4l2_subdev *sd,
645 struct v4l2_dbg_register *reg)
648 switch (reg->reg >> 8) {
650 reg->val = io_read(sd, reg->reg & 0xff);
653 reg->val = avlink_read(sd, reg->reg & 0xff);
656 reg->val = cec_read(sd, reg->reg & 0xff);
659 reg->val = infoframe_read(sd, reg->reg & 0xff);
662 reg->val = esdp_read(sd, reg->reg & 0xff);
665 reg->val = dpp_read(sd, reg->reg & 0xff);
668 reg->val = afe_read(sd, reg->reg & 0xff);
671 reg->val = rep_read(sd, reg->reg & 0xff);
674 reg->val = edid_read(sd, reg->reg & 0xff);
677 reg->val = hdmi_read(sd, reg->reg & 0xff);
680 reg->val = test_read(sd, reg->reg & 0xff);
683 reg->val = cp_read(sd, reg->reg & 0xff);
686 reg->val = vdp_read(sd, reg->reg & 0xff);
689 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
690 adv7604_inv_register(sd);
696 static int adv7604_s_register(struct v4l2_subdev *sd,
697 const struct v4l2_dbg_register *reg)
699 u8 val = reg->val & 0xff;
701 switch (reg->reg >> 8) {
703 io_write(sd, reg->reg & 0xff, val);
706 avlink_write(sd, reg->reg & 0xff, val);
709 cec_write(sd, reg->reg & 0xff, val);
712 infoframe_write(sd, reg->reg & 0xff, val);
715 esdp_write(sd, reg->reg & 0xff, val);
718 dpp_write(sd, reg->reg & 0xff, val);
721 afe_write(sd, reg->reg & 0xff, val);
724 rep_write(sd, reg->reg & 0xff, val);
727 edid_write(sd, reg->reg & 0xff, val);
730 hdmi_write(sd, reg->reg & 0xff, val);
733 test_write(sd, reg->reg & 0xff, val);
736 cp_write(sd, reg->reg & 0xff, val);
739 vdp_write(sd, reg->reg & 0xff, val);
742 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
743 adv7604_inv_register(sd);
750 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
752 struct adv7604_state *state = to_state(sd);
753 u8 reg_io_6f = io_read(sd, 0x6f);
755 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
756 ((reg_io_6f & 0x10) >> 4) |
757 ((reg_io_6f & 0x08) >> 2) |
759 ((reg_io_6f & 0x02) << 2));
762 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
764 const struct adv7604_video_standards *predef_vid_timings,
765 const struct v4l2_dv_timings *timings)
769 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
770 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
771 is_digital_input(sd) ? 250000 : 1000000))
773 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
774 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
775 prim_mode); /* v_freq and prim mode */
782 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
783 struct v4l2_dv_timings *timings)
785 struct adv7604_state *state = to_state(sd);
788 v4l2_dbg(1, debug, sd, "%s", __func__);
790 /* reset to default values */
791 io_write(sd, 0x16, 0x43);
792 io_write(sd, 0x17, 0x5a);
793 /* disable embedded syncs for auto graphics mode */
794 cp_write_and_or(sd, 0x81, 0xef, 0x00);
795 cp_write(sd, 0x8f, 0x00);
796 cp_write(sd, 0x90, 0x00);
797 cp_write(sd, 0xa2, 0x00);
798 cp_write(sd, 0xa3, 0x00);
799 cp_write(sd, 0xa4, 0x00);
800 cp_write(sd, 0xa5, 0x00);
801 cp_write(sd, 0xa6, 0x00);
802 cp_write(sd, 0xa7, 0x00);
803 cp_write(sd, 0xab, 0x00);
804 cp_write(sd, 0xac, 0x00);
806 if (is_analog_input(sd)) {
807 err = find_and_set_predefined_video_timings(sd,
808 0x01, adv7604_prim_mode_comp, timings);
810 err = find_and_set_predefined_video_timings(sd,
811 0x02, adv7604_prim_mode_gr, timings);
812 } else if (is_digital_input(sd)) {
813 err = find_and_set_predefined_video_timings(sd,
814 0x05, adv7604_prim_mode_hdmi_comp, timings);
816 err = find_and_set_predefined_video_timings(sd,
817 0x06, adv7604_prim_mode_hdmi_gr, timings);
819 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
820 __func__, state->selected_input);
828 static void configure_custom_video_timings(struct v4l2_subdev *sd,
829 const struct v4l2_bt_timings *bt)
831 struct adv7604_state *state = to_state(sd);
832 struct i2c_client *client = v4l2_get_subdevdata(sd);
833 u32 width = htotal(bt);
834 u32 height = vtotal(bt);
835 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
836 u16 cp_start_eav = width - bt->hfrontporch;
837 u16 cp_start_vbi = height - bt->vfrontporch;
838 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
839 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
840 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
842 0xc0 | ((width >> 8) & 0x1f),
846 v4l2_dbg(2, debug, sd, "%s\n", __func__);
848 if (is_analog_input(sd)) {
850 io_write(sd, 0x00, 0x07); /* video std */
851 io_write(sd, 0x01, 0x02); /* prim mode */
852 /* enable embedded syncs for auto graphics mode */
853 cp_write_and_or(sd, 0x81, 0xef, 0x10);
855 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
856 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
857 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
858 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
859 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
861 /* active video - horizontal timing */
862 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
863 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
864 ((cp_start_eav >> 8) & 0x0f));
865 cp_write(sd, 0xa4, cp_start_eav & 0xff);
867 /* active video - vertical timing */
868 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
869 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
870 ((cp_end_vbi >> 8) & 0xf));
871 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
872 } else if (is_digital_input(sd)) {
873 /* set default prim_mode/vid_std for HDMI
874 according to [REF_03, c. 4.2] */
875 io_write(sd, 0x00, 0x02); /* video std */
876 io_write(sd, 0x01, 0x06); /* prim mode */
878 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
879 __func__, state->selected_input);
882 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
883 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
884 cp_write(sd, 0xab, (height >> 4) & 0xff);
885 cp_write(sd, 0xac, (height & 0x0f) << 4);
888 static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
890 struct adv7604_state *state = to_state(sd);
899 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
900 __func__, auto_offset ? "Auto" : "Manual",
901 offset_a, offset_b, offset_c);
903 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
904 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
905 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
906 offset_buf[3] = offset_c & 0x0ff;
908 /* Registers must be written in this order with no i2c access in between */
909 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
910 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
913 static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
915 struct adv7604_state *state = to_state(sd);
928 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
929 __func__, auto_gain ? "Auto" : "Manual",
930 gain_a, gain_b, gain_c);
932 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
933 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
934 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
935 gain_buf[3] = ((gain_c & 0x0ff));
937 /* Registers must be written in this order with no i2c access in between */
938 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
939 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
942 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
944 struct adv7604_state *state = to_state(sd);
945 bool rgb_output = io_read(sd, 0x02) & 0x02;
946 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
948 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
949 __func__, state->rgb_quantization_range,
950 rgb_output, hdmi_signal);
952 adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
953 adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
955 switch (state->rgb_quantization_range) {
956 case V4L2_DV_RGB_RANGE_AUTO:
957 if (state->selected_input == ADV7604_INPUT_VGA_RGB) {
958 /* Receiving analog RGB signal
959 * Set RGB full range (0-255) */
960 io_write_and_or(sd, 0x02, 0x0f, 0x10);
964 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
965 /* Receiving analog YPbPr signal
967 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
972 /* Receiving HDMI signal
974 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
978 /* Receiving DVI-D signal
979 * ADV7604 selects RGB limited range regardless of
980 * input format (CE/IT) in automatic mode */
981 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
982 /* RGB limited range (16-235) */
983 io_write_and_or(sd, 0x02, 0x0f, 0x00);
985 /* RGB full range (0-255) */
986 io_write_and_or(sd, 0x02, 0x0f, 0x10);
988 if (is_digital_input(sd) && rgb_output) {
989 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
991 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
992 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
996 case V4L2_DV_RGB_RANGE_LIMITED:
997 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
998 /* YCrCb limited range (16-235) */
999 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1003 /* RGB limited range (16-235) */
1004 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1007 case V4L2_DV_RGB_RANGE_FULL:
1008 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
1009 /* YCrCb full range (0-255) */
1010 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1014 /* RGB full range (0-255) */
1015 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1017 if (is_analog_input(sd) || hdmi_signal)
1020 /* Adjust gain/offset for DVI-D signals only */
1022 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1024 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1025 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1031 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1033 struct v4l2_subdev *sd = to_sd(ctrl);
1034 struct adv7604_state *state = to_state(sd);
1037 case V4L2_CID_BRIGHTNESS:
1038 cp_write(sd, 0x3c, ctrl->val);
1040 case V4L2_CID_CONTRAST:
1041 cp_write(sd, 0x3a, ctrl->val);
1043 case V4L2_CID_SATURATION:
1044 cp_write(sd, 0x3b, ctrl->val);
1047 cp_write(sd, 0x3d, ctrl->val);
1049 case V4L2_CID_DV_RX_RGB_RANGE:
1050 state->rgb_quantization_range = ctrl->val;
1051 set_rgb_quantization_range(sd);
1053 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1054 /* Set the analog sampling phase. This is needed to find the
1055 best sampling phase for analog video: an application or
1056 driver has to try a number of phases and analyze the picture
1057 quality before settling on the best performing phase. */
1058 afe_write(sd, 0xc8, ctrl->val);
1060 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1061 /* Use the default blue color for free running mode,
1062 or supply your own. */
1063 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1065 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1066 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1067 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1068 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1074 /* ----------------------------------------------------------------------- */
1076 static inline bool no_power(struct v4l2_subdev *sd)
1078 /* Entire chip or CP powered off */
1079 return io_read(sd, 0x0c) & 0x24;
1082 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1084 struct adv7604_state *state = to_state(sd);
1086 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1089 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1091 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1094 static inline bool is_hdmi(struct v4l2_subdev *sd)
1096 return hdmi_read(sd, 0x05) & 0x80;
1099 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1101 /* TODO channel 2 */
1102 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1105 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1107 /* TODO channel 2 */
1108 return !(cp_read(sd, 0xb1) & 0x80);
1111 static inline bool no_signal(struct v4l2_subdev *sd)
1117 ret |= no_lock_stdi(sd);
1118 ret |= no_lock_sspd(sd);
1120 if (is_digital_input(sd)) {
1121 ret |= no_lock_tmds(sd);
1122 ret |= no_signal_tmds(sd);
1128 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1130 /* CP has detected a non standard number of lines on the incoming
1131 video compared to what it is configured to receive by s_dv_timings */
1132 return io_read(sd, 0x12) & 0x01;
1135 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1138 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1139 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1141 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1143 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1148 /* ----------------------------------------------------------------------- */
1150 struct stdi_readback {
1156 static int stdi2dv_timings(struct v4l2_subdev *sd,
1157 struct stdi_readback *stdi,
1158 struct v4l2_dv_timings *timings)
1160 struct adv7604_state *state = to_state(sd);
1161 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1165 for (i = 0; adv7604_timings[i].bt.height; i++) {
1166 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1168 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1171 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1173 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1174 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1175 *timings = adv7604_timings[i];
1180 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1181 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1182 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1185 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1186 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1187 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1188 state->aspect_ratio, timings))
1191 v4l2_dbg(2, debug, sd,
1192 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1193 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1194 stdi->hs_pol, stdi->vs_pol);
1198 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1200 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1201 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1206 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1207 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1208 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1209 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1212 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1213 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1214 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1215 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1216 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1222 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1223 v4l2_dbg(2, debug, sd,
1224 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1228 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1229 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1230 memset(stdi, 0, sizeof(struct stdi_readback));
1234 v4l2_dbg(2, debug, sd,
1235 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1236 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1237 stdi->hs_pol, stdi->vs_pol,
1238 stdi->interlaced ? "interlaced" : "progressive");
1243 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1244 struct v4l2_enum_dv_timings *timings)
1246 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1248 memset(timings->reserved, 0, sizeof(timings->reserved));
1249 timings->timings = adv7604_timings[timings->index];
1253 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1254 struct v4l2_dv_timings_cap *cap)
1256 cap->type = V4L2_DV_BT_656_1120;
1257 cap->bt.max_width = 1920;
1258 cap->bt.max_height = 1200;
1259 cap->bt.min_pixelclock = 25000000;
1260 if (is_digital_input(sd))
1261 cap->bt.max_pixelclock = 225000000;
1263 cap->bt.max_pixelclock = 170000000;
1264 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1265 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1266 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1267 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1271 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1272 if the format is listed in adv7604_timings[] */
1273 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1274 struct v4l2_dv_timings *timings)
1278 for (i = 0; adv7604_timings[i].bt.width; i++) {
1279 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
1280 is_digital_input(sd) ? 250000 : 1000000)) {
1281 *timings = adv7604_timings[i];
1287 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1288 struct v4l2_dv_timings *timings)
1290 struct adv7604_state *state = to_state(sd);
1291 struct v4l2_bt_timings *bt = &timings->bt;
1292 struct stdi_readback stdi;
1297 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1299 if (no_signal(sd)) {
1300 state->restart_stdi_once = true;
1301 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1306 if (read_stdi(sd, &stdi)) {
1307 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1310 bt->interlaced = stdi.interlaced ?
1311 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1313 if (is_digital_input(sd)) {
1316 timings->type = V4L2_DV_BT_656_1120;
1318 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1319 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1320 freq = (hdmi_read(sd, 0x06) * 1000000) +
1321 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1323 /* adjust for deep color mode */
1324 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1326 freq = freq * 8 / bits_per_channel;
1328 bt->pixelclock = freq;
1329 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1330 hdmi_read(sd, 0x21);
1331 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1332 hdmi_read(sd, 0x23);
1333 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1334 hdmi_read(sd, 0x25);
1335 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1336 hdmi_read(sd, 0x2b)) / 2;
1337 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1338 hdmi_read(sd, 0x2f)) / 2;
1339 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1340 hdmi_read(sd, 0x33)) / 2;
1341 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1342 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1343 if (bt->interlaced == V4L2_DV_INTERLACED) {
1344 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1345 hdmi_read(sd, 0x0c);
1346 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1347 hdmi_read(sd, 0x2d)) / 2;
1348 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1349 hdmi_read(sd, 0x31)) / 2;
1350 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1351 hdmi_read(sd, 0x35)) / 2;
1353 adv7604_fill_optional_dv_timings_fields(sd, timings);
1356 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1357 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1359 if (!stdi2dv_timings(sd, &stdi, timings))
1362 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1363 if (!stdi2dv_timings(sd, &stdi, timings))
1366 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1367 if (stdi2dv_timings(sd, &stdi, timings)) {
1369 * The STDI block may measure wrong values, especially
1370 * for lcvs and lcf. If the driver can not find any
1371 * valid timing, the STDI block is restarted to measure
1372 * the video timings again. The function will return an
1373 * error, but the restart of STDI will generate a new
1374 * STDI interrupt and the format detection process will
1377 if (state->restart_stdi_once) {
1378 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1379 /* TODO restart STDI for Sync Channel 2 */
1380 /* enter one-shot mode */
1381 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1382 /* trigger STDI restart */
1383 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1384 /* reset to continuous mode */
1385 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1386 state->restart_stdi_once = false;
1389 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1392 state->restart_stdi_once = true;
1396 if (no_signal(sd)) {
1397 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1398 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1402 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1403 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1404 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1405 __func__, (u32)bt->pixelclock);
1410 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1416 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1417 struct v4l2_dv_timings *timings)
1419 struct adv7604_state *state = to_state(sd);
1420 struct v4l2_bt_timings *bt;
1428 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1429 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1430 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1431 __func__, (u32)bt->pixelclock);
1435 adv7604_fill_optional_dv_timings_fields(sd, timings);
1437 state->timings = *timings;
1439 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1441 /* Use prim_mode and vid_std when available */
1442 err = configure_predefined_video_timings(sd, timings);
1444 /* custom settings when the video format
1445 does not have prim_mode/vid_std */
1446 configure_custom_video_timings(sd, bt);
1449 set_rgb_quantization_range(sd);
1452 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1457 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1458 struct v4l2_dv_timings *timings)
1460 struct adv7604_state *state = to_state(sd);
1462 *timings = state->timings;
1466 static void enable_input(struct v4l2_subdev *sd)
1468 struct adv7604_state *state = to_state(sd);
1470 if (is_analog_input(sd)) {
1471 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1472 } else if (is_digital_input(sd)) {
1473 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
1474 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1475 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1476 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1478 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1479 __func__, state->selected_input);
1483 static void disable_input(struct v4l2_subdev *sd)
1485 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio */
1486 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1487 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1488 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1491 static void select_input(struct v4l2_subdev *sd)
1493 struct adv7604_state *state = to_state(sd);
1495 if (is_analog_input(sd)) {
1496 /* reset ADI recommended settings for HDMI: */
1497 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1498 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1499 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1500 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1501 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1502 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1503 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1504 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1505 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1506 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1507 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1508 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1510 afe_write(sd, 0x00, 0x08); /* power up ADC */
1511 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1512 afe_write(sd, 0xc8, 0x00); /* phase control */
1514 /* set ADI recommended settings for digitizer */
1515 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1516 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1517 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1518 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1519 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1520 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1521 } else if (is_digital_input(sd)) {
1522 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1524 /* set ADI recommended settings for HDMI: */
1525 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1526 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1527 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1528 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1529 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1530 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1531 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1532 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1533 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1534 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1535 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1536 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1538 afe_write(sd, 0x00, 0xff); /* power down ADC */
1539 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1540 afe_write(sd, 0xc8, 0x40); /* phase control */
1542 /* reset ADI recommended settings for digitizer */
1543 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1544 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1545 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1546 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1547 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1548 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1550 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1551 __func__, state->selected_input);
1555 static int adv7604_s_routing(struct v4l2_subdev *sd,
1556 u32 input, u32 output, u32 config)
1558 struct adv7604_state *state = to_state(sd);
1560 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1561 __func__, input, state->selected_input);
1563 if (input == state->selected_input)
1566 state->selected_input = input;
1577 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1578 enum v4l2_mbus_pixelcode *code)
1582 /* Good enough for now */
1583 *code = V4L2_MBUS_FMT_FIXED;
1587 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1588 struct v4l2_mbus_framefmt *fmt)
1590 struct adv7604_state *state = to_state(sd);
1592 fmt->width = state->timings.bt.width;
1593 fmt->height = state->timings.bt.height;
1594 fmt->code = V4L2_MBUS_FMT_FIXED;
1595 fmt->field = V4L2_FIELD_NONE;
1596 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1597 fmt->colorspace = (state->timings.bt.height <= 576) ?
1598 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1603 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1605 u8 fmt_change, fmt_change_digital, tx_5v;
1607 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1610 fmt_change = io_read(sd, 0x43) & 0x98;
1612 io_write(sd, 0x44, fmt_change);
1614 fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0;
1615 if (fmt_change_digital)
1616 io_write(sd, 0x6c, fmt_change_digital);
1618 if (fmt_change || fmt_change_digital) {
1619 v4l2_dbg(1, debug, sd,
1620 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1621 __func__, fmt_change, fmt_change_digital);
1623 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1629 tx_5v = io_read(sd, 0x70) & 0x1e;
1631 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1632 io_write(sd, 0x71, tx_5v);
1633 adv7604_s_detect_tx_5v_ctrl(sd);
1640 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1642 struct adv7604_state *state = to_state(sd);
1645 if (edid->pad > ADV7604_EDID_PORT_D)
1647 if (edid->blocks == 0)
1649 if (edid->blocks > 2)
1651 if (edid->start_block > 1)
1653 if (edid->start_block == 1)
1658 if (edid->blocks > state->edid.blocks)
1659 edid->blocks = state->edid.blocks;
1661 switch (edid->pad) {
1662 case ADV7604_EDID_PORT_A:
1663 case ADV7604_EDID_PORT_B:
1664 case ADV7604_EDID_PORT_C:
1665 case ADV7604_EDID_PORT_D:
1666 if (state->edid.present & (1 << edid->pad))
1667 data = state->edid.edid;
1677 data + edid->start_block * 128,
1678 edid->blocks * 128);
1682 static int get_edid_spa_location(const u8 *edid)
1686 if ((edid[0x7e] != 1) ||
1687 (edid[0x80] != 0x02) ||
1688 (edid[0x81] != 0x03)) {
1692 /* search Vendor Specific Data Block (tag 3) */
1693 d = edid[0x82] & 0x7f;
1699 u8 tag = edid[i] >> 5;
1700 u8 len = edid[i] & 0x1f;
1702 if ((tag == 3) && (len >= 5))
1710 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1712 struct adv7604_state *state = to_state(sd);
1718 if (edid->pad > ADV7604_EDID_PORT_D)
1720 if (edid->start_block != 0)
1722 if (edid->blocks == 0) {
1723 /* Disable hotplug and I2C access to EDID RAM from DDC port */
1724 state->edid.present &= ~(1 << edid->pad);
1725 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
1726 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1728 /* Fall back to a 16:9 aspect ratio */
1729 state->aspect_ratio.numerator = 16;
1730 state->aspect_ratio.denominator = 9;
1732 if (!state->edid.present)
1733 state->edid.blocks = 0;
1735 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
1736 __func__, edid->pad, state->edid.present);
1739 if (edid->blocks > 2) {
1746 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
1747 __func__, edid->pad, state->edid.present);
1749 /* Disable hotplug and I2C access to EDID RAM from DDC port */
1750 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
1751 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
1752 rep_write_and_or(sd, 0x77, 0xf0, 0x00);
1754 spa_loc = get_edid_spa_location(edid->edid);
1756 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
1758 switch (edid->pad) {
1759 case ADV7604_EDID_PORT_A:
1760 state->spa_port_a[0] = edid->edid[spa_loc];
1761 state->spa_port_a[1] = edid->edid[spa_loc + 1];
1763 case ADV7604_EDID_PORT_B:
1764 rep_write(sd, 0x70, edid->edid[spa_loc]);
1765 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
1767 case ADV7604_EDID_PORT_C:
1768 rep_write(sd, 0x72, edid->edid[spa_loc]);
1769 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
1771 case ADV7604_EDID_PORT_D:
1772 rep_write(sd, 0x74, edid->edid[spa_loc]);
1773 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
1778 rep_write(sd, 0x76, spa_loc & 0xff);
1779 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
1781 edid->edid[spa_loc] = state->spa_port_a[0];
1782 edid->edid[spa_loc + 1] = state->spa_port_a[1];
1784 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1785 state->edid.blocks = edid->blocks;
1786 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1788 state->edid.present |= 1 << edid->pad;
1790 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1792 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
1796 /* adv7604 calculates the checksums and enables I2C access to internal
1797 EDID RAM from DDC port. */
1798 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1800 for (i = 0; i < 1000; i++) {
1801 if (rep_read(sd, 0x7d) & state->edid.present)
1806 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
1811 /* enable hotplug after 100 ms */
1812 queue_delayed_work(state->work_queues,
1813 &state->delayed_work_enable_hotplug, HZ / 10);
1817 /*********** avi info frame CEA-861-E **************/
1819 static void print_avi_infoframe(struct v4l2_subdev *sd)
1827 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1830 if (!(io_read(sd, 0x60) & 0x01)) {
1831 v4l2_info(sd, "AVI infoframe not received\n");
1835 if (io_read(sd, 0x83) & 0x01) {
1836 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1837 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1838 if (io_read(sd, 0x83) & 0x01) {
1839 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1840 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1844 avi_len = infoframe_read(sd, 0xe2);
1845 avi_ver = infoframe_read(sd, 0xe1);
1846 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1849 if (avi_ver != 0x02)
1852 for (i = 0; i < 14; i++)
1853 buf[i] = infoframe_read(sd, i);
1856 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1857 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1858 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1861 static int adv7604_log_status(struct v4l2_subdev *sd)
1863 struct adv7604_state *state = to_state(sd);
1864 struct v4l2_dv_timings timings;
1865 struct stdi_readback stdi;
1866 u8 reg_io_0x02 = io_read(sd, 0x02);
1868 char *csc_coeff_sel_rb[16] = {
1869 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1870 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1871 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1872 "reserved", "reserved", "reserved", "reserved", "manual"
1874 char *input_color_space_txt[16] = {
1875 "RGB limited range (16-235)", "RGB full range (0-255)",
1876 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1877 "xvYCC Bt.601", "xvYCC Bt.709",
1878 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1879 "invalid", "invalid", "invalid", "invalid", "invalid",
1880 "invalid", "invalid", "automatic"
1882 char *rgb_quantization_range_txt[] = {
1884 "RGB limited range (16-235)",
1885 "RGB full range (0-255)",
1887 char *deep_color_mode_txt[4] = {
1888 "8-bits per channel",
1889 "10-bits per channel",
1890 "12-bits per channel",
1891 "16-bits per channel (not supported)"
1894 v4l2_info(sd, "-----Chip status-----\n");
1895 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1896 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1897 ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1898 ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1899 ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1900 ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
1901 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1902 "enabled" : "disabled");
1904 v4l2_info(sd, "-----Signal status-----\n");
1905 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1906 ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1907 ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1908 ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1909 ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
1910 v4l2_info(sd, "TMDS signal detected: %s\n",
1911 no_signal_tmds(sd) ? "false" : "true");
1912 v4l2_info(sd, "TMDS signal locked: %s\n",
1913 no_lock_tmds(sd) ? "false" : "true");
1914 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1915 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1916 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1917 v4l2_info(sd, "CP free run: %s\n",
1918 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1919 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1920 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1921 (io_read(sd, 0x01) & 0x70) >> 4);
1923 v4l2_info(sd, "-----Video Timings-----\n");
1924 if (read_stdi(sd, &stdi))
1925 v4l2_info(sd, "STDI: not locked\n");
1927 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1928 stdi.lcf, stdi.bl, stdi.lcvs,
1929 stdi.interlaced ? "interlaced" : "progressive",
1930 stdi.hs_pol, stdi.vs_pol);
1931 if (adv7604_query_dv_timings(sd, &timings))
1932 v4l2_info(sd, "No video detected\n");
1934 v4l2_print_dv_timings(sd->name, "Detected format: ",
1936 v4l2_print_dv_timings(sd->name, "Configured format: ",
1937 &state->timings, true);
1942 v4l2_info(sd, "-----Color space-----\n");
1943 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1944 rgb_quantization_range_txt[state->rgb_quantization_range]);
1945 v4l2_info(sd, "Input color space: %s\n",
1946 input_color_space_txt[reg_io_0x02 >> 4]);
1947 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1948 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1949 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1950 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1951 "enabled" : "disabled");
1952 v4l2_info(sd, "Color space conversion: %s\n",
1953 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1955 if (!is_digital_input(sd))
1958 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1959 v4l2_info(sd, "Digital video port selected: %c\n",
1960 (hdmi_read(sd, 0x00) & 0x03) + 'A');
1961 v4l2_info(sd, "HDCP encrypted content: %s\n",
1962 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
1963 v4l2_info(sd, "HDCP keys read: %s%s\n",
1964 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1965 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1967 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1968 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1969 bool audio_mute = io_read(sd, 0x65) & 0x40;
1971 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1972 audio_pll_locked ? "locked" : "not locked",
1973 audio_sample_packet_detect ? "detected" : "not detected",
1974 audio_mute ? "muted" : "enabled");
1975 if (audio_pll_locked && audio_sample_packet_detect) {
1976 v4l2_info(sd, "Audio format: %s\n",
1977 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1979 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1980 (hdmi_read(sd, 0x5c) << 8) +
1981 (hdmi_read(sd, 0x5d) & 0xf0));
1982 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
1983 (hdmi_read(sd, 0x5e) << 8) +
1984 hdmi_read(sd, 0x5f));
1985 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
1987 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
1989 print_avi_infoframe(sd);
1995 /* ----------------------------------------------------------------------- */
1997 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1998 .s_ctrl = adv7604_s_ctrl,
2001 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
2002 .log_status = adv7604_log_status,
2003 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
2004 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
2005 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
2006 .g_ctrl = v4l2_subdev_g_ctrl,
2007 .s_ctrl = v4l2_subdev_s_ctrl,
2008 .queryctrl = v4l2_subdev_queryctrl,
2009 .querymenu = v4l2_subdev_querymenu,
2010 .interrupt_service_routine = adv7604_isr,
2011 #ifdef CONFIG_VIDEO_ADV_DEBUG
2012 .g_register = adv7604_g_register,
2013 .s_register = adv7604_s_register,
2017 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
2018 .s_routing = adv7604_s_routing,
2019 .g_input_status = adv7604_g_input_status,
2020 .s_dv_timings = adv7604_s_dv_timings,
2021 .g_dv_timings = adv7604_g_dv_timings,
2022 .query_dv_timings = adv7604_query_dv_timings,
2023 .enum_dv_timings = adv7604_enum_dv_timings,
2024 .dv_timings_cap = adv7604_dv_timings_cap,
2025 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
2026 .g_mbus_fmt = adv7604_g_mbus_fmt,
2027 .try_mbus_fmt = adv7604_g_mbus_fmt,
2028 .s_mbus_fmt = adv7604_g_mbus_fmt,
2031 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
2032 .get_edid = adv7604_get_edid,
2033 .set_edid = adv7604_set_edid,
2036 static const struct v4l2_subdev_ops adv7604_ops = {
2037 .core = &adv7604_core_ops,
2038 .video = &adv7604_video_ops,
2039 .pad = &adv7604_pad_ops,
2042 /* -------------------------- custom ctrls ---------------------------------- */
2044 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2045 .ops = &adv7604_ctrl_ops,
2046 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2047 .name = "Analog Sampling Phase",
2048 .type = V4L2_CTRL_TYPE_INTEGER,
2055 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2056 .ops = &adv7604_ctrl_ops,
2057 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2058 .name = "Free Running Color, Manual",
2059 .type = V4L2_CTRL_TYPE_BOOLEAN,
2066 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2067 .ops = &adv7604_ctrl_ops,
2068 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2069 .name = "Free Running Color",
2070 .type = V4L2_CTRL_TYPE_INTEGER,
2077 /* ----------------------------------------------------------------------- */
2079 static int adv7604_core_init(struct v4l2_subdev *sd)
2081 struct adv7604_state *state = to_state(sd);
2082 struct adv7604_platform_data *pdata = &state->pdata;
2084 hdmi_write(sd, 0x48,
2085 (pdata->disable_pwrdnb ? 0x80 : 0) |
2086 (pdata->disable_cable_det_rst ? 0x40 : 0));
2091 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2092 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2093 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2096 io_write_and_or(sd, 0x02, 0xf0,
2097 pdata->alt_gamma << 3 |
2098 pdata->op_656_range << 2 |
2099 pdata->rgb_out << 1 |
2100 pdata->alt_data_sat << 0);
2101 io_write(sd, 0x03, pdata->op_format_sel);
2102 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2103 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2104 pdata->insert_av_codes << 2 |
2105 pdata->replicate_av_codes << 1 |
2106 pdata->invert_cbcr << 0);
2108 /* TODO from platform data */
2109 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2110 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
2112 /* Adjust drive strength */
2113 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2114 pdata->dr_str_clk << 2 |
2115 pdata->dr_str_sync);
2117 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2118 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2119 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2120 ADI recommended setting [REF_01, c. 2.3.3] */
2121 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2122 ADI recommended setting [REF_01, c. 2.3.3] */
2123 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2124 for digital formats */
2127 hdmi_write_and_or(sd, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2128 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2129 hdmi_write_and_or(sd, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2131 /* TODO from platform data */
2132 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2134 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2135 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2138 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
2139 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2140 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2141 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2142 io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
2144 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2147 static void adv7604_unregister_clients(struct adv7604_state *state)
2149 if (state->i2c_avlink)
2150 i2c_unregister_device(state->i2c_avlink);
2152 i2c_unregister_device(state->i2c_cec);
2153 if (state->i2c_infoframe)
2154 i2c_unregister_device(state->i2c_infoframe);
2155 if (state->i2c_esdp)
2156 i2c_unregister_device(state->i2c_esdp);
2158 i2c_unregister_device(state->i2c_dpp);
2160 i2c_unregister_device(state->i2c_afe);
2161 if (state->i2c_repeater)
2162 i2c_unregister_device(state->i2c_repeater);
2163 if (state->i2c_edid)
2164 i2c_unregister_device(state->i2c_edid);
2165 if (state->i2c_hdmi)
2166 i2c_unregister_device(state->i2c_hdmi);
2167 if (state->i2c_test)
2168 i2c_unregister_device(state->i2c_test);
2170 i2c_unregister_device(state->i2c_cp);
2172 i2c_unregister_device(state->i2c_vdp);
2175 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2178 struct i2c_client *client = v4l2_get_subdevdata(sd);
2181 io_write(sd, io_reg, addr << 1);
2182 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2185 static int adv7604_probe(struct i2c_client *client,
2186 const struct i2c_device_id *id)
2188 struct adv7604_state *state;
2189 struct adv7604_platform_data *pdata = client->dev.platform_data;
2190 struct v4l2_ctrl_handler *hdl;
2191 struct v4l2_subdev *sd;
2194 /* Check if the adapter supports the needed features */
2195 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2197 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2200 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2202 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2206 /* initialize variables */
2207 state->restart_stdi_once = true;
2208 state->selected_input = ~0;
2212 v4l_err(client, "No platform data!\n");
2215 memcpy(&state->pdata, pdata, sizeof(state->pdata));
2218 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2219 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2221 /* i2c access to adv7604? */
2222 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2223 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2228 /* control handlers */
2230 v4l2_ctrl_handler_init(hdl, 9);
2232 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2233 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2234 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2235 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2236 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2237 V4L2_CID_SATURATION, 0, 255, 1, 128);
2238 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2239 V4L2_CID_HUE, 0, 128, 1, 0);
2241 /* private controls */
2242 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2243 V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
2244 state->rgb_quantization_range_ctrl =
2245 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2246 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2247 0, V4L2_DV_RGB_RANGE_AUTO);
2249 /* custom controls */
2250 state->analog_sampling_phase_ctrl =
2251 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2252 state->free_run_color_manual_ctrl =
2253 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2254 state->free_run_color_ctrl =
2255 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2257 sd->ctrl_handler = hdl;
2262 state->detect_tx_5v_ctrl->is_private = true;
2263 state->rgb_quantization_range_ctrl->is_private = true;
2264 state->analog_sampling_phase_ctrl->is_private = true;
2265 state->free_run_color_manual_ctrl->is_private = true;
2266 state->free_run_color_ctrl->is_private = true;
2268 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2273 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2274 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2275 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2276 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2277 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2278 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2279 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2280 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2281 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2282 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2283 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2284 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2285 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2286 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2287 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2288 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2290 v4l2_err(sd, "failed to create all i2c clients\n");
2295 state->work_queues = create_singlethread_workqueue(client->name);
2296 if (!state->work_queues) {
2297 v4l2_err(sd, "Could not create work queue\n");
2302 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2303 adv7604_delayed_work_enable_hotplug);
2305 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2306 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2308 goto err_work_queues;
2310 err = adv7604_core_init(sd);
2313 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2314 client->addr << 1, client->adapter->name);
2318 media_entity_cleanup(&sd->entity);
2320 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2321 destroy_workqueue(state->work_queues);
2323 adv7604_unregister_clients(state);
2325 v4l2_ctrl_handler_free(hdl);
2329 /* ----------------------------------------------------------------------- */
2331 static int adv7604_remove(struct i2c_client *client)
2333 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2334 struct adv7604_state *state = to_state(sd);
2336 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2337 destroy_workqueue(state->work_queues);
2338 v4l2_device_unregister_subdev(sd);
2339 media_entity_cleanup(&sd->entity);
2340 adv7604_unregister_clients(to_state(sd));
2341 v4l2_ctrl_handler_free(sd->ctrl_handler);
2345 /* ----------------------------------------------------------------------- */
2347 static struct i2c_device_id adv7604_id[] = {
2351 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2353 static struct i2c_driver adv7604_driver = {
2355 .owner = THIS_MODULE,
2358 .probe = adv7604_probe,
2359 .remove = adv7604_remove,
2360 .id_table = adv7604_id,
2363 module_i2c_driver(adv7604_driver);