drivers/media/i2c/adv7842.c

   1 /*
   2  * adv7842 - Analog Devices ADV7842 video decoder driver
   3  *
   4  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7842, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Software User Guide, UG-206,
  26  *              ADV7842 I2C Register Maps, Rev. 0, November 2010
  27  */
  28
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/i2c.h>
  34 #include <linux/delay.h>
  35 #include <linux/videodev2.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/v4l2-dv-timings.h>
  38 #include <media/v4l2-device.h>
  39 #include <media/v4l2-ctrls.h>
  40 #include <media/v4l2-dv-timings.h>
  41 #include <media/adv7842.h>
  42
  43 static int debug;
  44 module_param(debug, int, 0644);
  45 MODULE_PARM_DESC(debug, "debug level (0-2)");
  46
  47 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
  48 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  49 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
  50 MODULE_LICENSE("GPL");
  51
  52 /* ADV7842 system clock frequency */
  53 #define ADV7842_fsc (28636360)
  54
  55 /*
  56 **********************************************************************
  57 *
  58 *  Arrays with configuration parameters for the ADV7842
  59 *
  60 **********************************************************************
  61 */
  62
  63 struct adv7842_state {
  64         struct adv7842_platform_data pdata;
  65         struct v4l2_subdev sd;
  66         struct media_pad pad;
  67         struct v4l2_ctrl_handler hdl;
  68         enum adv7842_mode mode;
  69         struct v4l2_dv_timings timings;
  70         enum adv7842_vid_std_select vid_std_select;
  71         v4l2_std_id norm;
  72         struct {
  73                 u8 edid[256];
  74                 u32 present;
  75         } hdmi_edid;
  76         struct {
  77                 u8 edid[256];
  78                 u32 present;
  79         } vga_edid;
  80         struct v4l2_fract aspect_ratio;
  81         u32 rgb_quantization_range;
  82         bool is_cea_format;
  83         struct workqueue_struct *work_queues;
  84         struct delayed_work delayed_work_enable_hotplug;
  85         bool hdmi_port_a;
  86
  87         /* i2c clients */
  88         struct i2c_client *i2c_sdp_io;
  89         struct i2c_client *i2c_sdp;
  90         struct i2c_client *i2c_cp;
  91         struct i2c_client *i2c_vdp;
  92         struct i2c_client *i2c_afe;
  93         struct i2c_client *i2c_hdmi;
  94         struct i2c_client *i2c_repeater;
  95         struct i2c_client *i2c_edid;
  96         struct i2c_client *i2c_infoframe;
  97         struct i2c_client *i2c_cec;
  98         struct i2c_client *i2c_avlink;
  99
 100         /* controls */
 101         struct v4l2_ctrl *detect_tx_5v_ctrl;
 102         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 103         struct v4l2_ctrl *free_run_color_ctrl_manual;
 104         struct v4l2_ctrl *free_run_color_ctrl;
 105         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 106 };
 107
 108 /* Unsupported timings. This device cannot support 720p30. */
 109 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
 110         V4L2_DV_BT_CEA_1280X720P30,
 111         { }
 112 };
 113
 114 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
 115 {
 116         int i;
 117
 118         for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
 119                 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
 120                         return false;
 121         return true;
 122 }
 123
 124 struct adv7842_video_standards {
 125         struct v4l2_dv_timings timings;
 126         u8 vid_std;
 127         u8 v_freq;
 128 };
 129
 130 /* sorted by number of lines */
 131 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
 132         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 133         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 134         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 135         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 136         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 137         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 138         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 139         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 140         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 141         /* TODO add 1920x1080P60_RB (CVT timing) */
 142         { },
 143 };
 144
 145 /* sorted by number of lines */
 146 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
 147         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 148         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 149         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 150         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 151         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 152         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 153         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 154         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 155         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 156         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 157         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 158         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 159         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 160         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 161         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 162         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 163         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 164         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 165         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 166         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 167         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 168         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 169         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 170         { },
 171 };
 172
 173 /* sorted by number of lines */
 174 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
 175         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 176         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 177         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 178         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 179         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 180         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 181         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 182         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 183         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 184         { },
 185 };
 186
 187 /* sorted by number of lines */
 188 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
 189         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 190         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 191         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 192         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 193         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 194         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 195         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 196         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 198         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 199         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 200         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 201         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 202         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 203         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 204         { },
 205 };
 206
 207 /* ----------------------------------------------------------------------- */
 208
 209 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
 210 {
 211         return container_of(sd, struct adv7842_state, sd);
 212 }
 213
 214 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 215 {
 216         return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
 217 }
 218
 219 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 220 {
 221         return V4L2_DV_BT_BLANKING_WIDTH(t);
 222 }
 223
 224 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 225 {
 226         return V4L2_DV_BT_FRAME_WIDTH(t);
 227 }
 228
 229 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 230 {
 231         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 232 }
 233
 234 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 235 {
 236         return V4L2_DV_BT_FRAME_HEIGHT(t);
 237 }
 238
 239
 240 /* ----------------------------------------------------------------------- */
 241
 242 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 243                                           u8 command, bool check)
 244 {
 245         union i2c_smbus_data data;
 246
 247         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 248                             I2C_SMBUS_READ, command,
 249                             I2C_SMBUS_BYTE_DATA, &data))
 250                 return data.byte;
 251         if (check)
 252                 v4l_err(client, "error reading %02x, %02x\n",
 253                         client->addr, command);
 254         return -EIO;
 255 }
 256
 257 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 258 {
 259         int i;
 260
 261         for (i = 0; i < 3; i++) {
 262                 int ret = adv_smbus_read_byte_data_check(client, command, true);
 263
 264                 if (ret >= 0) {
 265                         if (i)
 266                                 v4l_err(client, "read ok after %d retries\n", i);
 267                         return ret;
 268                 }
 269         }
 270         v4l_err(client, "read failed\n");
 271         return -EIO;
 272 }
 273
 274 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 275                                      u8 command, u8 value)
 276 {
 277         union i2c_smbus_data data;
 278         int err;
 279         int i;
 280
 281         data.byte = value;
 282         for (i = 0; i < 3; i++) {
 283                 err = i2c_smbus_xfer(client->adapter, client->addr,
 284                                      client->flags,
 285                                      I2C_SMBUS_WRITE, command,
 286                                      I2C_SMBUS_BYTE_DATA, &data);
 287                 if (!err)
 288                         break;
 289         }
 290         if (err < 0)
 291                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 292                         client->addr, command, value);
 293         return err;
 294 }
 295
 296 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
 297                                           u8 command, u8 value)
 298 {
 299         union i2c_smbus_data data;
 300         data.byte = value;
 301
 302         i2c_smbus_xfer(client->adapter, client->addr,
 303                        client->flags,
 304                        I2C_SMBUS_WRITE, command,
 305                        I2C_SMBUS_BYTE_DATA, &data);
 306 }
 307
 308 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 309                                   u8 command, unsigned length, const u8 *values)
 310 {
 311         union i2c_smbus_data data;
 312
 313         if (length > I2C_SMBUS_BLOCK_MAX)
 314                 length = I2C_SMBUS_BLOCK_MAX;
 315         data.block[0] = length;
 316         memcpy(data.block + 1, values, length);
 317         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 318                               I2C_SMBUS_WRITE, command,
 319                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 320 }
 321
 322 /* ----------------------------------------------------------------------- */
 323
 324 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 325 {
 326         struct i2c_client *client = v4l2_get_subdevdata(sd);
 327
 328         return adv_smbus_read_byte_data(client, reg);
 329 }
 330
 331 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 332 {
 333         struct i2c_client *client = v4l2_get_subdevdata(sd);
 334
 335         return adv_smbus_write_byte_data(client, reg, val);
 336 }
 337
 338 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 339 {
 340         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 341 }
 342
 343 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 344 {
 345         struct adv7842_state *state = to_state(sd);
 346
 347         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 348 }
 349
 350 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 351 {
 352         struct adv7842_state *state = to_state(sd);
 353
 354         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 355 }
 356
 357 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 358 {
 359         struct adv7842_state *state = to_state(sd);
 360
 361         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 362 }
 363
 364 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 365 {
 366         struct adv7842_state *state = to_state(sd);
 367
 368         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 369 }
 370
 371 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 372 {
 373         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 374 }
 375
 376 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 377 {
 378         struct adv7842_state *state = to_state(sd);
 379
 380         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 381 }
 382
 383 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 384 {
 385         struct adv7842_state *state = to_state(sd);
 386
 387         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 388 }
 389
 390 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
 391 {
 392         struct adv7842_state *state = to_state(sd);
 393
 394         return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
 395 }
 396
 397 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 398 {
 399         struct adv7842_state *state = to_state(sd);
 400
 401         return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
 402 }
 403
 404 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 405 {
 406         return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
 407 }
 408
 409 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
 410 {
 411         struct adv7842_state *state = to_state(sd);
 412
 413         return adv_smbus_read_byte_data(state->i2c_sdp, reg);
 414 }
 415
 416 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 417 {
 418         struct adv7842_state *state = to_state(sd);
 419
 420         return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
 421 }
 422
 423 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 424 {
 425         return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
 426 }
 427
 428 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 429 {
 430         struct adv7842_state *state = to_state(sd);
 431
 432         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 433 }
 434
 435 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 436 {
 437         struct adv7842_state *state = to_state(sd);
 438
 439         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 440 }
 441
 442 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 443 {
 444         return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
 445 }
 446
 447 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 448 {
 449         struct adv7842_state *state = to_state(sd);
 450
 451         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 452 }
 453
 454 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 455 {
 456         struct adv7842_state *state = to_state(sd);
 457
 458         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 459 }
 460
 461 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 462 {
 463         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 464 }
 465
 466 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 467 {
 468         struct adv7842_state *state = to_state(sd);
 469
 470         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 471 }
 472
 473 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 474 {
 475         struct adv7842_state *state = to_state(sd);
 476
 477         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 478 }
 479
 480 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 481 {
 482         struct adv7842_state *state = to_state(sd);
 483
 484         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 485 }
 486
 487 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 488 {
 489         struct adv7842_state *state = to_state(sd);
 490
 491         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 492 }
 493
 494 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 495 {
 496         struct adv7842_state *state = to_state(sd);
 497
 498         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 499 }
 500
 501 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 502 {
 503         struct adv7842_state *state = to_state(sd);
 504
 505         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 506 }
 507
 508 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 509 {
 510         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 511 }
 512
 513 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 514 {
 515         struct adv7842_state *state = to_state(sd);
 516
 517         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 518 }
 519
 520 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 521 {
 522         struct adv7842_state *state = to_state(sd);
 523
 524         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 525 }
 526
 527 static void main_reset(struct v4l2_subdev *sd)
 528 {
 529         struct i2c_client *client = v4l2_get_subdevdata(sd);
 530
 531         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 532
 533         adv_smbus_write_byte_no_check(client, 0xff, 0x80);
 534
 535         mdelay(5);
 536 }
 537
 538 /* ----------------------------------------------------------------------- */
 539
 540 static inline bool is_digital_input(struct v4l2_subdev *sd)
 541 {
 542         struct adv7842_state *state = to_state(sd);
 543
 544         return state->mode == ADV7842_MODE_HDMI;
 545 }
 546
 547 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
 548         .type = V4L2_DV_BT_656_1120,
 549         /* keep this initialization for compatibility with GCC < 4.4.6 */
 550         .reserved = { 0 },
 551         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
 552                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 553                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 554                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 555                         V4L2_DV_BT_CAP_CUSTOM)
 556 };
 557
 558 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
 559         .type = V4L2_DV_BT_656_1120,
 560         /* keep this initialization for compatibility with GCC < 4.4.6 */
 561         .reserved = { 0 },
 562         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
 563                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 564                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 565                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 566                         V4L2_DV_BT_CAP_CUSTOM)
 567 };
 568
 569 static inline const struct v4l2_dv_timings_cap *
 570 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
 571 {
 572         return is_digital_input(sd) ? &adv7842_timings_cap_digital :
 573                                       &adv7842_timings_cap_analog;
 574 }
 575
 576 /* ----------------------------------------------------------------------- */
 577
 578 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
 579 {
 580         struct delayed_work *dwork = to_delayed_work(work);
 581         struct adv7842_state *state = container_of(dwork,
 582                         struct adv7842_state, delayed_work_enable_hotplug);
 583         struct v4l2_subdev *sd = &state->sd;
 584         int present = state->hdmi_edid.present;
 585         u8 mask = 0;
 586
 587         v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
 588                         __func__, present);
 589
 590         if (present & (0x04 << ADV7842_EDID_PORT_A))
 591                 mask |= 0x20;
 592         if (present & (0x04 << ADV7842_EDID_PORT_B))
 593                 mask |= 0x10;
 594         io_write_and_or(sd, 0x20, 0xcf, mask);
 595 }
 596
 597 static int edid_write_vga_segment(struct v4l2_subdev *sd)
 598 {
 599         struct i2c_client *client = v4l2_get_subdevdata(sd);
 600         struct adv7842_state *state = to_state(sd);
 601         const u8 *val = state->vga_edid.edid;
 602         int err = 0;
 603         int i;
 604
 605         v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
 606
 607         /* HPA disable on port A and B */
 608         io_write_and_or(sd, 0x20, 0xcf, 0x00);
 609
 610         /* Disable I2C access to internal EDID ram from VGA DDC port */
 611         rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
 612
 613         /* edid segment pointer '1' for VGA port */
 614         rep_write_and_or(sd, 0x77, 0xef, 0x10);
 615
 616         for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
 617                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 618                                              I2C_SMBUS_BLOCK_MAX, val + i);
 619         if (err)
 620                 return err;
 621
 622         /* Calculates the checksums and enables I2C access
 623          * to internal EDID ram from VGA DDC port.
 624          */
 625         rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
 626
 627         for (i = 0; i < 1000; i++) {
 628                 if (rep_read(sd, 0x79) & 0x20)
 629                         break;
 630                 mdelay(1);
 631         }
 632         if (i == 1000) {
 633                 v4l_err(client, "error enabling edid on VGA port\n");
 634                 return -EIO;
 635         }
 636
 637         /* enable hotplug after 200 ms */
 638         queue_delayed_work(state->work_queues,
 639                         &state->delayed_work_enable_hotplug, HZ / 5);
 640
 641         return 0;
 642 }
 643
 644 static int edid_spa_location(const u8 *edid)
 645 {
 646         u8 d;
 647
 648         /*
 649          * TODO, improve and update for other CEA extensions
 650          * currently only for 1 segment (256 bytes),
 651          * i.e. 1 extension block and CEA revision 3.
 652          */
 653         if ((edid[0x7e] != 1) ||
 654             (edid[0x80] != 0x02) ||
 655             (edid[0x81] != 0x03)) {
 656                 return -EINVAL;
 657         }
 658         /*
 659          * search Vendor Specific Data Block (tag 3)
 660          */
 661         d = edid[0x82] & 0x7f;
 662         if (d > 4) {
 663                 int i = 0x84;
 664                 int end = 0x80 + d;
 665                 do {
 666                         u8 tag = edid[i]>>5;
 667                         u8 len = edid[i] & 0x1f;
 668
 669                         if ((tag == 3) && (len >= 5))
 670                                 return i + 4;
 671                         i += len + 1;
 672                 } while (i < end);
 673         }
 674         return -EINVAL;
 675 }
 676
 677 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
 678 {
 679         struct i2c_client *client = v4l2_get_subdevdata(sd);
 680         struct adv7842_state *state = to_state(sd);
 681         const u8 *val = state->hdmi_edid.edid;
 682         int spa_loc = edid_spa_location(val);
 683         int err = 0;
 684         int i;
 685
 686         v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
 687                         __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
 688
 689         /* HPA disable on port A and B */
 690         io_write_and_or(sd, 0x20, 0xcf, 0x00);
 691
 692         /* Disable I2C access to internal EDID ram from HDMI DDC ports */
 693         rep_write_and_or(sd, 0x77, 0xf3, 0x00);
 694
 695         /* edid segment pointer '0' for HDMI ports */
 696         rep_write_and_or(sd, 0x77, 0xef, 0x00);
 697
 698         for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
 699                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 700                                                      I2C_SMBUS_BLOCK_MAX, val + i);
 701         if (err)
 702                 return err;
 703
 704         if (spa_loc < 0)
 705                 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
 706
 707         if (port == ADV7842_EDID_PORT_A) {
 708                 rep_write(sd, 0x72, val[spa_loc]);
 709                 rep_write(sd, 0x73, val[spa_loc + 1]);
 710         } else {
 711                 rep_write(sd, 0x74, val[spa_loc]);
 712                 rep_write(sd, 0x75, val[spa_loc + 1]);
 713         }
 714         rep_write(sd, 0x76, spa_loc & 0xff);
 715         rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
 716
 717         /* Calculates the checksums and enables I2C access to internal
 718          * EDID ram from HDMI DDC ports
 719          */
 720         rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
 721
 722         for (i = 0; i < 1000; i++) {
 723                 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
 724                         break;
 725                 mdelay(1);
 726         }
 727         if (i == 1000) {
 728                 v4l_err(client, "error enabling edid on port %c\n",
 729                                 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
 730                 return -EIO;
 731         }
 732
 733         /* enable hotplug after 200 ms */
 734         queue_delayed_work(state->work_queues,
 735                         &state->delayed_work_enable_hotplug, HZ / 5);
 736
 737         return 0;
 738 }
 739
 740 /* ----------------------------------------------------------------------- */
 741
 742 #ifdef CONFIG_VIDEO_ADV_DEBUG
 743 static void adv7842_inv_register(struct v4l2_subdev *sd)
 744 {
 745         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 746         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 747         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 748         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 749         v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
 750         v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
 751         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 752         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 753         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 754         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 755         v4l2_info(sd, "0xa00-0xaff: CP Map\n");
 756         v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
 757 }
 758
 759 static int adv7842_g_register(struct v4l2_subdev *sd,
 760                               struct v4l2_dbg_register *reg)
 761 {
 762         reg->size = 1;
 763         switch (reg->reg >> 8) {
 764         case 0:
 765                 reg->val = io_read(sd, reg->reg & 0xff);
 766                 break;
 767         case 1:
 768                 reg->val = avlink_read(sd, reg->reg & 0xff);
 769                 break;
 770         case 2:
 771                 reg->val = cec_read(sd, reg->reg & 0xff);
 772                 break;
 773         case 3:
 774                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 775                 break;
 776         case 4:
 777                 reg->val = sdp_io_read(sd, reg->reg & 0xff);
 778                 break;
 779         case 5:
 780                 reg->val = sdp_read(sd, reg->reg & 0xff);
 781                 break;
 782         case 6:
 783                 reg->val = afe_read(sd, reg->reg & 0xff);
 784                 break;
 785         case 7:
 786                 reg->val = rep_read(sd, reg->reg & 0xff);
 787                 break;
 788         case 8:
 789                 reg->val = edid_read(sd, reg->reg & 0xff);
 790                 break;
 791         case 9:
 792                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 793                 break;
 794         case 0xa:
 795                 reg->val = cp_read(sd, reg->reg & 0xff);
 796                 break;
 797         case 0xb:
 798                 reg->val = vdp_read(sd, reg->reg & 0xff);
 799                 break;
 800         default:
 801                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 802                 adv7842_inv_register(sd);
 803                 break;
 804         }
 805         return 0;
 806 }
 807
 808 static int adv7842_s_register(struct v4l2_subdev *sd,
 809                 const struct v4l2_dbg_register *reg)
 810 {
 811         u8 val = reg->val & 0xff;
 812
 813         switch (reg->reg >> 8) {
 814         case 0:
 815                 io_write(sd, reg->reg & 0xff, val);
 816                 break;
 817         case 1:
 818                 avlink_write(sd, reg->reg & 0xff, val);
 819                 break;
 820         case 2:
 821                 cec_write(sd, reg->reg & 0xff, val);
 822                 break;
 823         case 3:
 824                 infoframe_write(sd, reg->reg & 0xff, val);
 825                 break;
 826         case 4:
 827                 sdp_io_write(sd, reg->reg & 0xff, val);
 828                 break;
 829         case 5:
 830                 sdp_write(sd, reg->reg & 0xff, val);
 831                 break;
 832         case 6:
 833                 afe_write(sd, reg->reg & 0xff, val);
 834                 break;
 835         case 7:
 836                 rep_write(sd, reg->reg & 0xff, val);
 837                 break;
 838         case 8:
 839                 edid_write(sd, reg->reg & 0xff, val);
 840                 break;
 841         case 9:
 842                 hdmi_write(sd, reg->reg & 0xff, val);
 843                 break;
 844         case 0xa:
 845                 cp_write(sd, reg->reg & 0xff, val);
 846                 break;
 847         case 0xb:
 848                 vdp_write(sd, reg->reg & 0xff, val);
 849                 break;
 850         default:
 851                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 852                 adv7842_inv_register(sd);
 853                 break;
 854         }
 855         return 0;
 856 }
 857 #endif
 858
 859 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 860 {
 861         struct adv7842_state *state = to_state(sd);
 862         int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
 863         u8 reg_io_6f = io_read(sd, 0x6f);
 864         int val = 0;
 865
 866         if (reg_io_6f & 0x02)
 867                 val |= 1; /* port A */
 868         if (reg_io_6f & 0x01)
 869                 val |= 2; /* port B */
 870
 871         v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
 872
 873         if (val != prev)
 874                 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
 875         return 0;
 876 }
 877
 878 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 879                 u8 prim_mode,
 880                 const struct adv7842_video_standards *predef_vid_timings,
 881                 const struct v4l2_dv_timings *timings)
 882 {
 883         int i;
 884
 885         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 886                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 887                                           is_digital_input(sd) ? 250000 : 1000000))
 888                         continue;
 889                 /* video std */
 890                 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
 891                 /* v_freq and prim mode */
 892                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
 893                 return 0;
 894         }
 895
 896         return -1;
 897 }
 898
 899 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 900                 struct v4l2_dv_timings *timings)
 901 {
 902         struct adv7842_state *state = to_state(sd);
 903         int err;
 904
 905         v4l2_dbg(1, debug, sd, "%s\n", __func__);
 906
 907         /* reset to default values */
 908         io_write(sd, 0x16, 0x43);
 909         io_write(sd, 0x17, 0x5a);
 910         /* disable embedded syncs for auto graphics mode */
 911         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 912         cp_write(sd, 0x26, 0x00);
 913         cp_write(sd, 0x27, 0x00);
 914         cp_write(sd, 0x28, 0x00);
 915         cp_write(sd, 0x29, 0x00);
 916         cp_write(sd, 0x8f, 0x40);
 917         cp_write(sd, 0x90, 0x00);
 918         cp_write(sd, 0xa5, 0x00);
 919         cp_write(sd, 0xa6, 0x00);
 920         cp_write(sd, 0xa7, 0x00);
 921         cp_write(sd, 0xab, 0x00);
 922         cp_write(sd, 0xac, 0x00);
 923
 924         switch (state->mode) {
 925         case ADV7842_MODE_COMP:
 926         case ADV7842_MODE_RGB:
 927                 err = find_and_set_predefined_video_timings(sd,
 928                                 0x01, adv7842_prim_mode_comp, timings);
 929                 if (err)
 930                         err = find_and_set_predefined_video_timings(sd,
 931                                         0x02, adv7842_prim_mode_gr, timings);
 932                 break;
 933         case ADV7842_MODE_HDMI:
 934                 err = find_and_set_predefined_video_timings(sd,
 935                                 0x05, adv7842_prim_mode_hdmi_comp, timings);
 936                 if (err)
 937                         err = find_and_set_predefined_video_timings(sd,
 938                                         0x06, adv7842_prim_mode_hdmi_gr, timings);
 939                 break;
 940         default:
 941                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
 942                                 __func__, state->mode);
 943                 err = -1;
 944                 break;
 945         }
 946
 947
 948         return err;
 949 }
 950
 951 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 952                 const struct v4l2_bt_timings *bt)
 953 {
 954         struct adv7842_state *state = to_state(sd);
 955         struct i2c_client *client = v4l2_get_subdevdata(sd);
 956         u32 width = htotal(bt);
 957         u32 height = vtotal(bt);
 958         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 959         u16 cp_start_eav = width - bt->hfrontporch;
 960         u16 cp_start_vbi = height - bt->vfrontporch + 1;
 961         u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
 962         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 963                 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 964         const u8 pll[2] = {
 965                 0xc0 | ((width >> 8) & 0x1f),
 966                 width & 0xff
 967         };
 968
 969         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 970
 971         switch (state->mode) {
 972         case ADV7842_MODE_COMP:
 973         case ADV7842_MODE_RGB:
 974                 /* auto graphics */
 975                 io_write(sd, 0x00, 0x07); /* video std */
 976                 io_write(sd, 0x01, 0x02); /* prim mode */
 977                 /* enable embedded syncs for auto graphics mode */
 978                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 979
 980                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 981                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 982                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 983                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
 984                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 985                         break;
 986                 }
 987
 988                 /* active video - horizontal timing */
 989                 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
 990                 cp_write(sd, 0x27, (cp_start_sav & 0xff));
 991                 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
 992                 cp_write(sd, 0x29, (cp_start_eav & 0xff));
 993
 994                 /* active video - vertical timing */
 995                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 996                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 997                                         ((cp_end_vbi >> 8) & 0xf));
 998                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 999                 break;
1000         case ADV7842_MODE_HDMI:
1001                 /* set default prim_mode/vid_std for HDMI
1002                    according to [REF_03, c. 4.2] */
1003                 io_write(sd, 0x00, 0x02); /* video std */
1004                 io_write(sd, 0x01, 0x06); /* prim mode */
1005                 break;
1006         default:
1007                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1008                                 __func__, state->mode);
1009                 break;
1010         }
1011
1012         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1013         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1014         cp_write(sd, 0xab, (height >> 4) & 0xff);
1015         cp_write(sd, 0xac, (height & 0x0f) << 4);
1016 }
1017
1018 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1019 {
1020         struct adv7842_state *state = to_state(sd);
1021
1022         v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
1023                        __func__, state->rgb_quantization_range);
1024
1025         switch (state->rgb_quantization_range) {
1026         case V4L2_DV_RGB_RANGE_AUTO:
1027                 if (state->mode == ADV7842_MODE_RGB) {
1028                         /* Receiving analog RGB signal
1029                          * Set RGB full range (0-255) */
1030                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1031                         break;
1032                 }
1033
1034                 if (state->mode == ADV7842_MODE_COMP) {
1035                         /* Receiving analog YPbPr signal
1036                          * Set automode */
1037                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1038                         break;
1039                 }
1040
1041                 if (hdmi_read(sd, 0x05) & 0x80) {
1042                         /* Receiving HDMI signal
1043                          * Set automode */
1044                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1045                         break;
1046                 }
1047
1048                 /* Receiving DVI-D signal
1049                  * ADV7842 selects RGB limited range regardless of
1050                  * input format (CE/IT) in automatic mode */
1051                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1052                         /* RGB limited range (16-235) */
1053                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
1054                 } else {
1055                         /* RGB full range (0-255) */
1056                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1057                 }
1058                 break;
1059         case V4L2_DV_RGB_RANGE_LIMITED:
1060                 if (state->mode == ADV7842_MODE_COMP) {
1061                         /* YCrCb limited range (16-235) */
1062                         io_write_and_or(sd, 0x02, 0x0f, 0x20);
1063                 } else {
1064                         /* RGB limited range (16-235) */
1065                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
1066                 }
1067                 break;
1068         case V4L2_DV_RGB_RANGE_FULL:
1069                 if (state->mode == ADV7842_MODE_COMP) {
1070                         /* YCrCb full range (0-255) */
1071                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1072                 } else {
1073                         /* RGB full range (0-255) */
1074                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1075                 }
1076                 break;
1077         }
1078 }
1079
1080 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1081 {
1082         struct v4l2_subdev *sd = to_sd(ctrl);
1083         struct adv7842_state *state = to_state(sd);
1084
1085         /* TODO SDP ctrls
1086            contrast/brightness/hue/free run is acting a bit strange,
1087            not sure if sdp csc is correct.
1088          */
1089         switch (ctrl->id) {
1090         /* standard ctrls */
1091         case V4L2_CID_BRIGHTNESS:
1092                 cp_write(sd, 0x3c, ctrl->val);
1093                 sdp_write(sd, 0x14, ctrl->val);
1094                 /* ignore lsb sdp 0x17[3:2] */
1095                 return 0;
1096         case V4L2_CID_CONTRAST:
1097                 cp_write(sd, 0x3a, ctrl->val);
1098                 sdp_write(sd, 0x13, ctrl->val);
1099                 /* ignore lsb sdp 0x17[1:0] */
1100                 return 0;
1101         case V4L2_CID_SATURATION:
1102                 cp_write(sd, 0x3b, ctrl->val);
1103                 sdp_write(sd, 0x15, ctrl->val);
1104                 /* ignore lsb sdp 0x17[5:4] */
1105                 return 0;
1106         case V4L2_CID_HUE:
1107                 cp_write(sd, 0x3d, ctrl->val);
1108                 sdp_write(sd, 0x16, ctrl->val);
1109                 /* ignore lsb sdp 0x17[7:6] */
1110                 return 0;
1111                 /* custom ctrls */
1112         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1113                 afe_write(sd, 0xc8, ctrl->val);
1114                 return 0;
1115         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1116                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1117                 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1118                 return 0;
1119         case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1120                 u8 R = (ctrl->val & 0xff0000) >> 16;
1121                 u8 G = (ctrl->val & 0x00ff00) >> 8;
1122                 u8 B = (ctrl->val & 0x0000ff);
1123                 /* RGB -> YUV, numerical approximation */
1124                 int Y = 66 * R + 129 * G + 25 * B;
1125                 int U = -38 * R - 74 * G + 112 * B;
1126                 int V = 112 * R - 94 * G - 18 * B;
1127
1128                 /* Scale down to 8 bits with rounding */
1129                 Y = (Y + 128) >> 8;
1130                 U = (U + 128) >> 8;
1131                 V = (V + 128) >> 8;
1132                 /* make U,V positive */
1133                 Y += 16;
1134                 U += 128;
1135                 V += 128;
1136
1137                 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1138                 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1139
1140                 /* CP */
1141                 cp_write(sd, 0xc1, R);
1142                 cp_write(sd, 0xc0, G);
1143                 cp_write(sd, 0xc2, B);
1144                 /* SDP */
1145                 sdp_write(sd, 0xde, Y);
1146                 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1147                 return 0;
1148         }
1149         case V4L2_CID_DV_RX_RGB_RANGE:
1150                 state->rgb_quantization_range = ctrl->val;
1151                 set_rgb_quantization_range(sd);
1152                 return 0;
1153         }
1154         return -EINVAL;
1155 }
1156
1157 static inline bool no_power(struct v4l2_subdev *sd)
1158 {
1159         return io_read(sd, 0x0c) & 0x24;
1160 }
1161
1162 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1163 {
1164         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1165 }
1166
1167 static inline bool is_hdmi(struct v4l2_subdev *sd)
1168 {
1169         return hdmi_read(sd, 0x05) & 0x80;
1170 }
1171
1172 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1173 {
1174         struct adv7842_state *state = to_state(sd);
1175
1176         *status = 0;
1177
1178         if (io_read(sd, 0x0c) & 0x24)
1179                 *status |= V4L2_IN_ST_NO_POWER;
1180
1181         if (state->mode == ADV7842_MODE_SDP) {
1182                 /* status from SDP block */
1183                 if (!(sdp_read(sd, 0x5A) & 0x01))
1184                         *status |= V4L2_IN_ST_NO_SIGNAL;
1185
1186                 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1187                                 __func__, *status);
1188                 return 0;
1189         }
1190         /* status from CP block */
1191         if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1192                         !(cp_read(sd, 0xb1) & 0x80))
1193                 /* TODO channel 2 */
1194                 *status |= V4L2_IN_ST_NO_SIGNAL;
1195
1196         if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1197                 *status |= V4L2_IN_ST_NO_SIGNAL;
1198
1199         v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1200                         __func__, *status);
1201
1202         return 0;
1203 }
1204
1205 struct stdi_readback {
1206         u16 bl, lcf, lcvs;
1207         u8 hs_pol, vs_pol;
1208         bool interlaced;
1209 };
1210
1211 static int stdi2dv_timings(struct v4l2_subdev *sd,
1212                 struct stdi_readback *stdi,
1213                 struct v4l2_dv_timings *timings)
1214 {
1215         struct adv7842_state *state = to_state(sd);
1216         u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1217         u32 pix_clk;
1218         int i;
1219
1220         for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1221                 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1222
1223                 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1224                                            adv7842_get_dv_timings_cap(sd),
1225                                            adv7842_check_dv_timings, NULL))
1226                         continue;
1227                 if (vtotal(bt) != stdi->lcf + 1)
1228                         continue;
1229                 if (bt->vsync != stdi->lcvs)
1230                         continue;
1231
1232                 pix_clk = hfreq * htotal(bt);
1233
1234                 if ((pix_clk < bt->pixelclock + 1000000) &&
1235                     (pix_clk > bt->pixelclock - 1000000)) {
1236                         *timings = v4l2_dv_timings_presets[i];
1237                         return 0;
1238                 }
1239         }
1240
1241         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1242                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1243                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1244                             timings))
1245                 return 0;
1246         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1247                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1248                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1249                             state->aspect_ratio, timings))
1250                 return 0;
1251
1252         v4l2_dbg(2, debug, sd,
1253                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1254                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1255                 stdi->hs_pol, stdi->vs_pol);
1256         return -1;
1257 }
1258
1259 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1260 {
1261         u32 status;
1262
1263         adv7842_g_input_status(sd, &status);
1264         if (status & V4L2_IN_ST_NO_SIGNAL) {
1265                 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1266                 return -ENOLINK;
1267         }
1268
1269         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1270         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1271         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1272
1273         if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1274                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1275                         ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1276                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1277                         ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1278         } else {
1279                 stdi->hs_pol = 'x';
1280                 stdi->vs_pol = 'x';
1281         }
1282         stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1283
1284         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1285                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1286                 return -ENOLINK;
1287         }
1288
1289         v4l2_dbg(2, debug, sd,
1290                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1291                  __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1292                  stdi->hs_pol, stdi->vs_pol,
1293                  stdi->interlaced ? "interlaced" : "progressive");
1294
1295         return 0;
1296 }
1297
1298 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1299                                    struct v4l2_enum_dv_timings *timings)
1300 {
1301         return v4l2_enum_dv_timings_cap(timings,
1302                 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1303 }
1304
1305 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1306                                   struct v4l2_dv_timings_cap *cap)
1307 {
1308         *cap = *adv7842_get_dv_timings_cap(sd);
1309         return 0;
1310 }
1311
1312 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1313    if the format is listed in adv7842_timings[] */
1314 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1315                 struct v4l2_dv_timings *timings)
1316 {
1317         v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1318                         is_digital_input(sd) ? 250000 : 1000000,
1319                         adv7842_check_dv_timings, NULL);
1320 }
1321
1322 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1323                                     struct v4l2_dv_timings *timings)
1324 {
1325         struct adv7842_state *state = to_state(sd);
1326         struct v4l2_bt_timings *bt = &timings->bt;
1327         struct stdi_readback stdi = { 0 };
1328
1329         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1330
1331         /* SDP block */
1332         if (state->mode == ADV7842_MODE_SDP)
1333                 return -ENODATA;
1334
1335         /* read STDI */
1336         if (read_stdi(sd, &stdi)) {
1337                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1338                 return -ENOLINK;
1339         }
1340         bt->interlaced = stdi.interlaced ?
1341                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1342
1343         if (is_digital_input(sd)) {
1344                 uint32_t freq;
1345
1346                 timings->type = V4L2_DV_BT_656_1120;
1347                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1348                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1349                 freq = (hdmi_read(sd, 0x06) * 1000000) +
1350                        ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1351
1352                 if (is_hdmi(sd)) {
1353                         /* adjust for deep color mode */
1354                         freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8);
1355                 }
1356                 bt->pixelclock = freq;
1357                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1358                         hdmi_read(sd, 0x21);
1359                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1360                         hdmi_read(sd, 0x23);
1361                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1362                         hdmi_read(sd, 0x25);
1363                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1364                         hdmi_read(sd, 0x2b)) / 2;
1365                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1366                         hdmi_read(sd, 0x2f)) / 2;
1367                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1368                         hdmi_read(sd, 0x33)) / 2;
1369                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1370                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1371                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1372                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1373                                         hdmi_read(sd, 0x0c);
1374                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1375                                         hdmi_read(sd, 0x2d)) / 2;
1376                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1377                                         hdmi_read(sd, 0x31)) / 2;
1378                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1379                                         hdmi_read(sd, 0x35)) / 2;
1380                 }
1381                 adv7842_fill_optional_dv_timings_fields(sd, timings);
1382         } else {
1383                 /* Interlaced? */
1384                 if (stdi.interlaced) {
1385                         v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__);
1386                         return -ERANGE;
1387                 }
1388
1389                 if (stdi2dv_timings(sd, &stdi, timings)) {
1390                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1391                         return -ERANGE;
1392                 }
1393         }
1394
1395         if (debug > 1)
1396                 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings: ",
1397                                       timings, true);
1398         return 0;
1399 }
1400
1401 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1402                                 struct v4l2_dv_timings *timings)
1403 {
1404         struct adv7842_state *state = to_state(sd);
1405         struct v4l2_bt_timings *bt;
1406         int err;
1407
1408         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1409
1410         if (state->mode == ADV7842_MODE_SDP)
1411                 return -ENODATA;
1412
1413         bt = &timings->bt;
1414
1415         if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1416                                    adv7842_check_dv_timings, NULL))
1417                 return -ERANGE;
1418
1419         adv7842_fill_optional_dv_timings_fields(sd, timings);
1420
1421         state->timings = *timings;
1422
1423         cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1424
1425         /* Use prim_mode and vid_std when available */
1426         err = configure_predefined_video_timings(sd, timings);
1427         if (err) {
1428                 /* custom settings when the video format
1429                   does not have prim_mode/vid_std */
1430                 configure_custom_video_timings(sd, bt);
1431         }
1432
1433         set_rgb_quantization_range(sd);
1434
1435
1436         if (debug > 1)
1437                 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1438                                       timings, true);
1439         return 0;
1440 }
1441
1442 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1443                                 struct v4l2_dv_timings *timings)
1444 {
1445         struct adv7842_state *state = to_state(sd);
1446
1447         if (state->mode == ADV7842_MODE_SDP)
1448                 return -ENODATA;
1449         *timings = state->timings;
1450         return 0;
1451 }
1452
1453 static void enable_input(struct v4l2_subdev *sd)
1454 {
1455         struct adv7842_state *state = to_state(sd);
1456
1457         set_rgb_quantization_range(sd);
1458         switch (state->mode) {
1459         case ADV7842_MODE_SDP:
1460         case ADV7842_MODE_COMP:
1461         case ADV7842_MODE_RGB:
1462                 /* enable */
1463                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1464                 break;
1465         case ADV7842_MODE_HDMI:
1466                 /* enable */
1467                 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1468                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1469                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1470                 break;
1471         default:
1472                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1473                          __func__, state->mode);
1474                 break;
1475         }
1476 }
1477
1478 static void disable_input(struct v4l2_subdev *sd)
1479 {
1480         /* disable */
1481         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1482         hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1483         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1484 }
1485
1486 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1487                           const struct adv7842_sdp_csc_coeff *c)
1488 {
1489         /* csc auto/manual */
1490         sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1491
1492         if (!c->manual)
1493                 return;
1494
1495         /* csc scaling */
1496         sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1497
1498         /* A coeff */
1499         sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1500         sdp_io_write(sd, 0xe1, c->A1);
1501         sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1502         sdp_io_write(sd, 0xe3, c->A2);
1503         sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1504         sdp_io_write(sd, 0xe5, c->A3);
1505
1506         /* A scale */
1507         sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1508         sdp_io_write(sd, 0xe7, c->A4);
1509
1510         /* B coeff */
1511         sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1512         sdp_io_write(sd, 0xe9, c->B1);
1513         sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1514         sdp_io_write(sd, 0xeb, c->B2);
1515         sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1516         sdp_io_write(sd, 0xed, c->B3);
1517
1518         /* B scale */
1519         sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1520         sdp_io_write(sd, 0xef, c->B4);
1521
1522         /* C coeff */
1523         sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1524         sdp_io_write(sd, 0xf1, c->C1);
1525         sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1526         sdp_io_write(sd, 0xf3, c->C2);
1527         sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1528         sdp_io_write(sd, 0xf5, c->C3);
1529
1530         /* C scale */
1531         sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1532         sdp_io_write(sd, 0xf7, c->C4);
1533 }
1534
1535 static void select_input(struct v4l2_subdev *sd,
1536                          enum adv7842_vid_std_select vid_std_select)
1537 {
1538         struct adv7842_state *state = to_state(sd);
1539
1540         switch (state->mode) {
1541         case ADV7842_MODE_SDP:
1542                 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1543                 io_write(sd, 0x01, 0); /* prim mode */
1544                 /* enable embedded syncs for auto graphics mode */
1545                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1546
1547                 afe_write(sd, 0x00, 0x00); /* power up ADC */
1548                 afe_write(sd, 0xc8, 0x00); /* phase control */
1549
1550                 io_write(sd, 0x19, 0x83); /* LLC DLL phase */
1551                 io_write(sd, 0x33, 0x40); /* LLC DLL enable */
1552
1553                 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1554                 /* script says register 0xde, which don't exist in manual */
1555
1556                 /* Manual analog input muxing mode, CVBS (6.4)*/
1557                 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1558                 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1559                         afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1560                         afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1561                 } else {
1562                         afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1563                         afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1564                 }
1565                 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1566                 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1567
1568                 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1569                 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1570
1571                 /* SDP recommended settings */
1572                 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1573                 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1574
1575                 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1576                 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1577                 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1578                 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1579                 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1580                 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1581                 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1582
1583                 /* deinterlacer enabled and 3D comb */
1584                 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1585
1586                 sdp_write(sd, 0xdd, 0x08); /* free run auto */
1587
1588                 break;
1589
1590         case ADV7842_MODE_COMP:
1591         case ADV7842_MODE_RGB:
1592                 /* Automatic analog input muxing mode */
1593                 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1594                 /* set mode and select free run resolution */
1595                 io_write(sd, 0x00, vid_std_select); /* video std */
1596                 io_write(sd, 0x01, 0x02); /* prim mode */
1597                 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1598                                                           for auto graphics mode */
1599
1600                 afe_write(sd, 0x00, 0x00); /* power up ADC */
1601                 afe_write(sd, 0xc8, 0x00); /* phase control */
1602                 if (state->mode == ADV7842_MODE_COMP) {
1603                         /* force to YCrCb */
1604                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1605                 } else {
1606                         /* force to RGB */
1607                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1608                 }
1609
1610                 /* set ADI recommended settings for digitizer */
1611                 /* "ADV7842 Register Settings Recommendations
1612                  * (rev. 1.8, November 2010)" p. 9. */
1613                 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1614                 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1615
1616                 /* set to default gain for RGB */
1617                 cp_write(sd, 0x73, 0x10);
1618                 cp_write(sd, 0x74, 0x04);
1619                 cp_write(sd, 0x75, 0x01);
1620                 cp_write(sd, 0x76, 0x00);
1621
1622                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1623                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1624                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1625                 break;
1626
1627         case ADV7842_MODE_HDMI:
1628                 /* Automatic analog input muxing mode */
1629                 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1630                 /* set mode and select free run resolution */
1631                 if (state->hdmi_port_a)
1632                         hdmi_write(sd, 0x00, 0x02); /* select port A */
1633                 else
1634                         hdmi_write(sd, 0x00, 0x03); /* select port B */
1635                 io_write(sd, 0x00, vid_std_select); /* video std */
1636                 io_write(sd, 0x01, 5); /* prim mode */
1637                 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1638                                                           for auto graphics mode */
1639
1640                 /* set ADI recommended settings for HDMI: */
1641                 /* "ADV7842 Register Settings Recommendations
1642                  * (rev. 1.8, November 2010)" p. 3. */
1643                 hdmi_write(sd, 0xc0, 0x00);
1644                 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1645                 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1646                 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1647                 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1648                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1649                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1650                 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1651                 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1652                 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1653                                                Improve robustness */
1654                 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1655                 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1656                 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1657                 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1658                 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1659                 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1660                 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1661                 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1662                 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1663                 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1664
1665                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1666                 afe_write(sd, 0xc8, 0x40); /* phase control */
1667
1668                 /* set to default gain for HDMI */
1669                 cp_write(sd, 0x73, 0x10);
1670                 cp_write(sd, 0x74, 0x04);
1671                 cp_write(sd, 0x75, 0x01);
1672                 cp_write(sd, 0x76, 0x00);
1673
1674                 /* reset ADI recommended settings for digitizer */
1675                 /* "ADV7842 Register Settings Recommendations
1676                  * (rev. 2.5, June 2010)" p. 17. */
1677                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1678                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1679                 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control,
1680                                              enable color control */
1681                 /* CP coast control */
1682                 cp_write(sd, 0xc3, 0x33); /* Component mode */
1683
1684                 /* color space conversion, autodetect color space */
1685                 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1686                 break;
1687
1688         default:
1689                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1690                          __func__, state->mode);
1691                 break;
1692         }
1693 }
1694
1695 static int adv7842_s_routing(struct v4l2_subdev *sd,
1696                 u32 input, u32 output, u32 config)
1697 {
1698         struct adv7842_state *state = to_state(sd);
1699
1700         v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1701
1702         switch (input) {
1703         case ADV7842_SELECT_HDMI_PORT_A:
1704                 state->mode = ADV7842_MODE_HDMI;
1705                 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1706                 state->hdmi_port_a = true;
1707                 break;
1708         case ADV7842_SELECT_HDMI_PORT_B:
1709                 state->mode = ADV7842_MODE_HDMI;
1710                 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1711                 state->hdmi_port_a = false;
1712                 break;
1713         case ADV7842_SELECT_VGA_COMP:
1714                 state->mode = ADV7842_MODE_COMP;
1715                 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1716                 break;
1717         case ADV7842_SELECT_VGA_RGB:
1718                 state->mode = ADV7842_MODE_RGB;
1719                 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1720                 break;
1721         case ADV7842_SELECT_SDP_CVBS:
1722                 state->mode = ADV7842_MODE_SDP;
1723                 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1724                 break;
1725         case ADV7842_SELECT_SDP_YC:
1726                 state->mode = ADV7842_MODE_SDP;
1727                 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1728                 break;
1729         default:
1730                 return -EINVAL;
1731         }
1732
1733         disable_input(sd);
1734         select_input(sd, state->vid_std_select);
1735         enable_input(sd);
1736
1737         v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1738
1739         return 0;
1740 }
1741
1742 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1743                                  enum v4l2_mbus_pixelcode *code)
1744 {
1745         if (index)
1746                 return -EINVAL;
1747         /* Good enough for now */
1748         *code = V4L2_MBUS_FMT_FIXED;
1749         return 0;
1750 }
1751
1752 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1753                               struct v4l2_mbus_framefmt *fmt)
1754 {
1755         struct adv7842_state *state = to_state(sd);
1756
1757         fmt->width = state->timings.bt.width;
1758         fmt->height = state->timings.bt.height;
1759         fmt->code = V4L2_MBUS_FMT_FIXED;
1760         fmt->field = V4L2_FIELD_NONE;
1761
1762         if (state->mode == ADV7842_MODE_SDP) {
1763                 /* SPD block */
1764                 if (!(sdp_read(sd, 0x5A) & 0x01))
1765                         return -EINVAL;
1766                 fmt->width = 720;
1767                 /* valid signal */
1768                 if (state->norm & V4L2_STD_525_60)
1769                         fmt->height = 480;
1770                 else
1771                         fmt->height = 576;
1772                 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1773                 return 0;
1774         }
1775
1776         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1777                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1778                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1779         }
1780         return 0;
1781 }
1782
1783 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1784 {
1785         if (enable) {
1786                 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1787                 io_write(sd, 0x46, 0x9c);
1788                 /* ESDP_50HZ_DET interrupt */
1789                 io_write(sd, 0x5a, 0x10);
1790                 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1791                 io_write(sd, 0x73, 0x03);
1792                 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1793                 io_write(sd, 0x78, 0x03);
1794                 /* Enable SDP Standard Detection Change and SDP Video Detected */
1795                 io_write(sd, 0xa0, 0x09);
1796         } else {
1797                 io_write(sd, 0x46, 0x0);
1798                 io_write(sd, 0x5a, 0x0);
1799                 io_write(sd, 0x73, 0x0);
1800                 io_write(sd, 0x78, 0x0);
1801                 io_write(sd, 0xa0, 0x0);
1802         }
1803 }
1804
1805 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1806 {
1807         struct adv7842_state *state = to_state(sd);
1808         u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1809         u8 irq_status[5];
1810
1811         adv7842_irq_enable(sd, false);
1812
1813         /* read status */
1814         irq_status[0] = io_read(sd, 0x43);
1815         irq_status[1] = io_read(sd, 0x57);
1816         irq_status[2] = io_read(sd, 0x70);
1817         irq_status[3] = io_read(sd, 0x75);
1818         irq_status[4] = io_read(sd, 0x9d);
1819
1820         /* and clear */
1821         if (irq_status[0])
1822                 io_write(sd, 0x44, irq_status[0]);
1823         if (irq_status[1])
1824                 io_write(sd, 0x58, irq_status[1]);
1825         if (irq_status[2])
1826                 io_write(sd, 0x71, irq_status[2]);
1827         if (irq_status[3])
1828                 io_write(sd, 0x76, irq_status[3]);
1829         if (irq_status[4])
1830                 io_write(sd, 0x9e, irq_status[4]);
1831
1832         adv7842_irq_enable(sd, true);
1833
1834         v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__,
1835                  irq_status[0], irq_status[1], irq_status[2],
1836                  irq_status[3], irq_status[4]);
1837
1838         /* format change CP */
1839         fmt_change_cp = irq_status[0] & 0x9c;
1840
1841         /* format change SDP */
1842         if (state->mode == ADV7842_MODE_SDP)
1843                 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1844         else
1845                 fmt_change_sdp = 0;
1846
1847         /* digital format CP */
1848         if (is_digital_input(sd))
1849                 fmt_change_digital = irq_status[3] & 0x03;
1850         else
1851                 fmt_change_digital = 0;
1852
1853         /* notify */
1854         if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1855                 v4l2_dbg(1, debug, sd,
1856                          "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1857                          __func__, fmt_change_cp, fmt_change_digital,
1858                          fmt_change_sdp);
1859                 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1860         }
1861
1862         /* 5v cable detect */
1863         if (irq_status[2])
1864                 adv7842_s_detect_tx_5v_ctrl(sd);
1865
1866         if (handled)
1867                 *handled = true;
1868
1869         return 0;
1870 }
1871
1872 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
1873 {
1874         struct adv7842_state *state = to_state(sd);
1875         int err = 0;
1876
1877         if (e->pad > ADV7842_EDID_PORT_VGA)
1878                 return -EINVAL;
1879         if (e->start_block != 0)
1880                 return -EINVAL;
1881         if (e->blocks > 2)
1882                 return -E2BIG;
1883         if (!e->edid)
1884                 return -EINVAL;
1885
1886         /* todo, per edid */
1887         state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
1888                         e->edid[0x16]);
1889
1890         switch (e->pad) {
1891         case ADV7842_EDID_PORT_VGA:
1892                 memset(&state->vga_edid.edid, 0, 256);
1893                 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
1894                 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
1895                 err = edid_write_vga_segment(sd);
1896                 break;
1897         case ADV7842_EDID_PORT_A:
1898         case ADV7842_EDID_PORT_B:
1899                 memset(&state->hdmi_edid.edid, 0, 256);
1900                 if (e->blocks)
1901                         state->hdmi_edid.present |= 0x04 << e->pad;
1902                 else
1903                         state->hdmi_edid.present &= ~(0x04 << e->pad);
1904                 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
1905                 err = edid_write_hdmi_segment(sd, e->pad);
1906                 break;
1907         default:
1908                 return -EINVAL;
1909         }
1910         if (err < 0)
1911                 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
1912         return err;
1913 }
1914
1915 /*********** avi info frame CEA-861-E **************/
1916 /* TODO move to common library */
1917
1918 struct avi_info_frame {
1919         uint8_t f17;
1920         uint8_t y10;
1921         uint8_t a0;
1922         uint8_t b10;
1923         uint8_t s10;
1924         uint8_t c10;
1925         uint8_t m10;
1926         uint8_t r3210;
1927         uint8_t itc;
1928         uint8_t ec210;
1929         uint8_t q10;
1930         uint8_t sc10;
1931         uint8_t f47;
1932         uint8_t vic;
1933         uint8_t yq10;
1934         uint8_t cn10;
1935         uint8_t pr3210;
1936         uint16_t etb;
1937         uint16_t sbb;
1938         uint16_t elb;
1939         uint16_t srb;
1940 };
1941
1942 static const char *y10_txt[4] = {
1943         "RGB",
1944         "YCbCr 4:2:2",
1945         "YCbCr 4:4:4",
1946         "Future",
1947 };
1948
1949 static const char *c10_txt[4] = {
1950         "No Data",
1951         "SMPTE 170M",
1952         "ITU-R 709",
1953         "Extended Colorimetry information valied",
1954 };
1955
1956 static const char *itc_txt[2] = {
1957         "No Data",
1958         "IT content",
1959 };
1960
1961 static const char *ec210_txt[8] = {
1962         "xvYCC601",
1963         "xvYCC709",
1964         "sYCC601",
1965         "AdobeYCC601",
1966         "AdobeRGB",
1967         "5 reserved",
1968         "6 reserved",
1969         "7 reserved",
1970 };
1971
1972 static const char *q10_txt[4] = {
1973         "Default",
1974         "Limited Range",
1975         "Full Range",
1976         "Reserved",
1977 };
1978
1979 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
1980                                 struct avi_info_frame *avi)
1981 {
1982         avi->f17 = (buf[1] >> 7) & 0x1;
1983         avi->y10 = (buf[1] >> 5) & 0x3;
1984         avi->a0 = (buf[1] >> 4) & 0x1;
1985         avi->b10 = (buf[1] >> 2) & 0x3;
1986         avi->s10 = buf[1] & 0x3;
1987         avi->c10 = (buf[2] >> 6) & 0x3;
1988         avi->m10 = (buf[2] >> 4) & 0x3;
1989         avi->r3210 = buf[2] & 0xf;
1990         avi->itc = (buf[3] >> 7) & 0x1;
1991         avi->ec210 = (buf[3] >> 4) & 0x7;
1992         avi->q10 = (buf[3] >> 2) & 0x3;
1993         avi->sc10 = buf[3] & 0x3;
1994         avi->f47 = (buf[4] >> 7) & 0x1;
1995         avi->vic = buf[4] & 0x7f;
1996         avi->yq10 = (buf[5] >> 6) & 0x3;
1997         avi->cn10 = (buf[5] >> 4) & 0x3;
1998         avi->pr3210 = buf[5] & 0xf;
1999         avi->etb = buf[6] + 256*buf[7];
2000         avi->sbb = buf[8] + 256*buf[9];
2001         avi->elb = buf[10] + 256*buf[11];
2002         avi->srb = buf[12] + 256*buf[13];
2003 }
2004
2005 static void print_avi_infoframe(struct v4l2_subdev *sd)
2006 {
2007         int i;
2008         uint8_t buf[14];
2009         uint8_t avi_inf_len;
2010         struct avi_info_frame avi;
2011
2012         if (!(hdmi_read(sd, 0x05) & 0x80)) {
2013                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2014                 return;
2015         }
2016         if (!(io_read(sd, 0x60) & 0x01)) {
2017                 v4l2_info(sd, "AVI infoframe not received\n");
2018                 return;
2019         }
2020
2021         if (io_read(sd, 0x88) & 0x10) {
2022                 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2023                    with a length of 14 or 15. See the ADV7842 Register Settings
2024                    Recommendations document for more details. */
2025                 v4l2_info(sd, "AVI infoframe checksum error\n");
2026                 return;
2027         }
2028
2029         avi_inf_len = infoframe_read(sd, 0xe2);
2030         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2031                   infoframe_read(sd, 0xe1), avi_inf_len);
2032
2033         if (infoframe_read(sd, 0xe1) != 0x02)
2034                 return;
2035
2036         for (i = 0; i < 14; i++)
2037                 buf[i] = infoframe_read(sd, i);
2038
2039         v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2040                   buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2041                   buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2042
2043         parse_avi_infoframe(sd, buf, &avi);
2044
2045         if (avi.vic)
2046                 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2047         if (avi.itc)
2048                 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2049
2050         if (avi.y10)
2051                 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2052                         (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2053         else
2054                 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2055 }
2056
2057 static const char * const prim_mode_txt[] = {
2058         "SDP",
2059         "Component",
2060         "Graphics",
2061         "Reserved",
2062         "CVBS & HDMI AUDIO",
2063         "HDMI-Comp",
2064         "HDMI-GR",
2065         "Reserved",
2066         "Reserved",
2067         "Reserved",
2068         "Reserved",
2069         "Reserved",
2070         "Reserved",
2071         "Reserved",
2072         "Reserved",
2073         "Reserved",
2074 };
2075
2076 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2077 {
2078         /* SDP (Standard definition processor) block */
2079         uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2080
2081         v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2082         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2083                   io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2084
2085         v4l2_info(sd, "SDP: free run: %s\n",
2086                 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2087         v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2088                 "valid SD/PR signal detected" : "invalid/no signal");
2089         if (sdp_signal_detected) {
2090                 static const char * const sdp_std_txt[] = {
2091                         "NTSC-M/J",
2092                         "1?",
2093                         "NTSC-443",
2094                         "60HzSECAM",
2095                         "PAL-M",
2096                         "5?",
2097                         "PAL-60",
2098                         "7?", "8?", "9?", "a?", "b?",
2099                         "PAL-CombN",
2100                         "d?",
2101                         "PAL-BGHID",
2102                         "SECAM"
2103                 };
2104                 v4l2_info(sd, "SDP: standard %s\n",
2105                         sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2106                 v4l2_info(sd, "SDP: %s\n",
2107                         (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2108                 v4l2_info(sd, "SDP: %s\n",
2109                         (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2110                 v4l2_info(sd, "SDP: deinterlacer %s\n",
2111                         (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2112                 v4l2_info(sd, "SDP: csc %s mode\n",
2113                         (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2114         }
2115         return 0;
2116 }
2117
2118 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2119 {
2120         /* CP block */
2121         struct adv7842_state *state = to_state(sd);
2122         struct v4l2_dv_timings timings;
2123         uint8_t reg_io_0x02 = io_read(sd, 0x02);
2124         uint8_t reg_io_0x21 = io_read(sd, 0x21);
2125         uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2126         uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2127         bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2128         bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2129         bool audio_mute = io_read(sd, 0x65) & 0x40;
2130
2131         static const char * const csc_coeff_sel_rb[16] = {
2132                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2133                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2134                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2135                 "reserved", "reserved", "reserved", "reserved", "manual"
2136         };
2137         static const char * const input_color_space_txt[16] = {
2138                 "RGB limited range (16-235)", "RGB full range (0-255)",
2139                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2140                 "xvYCC Bt.601", "xvYCC Bt.709",
2141                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2142                 "invalid", "invalid", "invalid", "invalid", "invalid",
2143                 "invalid", "invalid", "automatic"
2144         };
2145         static const char * const rgb_quantization_range_txt[] = {
2146                 "Automatic",
2147                 "RGB limited range (16-235)",
2148                 "RGB full range (0-255)",
2149         };
2150         static const char * const deep_color_mode_txt[4] = {
2151                 "8-bits per channel",
2152                 "10-bits per channel",
2153                 "12-bits per channel",
2154                 "16-bits per channel (not supported)"
2155         };
2156
2157         v4l2_info(sd, "-----Chip status-----\n");
2158         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2159         v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2160                         state->hdmi_port_a ? "A" : "B");
2161         v4l2_info(sd, "EDID A %s, B %s\n",
2162                   ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2163                   "enabled" : "disabled",
2164                   ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2165                   "enabled" : "disabled");
2166         v4l2_info(sd, "HPD A %s, B %s\n",
2167                   reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2168                   reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2169         v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2170                         "enabled" : "disabled");
2171
2172         v4l2_info(sd, "-----Signal status-----\n");
2173         if (state->hdmi_port_a) {
2174                 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2175                           io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2176                 v4l2_info(sd, "TMDS signal detected: %s\n",
2177                           (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2178                 v4l2_info(sd, "TMDS signal locked: %s\n",
2179                           (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2180         } else {
2181                 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2182                           io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2183                 v4l2_info(sd, "TMDS signal detected: %s\n",
2184                           (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2185                 v4l2_info(sd, "TMDS signal locked: %s\n",
2186                           (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2187         }
2188         v4l2_info(sd, "CP free run: %s\n",
2189                   (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2190         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2191                   io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2192                   (io_read(sd, 0x01) & 0x70) >> 4);
2193
2194         v4l2_info(sd, "-----Video Timings-----\n");
2195         if (no_cp_signal(sd)) {
2196                 v4l2_info(sd, "STDI: not locked\n");
2197         } else {
2198                 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2199                 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2200                 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2201                 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2202                 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2203                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2204                 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2205                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2206                 v4l2_info(sd,
2207                         "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2208                         lcf, bl, lcvs, fcl,
2209                         (cp_read(sd, 0xb1) & 0x40) ?
2210                                 "interlaced" : "progressive",
2211                         hs_pol, vs_pol);
2212         }
2213         if (adv7842_query_dv_timings(sd, &timings))
2214                 v4l2_info(sd, "No video detected\n");
2215         else
2216                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2217                                       &timings, true);
2218         v4l2_print_dv_timings(sd->name, "Configured format: ",
2219                         &state->timings, true);
2220
2221         if (no_cp_signal(sd))
2222                 return 0;
2223
2224         v4l2_info(sd, "-----Color space-----\n");
2225         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2226                   rgb_quantization_range_txt[state->rgb_quantization_range]);
2227         v4l2_info(sd, "Input color space: %s\n",
2228                   input_color_space_txt[reg_io_0x02 >> 4]);
2229         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2230                   (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2231                   (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2232                   ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2233                                         "enabled" : "disabled");
2234         v4l2_info(sd, "Color space conversion: %s\n",
2235                   csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2236
2237         if (!is_digital_input(sd))
2238                 return 0;
2239
2240         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2241         v4l2_info(sd, "HDCP encrypted content: %s\n",
2242                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2243         v4l2_info(sd, "HDCP keys read: %s%s\n",
2244                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2245                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2246         if (!is_hdmi(sd))
2247                 return 0;
2248
2249         v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2250                         audio_pll_locked ? "locked" : "not locked",
2251                         audio_sample_packet_detect ? "detected" : "not detected",
2252                         audio_mute ? "muted" : "enabled");
2253         if (audio_pll_locked && audio_sample_packet_detect) {
2254                 v4l2_info(sd, "Audio format: %s\n",
2255                         (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2256         }
2257         v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2258                         (hdmi_read(sd, 0x5c) << 8) +
2259                         (hdmi_read(sd, 0x5d) & 0xf0));
2260         v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2261                         (hdmi_read(sd, 0x5e) << 8) +
2262                         hdmi_read(sd, 0x5f));
2263         v4l2_info(sd, "AV Mute: %s\n",
2264                         (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2265         v4l2_info(sd, "Deep color mode: %s\n",
2266                         deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2267
2268         print_avi_infoframe(sd);
2269         return 0;
2270 }
2271
2272 static int adv7842_log_status(struct v4l2_subdev *sd)
2273 {
2274         struct adv7842_state *state = to_state(sd);
2275
2276         if (state->mode == ADV7842_MODE_SDP)
2277                 return adv7842_sdp_log_status(sd);
2278         return adv7842_cp_log_status(sd);
2279 }
2280
2281 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2282 {
2283         struct adv7842_state *state = to_state(sd);
2284
2285         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2286
2287         if (state->mode != ADV7842_MODE_SDP)
2288                 return -ENODATA;
2289
2290         if (!(sdp_read(sd, 0x5A) & 0x01)) {
2291                 *std = 0;
2292                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2293                 return 0;
2294         }
2295
2296         switch (sdp_read(sd, 0x52) & 0x0f) {
2297         case 0:
2298                 /* NTSC-M/J */
2299                 *std &= V4L2_STD_NTSC;
2300                 break;
2301         case 2:
2302                 /* NTSC-443 */
2303                 *std &= V4L2_STD_NTSC_443;
2304                 break;
2305         case 3:
2306                 /* 60HzSECAM */
2307                 *std &= V4L2_STD_SECAM;
2308                 break;
2309         case 4:
2310                 /* PAL-M */
2311                 *std &= V4L2_STD_PAL_M;
2312                 break;
2313         case 6:
2314                 /* PAL-60 */
2315                 *std &= V4L2_STD_PAL_60;
2316                 break;
2317         case 0xc:
2318                 /* PAL-CombN */
2319                 *std &= V4L2_STD_PAL_Nc;
2320                 break;
2321         case 0xe:
2322                 /* PAL-BGHID */
2323                 *std &= V4L2_STD_PAL;
2324                 break;
2325         case 0xf:
2326                 /* SECAM */
2327                 *std &= V4L2_STD_SECAM;
2328                 break;
2329         default:
2330                 *std &= V4L2_STD_ALL;
2331                 break;
2332         }
2333         return 0;
2334 }
2335
2336 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2337 {
2338         if (s && s->adjust) {
2339                 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2340                 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2341                 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2342                 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2343                 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2344                 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2345                 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2346                 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2347                 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2348                 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2349                 sdp_io_write(sd, 0xae, s->de_v_end_o);
2350                 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2351         } else {
2352                 /* set to default */
2353                 sdp_io_write(sd, 0x94, 0x00);
2354                 sdp_io_write(sd, 0x95, 0x00);
2355                 sdp_io_write(sd, 0x96, 0x00);
2356                 sdp_io_write(sd, 0x97, 0x20);
2357                 sdp_io_write(sd, 0x98, 0x00);
2358                 sdp_io_write(sd, 0x99, 0x00);
2359                 sdp_io_write(sd, 0x9a, 0x00);
2360                 sdp_io_write(sd, 0x9b, 0x00);
2361                 sdp_io_write(sd, 0xac, 0x04);
2362                 sdp_io_write(sd, 0xad, 0x04);
2363                 sdp_io_write(sd, 0xae, 0x04);
2364                 sdp_io_write(sd, 0xaf, 0x04);
2365         }
2366 }
2367
2368 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2369 {
2370         struct adv7842_state *state = to_state(sd);
2371         struct adv7842_platform_data *pdata = &state->pdata;
2372
2373         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2374
2375         if (state->mode != ADV7842_MODE_SDP)
2376                 return -ENODATA;
2377
2378         if (norm & V4L2_STD_625_50)
2379                 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2380         else if (norm & V4L2_STD_525_60)
2381                 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2382         else
2383                 adv7842_s_sdp_io(sd, NULL);
2384
2385         if (norm & V4L2_STD_ALL) {
2386                 state->norm = norm;
2387                 return 0;
2388         }
2389         return -EINVAL;
2390 }
2391
2392 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2393 {
2394         struct adv7842_state *state = to_state(sd);
2395
2396         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2397
2398         if (state->mode != ADV7842_MODE_SDP)
2399                 return -ENODATA;
2400
2401         *norm = state->norm;
2402         return 0;
2403 }
2404
2405 /* ----------------------------------------------------------------------- */
2406
2407 static int adv7842_core_init(struct v4l2_subdev *sd)
2408 {
2409         struct adv7842_state *state = to_state(sd);
2410         struct adv7842_platform_data *pdata = &state->pdata;
2411         hdmi_write(sd, 0x48,
2412                    (pdata->disable_pwrdnb ? 0x80 : 0) |
2413                    (pdata->disable_cable_det_rst ? 0x40 : 0));
2414
2415         disable_input(sd);
2416
2417         /* power */
2418         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2419         io_write(sd, 0x15, 0x80);   /* Power up pads */
2420
2421         /* video format */
2422         io_write(sd, 0x02,
2423                  0xf0 |
2424                  pdata->alt_gamma << 3 |
2425                  pdata->op_656_range << 2 |
2426                  pdata->rgb_out << 1 |
2427                  pdata->alt_data_sat << 0);
2428         io_write(sd, 0x03, pdata->op_format_sel);
2429         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2430         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2431                         pdata->insert_av_codes << 2 |
2432                         pdata->replicate_av_codes << 1 |
2433                         pdata->invert_cbcr << 0);
2434
2435         /* Drive strength */
2436         io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
2437                         pdata->drive_strength.clock<<2 |
2438                         pdata->drive_strength.sync);
2439
2440         /* HDMI free run */
2441         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01);
2442
2443         /* TODO from platform data */
2444         cp_write(sd, 0x69, 0x14);   /* Enable CP CSC */
2445         io_write(sd, 0x06, 0xa6);   /* positive VS and HS and DE */
2446         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2447         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2448
2449         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2450         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2451
2452         sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2453
2454         /* todo, improve settings for sdram */
2455         if (pdata->sd_ram_size >= 128) {
2456                 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2457                 if (pdata->sd_ram_ddr) {
2458                         /* SDP setup for the AD eval board */
2459                         sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2460                         sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2461                         sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2462                         sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2463                         sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2464                 } else {
2465                         sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2466                         sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2467                         sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2468                                                          depends on memory */
2469                         sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2470                         sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2471                         sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2472                         sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2473                 }
2474         } else {
2475                 /*
2476                  * Manual UG-214, rev 0 is bit confusing on this bit
2477                  * but a '1' disables any signal if the Ram is active.
2478                  */
2479                 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2480         }
2481
2482         select_input(sd, pdata->vid_std_select);
2483
2484         enable_input(sd);
2485
2486         /* disable I2C access to internal EDID ram from HDMI DDC ports */
2487         rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2488
2489         hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2490         /* HPA disable on port A and B */
2491         io_write_and_or(sd, 0x20, 0xcf, 0x00);
2492
2493         /* LLC */
2494         /* Set phase to 16. TODO: get this from platform_data */
2495         io_write(sd, 0x19, 0x90);
2496         io_write(sd, 0x33, 0x40);
2497
2498         /* interrupts */
2499         io_write(sd, 0x40, 0xf2); /* Configure INT1 */
2500
2501         adv7842_irq_enable(sd, true);
2502
2503         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2504 }
2505
2506 /* ----------------------------------------------------------------------- */
2507
2508 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2509 {
2510         /*
2511          * From ADV784x external Memory test.pdf
2512          *
2513          * Reset must just been performed before running test.
2514          * Recommended to reset after test.
2515          */
2516         int i;
2517         int pass = 0;
2518         int fail = 0;
2519         int complete = 0;
2520
2521         io_write(sd, 0x00, 0x01);  /* Program SDP 4x1 */
2522         io_write(sd, 0x01, 0x00);  /* Program SDP mode */
2523         afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2524         afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2525         afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2526         afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2527         afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2528         afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2529         io_write(sd, 0x0C, 0x40);  /* Power up ADV7844 */
2530         io_write(sd, 0x15, 0xBA);  /* Enable outputs */
2531         sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2532         io_write(sd, 0xFF, 0x04);  /* Reset memory controller */
2533
2534         mdelay(5);
2535
2536         sdp_write(sd, 0x12, 0x00);    /* Disable 3D Comb, Frame TBC & 3DNR */
2537         sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2538         sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2539         sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2540         sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2541         sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2542         sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2543         sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2544         sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2545         sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2546         sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2547
2548         mdelay(5);
2549
2550         sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2551         sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2552
2553         mdelay(20);
2554
2555         for (i = 0; i < 10; i++) {
2556                 u8 result = sdp_io_read(sd, 0xdb);
2557                 if (result & 0x10) {
2558                         complete++;
2559                         if (result & 0x20)
2560                                 fail++;
2561                         else
2562                                 pass++;
2563                 }
2564                 mdelay(20);
2565         }
2566
2567         v4l2_dbg(1, debug, sd,
2568                 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2569                 complete, i, pass, fail);
2570
2571         if (!complete || fail)
2572                 return -EIO;
2573         return 0;
2574 }
2575
2576 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2577                 struct adv7842_platform_data *pdata)
2578 {
2579         io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2580         io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2581         io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2582         io_write(sd, 0xf4, pdata->i2c_cec << 1);
2583         io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2584
2585         io_write(sd, 0xf8, pdata->i2c_afe << 1);
2586         io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2587         io_write(sd, 0xfa, pdata->i2c_edid << 1);
2588         io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2589
2590         io_write(sd, 0xfd, pdata->i2c_cp << 1);
2591         io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2592 }
2593
2594 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2595 {
2596         struct i2c_client *client = v4l2_get_subdevdata(sd);
2597         struct adv7842_state *state = to_state(sd);
2598         struct adv7842_platform_data *pdata = client->dev.platform_data;
2599         int ret = 0;
2600
2601         if (!pdata)
2602                 return -ENODEV;
2603
2604         if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2605                 v4l2_info(sd, "no sdram or no ddr sdram\n");
2606                 return -EINVAL;
2607         }
2608
2609         main_reset(sd);
2610
2611         adv7842_rewrite_i2c_addresses(sd, pdata);
2612
2613         /* run ram test */
2614         ret = adv7842_ddr_ram_test(sd);
2615
2616         main_reset(sd);
2617
2618         adv7842_rewrite_i2c_addresses(sd, pdata);
2619
2620         /* and re-init chip and state */
2621         adv7842_core_init(sd);
2622
2623         disable_input(sd);
2624
2625         select_input(sd, state->vid_std_select);
2626
2627         enable_input(sd);
2628
2629         adv7842_s_dv_timings(sd, &state->timings);
2630
2631         edid_write_vga_segment(sd);
2632         edid_write_hdmi_segment(sd, 0);
2633         edid_write_hdmi_segment(sd, 1);
2634
2635         return ret;
2636 }
2637
2638 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2639 {
2640         switch (cmd) {
2641         case ADV7842_CMD_RAM_TEST:
2642                 return adv7842_command_ram_test(sd);
2643         }
2644         return -ENOTTY;
2645 }
2646
2647 /* ----------------------------------------------------------------------- */
2648
2649 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2650         .s_ctrl = adv7842_s_ctrl,
2651 };
2652
2653 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2654         .log_status = adv7842_log_status,
2655         .g_std = adv7842_g_std,
2656         .s_std = adv7842_s_std,
2657         .ioctl = adv7842_ioctl,
2658         .interrupt_service_routine = adv7842_isr,
2659 #ifdef CONFIG_VIDEO_ADV_DEBUG
2660         .g_register = adv7842_g_register,
2661         .s_register = adv7842_s_register,
2662 #endif
2663 };
2664
2665 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2666         .s_routing = adv7842_s_routing,
2667         .querystd = adv7842_querystd,
2668         .g_input_status = adv7842_g_input_status,
2669         .s_dv_timings = adv7842_s_dv_timings,
2670         .g_dv_timings = adv7842_g_dv_timings,
2671         .query_dv_timings = adv7842_query_dv_timings,
2672         .enum_dv_timings = adv7842_enum_dv_timings,
2673         .dv_timings_cap = adv7842_dv_timings_cap,
2674         .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2675         .g_mbus_fmt = adv7842_g_mbus_fmt,
2676         .try_mbus_fmt = adv7842_g_mbus_fmt,
2677         .s_mbus_fmt = adv7842_g_mbus_fmt,
2678 };
2679
2680 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2681         .set_edid = adv7842_set_edid,
2682 };
2683
2684 static const struct v4l2_subdev_ops adv7842_ops = {
2685         .core = &adv7842_core_ops,
2686         .video = &adv7842_video_ops,
2687         .pad = &adv7842_pad_ops,
2688 };
2689
2690 /* -------------------------- custom ctrls ---------------------------------- */
2691
2692 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2693         .ops = &adv7842_ctrl_ops,
2694         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2695         .name = "Analog Sampling Phase",
2696         .type = V4L2_CTRL_TYPE_INTEGER,
2697         .min = 0,
2698         .max = 0x1f,
2699         .step = 1,
2700         .def = 0,
2701 };
2702
2703 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2704         .ops = &adv7842_ctrl_ops,
2705         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2706         .name = "Free Running Color, Manual",
2707         .type = V4L2_CTRL_TYPE_BOOLEAN,
2708         .max = 1,
2709         .step = 1,
2710         .def = 1,
2711 };
2712
2713 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2714         .ops = &adv7842_ctrl_ops,
2715         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2716         .name = "Free Running Color",
2717         .type = V4L2_CTRL_TYPE_INTEGER,
2718         .max = 0xffffff,
2719         .step = 0x1,
2720 };
2721
2722
2723 static void adv7842_unregister_clients(struct adv7842_state *state)
2724 {
2725         if (state->i2c_avlink)
2726                 i2c_unregister_device(state->i2c_avlink);
2727         if (state->i2c_cec)
2728                 i2c_unregister_device(state->i2c_cec);
2729         if (state->i2c_infoframe)
2730                 i2c_unregister_device(state->i2c_infoframe);
2731         if (state->i2c_sdp_io)
2732                 i2c_unregister_device(state->i2c_sdp_io);
2733         if (state->i2c_sdp)
2734                 i2c_unregister_device(state->i2c_sdp);
2735         if (state->i2c_afe)
2736                 i2c_unregister_device(state->i2c_afe);
2737         if (state->i2c_repeater)
2738                 i2c_unregister_device(state->i2c_repeater);
2739         if (state->i2c_edid)
2740                 i2c_unregister_device(state->i2c_edid);
2741         if (state->i2c_hdmi)
2742                 i2c_unregister_device(state->i2c_hdmi);
2743         if (state->i2c_cp)
2744                 i2c_unregister_device(state->i2c_cp);
2745         if (state->i2c_vdp)
2746                 i2c_unregister_device(state->i2c_vdp);
2747 }
2748
2749 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd,
2750                                                u8 addr, u8 io_reg)
2751 {
2752         struct i2c_client *client = v4l2_get_subdevdata(sd);
2753
2754         io_write(sd, io_reg, addr << 1);
2755         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2756 }
2757
2758 static int adv7842_probe(struct i2c_client *client,
2759                          const struct i2c_device_id *id)
2760 {
2761         struct adv7842_state *state;
2762         struct adv7842_platform_data *pdata = client->dev.platform_data;
2763         struct v4l2_ctrl_handler *hdl;
2764         struct v4l2_subdev *sd;
2765         u16 rev;
2766         int err;
2767
2768         /* Check if the adapter supports the needed features */
2769         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2770                 return -EIO;
2771
2772         v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2773                 client->addr << 1);
2774
2775         if (!pdata) {
2776                 v4l_err(client, "No platform data!\n");
2777                 return -ENODEV;
2778         }
2779
2780         state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2781         if (!state) {
2782                 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2783                 return -ENOMEM;
2784         }
2785
2786         /* platform data */
2787         state->pdata = *pdata;
2788
2789         sd = &state->sd;
2790         v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2791         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2792         state->mode = pdata->mode;
2793
2794         state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
2795
2796         /* i2c access to adv7842? */
2797         rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2798                 adv_smbus_read_byte_data_check(client, 0xeb, false);
2799         if (rev != 0x2012) {
2800                 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
2801                 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2802                         adv_smbus_read_byte_data_check(client, 0xeb, false);
2803         }
2804         if (rev != 0x2012) {
2805                 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
2806                           client->addr << 1, rev);
2807                 return -ENODEV;
2808         }
2809
2810         if (pdata->chip_reset)
2811                 main_reset(sd);
2812
2813         /* control handlers */
2814         hdl = &state->hdl;
2815         v4l2_ctrl_handler_init(hdl, 6);
2816
2817         /* add in ascending ID order */
2818         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2819                           V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2820         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2821                           V4L2_CID_CONTRAST, 0, 255, 1, 128);
2822         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2823                           V4L2_CID_SATURATION, 0, 255, 1, 128);
2824         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2825                           V4L2_CID_HUE, 0, 128, 1, 0);
2826
2827         /* custom controls */
2828         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2829                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
2830         state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
2831                         &adv7842_ctrl_analog_sampling_phase, NULL);
2832         state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
2833                         &adv7842_ctrl_free_run_color_manual, NULL);
2834         state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
2835                         &adv7842_ctrl_free_run_color, NULL);
2836         state->rgb_quantization_range_ctrl =
2837                 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
2838                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2839                         0, V4L2_DV_RGB_RANGE_AUTO);
2840         sd->ctrl_handler = hdl;
2841         if (hdl->error) {
2842                 err = hdl->error;
2843                 goto err_hdl;
2844         }
2845         state->detect_tx_5v_ctrl->is_private = true;
2846         state->rgb_quantization_range_ctrl->is_private = true;
2847         state->analog_sampling_phase_ctrl->is_private = true;
2848         state->free_run_color_ctrl_manual->is_private = true;
2849         state->free_run_color_ctrl->is_private = true;
2850
2851         if (adv7842_s_detect_tx_5v_ctrl(sd)) {
2852                 err = -ENODEV;
2853                 goto err_hdl;
2854         }
2855
2856         state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2857         state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4);
2858         state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2859         state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2);
2860         state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1);
2861         state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8);
2862         state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2863         state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa);
2864         state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2865         state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd);
2866         state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2867         if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2868             !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe ||
2869             !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2870             !state->i2c_cp || !state->i2c_vdp) {
2871                 err = -ENOMEM;
2872                 v4l2_err(sd, "failed to create all i2c clients\n");
2873                 goto err_i2c;
2874         }
2875
2876         /* work queues */
2877         state->work_queues = create_singlethread_workqueue(client->name);
2878         if (!state->work_queues) {
2879                 v4l2_err(sd, "Could not create work queue\n");
2880                 err = -ENOMEM;
2881                 goto err_i2c;
2882         }
2883
2884         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2885                         adv7842_delayed_work_enable_hotplug);
2886
2887         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2888         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2889         if (err)
2890                 goto err_work_queues;
2891
2892         err = adv7842_core_init(sd);
2893         if (err)
2894                 goto err_entity;
2895
2896         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2897                   client->addr << 1, client->adapter->name);
2898         return 0;
2899
2900 err_entity:
2901         media_entity_cleanup(&sd->entity);
2902 err_work_queues:
2903         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2904         destroy_workqueue(state->work_queues);
2905 err_i2c:
2906         adv7842_unregister_clients(state);
2907 err_hdl:
2908         v4l2_ctrl_handler_free(hdl);
2909         return err;
2910 }
2911
2912 /* ----------------------------------------------------------------------- */
2913
2914 static int adv7842_remove(struct i2c_client *client)
2915 {
2916         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2917         struct adv7842_state *state = to_state(sd);
2918
2919         adv7842_irq_enable(sd, false);
2920
2921         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2922         destroy_workqueue(state->work_queues);
2923         v4l2_device_unregister_subdev(sd);
2924         media_entity_cleanup(&sd->entity);
2925         adv7842_unregister_clients(to_state(sd));
2926         v4l2_ctrl_handler_free(sd->ctrl_handler);
2927         return 0;
2928 }
2929
2930 /* ----------------------------------------------------------------------- */
2931
2932 static struct i2c_device_id adv7842_id[] = {
2933         { "adv7842", 0 },
2934         { }
2935 };
2936 MODULE_DEVICE_TABLE(i2c, adv7842_id);
2937
2938 /* ----------------------------------------------------------------------- */
2939
2940 static struct i2c_driver adv7842_driver = {
2941         .driver = {
2942                 .owner = THIS_MODULE,
2943                 .name = "adv7842",
2944         },
2945         .probe = adv7842_probe,
2946         .remove = adv7842_remove,
2947         .id_table = adv7842_id,
2948 };
2949
2950 module_i2c_driver(adv7842_driver);