2 * adv7842 - Analog Devices ADV7842 video decoder driver
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/i2c.h>
34 #include <linux/delay.h>
35 #include <linux/videodev2.h>
36 #include <linux/workqueue.h>
37 #include <linux/v4l2-dv-timings.h>
38 #include <media/v4l2-device.h>
39 #include <media/v4l2-ctrls.h>
40 #include <media/v4l2-dv-timings.h>
41 #include <media/adv7842.h>
44 module_param(debug, int, 0644);
45 MODULE_PARM_DESC(debug, "debug level (0-2)");
47 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
48 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
49 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
50 MODULE_LICENSE("GPL");
52 /* ADV7842 system clock frequency */
53 #define ADV7842_fsc (28636360)
56 **********************************************************************
58 * Arrays with configuration parameters for the ADV7842
60 **********************************************************************
63 struct adv7842_state {
64 struct adv7842_platform_data pdata;
65 struct v4l2_subdev sd;
67 struct v4l2_ctrl_handler hdl;
68 enum adv7842_mode mode;
69 struct v4l2_dv_timings timings;
70 enum adv7842_vid_std_select vid_std_select;
80 struct v4l2_fract aspect_ratio;
81 u32 rgb_quantization_range;
83 struct workqueue_struct *work_queues;
84 struct delayed_work delayed_work_enable_hotplug;
88 struct i2c_client *i2c_sdp_io;
89 struct i2c_client *i2c_sdp;
90 struct i2c_client *i2c_cp;
91 struct i2c_client *i2c_vdp;
92 struct i2c_client *i2c_afe;
93 struct i2c_client *i2c_hdmi;
94 struct i2c_client *i2c_repeater;
95 struct i2c_client *i2c_edid;
96 struct i2c_client *i2c_infoframe;
97 struct i2c_client *i2c_cec;
98 struct i2c_client *i2c_avlink;
101 struct v4l2_ctrl *detect_tx_5v_ctrl;
102 struct v4l2_ctrl *analog_sampling_phase_ctrl;
103 struct v4l2_ctrl *free_run_color_ctrl_manual;
104 struct v4l2_ctrl *free_run_color_ctrl;
105 struct v4l2_ctrl *rgb_quantization_range_ctrl;
108 /* Unsupported timings. This device cannot support 720p30. */
109 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
110 V4L2_DV_BT_CEA_1280X720P30,
114 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
118 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
119 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
124 struct adv7842_video_standards {
125 struct v4l2_dv_timings timings;
130 /* sorted by number of lines */
131 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
132 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
133 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
134 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
135 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
136 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
137 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
138 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
139 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
140 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
141 /* TODO add 1920x1080P60_RB (CVT timing) */
145 /* sorted by number of lines */
146 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
147 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
148 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
149 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
150 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
151 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
152 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
153 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
154 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
155 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
156 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
157 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
158 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
159 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
160 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
161 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
162 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
163 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
164 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
165 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
166 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
167 /* TODO add 1600X1200P60_RB (not a DMT timing) */
168 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
169 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
173 /* sorted by number of lines */
174 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
175 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
176 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
177 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
178 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
179 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
180 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
181 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
182 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
183 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
187 /* sorted by number of lines */
188 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
189 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
190 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
191 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
193 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
194 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
198 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
199 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
202 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
203 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
207 /* ----------------------------------------------------------------------- */
209 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
211 return container_of(sd, struct adv7842_state, sd);
214 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
216 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
219 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
221 return V4L2_DV_BT_BLANKING_WIDTH(t);
224 static inline unsigned htotal(const struct v4l2_bt_timings *t)
226 return V4L2_DV_BT_FRAME_WIDTH(t);
229 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
231 return V4L2_DV_BT_BLANKING_HEIGHT(t);
234 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
236 return V4L2_DV_BT_FRAME_HEIGHT(t);
240 /* ----------------------------------------------------------------------- */
242 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
243 u8 command, bool check)
245 union i2c_smbus_data data;
247 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
248 I2C_SMBUS_READ, command,
249 I2C_SMBUS_BYTE_DATA, &data))
252 v4l_err(client, "error reading %02x, %02x\n",
253 client->addr, command);
257 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
261 for (i = 0; i < 3; i++) {
262 int ret = adv_smbus_read_byte_data_check(client, command, true);
266 v4l_err(client, "read ok after %d retries\n", i);
270 v4l_err(client, "read failed\n");
274 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
275 u8 command, u8 value)
277 union i2c_smbus_data data;
282 for (i = 0; i < 3; i++) {
283 err = i2c_smbus_xfer(client->adapter, client->addr,
285 I2C_SMBUS_WRITE, command,
286 I2C_SMBUS_BYTE_DATA, &data);
291 v4l_err(client, "error writing %02x, %02x, %02x\n",
292 client->addr, command, value);
296 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
297 u8 command, u8 value)
299 union i2c_smbus_data data;
302 i2c_smbus_xfer(client->adapter, client->addr,
304 I2C_SMBUS_WRITE, command,
305 I2C_SMBUS_BYTE_DATA, &data);
308 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
309 u8 command, unsigned length, const u8 *values)
311 union i2c_smbus_data data;
313 if (length > I2C_SMBUS_BLOCK_MAX)
314 length = I2C_SMBUS_BLOCK_MAX;
315 data.block[0] = length;
316 memcpy(data.block + 1, values, length);
317 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
318 I2C_SMBUS_WRITE, command,
319 I2C_SMBUS_I2C_BLOCK_DATA, &data);
322 /* ----------------------------------------------------------------------- */
324 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
326 struct i2c_client *client = v4l2_get_subdevdata(sd);
328 return adv_smbus_read_byte_data(client, reg);
331 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
333 struct i2c_client *client = v4l2_get_subdevdata(sd);
335 return adv_smbus_write_byte_data(client, reg, val);
338 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
340 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
343 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
345 struct adv7842_state *state = to_state(sd);
347 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
350 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
352 struct adv7842_state *state = to_state(sd);
354 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
357 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
359 struct adv7842_state *state = to_state(sd);
361 return adv_smbus_read_byte_data(state->i2c_cec, reg);
364 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
366 struct adv7842_state *state = to_state(sd);
368 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
371 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
373 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
376 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
378 struct adv7842_state *state = to_state(sd);
380 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
383 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
385 struct adv7842_state *state = to_state(sd);
387 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
390 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
392 struct adv7842_state *state = to_state(sd);
394 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
397 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
399 struct adv7842_state *state = to_state(sd);
401 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
404 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
406 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
409 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
411 struct adv7842_state *state = to_state(sd);
413 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
416 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
418 struct adv7842_state *state = to_state(sd);
420 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
423 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
425 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
428 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
430 struct adv7842_state *state = to_state(sd);
432 return adv_smbus_read_byte_data(state->i2c_afe, reg);
435 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
437 struct adv7842_state *state = to_state(sd);
439 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
442 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
444 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
447 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
449 struct adv7842_state *state = to_state(sd);
451 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
454 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
456 struct adv7842_state *state = to_state(sd);
458 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
461 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
463 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
466 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
468 struct adv7842_state *state = to_state(sd);
470 return adv_smbus_read_byte_data(state->i2c_edid, reg);
473 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
475 struct adv7842_state *state = to_state(sd);
477 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
480 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
482 struct adv7842_state *state = to_state(sd);
484 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
487 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
489 struct adv7842_state *state = to_state(sd);
491 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
494 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
496 struct adv7842_state *state = to_state(sd);
498 return adv_smbus_read_byte_data(state->i2c_cp, reg);
501 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
503 struct adv7842_state *state = to_state(sd);
505 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
508 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
510 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
513 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
515 struct adv7842_state *state = to_state(sd);
517 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
520 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
522 struct adv7842_state *state = to_state(sd);
524 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
527 static void main_reset(struct v4l2_subdev *sd)
529 struct i2c_client *client = v4l2_get_subdevdata(sd);
531 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
533 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
538 /* ----------------------------------------------------------------------- */
540 static inline bool is_digital_input(struct v4l2_subdev *sd)
542 struct adv7842_state *state = to_state(sd);
544 return state->mode == ADV7842_MODE_HDMI;
547 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
548 .type = V4L2_DV_BT_656_1120,
549 /* keep this initialization for compatibility with GCC < 4.4.6 */
551 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
552 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
553 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
554 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
555 V4L2_DV_BT_CAP_CUSTOM)
558 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
559 .type = V4L2_DV_BT_656_1120,
560 /* keep this initialization for compatibility with GCC < 4.4.6 */
562 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
563 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
564 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
565 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
566 V4L2_DV_BT_CAP_CUSTOM)
569 static inline const struct v4l2_dv_timings_cap *
570 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
572 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
573 &adv7842_timings_cap_analog;
576 /* ----------------------------------------------------------------------- */
578 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
580 struct delayed_work *dwork = to_delayed_work(work);
581 struct adv7842_state *state = container_of(dwork,
582 struct adv7842_state, delayed_work_enable_hotplug);
583 struct v4l2_subdev *sd = &state->sd;
584 int present = state->hdmi_edid.present;
587 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
591 mask |= 0x20; /* port A */
593 mask |= 0x10; /* port B */
594 io_write_and_or(sd, 0x20, 0xcf, mask);
597 static int edid_write_vga_segment(struct v4l2_subdev *sd)
599 struct i2c_client *client = v4l2_get_subdevdata(sd);
600 struct adv7842_state *state = to_state(sd);
601 const u8 *val = state->vga_edid.edid;
605 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
607 /* HPA disable on port A and B */
608 io_write_and_or(sd, 0x20, 0xcf, 0x00);
610 /* Disable I2C access to internal EDID ram from VGA DDC port */
611 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
613 /* edid segment pointer '1' for VGA port */
614 rep_write_and_or(sd, 0x77, 0xef, 0x10);
616 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
617 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
618 I2C_SMBUS_BLOCK_MAX, val + i);
622 /* Calculates the checksums and enables I2C access
623 * to internal EDID ram from VGA DDC port.
625 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
627 for (i = 0; i < 1000; i++) {
628 if (rep_read(sd, 0x79) & 0x20)
633 v4l_err(client, "error enabling edid on VGA port\n");
637 /* enable hotplug after 200 ms */
638 queue_delayed_work(state->work_queues,
639 &state->delayed_work_enable_hotplug, HZ / 5);
644 static int edid_spa_location(const u8 *edid)
649 * TODO, improve and update for other CEA extensions
650 * currently only for 1 segment (256 bytes),
651 * i.e. 1 extension block and CEA revision 3.
653 if ((edid[0x7e] != 1) ||
654 (edid[0x80] != 0x02) ||
655 (edid[0x81] != 0x03)) {
659 * search Vendor Specific Data Block (tag 3)
661 d = edid[0x82] & 0x7f;
667 u8 len = edid[i] & 0x1f;
669 if ((tag == 3) && (len >= 5))
677 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
679 struct i2c_client *client = v4l2_get_subdevdata(sd);
680 struct adv7842_state *state = to_state(sd);
681 const u8 *val = state->hdmi_edid.edid;
682 u8 cur_mask = rep_read(sd, 0x77) & 0x0c;
683 u8 mask = port == 0 ? 0x4 : 0x8;
684 int spa_loc = edid_spa_location(val);
688 v4l2_dbg(2, debug, sd, "%s: write EDID on port %d (spa at 0x%x)\n",
689 __func__, port, spa_loc);
691 /* HPA disable on port A and B */
692 io_write_and_or(sd, 0x20, 0xcf, 0x00);
694 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
695 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
697 /* edid segment pointer '0' for HDMI ports */
698 rep_write_and_or(sd, 0x77, 0xef, 0x00);
700 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
701 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
702 I2C_SMBUS_BLOCK_MAX, val + i);
709 rep_write(sd, 0x72, val[spa_loc]);
710 rep_write(sd, 0x73, val[spa_loc + 1]);
713 rep_write(sd, 0x74, val[spa_loc]);
714 rep_write(sd, 0x75, val[spa_loc + 1]);
716 rep_write(sd, 0x76, spa_loc);
718 /* Edid values for SPA location */
721 rep_write(sd, 0x72, val[0xc0]);
722 rep_write(sd, 0x73, val[0xc1]);
725 rep_write(sd, 0x74, val[0xc0]);
726 rep_write(sd, 0x75, val[0xc1]);
728 rep_write(sd, 0x76, 0xc0);
730 rep_write_and_or(sd, 0x77, 0xbf, 0x00);
732 /* Calculates the checksums and enables I2C access to internal
733 * EDID ram from HDMI DDC ports
735 rep_write_and_or(sd, 0x77, 0xf3, mask | cur_mask);
737 for (i = 0; i < 1000; i++) {
738 if (rep_read(sd, 0x7d) & mask)
743 v4l_err(client, "error enabling edid on port %d\n", port);
747 /* enable hotplug after 200 ms */
748 queue_delayed_work(state->work_queues,
749 &state->delayed_work_enable_hotplug, HZ / 5);
754 /* ----------------------------------------------------------------------- */
756 #ifdef CONFIG_VIDEO_ADV_DEBUG
757 static void adv7842_inv_register(struct v4l2_subdev *sd)
759 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
760 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
761 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
762 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
763 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
764 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
765 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
766 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
767 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
768 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
769 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
770 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
773 static int adv7842_g_register(struct v4l2_subdev *sd,
774 struct v4l2_dbg_register *reg)
777 switch (reg->reg >> 8) {
779 reg->val = io_read(sd, reg->reg & 0xff);
782 reg->val = avlink_read(sd, reg->reg & 0xff);
785 reg->val = cec_read(sd, reg->reg & 0xff);
788 reg->val = infoframe_read(sd, reg->reg & 0xff);
791 reg->val = sdp_io_read(sd, reg->reg & 0xff);
794 reg->val = sdp_read(sd, reg->reg & 0xff);
797 reg->val = afe_read(sd, reg->reg & 0xff);
800 reg->val = rep_read(sd, reg->reg & 0xff);
803 reg->val = edid_read(sd, reg->reg & 0xff);
806 reg->val = hdmi_read(sd, reg->reg & 0xff);
809 reg->val = cp_read(sd, reg->reg & 0xff);
812 reg->val = vdp_read(sd, reg->reg & 0xff);
815 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
816 adv7842_inv_register(sd);
822 static int adv7842_s_register(struct v4l2_subdev *sd,
823 const struct v4l2_dbg_register *reg)
825 u8 val = reg->val & 0xff;
827 switch (reg->reg >> 8) {
829 io_write(sd, reg->reg & 0xff, val);
832 avlink_write(sd, reg->reg & 0xff, val);
835 cec_write(sd, reg->reg & 0xff, val);
838 infoframe_write(sd, reg->reg & 0xff, val);
841 sdp_io_write(sd, reg->reg & 0xff, val);
844 sdp_write(sd, reg->reg & 0xff, val);
847 afe_write(sd, reg->reg & 0xff, val);
850 rep_write(sd, reg->reg & 0xff, val);
853 edid_write(sd, reg->reg & 0xff, val);
856 hdmi_write(sd, reg->reg & 0xff, val);
859 cp_write(sd, reg->reg & 0xff, val);
862 vdp_write(sd, reg->reg & 0xff, val);
865 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
866 adv7842_inv_register(sd);
873 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
875 struct adv7842_state *state = to_state(sd);
876 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
877 u8 reg_io_6f = io_read(sd, 0x6f);
880 if (reg_io_6f & 0x02)
881 val |= 1; /* port A */
882 if (reg_io_6f & 0x01)
883 val |= 2; /* port B */
885 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
888 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
892 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
894 const struct adv7842_video_standards *predef_vid_timings,
895 const struct v4l2_dv_timings *timings)
899 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
900 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
901 is_digital_input(sd) ? 250000 : 1000000))
904 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
905 /* v_freq and prim mode */
906 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
913 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
914 struct v4l2_dv_timings *timings)
916 struct adv7842_state *state = to_state(sd);
919 v4l2_dbg(1, debug, sd, "%s\n", __func__);
921 /* reset to default values */
922 io_write(sd, 0x16, 0x43);
923 io_write(sd, 0x17, 0x5a);
924 /* disable embedded syncs for auto graphics mode */
925 cp_write_and_or(sd, 0x81, 0xef, 0x00);
926 cp_write(sd, 0x26, 0x00);
927 cp_write(sd, 0x27, 0x00);
928 cp_write(sd, 0x28, 0x00);
929 cp_write(sd, 0x29, 0x00);
930 cp_write(sd, 0x8f, 0x40);
931 cp_write(sd, 0x90, 0x00);
932 cp_write(sd, 0xa5, 0x00);
933 cp_write(sd, 0xa6, 0x00);
934 cp_write(sd, 0xa7, 0x00);
935 cp_write(sd, 0xab, 0x00);
936 cp_write(sd, 0xac, 0x00);
938 switch (state->mode) {
939 case ADV7842_MODE_COMP:
940 case ADV7842_MODE_RGB:
941 err = find_and_set_predefined_video_timings(sd,
942 0x01, adv7842_prim_mode_comp, timings);
944 err = find_and_set_predefined_video_timings(sd,
945 0x02, adv7842_prim_mode_gr, timings);
947 case ADV7842_MODE_HDMI:
948 err = find_and_set_predefined_video_timings(sd,
949 0x05, adv7842_prim_mode_hdmi_comp, timings);
951 err = find_and_set_predefined_video_timings(sd,
952 0x06, adv7842_prim_mode_hdmi_gr, timings);
955 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
956 __func__, state->mode);
965 static void configure_custom_video_timings(struct v4l2_subdev *sd,
966 const struct v4l2_bt_timings *bt)
968 struct adv7842_state *state = to_state(sd);
969 struct i2c_client *client = v4l2_get_subdevdata(sd);
970 u32 width = htotal(bt);
971 u32 height = vtotal(bt);
972 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
973 u16 cp_start_eav = width - bt->hfrontporch;
974 u16 cp_start_vbi = height - bt->vfrontporch + 1;
975 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
976 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
977 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
979 0xc0 | ((width >> 8) & 0x1f),
983 v4l2_dbg(2, debug, sd, "%s\n", __func__);
985 switch (state->mode) {
986 case ADV7842_MODE_COMP:
987 case ADV7842_MODE_RGB:
989 io_write(sd, 0x00, 0x07); /* video std */
990 io_write(sd, 0x01, 0x02); /* prim mode */
991 /* enable embedded syncs for auto graphics mode */
992 cp_write_and_or(sd, 0x81, 0xef, 0x10);
994 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
995 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
996 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
997 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
998 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1002 /* active video - horizontal timing */
1003 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1004 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1005 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1006 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1008 /* active video - vertical timing */
1009 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1010 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1011 ((cp_end_vbi >> 8) & 0xf));
1012 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1014 case ADV7842_MODE_HDMI:
1015 /* set default prim_mode/vid_std for HDMI
1016 according to [REF_03, c. 4.2] */
1017 io_write(sd, 0x00, 0x02); /* video std */
1018 io_write(sd, 0x01, 0x06); /* prim mode */
1021 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1022 __func__, state->mode);
1026 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1027 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1028 cp_write(sd, 0xab, (height >> 4) & 0xff);
1029 cp_write(sd, 0xac, (height & 0x0f) << 4);
1032 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1034 struct adv7842_state *state = to_state(sd);
1036 v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
1037 __func__, state->rgb_quantization_range);
1039 switch (state->rgb_quantization_range) {
1040 case V4L2_DV_RGB_RANGE_AUTO:
1041 if (state->mode == ADV7842_MODE_RGB) {
1042 /* Receiving analog RGB signal
1043 * Set RGB full range (0-255) */
1044 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1048 if (state->mode == ADV7842_MODE_COMP) {
1049 /* Receiving analog YPbPr signal
1051 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1055 if (hdmi_read(sd, 0x05) & 0x80) {
1056 /* Receiving HDMI signal
1058 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1062 /* Receiving DVI-D signal
1063 * ADV7842 selects RGB limited range regardless of
1064 * input format (CE/IT) in automatic mode */
1065 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1066 /* RGB limited range (16-235) */
1067 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1069 /* RGB full range (0-255) */
1070 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1073 case V4L2_DV_RGB_RANGE_LIMITED:
1074 if (state->mode == ADV7842_MODE_COMP) {
1075 /* YCrCb limited range (16-235) */
1076 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1078 /* RGB limited range (16-235) */
1079 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1082 case V4L2_DV_RGB_RANGE_FULL:
1083 if (state->mode == ADV7842_MODE_COMP) {
1084 /* YCrCb full range (0-255) */
1085 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1087 /* RGB full range (0-255) */
1088 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1094 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1096 struct v4l2_subdev *sd = to_sd(ctrl);
1097 struct adv7842_state *state = to_state(sd);
1100 contrast/brightness/hue/free run is acting a bit strange,
1101 not sure if sdp csc is correct.
1104 /* standard ctrls */
1105 case V4L2_CID_BRIGHTNESS:
1106 cp_write(sd, 0x3c, ctrl->val);
1107 sdp_write(sd, 0x14, ctrl->val);
1108 /* ignore lsb sdp 0x17[3:2] */
1110 case V4L2_CID_CONTRAST:
1111 cp_write(sd, 0x3a, ctrl->val);
1112 sdp_write(sd, 0x13, ctrl->val);
1113 /* ignore lsb sdp 0x17[1:0] */
1115 case V4L2_CID_SATURATION:
1116 cp_write(sd, 0x3b, ctrl->val);
1117 sdp_write(sd, 0x15, ctrl->val);
1118 /* ignore lsb sdp 0x17[5:4] */
1121 cp_write(sd, 0x3d, ctrl->val);
1122 sdp_write(sd, 0x16, ctrl->val);
1123 /* ignore lsb sdp 0x17[7:6] */
1126 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1127 afe_write(sd, 0xc8, ctrl->val);
1129 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1130 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1131 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1133 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1134 u8 R = (ctrl->val & 0xff0000) >> 16;
1135 u8 G = (ctrl->val & 0x00ff00) >> 8;
1136 u8 B = (ctrl->val & 0x0000ff);
1137 /* RGB -> YUV, numerical approximation */
1138 int Y = 66 * R + 129 * G + 25 * B;
1139 int U = -38 * R - 74 * G + 112 * B;
1140 int V = 112 * R - 94 * G - 18 * B;
1142 /* Scale down to 8 bits with rounding */
1146 /* make U,V positive */
1151 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1152 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1155 cp_write(sd, 0xc1, R);
1156 cp_write(sd, 0xc0, G);
1157 cp_write(sd, 0xc2, B);
1159 sdp_write(sd, 0xde, Y);
1160 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1163 case V4L2_CID_DV_RX_RGB_RANGE:
1164 state->rgb_quantization_range = ctrl->val;
1165 set_rgb_quantization_range(sd);
1171 static inline bool no_power(struct v4l2_subdev *sd)
1173 return io_read(sd, 0x0c) & 0x24;
1176 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1178 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1181 static inline bool is_hdmi(struct v4l2_subdev *sd)
1183 return hdmi_read(sd, 0x05) & 0x80;
1186 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1188 struct adv7842_state *state = to_state(sd);
1192 if (io_read(sd, 0x0c) & 0x24)
1193 *status |= V4L2_IN_ST_NO_POWER;
1195 if (state->mode == ADV7842_MODE_SDP) {
1196 /* status from SDP block */
1197 if (!(sdp_read(sd, 0x5A) & 0x01))
1198 *status |= V4L2_IN_ST_NO_SIGNAL;
1200 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1204 /* status from CP block */
1205 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1206 !(cp_read(sd, 0xb1) & 0x80))
1207 /* TODO channel 2 */
1208 *status |= V4L2_IN_ST_NO_SIGNAL;
1210 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1211 *status |= V4L2_IN_ST_NO_SIGNAL;
1213 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1219 struct stdi_readback {
1225 static int stdi2dv_timings(struct v4l2_subdev *sd,
1226 struct stdi_readback *stdi,
1227 struct v4l2_dv_timings *timings)
1229 struct adv7842_state *state = to_state(sd);
1230 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1234 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1235 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1237 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1238 adv7842_get_dv_timings_cap(sd),
1239 adv7842_check_dv_timings, NULL))
1241 if (vtotal(bt) != stdi->lcf + 1)
1243 if (bt->vsync != stdi->lcvs)
1246 pix_clk = hfreq * htotal(bt);
1248 if ((pix_clk < bt->pixelclock + 1000000) &&
1249 (pix_clk > bt->pixelclock - 1000000)) {
1250 *timings = v4l2_dv_timings_presets[i];
1255 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1256 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1257 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1260 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1261 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1262 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1263 state->aspect_ratio, timings))
1266 v4l2_dbg(2, debug, sd,
1267 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1268 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1269 stdi->hs_pol, stdi->vs_pol);
1273 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1277 adv7842_g_input_status(sd, &status);
1278 if (status & V4L2_IN_ST_NO_SIGNAL) {
1279 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1283 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1284 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1285 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1287 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1288 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1289 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1290 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1291 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1296 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1298 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1299 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1303 v4l2_dbg(2, debug, sd,
1304 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1305 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1306 stdi->hs_pol, stdi->vs_pol,
1307 stdi->interlaced ? "interlaced" : "progressive");
1312 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1313 struct v4l2_enum_dv_timings *timings)
1315 return v4l2_enum_dv_timings_cap(timings,
1316 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1319 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1320 struct v4l2_dv_timings_cap *cap)
1322 *cap = *adv7842_get_dv_timings_cap(sd);
1326 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1327 if the format is listed in adv7842_timings[] */
1328 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1329 struct v4l2_dv_timings *timings)
1331 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1332 is_digital_input(sd) ? 250000 : 1000000,
1333 adv7842_check_dv_timings, NULL);
1336 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1337 struct v4l2_dv_timings *timings)
1339 struct adv7842_state *state = to_state(sd);
1340 struct v4l2_bt_timings *bt = &timings->bt;
1341 struct stdi_readback stdi = { 0 };
1343 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1346 if (state->mode == ADV7842_MODE_SDP)
1350 if (read_stdi(sd, &stdi)) {
1351 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1354 bt->interlaced = stdi.interlaced ?
1355 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1357 if (is_digital_input(sd)) {
1360 timings->type = V4L2_DV_BT_656_1120;
1361 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1362 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1363 freq = (hdmi_read(sd, 0x06) * 1000000) +
1364 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1367 /* adjust for deep color mode */
1368 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8);
1370 bt->pixelclock = freq;
1371 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1372 hdmi_read(sd, 0x21);
1373 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1374 hdmi_read(sd, 0x23);
1375 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1376 hdmi_read(sd, 0x25);
1377 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1378 hdmi_read(sd, 0x2b)) / 2;
1379 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1380 hdmi_read(sd, 0x2f)) / 2;
1381 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1382 hdmi_read(sd, 0x33)) / 2;
1383 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1384 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1385 if (bt->interlaced == V4L2_DV_INTERLACED) {
1386 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1387 hdmi_read(sd, 0x0c);
1388 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1389 hdmi_read(sd, 0x2d)) / 2;
1390 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1391 hdmi_read(sd, 0x31)) / 2;
1392 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1393 hdmi_read(sd, 0x35)) / 2;
1395 adv7842_fill_optional_dv_timings_fields(sd, timings);
1398 if (stdi.interlaced) {
1399 v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__);
1403 if (stdi2dv_timings(sd, &stdi, timings)) {
1404 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1410 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings: ",
1415 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1416 struct v4l2_dv_timings *timings)
1418 struct adv7842_state *state = to_state(sd);
1419 struct v4l2_bt_timings *bt;
1422 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1424 if (state->mode == ADV7842_MODE_SDP)
1429 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1430 adv7842_check_dv_timings, NULL))
1433 adv7842_fill_optional_dv_timings_fields(sd, timings);
1435 state->timings = *timings;
1437 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1439 /* Use prim_mode and vid_std when available */
1440 err = configure_predefined_video_timings(sd, timings);
1442 /* custom settings when the video format
1443 does not have prim_mode/vid_std */
1444 configure_custom_video_timings(sd, bt);
1447 set_rgb_quantization_range(sd);
1451 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1456 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1457 struct v4l2_dv_timings *timings)
1459 struct adv7842_state *state = to_state(sd);
1461 if (state->mode == ADV7842_MODE_SDP)
1463 *timings = state->timings;
1467 static void enable_input(struct v4l2_subdev *sd)
1469 struct adv7842_state *state = to_state(sd);
1471 set_rgb_quantization_range(sd);
1472 switch (state->mode) {
1473 case ADV7842_MODE_SDP:
1474 case ADV7842_MODE_COMP:
1475 case ADV7842_MODE_RGB:
1477 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1479 case ADV7842_MODE_HDMI:
1481 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1482 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1483 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1486 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1487 __func__, state->mode);
1492 static void disable_input(struct v4l2_subdev *sd)
1495 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1496 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1497 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1500 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1501 const struct adv7842_sdp_csc_coeff *c)
1503 /* csc auto/manual */
1504 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1510 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1513 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1514 sdp_io_write(sd, 0xe1, c->A1);
1515 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1516 sdp_io_write(sd, 0xe3, c->A2);
1517 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1518 sdp_io_write(sd, 0xe5, c->A3);
1521 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1522 sdp_io_write(sd, 0xe7, c->A4);
1525 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1526 sdp_io_write(sd, 0xe9, c->B1);
1527 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1528 sdp_io_write(sd, 0xeb, c->B2);
1529 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1530 sdp_io_write(sd, 0xed, c->B3);
1533 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1534 sdp_io_write(sd, 0xef, c->B4);
1537 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1538 sdp_io_write(sd, 0xf1, c->C1);
1539 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1540 sdp_io_write(sd, 0xf3, c->C2);
1541 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1542 sdp_io_write(sd, 0xf5, c->C3);
1545 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1546 sdp_io_write(sd, 0xf7, c->C4);
1549 static void select_input(struct v4l2_subdev *sd,
1550 enum adv7842_vid_std_select vid_std_select)
1552 struct adv7842_state *state = to_state(sd);
1554 switch (state->mode) {
1555 case ADV7842_MODE_SDP:
1556 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1557 io_write(sd, 0x01, 0); /* prim mode */
1558 /* enable embedded syncs for auto graphics mode */
1559 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1561 afe_write(sd, 0x00, 0x00); /* power up ADC */
1562 afe_write(sd, 0xc8, 0x00); /* phase control */
1564 io_write(sd, 0x19, 0x83); /* LLC DLL phase */
1565 io_write(sd, 0x33, 0x40); /* LLC DLL enable */
1567 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1568 /* script says register 0xde, which don't exist in manual */
1570 /* Manual analog input muxing mode, CVBS (6.4)*/
1571 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1572 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1573 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1574 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1576 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1577 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1579 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1580 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1582 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1583 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1585 /* SDP recommended settings */
1586 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1587 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1589 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1590 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1591 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1592 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1593 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1594 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1595 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1597 /* deinterlacer enabled and 3D comb */
1598 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1600 sdp_write(sd, 0xdd, 0x08); /* free run auto */
1604 case ADV7842_MODE_COMP:
1605 case ADV7842_MODE_RGB:
1606 /* Automatic analog input muxing mode */
1607 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1608 /* set mode and select free run resolution */
1609 io_write(sd, 0x00, vid_std_select); /* video std */
1610 io_write(sd, 0x01, 0x02); /* prim mode */
1611 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1612 for auto graphics mode */
1614 afe_write(sd, 0x00, 0x00); /* power up ADC */
1615 afe_write(sd, 0xc8, 0x00); /* phase control */
1616 if (state->mode == ADV7842_MODE_COMP) {
1617 /* force to YCrCb */
1618 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1621 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1624 /* set ADI recommended settings for digitizer */
1625 /* "ADV7842 Register Settings Recommendations
1626 * (rev. 1.8, November 2010)" p. 9. */
1627 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1628 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1630 /* set to default gain for RGB */
1631 cp_write(sd, 0x73, 0x10);
1632 cp_write(sd, 0x74, 0x04);
1633 cp_write(sd, 0x75, 0x01);
1634 cp_write(sd, 0x76, 0x00);
1636 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1637 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1638 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1641 case ADV7842_MODE_HDMI:
1642 /* Automatic analog input muxing mode */
1643 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1644 /* set mode and select free run resolution */
1645 if (state->hdmi_port_a)
1646 hdmi_write(sd, 0x00, 0x02); /* select port A */
1648 hdmi_write(sd, 0x00, 0x03); /* select port B */
1649 io_write(sd, 0x00, vid_std_select); /* video std */
1650 io_write(sd, 0x01, 5); /* prim mode */
1651 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1652 for auto graphics mode */
1654 /* set ADI recommended settings for HDMI: */
1655 /* "ADV7842 Register Settings Recommendations
1656 * (rev. 1.8, November 2010)" p. 3. */
1657 hdmi_write(sd, 0xc0, 0x00);
1658 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1659 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1660 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1661 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1662 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1663 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1664 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1665 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1666 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1667 Improve robustness */
1668 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1669 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1670 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1671 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1672 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1673 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1674 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1675 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1676 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1677 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1679 afe_write(sd, 0x00, 0xff); /* power down ADC */
1680 afe_write(sd, 0xc8, 0x40); /* phase control */
1682 /* set to default gain for HDMI */
1683 cp_write(sd, 0x73, 0x10);
1684 cp_write(sd, 0x74, 0x04);
1685 cp_write(sd, 0x75, 0x01);
1686 cp_write(sd, 0x76, 0x00);
1688 /* reset ADI recommended settings for digitizer */
1689 /* "ADV7842 Register Settings Recommendations
1690 * (rev. 2.5, June 2010)" p. 17. */
1691 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1692 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1693 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control,
1694 enable color control */
1695 /* CP coast control */
1696 cp_write(sd, 0xc3, 0x33); /* Component mode */
1698 /* color space conversion, autodetect color space */
1699 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1703 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1704 __func__, state->mode);
1709 static int adv7842_s_routing(struct v4l2_subdev *sd,
1710 u32 input, u32 output, u32 config)
1712 struct adv7842_state *state = to_state(sd);
1714 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1717 case ADV7842_SELECT_HDMI_PORT_A:
1718 state->mode = ADV7842_MODE_HDMI;
1719 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1720 state->hdmi_port_a = true;
1722 case ADV7842_SELECT_HDMI_PORT_B:
1723 state->mode = ADV7842_MODE_HDMI;
1724 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1725 state->hdmi_port_a = false;
1727 case ADV7842_SELECT_VGA_COMP:
1728 state->mode = ADV7842_MODE_COMP;
1729 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1731 case ADV7842_SELECT_VGA_RGB:
1732 state->mode = ADV7842_MODE_RGB;
1733 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1735 case ADV7842_SELECT_SDP_CVBS:
1736 state->mode = ADV7842_MODE_SDP;
1737 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1739 case ADV7842_SELECT_SDP_YC:
1740 state->mode = ADV7842_MODE_SDP;
1741 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1748 select_input(sd, state->vid_std_select);
1751 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1756 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1757 enum v4l2_mbus_pixelcode *code)
1761 /* Good enough for now */
1762 *code = V4L2_MBUS_FMT_FIXED;
1766 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1767 struct v4l2_mbus_framefmt *fmt)
1769 struct adv7842_state *state = to_state(sd);
1771 fmt->width = state->timings.bt.width;
1772 fmt->height = state->timings.bt.height;
1773 fmt->code = V4L2_MBUS_FMT_FIXED;
1774 fmt->field = V4L2_FIELD_NONE;
1776 if (state->mode == ADV7842_MODE_SDP) {
1778 if (!(sdp_read(sd, 0x5A) & 0x01))
1782 if (state->norm & V4L2_STD_525_60)
1786 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1790 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1791 fmt->colorspace = (state->timings.bt.height <= 576) ?
1792 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1797 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1800 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1801 io_write(sd, 0x46, 0x9c);
1802 /* ESDP_50HZ_DET interrupt */
1803 io_write(sd, 0x5a, 0x10);
1804 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1805 io_write(sd, 0x73, 0x03);
1806 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1807 io_write(sd, 0x78, 0x03);
1808 /* Enable SDP Standard Detection Change and SDP Video Detected */
1809 io_write(sd, 0xa0, 0x09);
1811 io_write(sd, 0x46, 0x0);
1812 io_write(sd, 0x5a, 0x0);
1813 io_write(sd, 0x73, 0x0);
1814 io_write(sd, 0x78, 0x0);
1815 io_write(sd, 0xa0, 0x0);
1819 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1821 struct adv7842_state *state = to_state(sd);
1822 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1825 adv7842_irq_enable(sd, false);
1828 irq_status[0] = io_read(sd, 0x43);
1829 irq_status[1] = io_read(sd, 0x57);
1830 irq_status[2] = io_read(sd, 0x70);
1831 irq_status[3] = io_read(sd, 0x75);
1832 irq_status[4] = io_read(sd, 0x9d);
1836 io_write(sd, 0x44, irq_status[0]);
1838 io_write(sd, 0x58, irq_status[1]);
1840 io_write(sd, 0x71, irq_status[2]);
1842 io_write(sd, 0x76, irq_status[3]);
1844 io_write(sd, 0x9e, irq_status[4]);
1846 adv7842_irq_enable(sd, true);
1848 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__,
1849 irq_status[0], irq_status[1], irq_status[2],
1850 irq_status[3], irq_status[4]);
1852 /* format change CP */
1853 fmt_change_cp = irq_status[0] & 0x9c;
1855 /* format change SDP */
1856 if (state->mode == ADV7842_MODE_SDP)
1857 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1861 /* digital format CP */
1862 if (is_digital_input(sd))
1863 fmt_change_digital = irq_status[3] & 0x03;
1865 fmt_change_digital = 0;
1868 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1869 v4l2_dbg(1, debug, sd,
1870 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1871 __func__, fmt_change_cp, fmt_change_digital,
1873 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1876 /* 5v cable detect */
1878 adv7842_s_detect_tx_5v_ctrl(sd);
1886 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
1888 struct adv7842_state *state = to_state(sd);
1893 if (e->start_block != 0)
1900 /* todo, per edid */
1901 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
1905 memset(&state->vga_edid.edid, 0, 256);
1906 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
1907 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
1908 err = edid_write_vga_segment(sd);
1910 u32 mask = 0x1<<e->pad;
1911 memset(&state->hdmi_edid.edid, 0, 256);
1913 state->hdmi_edid.present |= mask;
1915 state->hdmi_edid.present &= ~mask;
1916 memcpy(&state->hdmi_edid.edid, e->edid, 128*e->blocks);
1917 err = edid_write_hdmi_segment(sd, e->pad);
1920 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
1924 /*********** avi info frame CEA-861-E **************/
1925 /* TODO move to common library */
1927 struct avi_info_frame {
1951 static const char *y10_txt[4] = {
1958 static const char *c10_txt[4] = {
1962 "Extended Colorimetry information valied",
1965 static const char *itc_txt[2] = {
1970 static const char *ec210_txt[8] = {
1981 static const char *q10_txt[4] = {
1988 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
1989 struct avi_info_frame *avi)
1991 avi->f17 = (buf[1] >> 7) & 0x1;
1992 avi->y10 = (buf[1] >> 5) & 0x3;
1993 avi->a0 = (buf[1] >> 4) & 0x1;
1994 avi->b10 = (buf[1] >> 2) & 0x3;
1995 avi->s10 = buf[1] & 0x3;
1996 avi->c10 = (buf[2] >> 6) & 0x3;
1997 avi->m10 = (buf[2] >> 4) & 0x3;
1998 avi->r3210 = buf[2] & 0xf;
1999 avi->itc = (buf[3] >> 7) & 0x1;
2000 avi->ec210 = (buf[3] >> 4) & 0x7;
2001 avi->q10 = (buf[3] >> 2) & 0x3;
2002 avi->sc10 = buf[3] & 0x3;
2003 avi->f47 = (buf[4] >> 7) & 0x1;
2004 avi->vic = buf[4] & 0x7f;
2005 avi->yq10 = (buf[5] >> 6) & 0x3;
2006 avi->cn10 = (buf[5] >> 4) & 0x3;
2007 avi->pr3210 = buf[5] & 0xf;
2008 avi->etb = buf[6] + 256*buf[7];
2009 avi->sbb = buf[8] + 256*buf[9];
2010 avi->elb = buf[10] + 256*buf[11];
2011 avi->srb = buf[12] + 256*buf[13];
2014 static void print_avi_infoframe(struct v4l2_subdev *sd)
2018 uint8_t avi_inf_len;
2019 struct avi_info_frame avi;
2021 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2022 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2025 if (!(io_read(sd, 0x60) & 0x01)) {
2026 v4l2_info(sd, "AVI infoframe not received\n");
2030 if (io_read(sd, 0x88) & 0x10) {
2031 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2032 with a length of 14 or 15. See the ADV7842 Register Settings
2033 Recommendations document for more details. */
2034 v4l2_info(sd, "AVI infoframe checksum error\n");
2038 avi_inf_len = infoframe_read(sd, 0xe2);
2039 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2040 infoframe_read(sd, 0xe1), avi_inf_len);
2042 if (infoframe_read(sd, 0xe1) != 0x02)
2045 for (i = 0; i < 14; i++)
2046 buf[i] = infoframe_read(sd, i);
2048 v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2049 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2050 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2052 parse_avi_infoframe(sd, buf, &avi);
2055 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2057 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2060 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2061 (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2063 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2066 static const char * const prim_mode_txt[] = {
2071 "CVBS & HDMI AUDIO",
2085 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2087 /* SDP (Standard definition processor) block */
2088 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2090 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2091 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2092 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2094 v4l2_info(sd, "SDP: free run: %s\n",
2095 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2096 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2097 "valid SD/PR signal detected" : "invalid/no signal");
2098 if (sdp_signal_detected) {
2099 static const char * const sdp_std_txt[] = {
2107 "7?", "8?", "9?", "a?", "b?",
2113 v4l2_info(sd, "SDP: standard %s\n",
2114 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2115 v4l2_info(sd, "SDP: %s\n",
2116 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2117 v4l2_info(sd, "SDP: %s\n",
2118 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2119 v4l2_info(sd, "SDP: deinterlacer %s\n",
2120 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2121 v4l2_info(sd, "SDP: csc %s mode\n",
2122 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2127 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2130 struct adv7842_state *state = to_state(sd);
2131 struct v4l2_dv_timings timings;
2132 uint8_t reg_io_0x02 = io_read(sd, 0x02);
2133 uint8_t reg_io_0x21 = io_read(sd, 0x21);
2134 uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2135 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2136 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2137 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2138 bool audio_mute = io_read(sd, 0x65) & 0x40;
2140 static const char * const csc_coeff_sel_rb[16] = {
2141 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2142 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2143 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2144 "reserved", "reserved", "reserved", "reserved", "manual"
2146 static const char * const input_color_space_txt[16] = {
2147 "RGB limited range (16-235)", "RGB full range (0-255)",
2148 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2149 "xvYCC Bt.601", "xvYCC Bt.709",
2150 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2151 "invalid", "invalid", "invalid", "invalid", "invalid",
2152 "invalid", "invalid", "automatic"
2154 static const char * const rgb_quantization_range_txt[] = {
2156 "RGB limited range (16-235)",
2157 "RGB full range (0-255)",
2159 static const char * const deep_color_mode_txt[4] = {
2160 "8-bits per channel",
2161 "10-bits per channel",
2162 "12-bits per channel",
2163 "16-bits per channel (not supported)"
2166 v4l2_info(sd, "-----Chip status-----\n");
2167 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2168 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2169 state->hdmi_port_a ? "A" : "B");
2170 v4l2_info(sd, "EDID A %s, B %s\n",
2171 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2172 "enabled" : "disabled",
2173 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2174 "enabled" : "disabled");
2175 v4l2_info(sd, "HPD A %s, B %s\n",
2176 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2177 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2178 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2179 "enabled" : "disabled");
2181 v4l2_info(sd, "-----Signal status-----\n");
2182 if (state->hdmi_port_a) {
2183 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2184 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2185 v4l2_info(sd, "TMDS signal detected: %s\n",
2186 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2187 v4l2_info(sd, "TMDS signal locked: %s\n",
2188 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2190 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2191 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2192 v4l2_info(sd, "TMDS signal detected: %s\n",
2193 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2194 v4l2_info(sd, "TMDS signal locked: %s\n",
2195 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2197 v4l2_info(sd, "CP free run: %s\n",
2198 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2199 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2200 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2201 (io_read(sd, 0x01) & 0x70) >> 4);
2203 v4l2_info(sd, "-----Video Timings-----\n");
2204 if (no_cp_signal(sd)) {
2205 v4l2_info(sd, "STDI: not locked\n");
2207 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2208 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2209 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2210 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2211 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2212 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2213 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2214 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2216 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2218 (cp_read(sd, 0xb1) & 0x40) ?
2219 "interlaced" : "progressive",
2222 if (adv7842_query_dv_timings(sd, &timings))
2223 v4l2_info(sd, "No video detected\n");
2225 v4l2_print_dv_timings(sd->name, "Detected format: ",
2227 v4l2_print_dv_timings(sd->name, "Configured format: ",
2228 &state->timings, true);
2230 if (no_cp_signal(sd))
2233 v4l2_info(sd, "-----Color space-----\n");
2234 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2235 rgb_quantization_range_txt[state->rgb_quantization_range]);
2236 v4l2_info(sd, "Input color space: %s\n",
2237 input_color_space_txt[reg_io_0x02 >> 4]);
2238 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2239 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2240 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2241 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2242 "enabled" : "disabled");
2243 v4l2_info(sd, "Color space conversion: %s\n",
2244 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2246 if (!is_digital_input(sd))
2249 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2250 v4l2_info(sd, "HDCP encrypted content: %s\n",
2251 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2252 v4l2_info(sd, "HDCP keys read: %s%s\n",
2253 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2254 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2258 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2259 audio_pll_locked ? "locked" : "not locked",
2260 audio_sample_packet_detect ? "detected" : "not detected",
2261 audio_mute ? "muted" : "enabled");
2262 if (audio_pll_locked && audio_sample_packet_detect) {
2263 v4l2_info(sd, "Audio format: %s\n",
2264 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2266 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2267 (hdmi_read(sd, 0x5c) << 8) +
2268 (hdmi_read(sd, 0x5d) & 0xf0));
2269 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2270 (hdmi_read(sd, 0x5e) << 8) +
2271 hdmi_read(sd, 0x5f));
2272 v4l2_info(sd, "AV Mute: %s\n",
2273 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2274 v4l2_info(sd, "Deep color mode: %s\n",
2275 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2277 print_avi_infoframe(sd);
2281 static int adv7842_log_status(struct v4l2_subdev *sd)
2283 struct adv7842_state *state = to_state(sd);
2285 if (state->mode == ADV7842_MODE_SDP)
2286 return adv7842_sdp_log_status(sd);
2287 return adv7842_cp_log_status(sd);
2290 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2292 struct adv7842_state *state = to_state(sd);
2294 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2296 if (state->mode != ADV7842_MODE_SDP)
2299 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2301 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2305 switch (sdp_read(sd, 0x52) & 0x0f) {
2308 *std &= V4L2_STD_NTSC;
2312 *std &= V4L2_STD_NTSC_443;
2316 *std &= V4L2_STD_SECAM;
2320 *std &= V4L2_STD_PAL_M;
2324 *std &= V4L2_STD_PAL_60;
2328 *std &= V4L2_STD_PAL_Nc;
2332 *std &= V4L2_STD_PAL;
2336 *std &= V4L2_STD_SECAM;
2339 *std &= V4L2_STD_ALL;
2345 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2347 if (s && s->adjust) {
2348 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2349 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2350 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2351 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2352 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2353 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2354 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2355 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2356 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2357 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2358 sdp_io_write(sd, 0xae, s->de_v_end_o);
2359 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2361 /* set to default */
2362 sdp_io_write(sd, 0x94, 0x00);
2363 sdp_io_write(sd, 0x95, 0x00);
2364 sdp_io_write(sd, 0x96, 0x00);
2365 sdp_io_write(sd, 0x97, 0x20);
2366 sdp_io_write(sd, 0x98, 0x00);
2367 sdp_io_write(sd, 0x99, 0x00);
2368 sdp_io_write(sd, 0x9a, 0x00);
2369 sdp_io_write(sd, 0x9b, 0x00);
2370 sdp_io_write(sd, 0xac, 0x04);
2371 sdp_io_write(sd, 0xad, 0x04);
2372 sdp_io_write(sd, 0xae, 0x04);
2373 sdp_io_write(sd, 0xaf, 0x04);
2377 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2379 struct adv7842_state *state = to_state(sd);
2380 struct adv7842_platform_data *pdata = &state->pdata;
2382 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2384 if (state->mode != ADV7842_MODE_SDP)
2387 if (norm & V4L2_STD_625_50)
2388 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2389 else if (norm & V4L2_STD_525_60)
2390 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2392 adv7842_s_sdp_io(sd, NULL);
2394 if (norm & V4L2_STD_ALL) {
2401 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2403 struct adv7842_state *state = to_state(sd);
2405 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2407 if (state->mode != ADV7842_MODE_SDP)
2410 *norm = state->norm;
2414 /* ----------------------------------------------------------------------- */
2416 static int adv7842_core_init(struct v4l2_subdev *sd)
2418 struct adv7842_state *state = to_state(sd);
2419 struct adv7842_platform_data *pdata = &state->pdata;
2420 hdmi_write(sd, 0x48,
2421 (pdata->disable_pwrdnb ? 0x80 : 0) |
2422 (pdata->disable_cable_det_rst ? 0x40 : 0));
2427 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2428 io_write(sd, 0x15, 0x80); /* Power up pads */
2433 pdata->alt_gamma << 3 |
2434 pdata->op_656_range << 2 |
2435 pdata->rgb_out << 1 |
2436 pdata->alt_data_sat << 0);
2437 io_write(sd, 0x03, pdata->op_format_sel);
2438 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2439 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2440 pdata->insert_av_codes << 2 |
2441 pdata->replicate_av_codes << 1 |
2442 pdata->invert_cbcr << 0);
2444 /* Drive strength */
2445 io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
2446 pdata->drive_strength.clock<<2 |
2447 pdata->drive_strength.sync);
2450 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01);
2452 /* TODO from platform data */
2453 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2454 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2455 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2456 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2458 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2459 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2461 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2463 /* todo, improve settings for sdram */
2464 if (pdata->sd_ram_size >= 128) {
2465 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2466 if (pdata->sd_ram_ddr) {
2467 /* SDP setup for the AD eval board */
2468 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2469 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2470 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2471 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2472 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2474 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2475 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2476 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2477 depends on memory */
2478 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2479 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2480 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2481 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2485 * Manual UG-214, rev 0 is bit confusing on this bit
2486 * but a '1' disables any signal if the Ram is active.
2488 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2491 select_input(sd, pdata->vid_std_select);
2495 /* disable I2C access to internal EDID ram from HDMI DDC ports */
2496 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2498 hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2499 /* HPA disable on port A and B */
2500 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2503 /* Set phase to 16. TODO: get this from platform_data */
2504 io_write(sd, 0x19, 0x90);
2505 io_write(sd, 0x33, 0x40);
2508 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
2510 adv7842_irq_enable(sd, true);
2512 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2515 /* ----------------------------------------------------------------------- */
2517 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2520 * From ADV784x external Memory test.pdf
2522 * Reset must just been performed before running test.
2523 * Recommended to reset after test.
2530 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2531 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2532 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2533 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2534 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2535 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2536 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2537 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2538 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2539 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2540 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2541 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2545 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2546 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2547 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2548 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2549 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2550 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2551 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2552 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2553 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2554 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2555 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2559 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2560 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2564 for (i = 0; i < 10; i++) {
2565 u8 result = sdp_io_read(sd, 0xdb);
2566 if (result & 0x10) {
2576 v4l2_dbg(1, debug, sd,
2577 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2578 complete, i, pass, fail);
2580 if (!complete || fail)
2585 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2586 struct adv7842_platform_data *pdata)
2588 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2589 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2590 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2591 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2592 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2594 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2595 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2596 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2597 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2599 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2600 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2603 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2605 struct i2c_client *client = v4l2_get_subdevdata(sd);
2606 struct adv7842_state *state = to_state(sd);
2607 struct adv7842_platform_data *pdata = client->dev.platform_data;
2613 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2614 v4l2_info(sd, "no sdram or no ddr sdram\n");
2620 adv7842_rewrite_i2c_addresses(sd, pdata);
2623 ret = adv7842_ddr_ram_test(sd);
2627 adv7842_rewrite_i2c_addresses(sd, pdata);
2629 /* and re-init chip and state */
2630 adv7842_core_init(sd);
2634 select_input(sd, state->vid_std_select);
2638 adv7842_s_dv_timings(sd, &state->timings);
2640 edid_write_vga_segment(sd);
2641 edid_write_hdmi_segment(sd, 0);
2642 edid_write_hdmi_segment(sd, 1);
2647 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2650 case ADV7842_CMD_RAM_TEST:
2651 return adv7842_command_ram_test(sd);
2656 /* ----------------------------------------------------------------------- */
2658 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2659 .s_ctrl = adv7842_s_ctrl,
2662 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2663 .log_status = adv7842_log_status,
2664 .g_std = adv7842_g_std,
2665 .s_std = adv7842_s_std,
2666 .ioctl = adv7842_ioctl,
2667 .interrupt_service_routine = adv7842_isr,
2668 #ifdef CONFIG_VIDEO_ADV_DEBUG
2669 .g_register = adv7842_g_register,
2670 .s_register = adv7842_s_register,
2674 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2675 .s_routing = adv7842_s_routing,
2676 .querystd = adv7842_querystd,
2677 .g_input_status = adv7842_g_input_status,
2678 .s_dv_timings = adv7842_s_dv_timings,
2679 .g_dv_timings = adv7842_g_dv_timings,
2680 .query_dv_timings = adv7842_query_dv_timings,
2681 .enum_dv_timings = adv7842_enum_dv_timings,
2682 .dv_timings_cap = adv7842_dv_timings_cap,
2683 .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2684 .g_mbus_fmt = adv7842_g_mbus_fmt,
2685 .try_mbus_fmt = adv7842_g_mbus_fmt,
2686 .s_mbus_fmt = adv7842_g_mbus_fmt,
2689 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2690 .set_edid = adv7842_set_edid,
2693 static const struct v4l2_subdev_ops adv7842_ops = {
2694 .core = &adv7842_core_ops,
2695 .video = &adv7842_video_ops,
2696 .pad = &adv7842_pad_ops,
2699 /* -------------------------- custom ctrls ---------------------------------- */
2701 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2702 .ops = &adv7842_ctrl_ops,
2703 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2704 .name = "Analog Sampling Phase",
2705 .type = V4L2_CTRL_TYPE_INTEGER,
2712 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2713 .ops = &adv7842_ctrl_ops,
2714 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2715 .name = "Free Running Color, Manual",
2716 .type = V4L2_CTRL_TYPE_BOOLEAN,
2722 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2723 .ops = &adv7842_ctrl_ops,
2724 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2725 .name = "Free Running Color",
2726 .type = V4L2_CTRL_TYPE_INTEGER,
2732 static void adv7842_unregister_clients(struct adv7842_state *state)
2734 if (state->i2c_avlink)
2735 i2c_unregister_device(state->i2c_avlink);
2737 i2c_unregister_device(state->i2c_cec);
2738 if (state->i2c_infoframe)
2739 i2c_unregister_device(state->i2c_infoframe);
2740 if (state->i2c_sdp_io)
2741 i2c_unregister_device(state->i2c_sdp_io);
2743 i2c_unregister_device(state->i2c_sdp);
2745 i2c_unregister_device(state->i2c_afe);
2746 if (state->i2c_repeater)
2747 i2c_unregister_device(state->i2c_repeater);
2748 if (state->i2c_edid)
2749 i2c_unregister_device(state->i2c_edid);
2750 if (state->i2c_hdmi)
2751 i2c_unregister_device(state->i2c_hdmi);
2753 i2c_unregister_device(state->i2c_cp);
2755 i2c_unregister_device(state->i2c_vdp);
2758 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd,
2761 struct i2c_client *client = v4l2_get_subdevdata(sd);
2763 io_write(sd, io_reg, addr << 1);
2764 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2767 static int adv7842_probe(struct i2c_client *client,
2768 const struct i2c_device_id *id)
2770 struct adv7842_state *state;
2771 struct adv7842_platform_data *pdata = client->dev.platform_data;
2772 struct v4l2_ctrl_handler *hdl;
2773 struct v4l2_subdev *sd;
2777 /* Check if the adapter supports the needed features */
2778 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2781 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2785 v4l_err(client, "No platform data!\n");
2789 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2791 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2796 state->pdata = *pdata;
2799 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2800 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2801 state->mode = pdata->mode;
2803 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
2805 /* i2c access to adv7842? */
2806 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2807 adv_smbus_read_byte_data_check(client, 0xeb, false);
2808 if (rev != 0x2012) {
2809 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
2810 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2811 adv_smbus_read_byte_data_check(client, 0xeb, false);
2813 if (rev != 0x2012) {
2814 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
2815 client->addr << 1, rev);
2819 if (pdata->chip_reset)
2822 /* control handlers */
2824 v4l2_ctrl_handler_init(hdl, 6);
2826 /* add in ascending ID order */
2827 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2828 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2829 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2830 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2831 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2832 V4L2_CID_SATURATION, 0, 255, 1, 128);
2833 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2834 V4L2_CID_HUE, 0, 128, 1, 0);
2836 /* custom controls */
2837 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2838 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
2839 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
2840 &adv7842_ctrl_analog_sampling_phase, NULL);
2841 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
2842 &adv7842_ctrl_free_run_color_manual, NULL);
2843 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
2844 &adv7842_ctrl_free_run_color, NULL);
2845 state->rgb_quantization_range_ctrl =
2846 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
2847 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2848 0, V4L2_DV_RGB_RANGE_AUTO);
2849 sd->ctrl_handler = hdl;
2854 state->detect_tx_5v_ctrl->is_private = true;
2855 state->rgb_quantization_range_ctrl->is_private = true;
2856 state->analog_sampling_phase_ctrl->is_private = true;
2857 state->free_run_color_ctrl_manual->is_private = true;
2858 state->free_run_color_ctrl->is_private = true;
2860 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
2865 state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2866 state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4);
2867 state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2868 state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2);
2869 state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1);
2870 state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8);
2871 state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2872 state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa);
2873 state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2874 state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd);
2875 state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2876 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2877 !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe ||
2878 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2879 !state->i2c_cp || !state->i2c_vdp) {
2881 v4l2_err(sd, "failed to create all i2c clients\n");
2886 state->work_queues = create_singlethread_workqueue(client->name);
2887 if (!state->work_queues) {
2888 v4l2_err(sd, "Could not create work queue\n");
2893 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2894 adv7842_delayed_work_enable_hotplug);
2896 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2897 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2899 goto err_work_queues;
2901 err = adv7842_core_init(sd);
2905 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2906 client->addr << 1, client->adapter->name);
2910 media_entity_cleanup(&sd->entity);
2912 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2913 destroy_workqueue(state->work_queues);
2915 adv7842_unregister_clients(state);
2917 v4l2_ctrl_handler_free(hdl);
2921 /* ----------------------------------------------------------------------- */
2923 static int adv7842_remove(struct i2c_client *client)
2925 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2926 struct adv7842_state *state = to_state(sd);
2928 adv7842_irq_enable(sd, false);
2930 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2931 destroy_workqueue(state->work_queues);
2932 v4l2_device_unregister_subdev(sd);
2933 media_entity_cleanup(&sd->entity);
2934 adv7842_unregister_clients(to_state(sd));
2935 v4l2_ctrl_handler_free(sd->ctrl_handler);
2939 /* ----------------------------------------------------------------------- */
2941 static struct i2c_device_id adv7842_id[] = {
2945 MODULE_DEVICE_TABLE(i2c, adv7842_id);
2947 /* ----------------------------------------------------------------------- */
2949 static struct i2c_driver adv7842_driver = {
2951 .owner = THIS_MODULE,
2954 .probe = adv7842_probe,
2955 .remove = adv7842_remove,
2956 .id_table = adv7842_id,
2959 module_i2c_driver(adv7842_driver);