drivers/media/i2c/adv7842.c

   1 /*
   2  * adv7842 - Analog Devices ADV7842 video decoder driver
   3  *
   4  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7842,
  24  *              Register Settings Recommendations, Rev. 1.9, April 2011
  25  * REF_02 - Analog devices, Software User Guide, UG-206,
  26  *              ADV7842 I2C Register Maps, Rev. 0, November 2010
  27  * REF_03 - Analog devices, Hardware User Guide, UG-214,
  28  *              ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
  29  *              Decoder and Digitizer , Rev. 0, January 2011
  30  */
  31
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/slab.h>
  36 #include <linux/i2c.h>
  37 #include <linux/delay.h>
  38 #include <linux/videodev2.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/v4l2-dv-timings.h>
  41 #include <media/v4l2-device.h>
  42 #include <media/v4l2-ctrls.h>
  43 #include <media/v4l2-dv-timings.h>
  44 #include <media/adv7842.h>
  45
  46 static int debug;
  47 module_param(debug, int, 0644);
  48 MODULE_PARM_DESC(debug, "debug level (0-2)");
  49
  50 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
  51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  52 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
  53 MODULE_LICENSE("GPL");
  54
  55 /* ADV7842 system clock frequency */
  56 #define ADV7842_fsc (28636360)
  57
  58 /*
  59 **********************************************************************
  60 *
  61 *  Arrays with configuration parameters for the ADV7842
  62 *
  63 **********************************************************************
  64 */
  65
  66 struct adv7842_state {
  67         struct adv7842_platform_data pdata;
  68         struct v4l2_subdev sd;
  69         struct media_pad pad;
  70         struct v4l2_ctrl_handler hdl;
  71         enum adv7842_mode mode;
  72         struct v4l2_dv_timings timings;
  73         enum adv7842_vid_std_select vid_std_select;
  74         v4l2_std_id norm;
  75         struct {
  76                 u8 edid[256];
  77                 u32 present;
  78         } hdmi_edid;
  79         struct {
  80                 u8 edid[256];
  81                 u32 present;
  82         } vga_edid;
  83         struct v4l2_fract aspect_ratio;
  84         u32 rgb_quantization_range;
  85         bool is_cea_format;
  86         struct workqueue_struct *work_queues;
  87         struct delayed_work delayed_work_enable_hotplug;
  88         bool restart_stdi_once;
  89         bool hdmi_port_a;
  90
  91         /* i2c clients */
  92         struct i2c_client *i2c_sdp_io;
  93         struct i2c_client *i2c_sdp;
  94         struct i2c_client *i2c_cp;
  95         struct i2c_client *i2c_vdp;
  96         struct i2c_client *i2c_afe;
  97         struct i2c_client *i2c_hdmi;
  98         struct i2c_client *i2c_repeater;
  99         struct i2c_client *i2c_edid;
 100         struct i2c_client *i2c_infoframe;
 101         struct i2c_client *i2c_cec;
 102         struct i2c_client *i2c_avlink;
 103
 104         /* controls */
 105         struct v4l2_ctrl *detect_tx_5v_ctrl;
 106         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 107         struct v4l2_ctrl *free_run_color_ctrl_manual;
 108         struct v4l2_ctrl *free_run_color_ctrl;
 109         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 110 };
 111
 112 /* Unsupported timings. This device cannot support 720p30. */
 113 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
 114         V4L2_DV_BT_CEA_1280X720P30,
 115         { }
 116 };
 117
 118 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
 119 {
 120         int i;
 121
 122         for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
 123                 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
 124                         return false;
 125         return true;
 126 }
 127
 128 struct adv7842_video_standards {
 129         struct v4l2_dv_timings timings;
 130         u8 vid_std;
 131         u8 v_freq;
 132 };
 133
 134 /* sorted by number of lines */
 135 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
 136         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 137         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 138         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 139         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 140         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 141         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 142         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 143         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 144         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 145         /* TODO add 1920x1080P60_RB (CVT timing) */
 146         { },
 147 };
 148
 149 /* sorted by number of lines */
 150 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
 151         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 152         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 153         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 154         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 155         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 156         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 157         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 158         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 159         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 160         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 161         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 162         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 163         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 164         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 165         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 166         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 167         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 168         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 169         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 170         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 171         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 172         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 173         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 174         { },
 175 };
 176
 177 /* sorted by number of lines */
 178 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
 179         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 180         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 181         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 182         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 183         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 184         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 185         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 186         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 187         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 188         { },
 189 };
 190
 191 /* sorted by number of lines */
 192 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
 193         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 194         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 195         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 196         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 199         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 200         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 201         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 203         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 204         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 205         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 206         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 207         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 208         { },
 209 };
 210
 211 /* ----------------------------------------------------------------------- */
 212
 213 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
 214 {
 215         return container_of(sd, struct adv7842_state, sd);
 216 }
 217
 218 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 219 {
 220         return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
 221 }
 222
 223 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 224 {
 225         return V4L2_DV_BT_BLANKING_WIDTH(t);
 226 }
 227
 228 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 229 {
 230         return V4L2_DV_BT_FRAME_WIDTH(t);
 231 }
 232
 233 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 234 {
 235         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 236 }
 237
 238 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 239 {
 240         return V4L2_DV_BT_FRAME_HEIGHT(t);
 241 }
 242
 243
 244 /* ----------------------------------------------------------------------- */
 245
 246 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 247                                           u8 command, bool check)
 248 {
 249         union i2c_smbus_data data;
 250
 251         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 252                             I2C_SMBUS_READ, command,
 253                             I2C_SMBUS_BYTE_DATA, &data))
 254                 return data.byte;
 255         if (check)
 256                 v4l_err(client, "error reading %02x, %02x\n",
 257                         client->addr, command);
 258         return -EIO;
 259 }
 260
 261 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 262 {
 263         int i;
 264
 265         for (i = 0; i < 3; i++) {
 266                 int ret = adv_smbus_read_byte_data_check(client, command, true);
 267
 268                 if (ret >= 0) {
 269                         if (i)
 270                                 v4l_err(client, "read ok after %d retries\n", i);
 271                         return ret;
 272                 }
 273         }
 274         v4l_err(client, "read failed\n");
 275         return -EIO;
 276 }
 277
 278 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 279                                      u8 command, u8 value)
 280 {
 281         union i2c_smbus_data data;
 282         int err;
 283         int i;
 284
 285         data.byte = value;
 286         for (i = 0; i < 3; i++) {
 287                 err = i2c_smbus_xfer(client->adapter, client->addr,
 288                                      client->flags,
 289                                      I2C_SMBUS_WRITE, command,
 290                                      I2C_SMBUS_BYTE_DATA, &data);
 291                 if (!err)
 292                         break;
 293         }
 294         if (err < 0)
 295                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 296                         client->addr, command, value);
 297         return err;
 298 }
 299
 300 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
 301                                           u8 command, u8 value)
 302 {
 303         union i2c_smbus_data data;
 304         data.byte = value;
 305
 306         i2c_smbus_xfer(client->adapter, client->addr,
 307                        client->flags,
 308                        I2C_SMBUS_WRITE, command,
 309                        I2C_SMBUS_BYTE_DATA, &data);
 310 }
 311
 312 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 313                                   u8 command, unsigned length, const u8 *values)
 314 {
 315         union i2c_smbus_data data;
 316
 317         if (length > I2C_SMBUS_BLOCK_MAX)
 318                 length = I2C_SMBUS_BLOCK_MAX;
 319         data.block[0] = length;
 320         memcpy(data.block + 1, values, length);
 321         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 322                               I2C_SMBUS_WRITE, command,
 323                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 324 }
 325
 326 /* ----------------------------------------------------------------------- */
 327
 328 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 329 {
 330         struct i2c_client *client = v4l2_get_subdevdata(sd);
 331
 332         return adv_smbus_read_byte_data(client, reg);
 333 }
 334
 335 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 336 {
 337         struct i2c_client *client = v4l2_get_subdevdata(sd);
 338
 339         return adv_smbus_write_byte_data(client, reg, val);
 340 }
 341
 342 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 343 {
 344         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 345 }
 346
 347 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 348 {
 349         struct adv7842_state *state = to_state(sd);
 350
 351         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 352 }
 353
 354 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 355 {
 356         struct adv7842_state *state = to_state(sd);
 357
 358         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 359 }
 360
 361 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 362 {
 363         struct adv7842_state *state = to_state(sd);
 364
 365         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 366 }
 367
 368 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 369 {
 370         struct adv7842_state *state = to_state(sd);
 371
 372         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 373 }
 374
 375 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 376 {
 377         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 378 }
 379
 380 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 381 {
 382         struct adv7842_state *state = to_state(sd);
 383
 384         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 385 }
 386
 387 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 388 {
 389         struct adv7842_state *state = to_state(sd);
 390
 391         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 392 }
 393
 394 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
 395 {
 396         struct adv7842_state *state = to_state(sd);
 397
 398         return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
 399 }
 400
 401 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 402 {
 403         struct adv7842_state *state = to_state(sd);
 404
 405         return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
 406 }
 407
 408 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 409 {
 410         return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
 411 }
 412
 413 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
 414 {
 415         struct adv7842_state *state = to_state(sd);
 416
 417         return adv_smbus_read_byte_data(state->i2c_sdp, reg);
 418 }
 419
 420 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 421 {
 422         struct adv7842_state *state = to_state(sd);
 423
 424         return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
 425 }
 426
 427 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 428 {
 429         return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
 430 }
 431
 432 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 433 {
 434         struct adv7842_state *state = to_state(sd);
 435
 436         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 437 }
 438
 439 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 440 {
 441         struct adv7842_state *state = to_state(sd);
 442
 443         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 444 }
 445
 446 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 447 {
 448         return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
 449 }
 450
 451 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 452 {
 453         struct adv7842_state *state = to_state(sd);
 454
 455         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 456 }
 457
 458 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 459 {
 460         struct adv7842_state *state = to_state(sd);
 461
 462         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 463 }
 464
 465 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 466 {
 467         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 468 }
 469
 470 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 471 {
 472         struct adv7842_state *state = to_state(sd);
 473
 474         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 475 }
 476
 477 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 478 {
 479         struct adv7842_state *state = to_state(sd);
 480
 481         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 482 }
 483
 484 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 485 {
 486         struct adv7842_state *state = to_state(sd);
 487
 488         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 489 }
 490
 491 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 492 {
 493         struct adv7842_state *state = to_state(sd);
 494
 495         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 496 }
 497
 498 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 499 {
 500         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
 501 }
 502
 503 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 504 {
 505         struct adv7842_state *state = to_state(sd);
 506
 507         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 508 }
 509
 510 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 511 {
 512         struct adv7842_state *state = to_state(sd);
 513
 514         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 515 }
 516
 517 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 518 {
 519         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 520 }
 521
 522 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 523 {
 524         struct adv7842_state *state = to_state(sd);
 525
 526         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 527 }
 528
 529 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 530 {
 531         struct adv7842_state *state = to_state(sd);
 532
 533         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 534 }
 535
 536 static void main_reset(struct v4l2_subdev *sd)
 537 {
 538         struct i2c_client *client = v4l2_get_subdevdata(sd);
 539
 540         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 541
 542         adv_smbus_write_byte_no_check(client, 0xff, 0x80);
 543
 544         mdelay(5);
 545 }
 546
 547 /* ----------------------------------------------------------------------- */
 548
 549 static inline bool is_digital_input(struct v4l2_subdev *sd)
 550 {
 551         struct adv7842_state *state = to_state(sd);
 552
 553         return state->mode == ADV7842_MODE_HDMI;
 554 }
 555
 556 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
 557         .type = V4L2_DV_BT_656_1120,
 558         /* keep this initialization for compatibility with GCC < 4.4.6 */
 559         .reserved = { 0 },
 560         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
 561                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 562                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 563                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 564                         V4L2_DV_BT_CAP_CUSTOM)
 565 };
 566
 567 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
 568         .type = V4L2_DV_BT_656_1120,
 569         /* keep this initialization for compatibility with GCC < 4.4.6 */
 570         .reserved = { 0 },
 571         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
 572                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 573                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 574                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 575                         V4L2_DV_BT_CAP_CUSTOM)
 576 };
 577
 578 static inline const struct v4l2_dv_timings_cap *
 579 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
 580 {
 581         return is_digital_input(sd) ? &adv7842_timings_cap_digital :
 582                                       &adv7842_timings_cap_analog;
 583 }
 584
 585 /* ----------------------------------------------------------------------- */
 586
 587 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
 588 {
 589         struct delayed_work *dwork = to_delayed_work(work);
 590         struct adv7842_state *state = container_of(dwork,
 591                         struct adv7842_state, delayed_work_enable_hotplug);
 592         struct v4l2_subdev *sd = &state->sd;
 593         int present = state->hdmi_edid.present;
 594         u8 mask = 0;
 595
 596         v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
 597                         __func__, present);
 598
 599         if (present & (0x04 << ADV7842_EDID_PORT_A))
 600                 mask |= 0x20;
 601         if (present & (0x04 << ADV7842_EDID_PORT_B))
 602                 mask |= 0x10;
 603         io_write_and_or(sd, 0x20, 0xcf, mask);
 604 }
 605
 606 static int edid_write_vga_segment(struct v4l2_subdev *sd)
 607 {
 608         struct i2c_client *client = v4l2_get_subdevdata(sd);
 609         struct adv7842_state *state = to_state(sd);
 610         const u8 *val = state->vga_edid.edid;
 611         int err = 0;
 612         int i;
 613
 614         v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
 615
 616         /* HPA disable on port A and B */
 617         io_write_and_or(sd, 0x20, 0xcf, 0x00);
 618
 619         /* Disable I2C access to internal EDID ram from VGA DDC port */
 620         rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
 621
 622         /* edid segment pointer '1' for VGA port */
 623         rep_write_and_or(sd, 0x77, 0xef, 0x10);
 624
 625         for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
 626                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 627                                              I2C_SMBUS_BLOCK_MAX, val + i);
 628         if (err)
 629                 return err;
 630
 631         /* Calculates the checksums and enables I2C access
 632          * to internal EDID ram from VGA DDC port.
 633          */
 634         rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
 635
 636         for (i = 0; i < 1000; i++) {
 637                 if (rep_read(sd, 0x79) & 0x20)
 638                         break;
 639                 mdelay(1);
 640         }
 641         if (i == 1000) {
 642                 v4l_err(client, "error enabling edid on VGA port\n");
 643                 return -EIO;
 644         }
 645
 646         /* enable hotplug after 200 ms */
 647         queue_delayed_work(state->work_queues,
 648                         &state->delayed_work_enable_hotplug, HZ / 5);
 649
 650         return 0;
 651 }
 652
 653 static int edid_spa_location(const u8 *edid)
 654 {
 655         u8 d;
 656
 657         /*
 658          * TODO, improve and update for other CEA extensions
 659          * currently only for 1 segment (256 bytes),
 660          * i.e. 1 extension block and CEA revision 3.
 661          */
 662         if ((edid[0x7e] != 1) ||
 663             (edid[0x80] != 0x02) ||
 664             (edid[0x81] != 0x03)) {
 665                 return -EINVAL;
 666         }
 667         /*
 668          * search Vendor Specific Data Block (tag 3)
 669          */
 670         d = edid[0x82] & 0x7f;
 671         if (d > 4) {
 672                 int i = 0x84;
 673                 int end = 0x80 + d;
 674                 do {
 675                         u8 tag = edid[i]>>5;
 676                         u8 len = edid[i] & 0x1f;
 677
 678                         if ((tag == 3) && (len >= 5))
 679                                 return i + 4;
 680                         i += len + 1;
 681                 } while (i < end);
 682         }
 683         return -EINVAL;
 684 }
 685
 686 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
 687 {
 688         struct i2c_client *client = v4l2_get_subdevdata(sd);
 689         struct adv7842_state *state = to_state(sd);
 690         const u8 *val = state->hdmi_edid.edid;
 691         int spa_loc = edid_spa_location(val);
 692         int err = 0;
 693         int i;
 694
 695         v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
 696                         __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
 697
 698         /* HPA disable on port A and B */
 699         io_write_and_or(sd, 0x20, 0xcf, 0x00);
 700
 701         /* Disable I2C access to internal EDID ram from HDMI DDC ports */
 702         rep_write_and_or(sd, 0x77, 0xf3, 0x00);
 703
 704         if (!state->hdmi_edid.present)
 705                 return 0;
 706
 707         /* edid segment pointer '0' for HDMI ports */
 708         rep_write_and_or(sd, 0x77, 0xef, 0x00);
 709
 710         for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
 711                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 712                                                      I2C_SMBUS_BLOCK_MAX, val + i);
 713         if (err)
 714                 return err;
 715
 716         if (spa_loc < 0)
 717                 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
 718
 719         if (port == ADV7842_EDID_PORT_A) {
 720                 rep_write(sd, 0x72, val[spa_loc]);
 721                 rep_write(sd, 0x73, val[spa_loc + 1]);
 722         } else {
 723                 rep_write(sd, 0x74, val[spa_loc]);
 724                 rep_write(sd, 0x75, val[spa_loc + 1]);
 725         }
 726         rep_write(sd, 0x76, spa_loc & 0xff);
 727         rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
 728
 729         /* Calculates the checksums and enables I2C access to internal
 730          * EDID ram from HDMI DDC ports
 731          */
 732         rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
 733
 734         for (i = 0; i < 1000; i++) {
 735                 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
 736                         break;
 737                 mdelay(1);
 738         }
 739         if (i == 1000) {
 740                 v4l_err(client, "error enabling edid on port %c\n",
 741                                 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
 742                 return -EIO;
 743         }
 744
 745         /* enable hotplug after 200 ms */
 746         queue_delayed_work(state->work_queues,
 747                         &state->delayed_work_enable_hotplug, HZ / 5);
 748
 749         return 0;
 750 }
 751
 752 /* ----------------------------------------------------------------------- */
 753
 754 #ifdef CONFIG_VIDEO_ADV_DEBUG
 755 static void adv7842_inv_register(struct v4l2_subdev *sd)
 756 {
 757         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 758         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 759         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 760         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 761         v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
 762         v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
 763         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 764         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 765         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 766         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 767         v4l2_info(sd, "0xa00-0xaff: CP Map\n");
 768         v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
 769 }
 770
 771 static int adv7842_g_register(struct v4l2_subdev *sd,
 772                               struct v4l2_dbg_register *reg)
 773 {
 774         reg->size = 1;
 775         switch (reg->reg >> 8) {
 776         case 0:
 777                 reg->val = io_read(sd, reg->reg & 0xff);
 778                 break;
 779         case 1:
 780                 reg->val = avlink_read(sd, reg->reg & 0xff);
 781                 break;
 782         case 2:
 783                 reg->val = cec_read(sd, reg->reg & 0xff);
 784                 break;
 785         case 3:
 786                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 787                 break;
 788         case 4:
 789                 reg->val = sdp_io_read(sd, reg->reg & 0xff);
 790                 break;
 791         case 5:
 792                 reg->val = sdp_read(sd, reg->reg & 0xff);
 793                 break;
 794         case 6:
 795                 reg->val = afe_read(sd, reg->reg & 0xff);
 796                 break;
 797         case 7:
 798                 reg->val = rep_read(sd, reg->reg & 0xff);
 799                 break;
 800         case 8:
 801                 reg->val = edid_read(sd, reg->reg & 0xff);
 802                 break;
 803         case 9:
 804                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 805                 break;
 806         case 0xa:
 807                 reg->val = cp_read(sd, reg->reg & 0xff);
 808                 break;
 809         case 0xb:
 810                 reg->val = vdp_read(sd, reg->reg & 0xff);
 811                 break;
 812         default:
 813                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 814                 adv7842_inv_register(sd);
 815                 break;
 816         }
 817         return 0;
 818 }
 819
 820 static int adv7842_s_register(struct v4l2_subdev *sd,
 821                 const struct v4l2_dbg_register *reg)
 822 {
 823         u8 val = reg->val & 0xff;
 824
 825         switch (reg->reg >> 8) {
 826         case 0:
 827                 io_write(sd, reg->reg & 0xff, val);
 828                 break;
 829         case 1:
 830                 avlink_write(sd, reg->reg & 0xff, val);
 831                 break;
 832         case 2:
 833                 cec_write(sd, reg->reg & 0xff, val);
 834                 break;
 835         case 3:
 836                 infoframe_write(sd, reg->reg & 0xff, val);
 837                 break;
 838         case 4:
 839                 sdp_io_write(sd, reg->reg & 0xff, val);
 840                 break;
 841         case 5:
 842                 sdp_write(sd, reg->reg & 0xff, val);
 843                 break;
 844         case 6:
 845                 afe_write(sd, reg->reg & 0xff, val);
 846                 break;
 847         case 7:
 848                 rep_write(sd, reg->reg & 0xff, val);
 849                 break;
 850         case 8:
 851                 edid_write(sd, reg->reg & 0xff, val);
 852                 break;
 853         case 9:
 854                 hdmi_write(sd, reg->reg & 0xff, val);
 855                 break;
 856         case 0xa:
 857                 cp_write(sd, reg->reg & 0xff, val);
 858                 break;
 859         case 0xb:
 860                 vdp_write(sd, reg->reg & 0xff, val);
 861                 break;
 862         default:
 863                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 864                 adv7842_inv_register(sd);
 865                 break;
 866         }
 867         return 0;
 868 }
 869 #endif
 870
 871 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 872 {
 873         struct adv7842_state *state = to_state(sd);
 874         int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
 875         u8 reg_io_6f = io_read(sd, 0x6f);
 876         int val = 0;
 877
 878         if (reg_io_6f & 0x02)
 879                 val |= 1; /* port A */
 880         if (reg_io_6f & 0x01)
 881                 val |= 2; /* port B */
 882
 883         v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
 884
 885         if (val != prev)
 886                 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
 887         return 0;
 888 }
 889
 890 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 891                 u8 prim_mode,
 892                 const struct adv7842_video_standards *predef_vid_timings,
 893                 const struct v4l2_dv_timings *timings)
 894 {
 895         int i;
 896
 897         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 898                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 899                                           is_digital_input(sd) ? 250000 : 1000000))
 900                         continue;
 901                 /* video std */
 902                 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
 903                 /* v_freq and prim mode */
 904                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
 905                 return 0;
 906         }
 907
 908         return -1;
 909 }
 910
 911 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 912                 struct v4l2_dv_timings *timings)
 913 {
 914         struct adv7842_state *state = to_state(sd);
 915         int err;
 916
 917         v4l2_dbg(1, debug, sd, "%s\n", __func__);
 918
 919         /* reset to default values */
 920         io_write(sd, 0x16, 0x43);
 921         io_write(sd, 0x17, 0x5a);
 922         /* disable embedded syncs for auto graphics mode */
 923         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 924         cp_write(sd, 0x26, 0x00);
 925         cp_write(sd, 0x27, 0x00);
 926         cp_write(sd, 0x28, 0x00);
 927         cp_write(sd, 0x29, 0x00);
 928         cp_write(sd, 0x8f, 0x40);
 929         cp_write(sd, 0x90, 0x00);
 930         cp_write(sd, 0xa5, 0x00);
 931         cp_write(sd, 0xa6, 0x00);
 932         cp_write(sd, 0xa7, 0x00);
 933         cp_write(sd, 0xab, 0x00);
 934         cp_write(sd, 0xac, 0x00);
 935
 936         switch (state->mode) {
 937         case ADV7842_MODE_COMP:
 938         case ADV7842_MODE_RGB:
 939                 err = find_and_set_predefined_video_timings(sd,
 940                                 0x01, adv7842_prim_mode_comp, timings);
 941                 if (err)
 942                         err = find_and_set_predefined_video_timings(sd,
 943                                         0x02, adv7842_prim_mode_gr, timings);
 944                 break;
 945         case ADV7842_MODE_HDMI:
 946                 err = find_and_set_predefined_video_timings(sd,
 947                                 0x05, adv7842_prim_mode_hdmi_comp, timings);
 948                 if (err)
 949                         err = find_and_set_predefined_video_timings(sd,
 950                                         0x06, adv7842_prim_mode_hdmi_gr, timings);
 951                 break;
 952         default:
 953                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
 954                                 __func__, state->mode);
 955                 err = -1;
 956                 break;
 957         }
 958
 959
 960         return err;
 961 }
 962
 963 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 964                 const struct v4l2_bt_timings *bt)
 965 {
 966         struct adv7842_state *state = to_state(sd);
 967         struct i2c_client *client = v4l2_get_subdevdata(sd);
 968         u32 width = htotal(bt);
 969         u32 height = vtotal(bt);
 970         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 971         u16 cp_start_eav = width - bt->hfrontporch;
 972         u16 cp_start_vbi = height - bt->vfrontporch + 1;
 973         u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
 974         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 975                 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 976         const u8 pll[2] = {
 977                 0xc0 | ((width >> 8) & 0x1f),
 978                 width & 0xff
 979         };
 980
 981         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 982
 983         switch (state->mode) {
 984         case ADV7842_MODE_COMP:
 985         case ADV7842_MODE_RGB:
 986                 /* auto graphics */
 987                 io_write(sd, 0x00, 0x07); /* video std */
 988                 io_write(sd, 0x01, 0x02); /* prim mode */
 989                 /* enable embedded syncs for auto graphics mode */
 990                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 991
 992                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 993                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 994                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 995                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
 996                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 997                         break;
 998                 }
 999
1000                 /* active video - horizontal timing */
1001                 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1002                 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1003                 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1004                 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1005
1006                 /* active video - vertical timing */
1007                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1008                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1009                                         ((cp_end_vbi >> 8) & 0xf));
1010                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1011                 break;
1012         case ADV7842_MODE_HDMI:
1013                 /* set default prim_mode/vid_std for HDMI
1014                    according to [REF_03, c. 4.2] */
1015                 io_write(sd, 0x00, 0x02); /* video std */
1016                 io_write(sd, 0x01, 0x06); /* prim mode */
1017                 break;
1018         default:
1019                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1020                                 __func__, state->mode);
1021                 break;
1022         }
1023
1024         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1025         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1026         cp_write(sd, 0xab, (height >> 4) & 0xff);
1027         cp_write(sd, 0xac, (height & 0x0f) << 4);
1028 }
1029
1030 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1031 {
1032         struct adv7842_state *state = to_state(sd);
1033
1034         v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
1035                        __func__, state->rgb_quantization_range);
1036
1037         switch (state->rgb_quantization_range) {
1038         case V4L2_DV_RGB_RANGE_AUTO:
1039                 if (state->mode == ADV7842_MODE_RGB) {
1040                         /* Receiving analog RGB signal
1041                          * Set RGB full range (0-255) */
1042                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1043                         break;
1044                 }
1045
1046                 if (state->mode == ADV7842_MODE_COMP) {
1047                         /* Receiving analog YPbPr signal
1048                          * Set automode */
1049                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1050                         break;
1051                 }
1052
1053                 if (hdmi_read(sd, 0x05) & 0x80) {
1054                         /* Receiving HDMI signal
1055                          * Set automode */
1056                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1057                         break;
1058                 }
1059
1060                 /* Receiving DVI-D signal
1061                  * ADV7842 selects RGB limited range regardless of
1062                  * input format (CE/IT) in automatic mode */
1063                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1064                         /* RGB limited range (16-235) */
1065                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
1066                 } else {
1067                         /* RGB full range (0-255) */
1068                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1069                 }
1070                 break;
1071         case V4L2_DV_RGB_RANGE_LIMITED:
1072                 if (state->mode == ADV7842_MODE_COMP) {
1073                         /* YCrCb limited range (16-235) */
1074                         io_write_and_or(sd, 0x02, 0x0f, 0x20);
1075                 } else {
1076                         /* RGB limited range (16-235) */
1077                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
1078                 }
1079                 break;
1080         case V4L2_DV_RGB_RANGE_FULL:
1081                 if (state->mode == ADV7842_MODE_COMP) {
1082                         /* YCrCb full range (0-255) */
1083                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1084                 } else {
1085                         /* RGB full range (0-255) */
1086                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1087                 }
1088                 break;
1089         }
1090 }
1091
1092 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1093 {
1094         struct v4l2_subdev *sd = to_sd(ctrl);
1095         struct adv7842_state *state = to_state(sd);
1096
1097         /* TODO SDP ctrls
1098            contrast/brightness/hue/free run is acting a bit strange,
1099            not sure if sdp csc is correct.
1100          */
1101         switch (ctrl->id) {
1102         /* standard ctrls */
1103         case V4L2_CID_BRIGHTNESS:
1104                 cp_write(sd, 0x3c, ctrl->val);
1105                 sdp_write(sd, 0x14, ctrl->val);
1106                 /* ignore lsb sdp 0x17[3:2] */
1107                 return 0;
1108         case V4L2_CID_CONTRAST:
1109                 cp_write(sd, 0x3a, ctrl->val);
1110                 sdp_write(sd, 0x13, ctrl->val);
1111                 /* ignore lsb sdp 0x17[1:0] */
1112                 return 0;
1113         case V4L2_CID_SATURATION:
1114                 cp_write(sd, 0x3b, ctrl->val);
1115                 sdp_write(sd, 0x15, ctrl->val);
1116                 /* ignore lsb sdp 0x17[5:4] */
1117                 return 0;
1118         case V4L2_CID_HUE:
1119                 cp_write(sd, 0x3d, ctrl->val);
1120                 sdp_write(sd, 0x16, ctrl->val);
1121                 /* ignore lsb sdp 0x17[7:6] */
1122                 return 0;
1123                 /* custom ctrls */
1124         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1125                 afe_write(sd, 0xc8, ctrl->val);
1126                 return 0;
1127         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1128                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1129                 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1130                 return 0;
1131         case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1132                 u8 R = (ctrl->val & 0xff0000) >> 16;
1133                 u8 G = (ctrl->val & 0x00ff00) >> 8;
1134                 u8 B = (ctrl->val & 0x0000ff);
1135                 /* RGB -> YUV, numerical approximation */
1136                 int Y = 66 * R + 129 * G + 25 * B;
1137                 int U = -38 * R - 74 * G + 112 * B;
1138                 int V = 112 * R - 94 * G - 18 * B;
1139
1140                 /* Scale down to 8 bits with rounding */
1141                 Y = (Y + 128) >> 8;
1142                 U = (U + 128) >> 8;
1143                 V = (V + 128) >> 8;
1144                 /* make U,V positive */
1145                 Y += 16;
1146                 U += 128;
1147                 V += 128;
1148
1149                 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1150                 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1151
1152                 /* CP */
1153                 cp_write(sd, 0xc1, R);
1154                 cp_write(sd, 0xc0, G);
1155                 cp_write(sd, 0xc2, B);
1156                 /* SDP */
1157                 sdp_write(sd, 0xde, Y);
1158                 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1159                 return 0;
1160         }
1161         case V4L2_CID_DV_RX_RGB_RANGE:
1162                 state->rgb_quantization_range = ctrl->val;
1163                 set_rgb_quantization_range(sd);
1164                 return 0;
1165         }
1166         return -EINVAL;
1167 }
1168
1169 static inline bool no_power(struct v4l2_subdev *sd)
1170 {
1171         return io_read(sd, 0x0c) & 0x24;
1172 }
1173
1174 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1175 {
1176         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1177 }
1178
1179 static inline bool is_hdmi(struct v4l2_subdev *sd)
1180 {
1181         return hdmi_read(sd, 0x05) & 0x80;
1182 }
1183
1184 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1185 {
1186         struct adv7842_state *state = to_state(sd);
1187
1188         *status = 0;
1189
1190         if (io_read(sd, 0x0c) & 0x24)
1191                 *status |= V4L2_IN_ST_NO_POWER;
1192
1193         if (state->mode == ADV7842_MODE_SDP) {
1194                 /* status from SDP block */
1195                 if (!(sdp_read(sd, 0x5A) & 0x01))
1196                         *status |= V4L2_IN_ST_NO_SIGNAL;
1197
1198                 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1199                                 __func__, *status);
1200                 return 0;
1201         }
1202         /* status from CP block */
1203         if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1204                         !(cp_read(sd, 0xb1) & 0x80))
1205                 /* TODO channel 2 */
1206                 *status |= V4L2_IN_ST_NO_SIGNAL;
1207
1208         if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1209                 *status |= V4L2_IN_ST_NO_SIGNAL;
1210
1211         v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1212                         __func__, *status);
1213
1214         return 0;
1215 }
1216
1217 struct stdi_readback {
1218         u16 bl, lcf, lcvs;
1219         u8 hs_pol, vs_pol;
1220         bool interlaced;
1221 };
1222
1223 static int stdi2dv_timings(struct v4l2_subdev *sd,
1224                 struct stdi_readback *stdi,
1225                 struct v4l2_dv_timings *timings)
1226 {
1227         struct adv7842_state *state = to_state(sd);
1228         u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1229         u32 pix_clk;
1230         int i;
1231
1232         for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1233                 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1234
1235                 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1236                                            adv7842_get_dv_timings_cap(sd),
1237                                            adv7842_check_dv_timings, NULL))
1238                         continue;
1239                 if (vtotal(bt) != stdi->lcf + 1)
1240                         continue;
1241                 if (bt->vsync != stdi->lcvs)
1242                         continue;
1243
1244                 pix_clk = hfreq * htotal(bt);
1245
1246                 if ((pix_clk < bt->pixelclock + 1000000) &&
1247                     (pix_clk > bt->pixelclock - 1000000)) {
1248                         *timings = v4l2_dv_timings_presets[i];
1249                         return 0;
1250                 }
1251         }
1252
1253         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1254                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1255                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1256                             timings))
1257                 return 0;
1258         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1259                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1260                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1261                             state->aspect_ratio, timings))
1262                 return 0;
1263
1264         v4l2_dbg(2, debug, sd,
1265                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1266                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1267                 stdi->hs_pol, stdi->vs_pol);
1268         return -1;
1269 }
1270
1271 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1272 {
1273         u32 status;
1274
1275         adv7842_g_input_status(sd, &status);
1276         if (status & V4L2_IN_ST_NO_SIGNAL) {
1277                 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1278                 return -ENOLINK;
1279         }
1280
1281         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1282         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1283         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1284
1285         if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1286                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1287                         ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1288                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1289                         ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1290         } else {
1291                 stdi->hs_pol = 'x';
1292                 stdi->vs_pol = 'x';
1293         }
1294         stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1295
1296         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1297                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1298                 return -ENOLINK;
1299         }
1300
1301         v4l2_dbg(2, debug, sd,
1302                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1303                  __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1304                  stdi->hs_pol, stdi->vs_pol,
1305                  stdi->interlaced ? "interlaced" : "progressive");
1306
1307         return 0;
1308 }
1309
1310 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1311                                    struct v4l2_enum_dv_timings *timings)
1312 {
1313         return v4l2_enum_dv_timings_cap(timings,
1314                 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1315 }
1316
1317 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1318                                   struct v4l2_dv_timings_cap *cap)
1319 {
1320         *cap = *adv7842_get_dv_timings_cap(sd);
1321         return 0;
1322 }
1323
1324 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1325    if the format is listed in adv7842_timings[] */
1326 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1327                 struct v4l2_dv_timings *timings)
1328 {
1329         v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1330                         is_digital_input(sd) ? 250000 : 1000000,
1331                         adv7842_check_dv_timings, NULL);
1332 }
1333
1334 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1335                                     struct v4l2_dv_timings *timings)
1336 {
1337         struct adv7842_state *state = to_state(sd);
1338         struct v4l2_bt_timings *bt = &timings->bt;
1339         struct stdi_readback stdi = { 0 };
1340
1341         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1342
1343         /* SDP block */
1344         if (state->mode == ADV7842_MODE_SDP)
1345                 return -ENODATA;
1346
1347         /* read STDI */
1348         if (read_stdi(sd, &stdi)) {
1349                 state->restart_stdi_once = true;
1350                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1351                 return -ENOLINK;
1352         }
1353         bt->interlaced = stdi.interlaced ?
1354                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1355
1356         if (is_digital_input(sd)) {
1357                 uint32_t freq;
1358
1359                 timings->type = V4L2_DV_BT_656_1120;
1360
1361                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1362                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1363                 freq = (hdmi_read(sd, 0x06) * 1000000) +
1364                        ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1365
1366                 if (is_hdmi(sd)) {
1367                         /* adjust for deep color mode */
1368                         freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8);
1369                 }
1370                 bt->pixelclock = freq;
1371                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1372                         hdmi_read(sd, 0x21);
1373                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1374                         hdmi_read(sd, 0x23);
1375                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1376                         hdmi_read(sd, 0x25);
1377                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1378                         hdmi_read(sd, 0x2b)) / 2;
1379                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1380                         hdmi_read(sd, 0x2f)) / 2;
1381                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1382                         hdmi_read(sd, 0x33)) / 2;
1383                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1384                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1385                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1386                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1387                                         hdmi_read(sd, 0x0c);
1388                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1389                                         hdmi_read(sd, 0x2d)) / 2;
1390                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1391                                         hdmi_read(sd, 0x31)) / 2;
1392                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1393                                         hdmi_read(sd, 0x35)) / 2;
1394                 }
1395                 adv7842_fill_optional_dv_timings_fields(sd, timings);
1396         } else {
1397                 /* find format
1398                  * Since LCVS values are inaccurate [REF_03, p. 339-340],
1399                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1400                  */
1401                 if (!stdi2dv_timings(sd, &stdi, timings))
1402                         goto found;
1403                 stdi.lcvs += 1;
1404                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1405                 if (!stdi2dv_timings(sd, &stdi, timings))
1406                         goto found;
1407                 stdi.lcvs -= 2;
1408                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1409                 if (stdi2dv_timings(sd, &stdi, timings)) {
1410                         /*
1411                          * The STDI block may measure wrong values, especially
1412                          * for lcvs and lcf. If the driver can not find any
1413                          * valid timing, the STDI block is restarted to measure
1414                          * the video timings again. The function will return an
1415                          * error, but the restart of STDI will generate a new
1416                          * STDI interrupt and the format detection process will
1417                          * restart.
1418                          */
1419                         if (state->restart_stdi_once) {
1420                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1421                                 /* TODO restart STDI for Sync Channel 2 */
1422                                 /* enter one-shot mode */
1423                                 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1424                                 /* trigger STDI restart */
1425                                 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1426                                 /* reset to continuous mode */
1427                                 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1428                                 state->restart_stdi_once = false;
1429                                 return -ENOLINK;
1430                         }
1431                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1432                         return -ERANGE;
1433                 }
1434                 state->restart_stdi_once = true;
1435         }
1436 found:
1437
1438         if (debug > 1)
1439                 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1440                                 timings, true);
1441         return 0;
1442 }
1443
1444 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1445                                 struct v4l2_dv_timings *timings)
1446 {
1447         struct adv7842_state *state = to_state(sd);
1448         struct v4l2_bt_timings *bt;
1449         int err;
1450
1451         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1452
1453         if (state->mode == ADV7842_MODE_SDP)
1454                 return -ENODATA;
1455
1456         bt = &timings->bt;
1457
1458         if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1459                                    adv7842_check_dv_timings, NULL))
1460                 return -ERANGE;
1461
1462         adv7842_fill_optional_dv_timings_fields(sd, timings);
1463
1464         state->timings = *timings;
1465
1466         cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1467
1468         /* Use prim_mode and vid_std when available */
1469         err = configure_predefined_video_timings(sd, timings);
1470         if (err) {
1471                 /* custom settings when the video format
1472                   does not have prim_mode/vid_std */
1473                 configure_custom_video_timings(sd, bt);
1474         }
1475
1476         set_rgb_quantization_range(sd);
1477
1478
1479         if (debug > 1)
1480                 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1481                                       timings, true);
1482         return 0;
1483 }
1484
1485 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1486                                 struct v4l2_dv_timings *timings)
1487 {
1488         struct adv7842_state *state = to_state(sd);
1489
1490         if (state->mode == ADV7842_MODE_SDP)
1491                 return -ENODATA;
1492         *timings = state->timings;
1493         return 0;
1494 }
1495
1496 static void enable_input(struct v4l2_subdev *sd)
1497 {
1498         struct adv7842_state *state = to_state(sd);
1499
1500         set_rgb_quantization_range(sd);
1501         switch (state->mode) {
1502         case ADV7842_MODE_SDP:
1503         case ADV7842_MODE_COMP:
1504         case ADV7842_MODE_RGB:
1505                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1506                 break;
1507         case ADV7842_MODE_HDMI:
1508                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1509                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1510                 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1511                 break;
1512         default:
1513                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1514                          __func__, state->mode);
1515                 break;
1516         }
1517 }
1518
1519 static void disable_input(struct v4l2_subdev *sd)
1520 {
1521         hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1522         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1523         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1524         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1525 }
1526
1527 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1528                           const struct adv7842_sdp_csc_coeff *c)
1529 {
1530         /* csc auto/manual */
1531         sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1532
1533         if (!c->manual)
1534                 return;
1535
1536         /* csc scaling */
1537         sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1538
1539         /* A coeff */
1540         sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1541         sdp_io_write(sd, 0xe1, c->A1);
1542         sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1543         sdp_io_write(sd, 0xe3, c->A2);
1544         sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1545         sdp_io_write(sd, 0xe5, c->A3);
1546
1547         /* A scale */
1548         sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1549         sdp_io_write(sd, 0xe7, c->A4);
1550
1551         /* B coeff */
1552         sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1553         sdp_io_write(sd, 0xe9, c->B1);
1554         sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1555         sdp_io_write(sd, 0xeb, c->B2);
1556         sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1557         sdp_io_write(sd, 0xed, c->B3);
1558
1559         /* B scale */
1560         sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1561         sdp_io_write(sd, 0xef, c->B4);
1562
1563         /* C coeff */
1564         sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1565         sdp_io_write(sd, 0xf1, c->C1);
1566         sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1567         sdp_io_write(sd, 0xf3, c->C2);
1568         sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1569         sdp_io_write(sd, 0xf5, c->C3);
1570
1571         /* C scale */
1572         sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1573         sdp_io_write(sd, 0xf7, c->C4);
1574 }
1575
1576 static void select_input(struct v4l2_subdev *sd,
1577                          enum adv7842_vid_std_select vid_std_select)
1578 {
1579         struct adv7842_state *state = to_state(sd);
1580
1581         switch (state->mode) {
1582         case ADV7842_MODE_SDP:
1583                 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1584                 io_write(sd, 0x01, 0); /* prim mode */
1585                 /* enable embedded syncs for auto graphics mode */
1586                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1587
1588                 afe_write(sd, 0x00, 0x00); /* power up ADC */
1589                 afe_write(sd, 0xc8, 0x00); /* phase control */
1590
1591                 io_write(sd, 0x19, 0x83); /* LLC DLL phase */
1592                 io_write(sd, 0x33, 0x40); /* LLC DLL enable */
1593
1594                 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1595                 /* script says register 0xde, which don't exist in manual */
1596
1597                 /* Manual analog input muxing mode, CVBS (6.4)*/
1598                 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1599                 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1600                         afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1601                         afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1602                 } else {
1603                         afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1604                         afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1605                 }
1606                 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1607                 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1608
1609                 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1610                 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1611
1612                 /* SDP recommended settings */
1613                 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1614                 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1615
1616                 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1617                 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1618                 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1619                 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1620                 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1621                 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1622                 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1623
1624                 /* deinterlacer enabled and 3D comb */
1625                 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1626
1627                 break;
1628
1629         case ADV7842_MODE_COMP:
1630         case ADV7842_MODE_RGB:
1631                 /* Automatic analog input muxing mode */
1632                 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1633                 /* set mode and select free run resolution */
1634                 io_write(sd, 0x00, vid_std_select); /* video std */
1635                 io_write(sd, 0x01, 0x02); /* prim mode */
1636                 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1637                                                           for auto graphics mode */
1638
1639                 afe_write(sd, 0x00, 0x00); /* power up ADC */
1640                 afe_write(sd, 0xc8, 0x00); /* phase control */
1641                 if (state->mode == ADV7842_MODE_COMP) {
1642                         /* force to YCrCb */
1643                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1644                 } else {
1645                         /* force to RGB */
1646                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1647                 }
1648
1649                 /* set ADI recommended settings for digitizer */
1650                 /* "ADV7842 Register Settings Recommendations
1651                  * (rev. 1.8, November 2010)" p. 9. */
1652                 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1653                 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1654
1655                 /* set to default gain for RGB */
1656                 cp_write(sd, 0x73, 0x10);
1657                 cp_write(sd, 0x74, 0x04);
1658                 cp_write(sd, 0x75, 0x01);
1659                 cp_write(sd, 0x76, 0x00);
1660
1661                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1662                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1663                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1664                 break;
1665
1666         case ADV7842_MODE_HDMI:
1667                 /* Automatic analog input muxing mode */
1668                 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1669                 /* set mode and select free run resolution */
1670                 if (state->hdmi_port_a)
1671                         hdmi_write(sd, 0x00, 0x02); /* select port A */
1672                 else
1673                         hdmi_write(sd, 0x00, 0x03); /* select port B */
1674                 io_write(sd, 0x00, vid_std_select); /* video std */
1675                 io_write(sd, 0x01, 5); /* prim mode */
1676                 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1677                                                           for auto graphics mode */
1678
1679                 /* set ADI recommended settings for HDMI: */
1680                 /* "ADV7842 Register Settings Recommendations
1681                  * (rev. 1.8, November 2010)" p. 3. */
1682                 hdmi_write(sd, 0xc0, 0x00);
1683                 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1684                 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1685                 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1686                 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1687                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1688                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1689                 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1690                 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1691                 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1692                                                Improve robustness */
1693                 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1694                 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1695                 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1696                 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1697                 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1698                 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1699                 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1700                 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1701                 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1702                 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1703
1704                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1705                 afe_write(sd, 0xc8, 0x40); /* phase control */
1706
1707                 /* set to default gain for HDMI */
1708                 cp_write(sd, 0x73, 0x10);
1709                 cp_write(sd, 0x74, 0x04);
1710                 cp_write(sd, 0x75, 0x01);
1711                 cp_write(sd, 0x76, 0x00);
1712
1713                 /* reset ADI recommended settings for digitizer */
1714                 /* "ADV7842 Register Settings Recommendations
1715                  * (rev. 2.5, June 2010)" p. 17. */
1716                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1717                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1718                 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control,
1719                                              enable color control */
1720                 /* CP coast control */
1721                 cp_write(sd, 0xc3, 0x33); /* Component mode */
1722
1723                 /* color space conversion, autodetect color space */
1724                 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1725                 break;
1726
1727         default:
1728                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1729                          __func__, state->mode);
1730                 break;
1731         }
1732 }
1733
1734 static int adv7842_s_routing(struct v4l2_subdev *sd,
1735                 u32 input, u32 output, u32 config)
1736 {
1737         struct adv7842_state *state = to_state(sd);
1738
1739         v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1740
1741         switch (input) {
1742         case ADV7842_SELECT_HDMI_PORT_A:
1743                 state->mode = ADV7842_MODE_HDMI;
1744                 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1745                 state->hdmi_port_a = true;
1746                 break;
1747         case ADV7842_SELECT_HDMI_PORT_B:
1748                 state->mode = ADV7842_MODE_HDMI;
1749                 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1750                 state->hdmi_port_a = false;
1751                 break;
1752         case ADV7842_SELECT_VGA_COMP:
1753                 state->mode = ADV7842_MODE_COMP;
1754                 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1755                 break;
1756         case ADV7842_SELECT_VGA_RGB:
1757                 state->mode = ADV7842_MODE_RGB;
1758                 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1759                 break;
1760         case ADV7842_SELECT_SDP_CVBS:
1761                 state->mode = ADV7842_MODE_SDP;
1762                 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1763                 break;
1764         case ADV7842_SELECT_SDP_YC:
1765                 state->mode = ADV7842_MODE_SDP;
1766                 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1767                 break;
1768         default:
1769                 return -EINVAL;
1770         }
1771
1772         disable_input(sd);
1773         select_input(sd, state->vid_std_select);
1774         enable_input(sd);
1775
1776         v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1777
1778         return 0;
1779 }
1780
1781 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1782                                  enum v4l2_mbus_pixelcode *code)
1783 {
1784         if (index)
1785                 return -EINVAL;
1786         /* Good enough for now */
1787         *code = V4L2_MBUS_FMT_FIXED;
1788         return 0;
1789 }
1790
1791 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1792                               struct v4l2_mbus_framefmt *fmt)
1793 {
1794         struct adv7842_state *state = to_state(sd);
1795
1796         fmt->width = state->timings.bt.width;
1797         fmt->height = state->timings.bt.height;
1798         fmt->code = V4L2_MBUS_FMT_FIXED;
1799         fmt->field = V4L2_FIELD_NONE;
1800
1801         if (state->mode == ADV7842_MODE_SDP) {
1802                 /* SPD block */
1803                 if (!(sdp_read(sd, 0x5A) & 0x01))
1804                         return -EINVAL;
1805                 fmt->width = 720;
1806                 /* valid signal */
1807                 if (state->norm & V4L2_STD_525_60)
1808                         fmt->height = 480;
1809                 else
1810                         fmt->height = 576;
1811                 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1812                 return 0;
1813         }
1814
1815         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1816                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1817                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1818         }
1819         return 0;
1820 }
1821
1822 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1823 {
1824         if (enable) {
1825                 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1826                 io_write(sd, 0x46, 0x9c);
1827                 /* ESDP_50HZ_DET interrupt */
1828                 io_write(sd, 0x5a, 0x10);
1829                 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1830                 io_write(sd, 0x73, 0x03);
1831                 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1832                 io_write(sd, 0x78, 0x03);
1833                 /* Enable SDP Standard Detection Change and SDP Video Detected */
1834                 io_write(sd, 0xa0, 0x09);
1835                 /* Enable HDMI_MODE interrupt */
1836                 io_write(sd, 0x69, 0x08);
1837         } else {
1838                 io_write(sd, 0x46, 0x0);
1839                 io_write(sd, 0x5a, 0x0);
1840                 io_write(sd, 0x73, 0x0);
1841                 io_write(sd, 0x78, 0x0);
1842                 io_write(sd, 0xa0, 0x0);
1843                 io_write(sd, 0x69, 0x0);
1844         }
1845 }
1846
1847 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1848 {
1849         struct adv7842_state *state = to_state(sd);
1850         u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1851         u8 irq_status[6];
1852
1853         adv7842_irq_enable(sd, false);
1854
1855         /* read status */
1856         irq_status[0] = io_read(sd, 0x43);
1857         irq_status[1] = io_read(sd, 0x57);
1858         irq_status[2] = io_read(sd, 0x70);
1859         irq_status[3] = io_read(sd, 0x75);
1860         irq_status[4] = io_read(sd, 0x9d);
1861         irq_status[5] = io_read(sd, 0x66);
1862
1863         /* and clear */
1864         if (irq_status[0])
1865                 io_write(sd, 0x44, irq_status[0]);
1866         if (irq_status[1])
1867                 io_write(sd, 0x58, irq_status[1]);
1868         if (irq_status[2])
1869                 io_write(sd, 0x71, irq_status[2]);
1870         if (irq_status[3])
1871                 io_write(sd, 0x76, irq_status[3]);
1872         if (irq_status[4])
1873                 io_write(sd, 0x9e, irq_status[4]);
1874         if (irq_status[5])
1875                 io_write(sd, 0x67, irq_status[5]);
1876
1877         adv7842_irq_enable(sd, true);
1878
1879         v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
1880                  irq_status[0], irq_status[1], irq_status[2],
1881                  irq_status[3], irq_status[4], irq_status[5]);
1882
1883         /* format change CP */
1884         fmt_change_cp = irq_status[0] & 0x9c;
1885
1886         /* format change SDP */
1887         if (state->mode == ADV7842_MODE_SDP)
1888                 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1889         else
1890                 fmt_change_sdp = 0;
1891
1892         /* digital format CP */
1893         if (is_digital_input(sd))
1894                 fmt_change_digital = irq_status[3] & 0x03;
1895         else
1896                 fmt_change_digital = 0;
1897
1898         /* format change */
1899         if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1900                 v4l2_dbg(1, debug, sd,
1901                          "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1902                          __func__, fmt_change_cp, fmt_change_digital,
1903                          fmt_change_sdp);
1904                 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1905                 if (handled)
1906                         *handled = true;
1907         }
1908
1909         /* HDMI/DVI mode */
1910         if (irq_status[5] & 0x08) {
1911                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1912                          (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
1913                 if (handled)
1914                         *handled = true;
1915         }
1916
1917         /* tx 5v detect */
1918         if (irq_status[2] & 0x3) {
1919                 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
1920                 adv7842_s_detect_tx_5v_ctrl(sd);
1921                 if (handled)
1922                         *handled = true;
1923         }
1924         return 0;
1925 }
1926
1927 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1928 {
1929         struct adv7842_state *state = to_state(sd);
1930         u8 *data = NULL;
1931
1932         if (edid->pad > ADV7842_EDID_PORT_VGA)
1933                 return -EINVAL;
1934         if (edid->blocks == 0)
1935                 return -EINVAL;
1936         if (edid->blocks > 2)
1937                 return -EINVAL;
1938         if (edid->start_block > 1)
1939                 return -EINVAL;
1940         if (edid->start_block == 1)
1941                 edid->blocks = 1;
1942         if (!edid->edid)
1943                 return -EINVAL;
1944
1945         switch (edid->pad) {
1946         case ADV7842_EDID_PORT_A:
1947         case ADV7842_EDID_PORT_B:
1948                 if (state->hdmi_edid.present & (0x04 << edid->pad))
1949                         data = state->hdmi_edid.edid;
1950                 break;
1951         case ADV7842_EDID_PORT_VGA:
1952                 if (state->vga_edid.present)
1953                         data = state->vga_edid.edid;
1954                 break;
1955         default:
1956                 return -EINVAL;
1957         }
1958         if (!data)
1959                 return -ENODATA;
1960
1961         memcpy(edid->edid,
1962                data + edid->start_block * 128,
1963                edid->blocks * 128);
1964         return 0;
1965 }
1966
1967 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
1968 {
1969         struct adv7842_state *state = to_state(sd);
1970         int err = 0;
1971
1972         if (e->pad > ADV7842_EDID_PORT_VGA)
1973                 return -EINVAL;
1974         if (e->start_block != 0)
1975                 return -EINVAL;
1976         if (e->blocks > 2)
1977                 return -E2BIG;
1978         if (!e->edid)
1979                 return -EINVAL;
1980
1981         /* todo, per edid */
1982         state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
1983                         e->edid[0x16]);
1984
1985         switch (e->pad) {
1986         case ADV7842_EDID_PORT_VGA:
1987                 memset(&state->vga_edid.edid, 0, 256);
1988                 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
1989                 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
1990                 err = edid_write_vga_segment(sd);
1991                 break;
1992         case ADV7842_EDID_PORT_A:
1993         case ADV7842_EDID_PORT_B:
1994                 memset(&state->hdmi_edid.edid, 0, 256);
1995                 if (e->blocks)
1996                         state->hdmi_edid.present |= 0x04 << e->pad;
1997                 else
1998                         state->hdmi_edid.present &= ~(0x04 << e->pad);
1999                 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2000                 err = edid_write_hdmi_segment(sd, e->pad);
2001                 break;
2002         default:
2003                 return -EINVAL;
2004         }
2005         if (err < 0)
2006                 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2007         return err;
2008 }
2009
2010 /*********** avi info frame CEA-861-E **************/
2011 /* TODO move to common library */
2012
2013 struct avi_info_frame {
2014         uint8_t f17;
2015         uint8_t y10;
2016         uint8_t a0;
2017         uint8_t b10;
2018         uint8_t s10;
2019         uint8_t c10;
2020         uint8_t m10;
2021         uint8_t r3210;
2022         uint8_t itc;
2023         uint8_t ec210;
2024         uint8_t q10;
2025         uint8_t sc10;
2026         uint8_t f47;
2027         uint8_t vic;
2028         uint8_t yq10;
2029         uint8_t cn10;
2030         uint8_t pr3210;
2031         uint16_t etb;
2032         uint16_t sbb;
2033         uint16_t elb;
2034         uint16_t srb;
2035 };
2036
2037 static const char *y10_txt[4] = {
2038         "RGB",
2039         "YCbCr 4:2:2",
2040         "YCbCr 4:4:4",
2041         "Future",
2042 };
2043
2044 static const char *c10_txt[4] = {
2045         "No Data",
2046         "SMPTE 170M",
2047         "ITU-R 709",
2048         "Extended Colorimetry information valied",
2049 };
2050
2051 static const char *itc_txt[2] = {
2052         "No Data",
2053         "IT content",
2054 };
2055
2056 static const char *ec210_txt[8] = {
2057         "xvYCC601",
2058         "xvYCC709",
2059         "sYCC601",
2060         "AdobeYCC601",
2061         "AdobeRGB",
2062         "5 reserved",
2063         "6 reserved",
2064         "7 reserved",
2065 };
2066
2067 static const char *q10_txt[4] = {
2068         "Default",
2069         "Limited Range",
2070         "Full Range",
2071         "Reserved",
2072 };
2073
2074 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
2075                                 struct avi_info_frame *avi)
2076 {
2077         avi->f17 = (buf[1] >> 7) & 0x1;
2078         avi->y10 = (buf[1] >> 5) & 0x3;
2079         avi->a0 = (buf[1] >> 4) & 0x1;
2080         avi->b10 = (buf[1] >> 2) & 0x3;
2081         avi->s10 = buf[1] & 0x3;
2082         avi->c10 = (buf[2] >> 6) & 0x3;
2083         avi->m10 = (buf[2] >> 4) & 0x3;
2084         avi->r3210 = buf[2] & 0xf;
2085         avi->itc = (buf[3] >> 7) & 0x1;
2086         avi->ec210 = (buf[3] >> 4) & 0x7;
2087         avi->q10 = (buf[3] >> 2) & 0x3;
2088         avi->sc10 = buf[3] & 0x3;
2089         avi->f47 = (buf[4] >> 7) & 0x1;
2090         avi->vic = buf[4] & 0x7f;
2091         avi->yq10 = (buf[5] >> 6) & 0x3;
2092         avi->cn10 = (buf[5] >> 4) & 0x3;
2093         avi->pr3210 = buf[5] & 0xf;
2094         avi->etb = buf[6] + 256*buf[7];
2095         avi->sbb = buf[8] + 256*buf[9];
2096         avi->elb = buf[10] + 256*buf[11];
2097         avi->srb = buf[12] + 256*buf[13];
2098 }
2099
2100 static void print_avi_infoframe(struct v4l2_subdev *sd)
2101 {
2102         int i;
2103         uint8_t buf[14];
2104         uint8_t avi_inf_len;
2105         struct avi_info_frame avi;
2106
2107         if (!(hdmi_read(sd, 0x05) & 0x80)) {
2108                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2109                 return;
2110         }
2111         if (!(io_read(sd, 0x60) & 0x01)) {
2112                 v4l2_info(sd, "AVI infoframe not received\n");
2113                 return;
2114         }
2115
2116         if (io_read(sd, 0x88) & 0x10) {
2117                 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2118                    with a length of 14 or 15. See the ADV7842 Register Settings
2119                    Recommendations document for more details. */
2120                 v4l2_info(sd, "AVI infoframe checksum error\n");
2121                 return;
2122         }
2123
2124         avi_inf_len = infoframe_read(sd, 0xe2);
2125         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2126                   infoframe_read(sd, 0xe1), avi_inf_len);
2127
2128         if (infoframe_read(sd, 0xe1) != 0x02)
2129                 return;
2130
2131         for (i = 0; i < 14; i++)
2132                 buf[i] = infoframe_read(sd, i);
2133
2134         v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2135                   buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2136                   buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2137
2138         parse_avi_infoframe(sd, buf, &avi);
2139
2140         if (avi.vic)
2141                 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2142         if (avi.itc)
2143                 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2144
2145         if (avi.y10)
2146                 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2147                         (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2148         else
2149                 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2150 }
2151
2152 static const char * const prim_mode_txt[] = {
2153         "SDP",
2154         "Component",
2155         "Graphics",
2156         "Reserved",
2157         "CVBS & HDMI AUDIO",
2158         "HDMI-Comp",
2159         "HDMI-GR",
2160         "Reserved",
2161         "Reserved",
2162         "Reserved",
2163         "Reserved",
2164         "Reserved",
2165         "Reserved",
2166         "Reserved",
2167         "Reserved",
2168         "Reserved",
2169 };
2170
2171 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2172 {
2173         /* SDP (Standard definition processor) block */
2174         uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2175
2176         v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2177         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2178                   io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2179
2180         v4l2_info(sd, "SDP: free run: %s\n",
2181                 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2182         v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2183                 "valid SD/PR signal detected" : "invalid/no signal");
2184         if (sdp_signal_detected) {
2185                 static const char * const sdp_std_txt[] = {
2186                         "NTSC-M/J",
2187                         "1?",
2188                         "NTSC-443",
2189                         "60HzSECAM",
2190                         "PAL-M",
2191                         "5?",
2192                         "PAL-60",
2193                         "7?", "8?", "9?", "a?", "b?",
2194                         "PAL-CombN",
2195                         "d?",
2196                         "PAL-BGHID",
2197                         "SECAM"
2198                 };
2199                 v4l2_info(sd, "SDP: standard %s\n",
2200                         sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2201                 v4l2_info(sd, "SDP: %s\n",
2202                         (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2203                 v4l2_info(sd, "SDP: %s\n",
2204                         (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2205                 v4l2_info(sd, "SDP: deinterlacer %s\n",
2206                         (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2207                 v4l2_info(sd, "SDP: csc %s mode\n",
2208                         (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2209         }
2210         return 0;
2211 }
2212
2213 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2214 {
2215         /* CP block */
2216         struct adv7842_state *state = to_state(sd);
2217         struct v4l2_dv_timings timings;
2218         uint8_t reg_io_0x02 = io_read(sd, 0x02);
2219         uint8_t reg_io_0x21 = io_read(sd, 0x21);
2220         uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2221         uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2222         bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2223         bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2224         bool audio_mute = io_read(sd, 0x65) & 0x40;
2225
2226         static const char * const csc_coeff_sel_rb[16] = {
2227                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2228                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2229                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2230                 "reserved", "reserved", "reserved", "reserved", "manual"
2231         };
2232         static const char * const input_color_space_txt[16] = {
2233                 "RGB limited range (16-235)", "RGB full range (0-255)",
2234                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2235                 "xvYCC Bt.601", "xvYCC Bt.709",
2236                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2237                 "invalid", "invalid", "invalid", "invalid", "invalid",
2238                 "invalid", "invalid", "automatic"
2239         };
2240         static const char * const rgb_quantization_range_txt[] = {
2241                 "Automatic",
2242                 "RGB limited range (16-235)",
2243                 "RGB full range (0-255)",
2244         };
2245         static const char * const deep_color_mode_txt[4] = {
2246                 "8-bits per channel",
2247                 "10-bits per channel",
2248                 "12-bits per channel",
2249                 "16-bits per channel (not supported)"
2250         };
2251
2252         v4l2_info(sd, "-----Chip status-----\n");
2253         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2254         v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2255                         state->hdmi_port_a ? "A" : "B");
2256         v4l2_info(sd, "EDID A %s, B %s\n",
2257                   ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2258                   "enabled" : "disabled",
2259                   ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2260                   "enabled" : "disabled");
2261         v4l2_info(sd, "HPD A %s, B %s\n",
2262                   reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2263                   reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2264         v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2265                         "enabled" : "disabled");
2266
2267         v4l2_info(sd, "-----Signal status-----\n");
2268         if (state->hdmi_port_a) {
2269                 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2270                           io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2271                 v4l2_info(sd, "TMDS signal detected: %s\n",
2272                           (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2273                 v4l2_info(sd, "TMDS signal locked: %s\n",
2274                           (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2275         } else {
2276                 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2277                           io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2278                 v4l2_info(sd, "TMDS signal detected: %s\n",
2279                           (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2280                 v4l2_info(sd, "TMDS signal locked: %s\n",
2281                           (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2282         }
2283         v4l2_info(sd, "CP free run: %s\n",
2284                   (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2285         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2286                   io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2287                   (io_read(sd, 0x01) & 0x70) >> 4);
2288
2289         v4l2_info(sd, "-----Video Timings-----\n");
2290         if (no_cp_signal(sd)) {
2291                 v4l2_info(sd, "STDI: not locked\n");
2292         } else {
2293                 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2294                 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2295                 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2296                 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2297                 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2298                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2299                 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2300                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2301                 v4l2_info(sd,
2302                         "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2303                         lcf, bl, lcvs, fcl,
2304                         (cp_read(sd, 0xb1) & 0x40) ?
2305                                 "interlaced" : "progressive",
2306                         hs_pol, vs_pol);
2307         }
2308         if (adv7842_query_dv_timings(sd, &timings))
2309                 v4l2_info(sd, "No video detected\n");
2310         else
2311                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2312                                       &timings, true);
2313         v4l2_print_dv_timings(sd->name, "Configured format: ",
2314                         &state->timings, true);
2315
2316         if (no_cp_signal(sd))
2317                 return 0;
2318
2319         v4l2_info(sd, "-----Color space-----\n");
2320         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2321                   rgb_quantization_range_txt[state->rgb_quantization_range]);
2322         v4l2_info(sd, "Input color space: %s\n",
2323                   input_color_space_txt[reg_io_0x02 >> 4]);
2324         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2325                   (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2326                   (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2327                   ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2328                                         "enabled" : "disabled");
2329         v4l2_info(sd, "Color space conversion: %s\n",
2330                   csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2331
2332         if (!is_digital_input(sd))
2333                 return 0;
2334
2335         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2336         v4l2_info(sd, "HDCP encrypted content: %s\n",
2337                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2338         v4l2_info(sd, "HDCP keys read: %s%s\n",
2339                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2340                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2341         if (!is_hdmi(sd))
2342                 return 0;
2343
2344         v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2345                         audio_pll_locked ? "locked" : "not locked",
2346                         audio_sample_packet_detect ? "detected" : "not detected",
2347                         audio_mute ? "muted" : "enabled");
2348         if (audio_pll_locked && audio_sample_packet_detect) {
2349                 v4l2_info(sd, "Audio format: %s\n",
2350                         (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2351         }
2352         v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2353                         (hdmi_read(sd, 0x5c) << 8) +
2354                         (hdmi_read(sd, 0x5d) & 0xf0));
2355         v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2356                         (hdmi_read(sd, 0x5e) << 8) +
2357                         hdmi_read(sd, 0x5f));
2358         v4l2_info(sd, "AV Mute: %s\n",
2359                         (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2360         v4l2_info(sd, "Deep color mode: %s\n",
2361                         deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2362
2363         print_avi_infoframe(sd);
2364         return 0;
2365 }
2366
2367 static int adv7842_log_status(struct v4l2_subdev *sd)
2368 {
2369         struct adv7842_state *state = to_state(sd);
2370
2371         if (state->mode == ADV7842_MODE_SDP)
2372                 return adv7842_sdp_log_status(sd);
2373         return adv7842_cp_log_status(sd);
2374 }
2375
2376 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2377 {
2378         struct adv7842_state *state = to_state(sd);
2379
2380         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2381
2382         if (state->mode != ADV7842_MODE_SDP)
2383                 return -ENODATA;
2384
2385         if (!(sdp_read(sd, 0x5A) & 0x01)) {
2386                 *std = 0;
2387                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2388                 return 0;
2389         }
2390
2391         switch (sdp_read(sd, 0x52) & 0x0f) {
2392         case 0:
2393                 /* NTSC-M/J */
2394                 *std &= V4L2_STD_NTSC;
2395                 break;
2396         case 2:
2397                 /* NTSC-443 */
2398                 *std &= V4L2_STD_NTSC_443;
2399                 break;
2400         case 3:
2401                 /* 60HzSECAM */
2402                 *std &= V4L2_STD_SECAM;
2403                 break;
2404         case 4:
2405                 /* PAL-M */
2406                 *std &= V4L2_STD_PAL_M;
2407                 break;
2408         case 6:
2409                 /* PAL-60 */
2410                 *std &= V4L2_STD_PAL_60;
2411                 break;
2412         case 0xc:
2413                 /* PAL-CombN */
2414                 *std &= V4L2_STD_PAL_Nc;
2415                 break;
2416         case 0xe:
2417                 /* PAL-BGHID */
2418                 *std &= V4L2_STD_PAL;
2419                 break;
2420         case 0xf:
2421                 /* SECAM */
2422                 *std &= V4L2_STD_SECAM;
2423                 break;
2424         default:
2425                 *std &= V4L2_STD_ALL;
2426                 break;
2427         }
2428         return 0;
2429 }
2430
2431 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2432 {
2433         if (s && s->adjust) {
2434                 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2435                 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2436                 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2437                 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2438                 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2439                 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2440                 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2441                 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2442                 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2443                 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2444                 sdp_io_write(sd, 0xaa, s->vs_end_o);
2445                 sdp_io_write(sd, 0xab, s->vs_end_e);
2446                 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2447                 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2448                 sdp_io_write(sd, 0xae, s->de_v_end_o);
2449                 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2450         } else {
2451                 /* set to default */
2452                 sdp_io_write(sd, 0x94, 0x00);
2453                 sdp_io_write(sd, 0x95, 0x00);
2454                 sdp_io_write(sd, 0x96, 0x00);
2455                 sdp_io_write(sd, 0x97, 0x20);
2456                 sdp_io_write(sd, 0x98, 0x00);
2457                 sdp_io_write(sd, 0x99, 0x00);
2458                 sdp_io_write(sd, 0x9a, 0x00);
2459                 sdp_io_write(sd, 0x9b, 0x00);
2460                 sdp_io_write(sd, 0xa8, 0x04);
2461                 sdp_io_write(sd, 0xa9, 0x04);
2462                 sdp_io_write(sd, 0xaa, 0x04);
2463                 sdp_io_write(sd, 0xab, 0x04);
2464                 sdp_io_write(sd, 0xac, 0x04);
2465                 sdp_io_write(sd, 0xad, 0x04);
2466                 sdp_io_write(sd, 0xae, 0x04);
2467                 sdp_io_write(sd, 0xaf, 0x04);
2468         }
2469 }
2470
2471 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2472 {
2473         struct adv7842_state *state = to_state(sd);
2474         struct adv7842_platform_data *pdata = &state->pdata;
2475
2476         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2477
2478         if (state->mode != ADV7842_MODE_SDP)
2479                 return -ENODATA;
2480
2481         if (norm & V4L2_STD_625_50)
2482                 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2483         else if (norm & V4L2_STD_525_60)
2484                 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2485         else
2486                 adv7842_s_sdp_io(sd, NULL);
2487
2488         if (norm & V4L2_STD_ALL) {
2489                 state->norm = norm;
2490                 return 0;
2491         }
2492         return -EINVAL;
2493 }
2494
2495 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2496 {
2497         struct adv7842_state *state = to_state(sd);
2498
2499         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2500
2501         if (state->mode != ADV7842_MODE_SDP)
2502                 return -ENODATA;
2503
2504         *norm = state->norm;
2505         return 0;
2506 }
2507
2508 /* ----------------------------------------------------------------------- */
2509
2510 static int adv7842_core_init(struct v4l2_subdev *sd)
2511 {
2512         struct adv7842_state *state = to_state(sd);
2513         struct adv7842_platform_data *pdata = &state->pdata;
2514         hdmi_write(sd, 0x48,
2515                    (pdata->disable_pwrdnb ? 0x80 : 0) |
2516                    (pdata->disable_cable_det_rst ? 0x40 : 0));
2517
2518         disable_input(sd);
2519
2520         /* power */
2521         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2522         io_write(sd, 0x15, 0x80);   /* Power up pads */
2523
2524         /* video format */
2525         io_write(sd, 0x02,
2526                  0xf0 |
2527                  pdata->alt_gamma << 3 |
2528                  pdata->op_656_range << 2 |
2529                  pdata->rgb_out << 1 |
2530                  pdata->alt_data_sat << 0);
2531         io_write(sd, 0x03, pdata->op_format_sel);
2532         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2533         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2534                         pdata->insert_av_codes << 2 |
2535                         pdata->replicate_av_codes << 1 |
2536                         pdata->invert_cbcr << 0);
2537
2538         /* HDMI audio */
2539         hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2540
2541         /* Drive strength */
2542         io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
2543                         pdata->drive_strength.clock<<2 |
2544                         pdata->drive_strength.sync);
2545
2546         /* HDMI free run */
2547         cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
2548                                         (pdata->hdmi_free_run_mode << 1));
2549
2550         /* SPD free run */
2551         sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
2552                                          (pdata->sdp_free_run_cbar_en << 1) |
2553                                          (pdata->sdp_free_run_man_col_en << 2) |
2554                                          (pdata->sdp_free_run_force << 3));
2555
2556         /* TODO from platform data */
2557         cp_write(sd, 0x69, 0x14);   /* Enable CP CSC */
2558         io_write(sd, 0x06, 0xa6);   /* positive VS and HS and DE */
2559         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2560         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2561
2562         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2563         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2564
2565         sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2566
2567         /* todo, improve settings for sdram */
2568         if (pdata->sd_ram_size >= 128) {
2569                 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2570                 if (pdata->sd_ram_ddr) {
2571                         /* SDP setup for the AD eval board */
2572                         sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2573                         sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2574                         sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2575                         sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2576                         sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2577                 } else {
2578                         sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2579                         sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2580                         sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2581                                                          depends on memory */
2582                         sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2583                         sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2584                         sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2585                         sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2586                 }
2587         } else {
2588                 /*
2589                  * Manual UG-214, rev 0 is bit confusing on this bit
2590                  * but a '1' disables any signal if the Ram is active.
2591                  */
2592                 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2593         }
2594
2595         select_input(sd, pdata->vid_std_select);
2596
2597         enable_input(sd);
2598
2599         /* disable I2C access to internal EDID ram from HDMI DDC ports */
2600         rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2601
2602         hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2603         /* HPA disable on port A and B */
2604         io_write_and_or(sd, 0x20, 0xcf, 0x00);
2605
2606         /* LLC */
2607         /* Set phase to 16. TODO: get this from platform_data */
2608         io_write(sd, 0x19, 0x90);
2609         io_write(sd, 0x33, 0x40);
2610
2611         /* interrupts */
2612         io_write(sd, 0x40, 0xf2); /* Configure INT1 */
2613
2614         adv7842_irq_enable(sd, true);
2615
2616         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2617 }
2618
2619 /* ----------------------------------------------------------------------- */
2620
2621 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2622 {
2623         /*
2624          * From ADV784x external Memory test.pdf
2625          *
2626          * Reset must just been performed before running test.
2627          * Recommended to reset after test.
2628          */
2629         int i;
2630         int pass = 0;
2631         int fail = 0;
2632         int complete = 0;
2633
2634         io_write(sd, 0x00, 0x01);  /* Program SDP 4x1 */
2635         io_write(sd, 0x01, 0x00);  /* Program SDP mode */
2636         afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2637         afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2638         afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2639         afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2640         afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2641         afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2642         io_write(sd, 0x0C, 0x40);  /* Power up ADV7844 */
2643         io_write(sd, 0x15, 0xBA);  /* Enable outputs */
2644         sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2645         io_write(sd, 0xFF, 0x04);  /* Reset memory controller */
2646
2647         mdelay(5);
2648
2649         sdp_write(sd, 0x12, 0x00);    /* Disable 3D Comb, Frame TBC & 3DNR */
2650         sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2651         sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2652         sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2653         sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2654         sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2655         sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2656         sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2657         sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2658         sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2659         sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2660
2661         mdelay(5);
2662
2663         sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2664         sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2665
2666         mdelay(20);
2667
2668         for (i = 0; i < 10; i++) {
2669                 u8 result = sdp_io_read(sd, 0xdb);
2670                 if (result & 0x10) {
2671                         complete++;
2672                         if (result & 0x20)
2673                                 fail++;
2674                         else
2675                                 pass++;
2676                 }
2677                 mdelay(20);
2678         }
2679
2680         v4l2_dbg(1, debug, sd,
2681                 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2682                 complete, i, pass, fail);
2683
2684         if (!complete || fail)
2685                 return -EIO;
2686         return 0;
2687 }
2688
2689 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2690                 struct adv7842_platform_data *pdata)
2691 {
2692         io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2693         io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2694         io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2695         io_write(sd, 0xf4, pdata->i2c_cec << 1);
2696         io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2697
2698         io_write(sd, 0xf8, pdata->i2c_afe << 1);
2699         io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2700         io_write(sd, 0xfa, pdata->i2c_edid << 1);
2701         io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2702
2703         io_write(sd, 0xfd, pdata->i2c_cp << 1);
2704         io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2705 }
2706
2707 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2708 {
2709         struct i2c_client *client = v4l2_get_subdevdata(sd);
2710         struct adv7842_state *state = to_state(sd);
2711         struct adv7842_platform_data *pdata = client->dev.platform_data;
2712         struct v4l2_dv_timings timings;
2713         int ret = 0;
2714
2715         if (!pdata)
2716                 return -ENODEV;
2717
2718         if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2719                 v4l2_info(sd, "no sdram or no ddr sdram\n");
2720                 return -EINVAL;
2721         }
2722
2723         main_reset(sd);
2724
2725         adv7842_rewrite_i2c_addresses(sd, pdata);
2726
2727         /* run ram test */
2728         ret = adv7842_ddr_ram_test(sd);
2729
2730         main_reset(sd);
2731
2732         adv7842_rewrite_i2c_addresses(sd, pdata);
2733
2734         /* and re-init chip and state */
2735         adv7842_core_init(sd);
2736
2737         disable_input(sd);
2738
2739         select_input(sd, state->vid_std_select);
2740
2741         enable_input(sd);
2742
2743         edid_write_vga_segment(sd);
2744         edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
2745         edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
2746
2747         timings = state->timings;
2748
2749         memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
2750
2751         adv7842_s_dv_timings(sd, &timings);
2752
2753         return ret;
2754 }
2755
2756 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2757 {
2758         switch (cmd) {
2759         case ADV7842_CMD_RAM_TEST:
2760                 return adv7842_command_ram_test(sd);
2761         }
2762         return -ENOTTY;
2763 }
2764
2765 /* ----------------------------------------------------------------------- */
2766
2767 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2768         .s_ctrl = adv7842_s_ctrl,
2769 };
2770
2771 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2772         .log_status = adv7842_log_status,
2773         .g_std = adv7842_g_std,
2774         .s_std = adv7842_s_std,
2775         .ioctl = adv7842_ioctl,
2776         .interrupt_service_routine = adv7842_isr,
2777 #ifdef CONFIG_VIDEO_ADV_DEBUG
2778         .g_register = adv7842_g_register,
2779         .s_register = adv7842_s_register,
2780 #endif
2781 };
2782
2783 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2784         .s_routing = adv7842_s_routing,
2785         .querystd = adv7842_querystd,
2786         .g_input_status = adv7842_g_input_status,
2787         .s_dv_timings = adv7842_s_dv_timings,
2788         .g_dv_timings = adv7842_g_dv_timings,
2789         .query_dv_timings = adv7842_query_dv_timings,
2790         .enum_dv_timings = adv7842_enum_dv_timings,
2791         .dv_timings_cap = adv7842_dv_timings_cap,
2792         .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2793         .g_mbus_fmt = adv7842_g_mbus_fmt,
2794         .try_mbus_fmt = adv7842_g_mbus_fmt,
2795         .s_mbus_fmt = adv7842_g_mbus_fmt,
2796 };
2797
2798 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2799         .get_edid = adv7842_get_edid,
2800         .set_edid = adv7842_set_edid,
2801 };
2802
2803 static const struct v4l2_subdev_ops adv7842_ops = {
2804         .core = &adv7842_core_ops,
2805         .video = &adv7842_video_ops,
2806         .pad = &adv7842_pad_ops,
2807 };
2808
2809 /* -------------------------- custom ctrls ---------------------------------- */
2810
2811 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2812         .ops = &adv7842_ctrl_ops,
2813         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2814         .name = "Analog Sampling Phase",
2815         .type = V4L2_CTRL_TYPE_INTEGER,
2816         .min = 0,
2817         .max = 0x1f,
2818         .step = 1,
2819         .def = 0,
2820 };
2821
2822 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2823         .ops = &adv7842_ctrl_ops,
2824         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2825         .name = "Free Running Color, Manual",
2826         .type = V4L2_CTRL_TYPE_BOOLEAN,
2827         .max = 1,
2828         .step = 1,
2829         .def = 1,
2830 };
2831
2832 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2833         .ops = &adv7842_ctrl_ops,
2834         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2835         .name = "Free Running Color",
2836         .type = V4L2_CTRL_TYPE_INTEGER,
2837         .max = 0xffffff,
2838         .step = 0x1,
2839 };
2840
2841
2842 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
2843 {
2844         struct adv7842_state *state = to_state(sd);
2845         if (state->i2c_avlink)
2846                 i2c_unregister_device(state->i2c_avlink);
2847         if (state->i2c_cec)
2848                 i2c_unregister_device(state->i2c_cec);
2849         if (state->i2c_infoframe)
2850                 i2c_unregister_device(state->i2c_infoframe);
2851         if (state->i2c_sdp_io)
2852                 i2c_unregister_device(state->i2c_sdp_io);
2853         if (state->i2c_sdp)
2854                 i2c_unregister_device(state->i2c_sdp);
2855         if (state->i2c_afe)
2856                 i2c_unregister_device(state->i2c_afe);
2857         if (state->i2c_repeater)
2858                 i2c_unregister_device(state->i2c_repeater);
2859         if (state->i2c_edid)
2860                 i2c_unregister_device(state->i2c_edid);
2861         if (state->i2c_hdmi)
2862                 i2c_unregister_device(state->i2c_hdmi);
2863         if (state->i2c_cp)
2864                 i2c_unregister_device(state->i2c_cp);
2865         if (state->i2c_vdp)
2866                 i2c_unregister_device(state->i2c_vdp);
2867
2868         state->i2c_avlink = NULL;
2869         state->i2c_cec = NULL;
2870         state->i2c_infoframe = NULL;
2871         state->i2c_sdp_io = NULL;
2872         state->i2c_sdp = NULL;
2873         state->i2c_afe = NULL;
2874         state->i2c_repeater = NULL;
2875         state->i2c_edid = NULL;
2876         state->i2c_hdmi = NULL;
2877         state->i2c_cp = NULL;
2878         state->i2c_vdp = NULL;
2879 }
2880
2881 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
2882                                                u8 addr, u8 io_reg)
2883 {
2884         struct i2c_client *client = v4l2_get_subdevdata(sd);
2885         struct i2c_client *cp;
2886
2887         io_write(sd, io_reg, addr << 1);
2888
2889         if (addr == 0) {
2890                 v4l2_err(sd, "no %s i2c addr configured\n", desc);
2891                 return NULL;
2892         }
2893
2894         cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2895         if (!cp)
2896                 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
2897
2898         return cp;
2899 }
2900
2901 static int adv7842_register_clients(struct v4l2_subdev *sd)
2902 {
2903         struct adv7842_state *state = to_state(sd);
2904         struct adv7842_platform_data *pdata = &state->pdata;
2905
2906         state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
2907         state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
2908         state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
2909         state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
2910         state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
2911         state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
2912         state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
2913         state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
2914         state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
2915         state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
2916         state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
2917
2918         if (!state->i2c_avlink ||
2919             !state->i2c_cec ||
2920             !state->i2c_infoframe ||
2921             !state->i2c_sdp_io ||
2922             !state->i2c_sdp ||
2923             !state->i2c_afe ||
2924             !state->i2c_repeater ||
2925             !state->i2c_edid ||
2926             !state->i2c_hdmi ||
2927             !state->i2c_cp ||
2928             !state->i2c_vdp)
2929                 return -1;
2930
2931         return 0;
2932 }
2933
2934 static int adv7842_probe(struct i2c_client *client,
2935                          const struct i2c_device_id *id)
2936 {
2937         struct adv7842_state *state;
2938         struct adv7842_platform_data *pdata = client->dev.platform_data;
2939         struct v4l2_ctrl_handler *hdl;
2940         struct v4l2_subdev *sd;
2941         u16 rev;
2942         int err;
2943
2944         /* Check if the adapter supports the needed features */
2945         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2946                 return -EIO;
2947
2948         v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2949                 client->addr << 1);
2950
2951         if (!pdata) {
2952                 v4l_err(client, "No platform data!\n");
2953                 return -ENODEV;
2954         }
2955
2956         state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2957         if (!state) {
2958                 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2959                 return -ENOMEM;
2960         }
2961
2962         /* platform data */
2963         state->pdata = *pdata;
2964
2965         sd = &state->sd;
2966         v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2967         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2968         state->mode = pdata->mode;
2969
2970         state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
2971         state->restart_stdi_once = true;
2972
2973         /* i2c access to adv7842? */
2974         rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2975                 adv_smbus_read_byte_data_check(client, 0xeb, false);
2976         if (rev != 0x2012) {
2977                 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
2978                 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2979                         adv_smbus_read_byte_data_check(client, 0xeb, false);
2980         }
2981         if (rev != 0x2012) {
2982                 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
2983                           client->addr << 1, rev);
2984                 return -ENODEV;
2985         }
2986
2987         if (pdata->chip_reset)
2988                 main_reset(sd);
2989
2990         /* control handlers */
2991         hdl = &state->hdl;
2992         v4l2_ctrl_handler_init(hdl, 6);
2993
2994         /* add in ascending ID order */
2995         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2996                           V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2997         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2998                           V4L2_CID_CONTRAST, 0, 255, 1, 128);
2999         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3000                           V4L2_CID_SATURATION, 0, 255, 1, 128);
3001         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3002                           V4L2_CID_HUE, 0, 128, 1, 0);
3003
3004         /* custom controls */
3005         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3006                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3007         state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3008                         &adv7842_ctrl_analog_sampling_phase, NULL);
3009         state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3010                         &adv7842_ctrl_free_run_color_manual, NULL);
3011         state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3012                         &adv7842_ctrl_free_run_color, NULL);
3013         state->rgb_quantization_range_ctrl =
3014                 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3015                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3016                         0, V4L2_DV_RGB_RANGE_AUTO);
3017         sd->ctrl_handler = hdl;
3018         if (hdl->error) {
3019                 err = hdl->error;
3020                 goto err_hdl;
3021         }
3022         state->detect_tx_5v_ctrl->is_private = true;
3023         state->rgb_quantization_range_ctrl->is_private = true;
3024         state->analog_sampling_phase_ctrl->is_private = true;
3025         state->free_run_color_ctrl_manual->is_private = true;
3026         state->free_run_color_ctrl->is_private = true;
3027
3028         if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3029                 err = -ENODEV;
3030                 goto err_hdl;
3031         }
3032
3033         if (adv7842_register_clients(sd) < 0) {
3034                 err = -ENOMEM;
3035                 v4l2_err(sd, "failed to create all i2c clients\n");
3036                 goto err_i2c;
3037         }
3038
3039         /* work queues */
3040         state->work_queues = create_singlethread_workqueue(client->name);
3041         if (!state->work_queues) {
3042                 v4l2_err(sd, "Could not create work queue\n");
3043                 err = -ENOMEM;
3044                 goto err_i2c;
3045         }
3046
3047         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3048                         adv7842_delayed_work_enable_hotplug);
3049
3050         state->pad.flags = MEDIA_PAD_FL_SOURCE;
3051         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
3052         if (err)
3053                 goto err_work_queues;
3054
3055         err = adv7842_core_init(sd);
3056         if (err)
3057                 goto err_entity;
3058
3059         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3060                   client->addr << 1, client->adapter->name);
3061         return 0;
3062
3063 err_entity:
3064         media_entity_cleanup(&sd->entity);
3065 err_work_queues:
3066         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3067         destroy_workqueue(state->work_queues);
3068 err_i2c:
3069         adv7842_unregister_clients(sd);
3070 err_hdl:
3071         v4l2_ctrl_handler_free(hdl);
3072         return err;
3073 }
3074
3075 /* ----------------------------------------------------------------------- */
3076
3077 static int adv7842_remove(struct i2c_client *client)
3078 {
3079         struct v4l2_subdev *sd = i2c_get_clientdata(client);
3080         struct adv7842_state *state = to_state(sd);
3081
3082         adv7842_irq_enable(sd, false);
3083
3084         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3085         destroy_workqueue(state->work_queues);
3086         v4l2_device_unregister_subdev(sd);
3087         media_entity_cleanup(&sd->entity);
3088         adv7842_unregister_clients(sd);
3089         v4l2_ctrl_handler_free(sd->ctrl_handler);
3090         return 0;
3091 }
3092
3093 /* ----------------------------------------------------------------------- */
3094
3095 static struct i2c_device_id adv7842_id[] = {
3096         { "adv7842", 0 },
3097         { }
3098 };
3099 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3100
3101 /* ----------------------------------------------------------------------- */
3102
3103 static struct i2c_driver adv7842_driver = {
3104         .driver = {
3105                 .owner = THIS_MODULE,
3106                 .name = "adv7842",
3107         },
3108         .probe = adv7842_probe,
3109         .remove = adv7842_remove,
3110         .id_table = adv7842_id,
3111 };
3112
3113 module_i2c_driver(adv7842_driver);