drivers/media/i2c/adv7842.c

   1 /*
   2  * adv7842 - Analog Devices ADV7842 video decoder driver
   3  *
   4  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7842, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  */
  28
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/i2c.h>
  34 #include <linux/delay.h>
  35 #include <linux/videodev2.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/v4l2-dv-timings.h>
  38 #include <media/v4l2-device.h>
  39 #include <media/v4l2-ctrls.h>
  40 #include <media/v4l2-dv-timings.h>
  41 #include <media/adv7842.h>
  42
  43 static int debug;
  44 module_param(debug, int, 0644);
  45 MODULE_PARM_DESC(debug, "debug level (0-2)");
  46
  47 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
  48 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  49 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
  50 MODULE_LICENSE("GPL");
  51
  52 /* ADV7842 system clock frequency */
  53 #define ADV7842_fsc (28636360)
  54
  55 /*
  56 **********************************************************************
  57 *
  58 *  Arrays with configuration parameters for the ADV7842
  59 *
  60 **********************************************************************
  61 */
  62
  63 struct adv7842_state {
  64         struct adv7842_platform_data pdata;
  65         struct v4l2_subdev sd;
  66         struct media_pad pad;
  67         struct v4l2_ctrl_handler hdl;
  68         enum adv7842_mode mode;
  69         struct v4l2_dv_timings timings;
  70         enum adv7842_vid_std_select vid_std_select;
  71         v4l2_std_id norm;
  72         struct {
  73                 u8 edid[256];
  74                 u32 present;
  75         } hdmi_edid;
  76         struct {
  77                 u8 edid[256];
  78                 u32 present;
  79         } vga_edid;
  80         struct v4l2_fract aspect_ratio;
  81         u32 rgb_quantization_range;
  82         bool is_cea_format;
  83         struct workqueue_struct *work_queues;
  84         struct delayed_work delayed_work_enable_hotplug;
  85         bool connector_hdmi;
  86         bool hdmi_port_a;
  87
  88         /* i2c clients */
  89         struct i2c_client *i2c_sdp_io;
  90         struct i2c_client *i2c_sdp;
  91         struct i2c_client *i2c_cp;
  92         struct i2c_client *i2c_vdp;
  93         struct i2c_client *i2c_afe;
  94         struct i2c_client *i2c_hdmi;
  95         struct i2c_client *i2c_repeater;
  96         struct i2c_client *i2c_edid;
  97         struct i2c_client *i2c_infoframe;
  98         struct i2c_client *i2c_cec;
  99         struct i2c_client *i2c_avlink;
 100
 101         /* controls */
 102         struct v4l2_ctrl *detect_tx_5v_ctrl;
 103         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 104         struct v4l2_ctrl *free_run_color_ctrl_manual;
 105         struct v4l2_ctrl *free_run_color_ctrl;
 106         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 107 };
 108
 109 /* Unsupported timings. This device cannot support 720p30. */
 110 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
 111         V4L2_DV_BT_CEA_1280X720P30,
 112         { }
 113 };
 114
 115 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
 116 {
 117         int i;
 118
 119         for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
 120                 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
 121                         return false;
 122         return true;
 123 }
 124
 125 struct adv7842_video_standards {
 126         struct v4l2_dv_timings timings;
 127         u8 vid_std;
 128         u8 v_freq;
 129 };
 130
 131 /* sorted by number of lines */
 132 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
 133         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 134         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 135         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 136         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 137         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 138         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 139         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 140         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 141         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 142         /* TODO add 1920x1080P60_RB (CVT timing) */
 143         { },
 144 };
 145
 146 /* sorted by number of lines */
 147 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
 148         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 149         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 150         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 151         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 152         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 153         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 154         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 155         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 156         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 157         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 158         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 159         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 160         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 161         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 162         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 163         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 164         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 165         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 166         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 167         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 168         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 169         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 170         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 171         { },
 172 };
 173
 174 /* sorted by number of lines */
 175 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
 176         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 177         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 178         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 179         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 180         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 181         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 182         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 183         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 184         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 185         { },
 186 };
 187
 188 /* sorted by number of lines */
 189 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
 190         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 191         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 192         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 193         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 194         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 195         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 196         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 199         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 200         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 201         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 203         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 204         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 205         { },
 206 };
 207
 208 /* ----------------------------------------------------------------------- */
 209
 210 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
 211 {
 212         return container_of(sd, struct adv7842_state, sd);
 213 }
 214
 215 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 216 {
 217         return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
 218 }
 219
 220 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 221 {
 222         return V4L2_DV_BT_BLANKING_WIDTH(t);
 223 }
 224
 225 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 226 {
 227         return V4L2_DV_BT_FRAME_WIDTH(t);
 228 }
 229
 230 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 231 {
 232         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 233 }
 234
 235 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 236 {
 237         return V4L2_DV_BT_FRAME_HEIGHT(t);
 238 }
 239
 240
 241 /* ----------------------------------------------------------------------- */
 242
 243 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 244                                           u8 command, bool check)
 245 {
 246         union i2c_smbus_data data;
 247
 248         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 249                             I2C_SMBUS_READ, command,
 250                             I2C_SMBUS_BYTE_DATA, &data))
 251                 return data.byte;
 252         if (check)
 253                 v4l_err(client, "error reading %02x, %02x\n",
 254                         client->addr, command);
 255         return -EIO;
 256 }
 257
 258 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 259 {
 260         int i;
 261
 262         for (i = 0; i < 3; i++) {
 263                 int ret = adv_smbus_read_byte_data_check(client, command, true);
 264
 265                 if (ret >= 0) {
 266                         if (i)
 267                                 v4l_err(client, "read ok after %d retries\n", i);
 268                         return ret;
 269                 }
 270         }
 271         v4l_err(client, "read failed\n");
 272         return -EIO;
 273 }
 274
 275 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 276                                      u8 command, u8 value)
 277 {
 278         union i2c_smbus_data data;
 279         int err;
 280         int i;
 281
 282         data.byte = value;
 283         for (i = 0; i < 3; i++) {
 284                 err = i2c_smbus_xfer(client->adapter, client->addr,
 285                                      client->flags,
 286                                      I2C_SMBUS_WRITE, command,
 287                                      I2C_SMBUS_BYTE_DATA, &data);
 288                 if (!err)
 289                         break;
 290         }
 291         if (err < 0)
 292                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 293                         client->addr, command, value);
 294         return err;
 295 }
 296
 297 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
 298                                           u8 command, u8 value)
 299 {
 300         union i2c_smbus_data data;
 301         data.byte = value;
 302
 303         i2c_smbus_xfer(client->adapter, client->addr,
 304                        client->flags,
 305                        I2C_SMBUS_WRITE, command,
 306                        I2C_SMBUS_BYTE_DATA, &data);
 307 }
 308
 309 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 310                                   u8 command, unsigned length, const u8 *values)
 311 {
 312         union i2c_smbus_data data;
 313
 314         if (length > I2C_SMBUS_BLOCK_MAX)
 315                 length = I2C_SMBUS_BLOCK_MAX;
 316         data.block[0] = length;
 317         memcpy(data.block + 1, values, length);
 318         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 319                               I2C_SMBUS_WRITE, command,
 320                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 321 }
 322
 323 /* ----------------------------------------------------------------------- */
 324
 325 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 326 {
 327         struct i2c_client *client = v4l2_get_subdevdata(sd);
 328
 329         return adv_smbus_read_byte_data(client, reg);
 330 }
 331
 332 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 333 {
 334         struct i2c_client *client = v4l2_get_subdevdata(sd);
 335
 336         return adv_smbus_write_byte_data(client, reg, val);
 337 }
 338
 339 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 340 {
 341         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 342 }
 343
 344 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 345 {
 346         struct adv7842_state *state = to_state(sd);
 347
 348         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 349 }
 350
 351 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 352 {
 353         struct adv7842_state *state = to_state(sd);
 354
 355         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 356 }
 357
 358 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 359 {
 360         struct adv7842_state *state = to_state(sd);
 361
 362         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 363 }
 364
 365 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 366 {
 367         struct adv7842_state *state = to_state(sd);
 368
 369         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 370 }
 371
 372 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 373 {
 374         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 375 }
 376
 377 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 378 {
 379         struct adv7842_state *state = to_state(sd);
 380
 381         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 382 }
 383
 384 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 385 {
 386         struct adv7842_state *state = to_state(sd);
 387
 388         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 389 }
 390
 391 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
 392 {
 393         struct adv7842_state *state = to_state(sd);
 394
 395         return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
 396 }
 397
 398 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 399 {
 400         struct adv7842_state *state = to_state(sd);
 401
 402         return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
 403 }
 404
 405 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 406 {
 407         return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
 408 }
 409
 410 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
 411 {
 412         struct adv7842_state *state = to_state(sd);
 413
 414         return adv_smbus_read_byte_data(state->i2c_sdp, reg);
 415 }
 416
 417 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 418 {
 419         struct adv7842_state *state = to_state(sd);
 420
 421         return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
 422 }
 423
 424 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 425 {
 426         return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
 427 }
 428
 429 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 430 {
 431         struct adv7842_state *state = to_state(sd);
 432
 433         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 434 }
 435
 436 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 437 {
 438         struct adv7842_state *state = to_state(sd);
 439
 440         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 441 }
 442
 443 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 444 {
 445         return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
 446 }
 447
 448 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 449 {
 450         struct adv7842_state *state = to_state(sd);
 451
 452         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 453 }
 454
 455 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 456 {
 457         struct adv7842_state *state = to_state(sd);
 458
 459         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 460 }
 461
 462 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 463 {
 464         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 465 }
 466
 467 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 468 {
 469         struct adv7842_state *state = to_state(sd);
 470
 471         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 472 }
 473
 474 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 475 {
 476         struct adv7842_state *state = to_state(sd);
 477
 478         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 479 }
 480
 481 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 482 {
 483         struct adv7842_state *state = to_state(sd);
 484
 485         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 486 }
 487
 488 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 489 {
 490         struct adv7842_state *state = to_state(sd);
 491
 492         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 493 }
 494
 495 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 496 {
 497         struct adv7842_state *state = to_state(sd);
 498
 499         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 500 }
 501
 502 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 503 {
 504         struct adv7842_state *state = to_state(sd);
 505
 506         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 507 }
 508
 509 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 510 {
 511         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 512 }
 513
 514 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 515 {
 516         struct adv7842_state *state = to_state(sd);
 517
 518         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 519 }
 520
 521 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 522 {
 523         struct adv7842_state *state = to_state(sd);
 524
 525         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 526 }
 527
 528 static void main_reset(struct v4l2_subdev *sd)
 529 {
 530         struct i2c_client *client = v4l2_get_subdevdata(sd);
 531
 532         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 533
 534         adv_smbus_write_byte_no_check(client, 0xff, 0x80);
 535
 536         mdelay(5);
 537 }
 538
 539 /* ----------------------------------------------------------------------- */
 540
 541 static inline bool is_digital_input(struct v4l2_subdev *sd)
 542 {
 543         struct adv7842_state *state = to_state(sd);
 544
 545         return state->mode == ADV7842_MODE_HDMI;
 546 }
 547
 548 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
 549         .type = V4L2_DV_BT_656_1120,
 550         /* keep this initialization for compatibility with GCC < 4.4.6 */
 551         .reserved = { 0 },
 552         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
 553                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 554                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 555                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 556                         V4L2_DV_BT_CAP_CUSTOM)
 557 };
 558
 559 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
 560         .type = V4L2_DV_BT_656_1120,
 561         /* keep this initialization for compatibility with GCC < 4.4.6 */
 562         .reserved = { 0 },
 563         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
 564                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 565                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 566                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 567                         V4L2_DV_BT_CAP_CUSTOM)
 568 };
 569
 570 static inline const struct v4l2_dv_timings_cap *
 571 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
 572 {
 573         return is_digital_input(sd) ? &adv7842_timings_cap_digital :
 574                                       &adv7842_timings_cap_analog;
 575 }
 576
 577 /* ----------------------------------------------------------------------- */
 578
 579 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
 580 {
 581         struct delayed_work *dwork = to_delayed_work(work);
 582         struct adv7842_state *state = container_of(dwork,
 583                         struct adv7842_state, delayed_work_enable_hotplug);
 584         struct v4l2_subdev *sd = &state->sd;
 585         int present = state->hdmi_edid.present;
 586         u8 mask = 0;
 587
 588         v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
 589                         __func__, present);
 590
 591         if (present & 0x1)
 592                 mask |= 0x20; /* port A */
 593         if (present & 0x2)
 594                 mask |= 0x10; /* port B */
 595         io_write_and_or(sd, 0x20, 0xcf, mask);
 596 }
 597
 598 static int edid_write_vga_segment(struct v4l2_subdev *sd)
 599 {
 600         struct i2c_client *client = v4l2_get_subdevdata(sd);
 601         struct adv7842_state *state = to_state(sd);
 602         const u8 *val = state->vga_edid.edid;
 603         int err = 0;
 604         int i;
 605
 606         v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
 607
 608         /* HPA disable on port A and B */
 609         io_write_and_or(sd, 0x20, 0xcf, 0x00);
 610
 611         /* Disable I2C access to internal EDID ram from VGA DDC port */
 612         rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
 613
 614         /* edid segment pointer '1' for VGA port */
 615         rep_write_and_or(sd, 0x77, 0xef, 0x10);
 616
 617         for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
 618                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 619                                              I2C_SMBUS_BLOCK_MAX, val + i);
 620         if (err)
 621                 return err;
 622
 623         /* Calculates the checksums and enables I2C access
 624          * to internal EDID ram from VGA DDC port.
 625          */
 626         rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
 627
 628         for (i = 0; i < 1000; i++) {
 629                 if (rep_read(sd, 0x79) & 0x20)
 630                         break;
 631                 mdelay(1);
 632         }
 633         if (i == 1000) {
 634                 v4l_err(client, "error enabling edid on VGA port\n");
 635                 return -EIO;
 636         }
 637
 638         /* enable hotplug after 200 ms */
 639         queue_delayed_work(state->work_queues,
 640                         &state->delayed_work_enable_hotplug, HZ / 5);
 641
 642         return 0;
 643 }
 644
 645 static int edid_spa_location(const u8 *edid)
 646 {
 647         u8 d;
 648
 649         /*
 650          * TODO, improve and update for other CEA extensions
 651          * currently only for 1 segment (256 bytes),
 652          * i.e. 1 extension block and CEA revision 3.
 653          */
 654         if ((edid[0x7e] != 1) ||
 655             (edid[0x80] != 0x02) ||
 656             (edid[0x81] != 0x03)) {
 657                 return -EINVAL;
 658         }
 659         /*
 660          * search Vendor Specific Data Block (tag 3)
 661          */
 662         d = edid[0x82] & 0x7f;
 663         if (d > 4) {
 664                 int i = 0x84;
 665                 int end = 0x80 + d;
 666                 do {
 667                         u8 tag = edid[i]>>5;
 668                         u8 len = edid[i] & 0x1f;
 669
 670                         if ((tag == 3) && (len >= 5))
 671                                 return i + 4;
 672                         i += len + 1;
 673                 } while (i < end);
 674         }
 675         return -EINVAL;
 676 }
 677
 678 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
 679 {
 680         struct i2c_client *client = v4l2_get_subdevdata(sd);
 681         struct adv7842_state *state = to_state(sd);
 682         const u8 *val = state->hdmi_edid.edid;
 683         u8 cur_mask = rep_read(sd, 0x77) & 0x0c;
 684         u8 mask = port == 0 ? 0x4 : 0x8;
 685         int spa_loc = edid_spa_location(val);
 686         int err = 0;
 687         int i;
 688
 689         v4l2_dbg(2, debug, sd, "%s: write EDID on port %d (spa at 0x%x)\n",
 690                         __func__, port, spa_loc);
 691
 692         /* HPA disable on port A and B */
 693         io_write_and_or(sd, 0x20, 0xcf, 0x00);
 694
 695         /* Disable I2C access to internal EDID ram from HDMI DDC ports */
 696         rep_write_and_or(sd, 0x77, 0xf3, 0x00);
 697
 698         /* edid segment pointer '0' for HDMI ports */
 699         rep_write_and_or(sd, 0x77, 0xef, 0x00);
 700
 701         for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
 702                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 703                                                      I2C_SMBUS_BLOCK_MAX, val + i);
 704         if (err)
 705                 return err;
 706
 707         if (spa_loc > 0) {
 708                 if (port == 0) {
 709                         /* port A SPA */
 710                         rep_write(sd, 0x72, val[spa_loc]);
 711                         rep_write(sd, 0x73, val[spa_loc + 1]);
 712                 } else {
 713                         /* port B SPA */
 714                         rep_write(sd, 0x74, val[spa_loc]);
 715                         rep_write(sd, 0x75, val[spa_loc + 1]);
 716                 }
 717                 rep_write(sd, 0x76, spa_loc);
 718         } else {
 719                 /* Edid values for SPA location */
 720                 if (port == 0) {
 721                         /* port A */
 722                         rep_write(sd, 0x72, val[0xc0]);
 723                         rep_write(sd, 0x73, val[0xc1]);
 724                 } else {
 725                         /* port B */
 726                         rep_write(sd, 0x74, val[0xc0]);
 727                         rep_write(sd, 0x75, val[0xc1]);
 728                 }
 729                 rep_write(sd, 0x76, 0xc0);
 730         }
 731         rep_write_and_or(sd, 0x77, 0xbf, 0x00);
 732
 733         /* Calculates the checksums and enables I2C access to internal
 734          * EDID ram from HDMI DDC ports
 735          */
 736         rep_write_and_or(sd, 0x77, 0xf3, mask | cur_mask);
 737
 738         for (i = 0; i < 1000; i++) {
 739                 if (rep_read(sd, 0x7d) & mask)
 740                         break;
 741                 mdelay(1);
 742         }
 743         if (i == 1000) {
 744                 v4l_err(client, "error enabling edid on port %d\n", port);
 745                 return -EIO;
 746         }
 747
 748         /* enable hotplug after 200 ms */
 749         queue_delayed_work(state->work_queues,
 750                         &state->delayed_work_enable_hotplug, HZ / 5);
 751
 752         return 0;
 753 }
 754
 755 /* ----------------------------------------------------------------------- */
 756
 757 #ifdef CONFIG_VIDEO_ADV_DEBUG
 758 static void adv7842_inv_register(struct v4l2_subdev *sd)
 759 {
 760         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 761         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 762         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 763         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 764         v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
 765         v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
 766         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 767         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 768         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 769         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 770         v4l2_info(sd, "0xa00-0xaff: CP Map\n");
 771         v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
 772 }
 773
 774 static int adv7842_g_register(struct v4l2_subdev *sd,
 775                               struct v4l2_dbg_register *reg)
 776 {
 777         reg->size = 1;
 778         switch (reg->reg >> 8) {
 779         case 0:
 780                 reg->val = io_read(sd, reg->reg & 0xff);
 781                 break;
 782         case 1:
 783                 reg->val = avlink_read(sd, reg->reg & 0xff);
 784                 break;
 785         case 2:
 786                 reg->val = cec_read(sd, reg->reg & 0xff);
 787                 break;
 788         case 3:
 789                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 790                 break;
 791         case 4:
 792                 reg->val = sdp_io_read(sd, reg->reg & 0xff);
 793                 break;
 794         case 5:
 795                 reg->val = sdp_read(sd, reg->reg & 0xff);
 796                 break;
 797         case 6:
 798                 reg->val = afe_read(sd, reg->reg & 0xff);
 799                 break;
 800         case 7:
 801                 reg->val = rep_read(sd, reg->reg & 0xff);
 802                 break;
 803         case 8:
 804                 reg->val = edid_read(sd, reg->reg & 0xff);
 805                 break;
 806         case 9:
 807                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 808                 break;
 809         case 0xa:
 810                 reg->val = cp_read(sd, reg->reg & 0xff);
 811                 break;
 812         case 0xb:
 813                 reg->val = vdp_read(sd, reg->reg & 0xff);
 814                 break;
 815         default:
 816                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 817                 adv7842_inv_register(sd);
 818                 break;
 819         }
 820         return 0;
 821 }
 822
 823 static int adv7842_s_register(struct v4l2_subdev *sd,
 824                 const struct v4l2_dbg_register *reg)
 825 {
 826         u8 val = reg->val & 0xff;
 827
 828         switch (reg->reg >> 8) {
 829         case 0:
 830                 io_write(sd, reg->reg & 0xff, val);
 831                 break;
 832         case 1:
 833                 avlink_write(sd, reg->reg & 0xff, val);
 834                 break;
 835         case 2:
 836                 cec_write(sd, reg->reg & 0xff, val);
 837                 break;
 838         case 3:
 839                 infoframe_write(sd, reg->reg & 0xff, val);
 840                 break;
 841         case 4:
 842                 sdp_io_write(sd, reg->reg & 0xff, val);
 843                 break;
 844         case 5:
 845                 sdp_write(sd, reg->reg & 0xff, val);
 846                 break;
 847         case 6:
 848                 afe_write(sd, reg->reg & 0xff, val);
 849                 break;
 850         case 7:
 851                 rep_write(sd, reg->reg & 0xff, val);
 852                 break;
 853         case 8:
 854                 edid_write(sd, reg->reg & 0xff, val);
 855                 break;
 856         case 9:
 857                 hdmi_write(sd, reg->reg & 0xff, val);
 858                 break;
 859         case 0xa:
 860                 cp_write(sd, reg->reg & 0xff, val);
 861                 break;
 862         case 0xb:
 863                 vdp_write(sd, reg->reg & 0xff, val);
 864                 break;
 865         default:
 866                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 867                 adv7842_inv_register(sd);
 868                 break;
 869         }
 870         return 0;
 871 }
 872 #endif
 873
 874 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 875 {
 876         struct adv7842_state *state = to_state(sd);
 877         int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
 878         u8 reg_io_6f = io_read(sd, 0x6f);
 879         int val = 0;
 880
 881         if (reg_io_6f & 0x02)
 882                 val |= 1; /* port A */
 883         if (reg_io_6f & 0x01)
 884                 val |= 2; /* port B */
 885
 886         v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
 887
 888         if (val != prev)
 889                 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
 890         return 0;
 891 }
 892
 893 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 894                 u8 prim_mode,
 895                 const struct adv7842_video_standards *predef_vid_timings,
 896                 const struct v4l2_dv_timings *timings)
 897 {
 898         int i;
 899
 900         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 901                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 902                                           is_digital_input(sd) ? 250000 : 1000000))
 903                         continue;
 904                 /* video std */
 905                 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
 906                 /* v_freq and prim mode */
 907                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
 908                 return 0;
 909         }
 910
 911         return -1;
 912 }
 913
 914 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 915                 struct v4l2_dv_timings *timings)
 916 {
 917         struct adv7842_state *state = to_state(sd);
 918         int err;
 919
 920         v4l2_dbg(1, debug, sd, "%s\n", __func__);
 921
 922         /* reset to default values */
 923         io_write(sd, 0x16, 0x43);
 924         io_write(sd, 0x17, 0x5a);
 925         /* disable embedded syncs for auto graphics mode */
 926         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 927         cp_write(sd, 0x26, 0x00);
 928         cp_write(sd, 0x27, 0x00);
 929         cp_write(sd, 0x28, 0x00);
 930         cp_write(sd, 0x29, 0x00);
 931         cp_write(sd, 0x8f, 0x40);
 932         cp_write(sd, 0x90, 0x00);
 933         cp_write(sd, 0xa5, 0x00);
 934         cp_write(sd, 0xa6, 0x00);
 935         cp_write(sd, 0xa7, 0x00);
 936         cp_write(sd, 0xab, 0x00);
 937         cp_write(sd, 0xac, 0x00);
 938
 939         switch (state->mode) {
 940         case ADV7842_MODE_COMP:
 941         case ADV7842_MODE_RGB:
 942                 err = find_and_set_predefined_video_timings(sd,
 943                                 0x01, adv7842_prim_mode_comp, timings);
 944                 if (err)
 945                         err = find_and_set_predefined_video_timings(sd,
 946                                         0x02, adv7842_prim_mode_gr, timings);
 947                 break;
 948         case ADV7842_MODE_HDMI:
 949                 err = find_and_set_predefined_video_timings(sd,
 950                                 0x05, adv7842_prim_mode_hdmi_comp, timings);
 951                 if (err)
 952                         err = find_and_set_predefined_video_timings(sd,
 953                                         0x06, adv7842_prim_mode_hdmi_gr, timings);
 954                 break;
 955         default:
 956                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
 957                                 __func__, state->mode);
 958                 err = -1;
 959                 break;
 960         }
 961
 962
 963         return err;
 964 }
 965
 966 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 967                 const struct v4l2_bt_timings *bt)
 968 {
 969         struct adv7842_state *state = to_state(sd);
 970         struct i2c_client *client = v4l2_get_subdevdata(sd);
 971         u32 width = htotal(bt);
 972         u32 height = vtotal(bt);
 973         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 974         u16 cp_start_eav = width - bt->hfrontporch;
 975         u16 cp_start_vbi = height - bt->vfrontporch + 1;
 976         u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
 977         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 978                 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 979         const u8 pll[2] = {
 980                 0xc0 | ((width >> 8) & 0x1f),
 981                 width & 0xff
 982         };
 983
 984         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 985
 986         switch (state->mode) {
 987         case ADV7842_MODE_COMP:
 988         case ADV7842_MODE_RGB:
 989                 /* auto graphics */
 990                 io_write(sd, 0x00, 0x07); /* video std */
 991                 io_write(sd, 0x01, 0x02); /* prim mode */
 992                 /* enable embedded syncs for auto graphics mode */
 993                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 994
 995                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 996                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 997                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 998                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
 999                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1000                         break;
1001                 }
1002
1003                 /* active video - horizontal timing */
1004                 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1005                 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1006                 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1007                 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1008
1009                 /* active video - vertical timing */
1010                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1011                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1012                                         ((cp_end_vbi >> 8) & 0xf));
1013                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1014                 break;
1015         case ADV7842_MODE_HDMI:
1016                 /* set default prim_mode/vid_std for HDMI
1017                    according to [REF_03, c. 4.2] */
1018                 io_write(sd, 0x00, 0x02); /* video std */
1019                 io_write(sd, 0x01, 0x06); /* prim mode */
1020                 break;
1021         default:
1022                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1023                                 __func__, state->mode);
1024                 break;
1025         }
1026
1027         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1028         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1029         cp_write(sd, 0xab, (height >> 4) & 0xff);
1030         cp_write(sd, 0xac, (height & 0x0f) << 4);
1031 }
1032
1033 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1034 {
1035         struct adv7842_state *state = to_state(sd);
1036
1037         v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
1038                        __func__, state->rgb_quantization_range);
1039
1040         switch (state->rgb_quantization_range) {
1041         case V4L2_DV_RGB_RANGE_AUTO:
1042                 if (state->mode == ADV7842_MODE_RGB) {
1043                         /* Receiving analog RGB signal
1044                          * Set RGB full range (0-255) */
1045                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1046                         break;
1047                 }
1048
1049                 if (state->mode == ADV7842_MODE_COMP) {
1050                         /* Receiving analog YPbPr signal
1051                          * Set automode */
1052                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1053                         break;
1054                 }
1055
1056                 if (hdmi_read(sd, 0x05) & 0x80) {
1057                         /* Receiving HDMI signal
1058                          * Set automode */
1059                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1060                         break;
1061                 }
1062
1063                 /* Receiving DVI-D signal
1064                  * ADV7842 selects RGB limited range regardless of
1065                  * input format (CE/IT) in automatic mode */
1066                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1067                         /* RGB limited range (16-235) */
1068                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
1069                 } else {
1070                         /* RGB full range (0-255) */
1071                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1072                 }
1073                 break;
1074         case V4L2_DV_RGB_RANGE_LIMITED:
1075                 if (state->mode == ADV7842_MODE_COMP) {
1076                         /* YCrCb limited range (16-235) */
1077                         io_write_and_or(sd, 0x02, 0x0f, 0x20);
1078                 } else {
1079                         /* RGB limited range (16-235) */
1080                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
1081                 }
1082                 break;
1083         case V4L2_DV_RGB_RANGE_FULL:
1084                 if (state->mode == ADV7842_MODE_COMP) {
1085                         /* YCrCb full range (0-255) */
1086                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1087                 } else {
1088                         /* RGB full range (0-255) */
1089                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1090                 }
1091                 break;
1092         }
1093 }
1094
1095 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1096 {
1097         struct v4l2_subdev *sd = to_sd(ctrl);
1098         struct adv7842_state *state = to_state(sd);
1099
1100         /* TODO SDP ctrls
1101            contrast/brightness/hue/free run is acting a bit strange,
1102            not sure if sdp csc is correct.
1103          */
1104         switch (ctrl->id) {
1105         /* standard ctrls */
1106         case V4L2_CID_BRIGHTNESS:
1107                 cp_write(sd, 0x3c, ctrl->val);
1108                 sdp_write(sd, 0x14, ctrl->val);
1109                 /* ignore lsb sdp 0x17[3:2] */
1110                 return 0;
1111         case V4L2_CID_CONTRAST:
1112                 cp_write(sd, 0x3a, ctrl->val);
1113                 sdp_write(sd, 0x13, ctrl->val);
1114                 /* ignore lsb sdp 0x17[1:0] */
1115                 return 0;
1116         case V4L2_CID_SATURATION:
1117                 cp_write(sd, 0x3b, ctrl->val);
1118                 sdp_write(sd, 0x15, ctrl->val);
1119                 /* ignore lsb sdp 0x17[5:4] */
1120                 return 0;
1121         case V4L2_CID_HUE:
1122                 cp_write(sd, 0x3d, ctrl->val);
1123                 sdp_write(sd, 0x16, ctrl->val);
1124                 /* ignore lsb sdp 0x17[7:6] */
1125                 return 0;
1126                 /* custom ctrls */
1127         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1128                 afe_write(sd, 0xc8, ctrl->val);
1129                 return 0;
1130         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1131                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1132                 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1133                 return 0;
1134         case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1135                 u8 R = (ctrl->val & 0xff0000) >> 16;
1136                 u8 G = (ctrl->val & 0x00ff00) >> 8;
1137                 u8 B = (ctrl->val & 0x0000ff);
1138                 /* RGB -> YUV, numerical approximation */
1139                 int Y = 66 * R + 129 * G + 25 * B;
1140                 int U = -38 * R - 74 * G + 112 * B;
1141                 int V = 112 * R - 94 * G - 18 * B;
1142
1143                 /* Scale down to 8 bits with rounding */
1144                 Y = (Y + 128) >> 8;
1145                 U = (U + 128) >> 8;
1146                 V = (V + 128) >> 8;
1147                 /* make U,V positive */
1148                 Y += 16;
1149                 U += 128;
1150                 V += 128;
1151
1152                 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1153                 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1154
1155                 /* CP */
1156                 cp_write(sd, 0xc1, R);
1157                 cp_write(sd, 0xc0, G);
1158                 cp_write(sd, 0xc2, B);
1159                 /* SDP */
1160                 sdp_write(sd, 0xde, Y);
1161                 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1162                 return 0;
1163         }
1164         case V4L2_CID_DV_RX_RGB_RANGE:
1165                 state->rgb_quantization_range = ctrl->val;
1166                 set_rgb_quantization_range(sd);
1167                 return 0;
1168         }
1169         return -EINVAL;
1170 }
1171
1172 static inline bool no_power(struct v4l2_subdev *sd)
1173 {
1174         return io_read(sd, 0x0c) & 0x24;
1175 }
1176
1177 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1178 {
1179         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1180 }
1181
1182 static inline bool is_hdmi(struct v4l2_subdev *sd)
1183 {
1184         return hdmi_read(sd, 0x05) & 0x80;
1185 }
1186
1187 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1188 {
1189         struct adv7842_state *state = to_state(sd);
1190
1191         *status = 0;
1192
1193         if (io_read(sd, 0x0c) & 0x24)
1194                 *status |= V4L2_IN_ST_NO_POWER;
1195
1196         if (state->mode == ADV7842_MODE_SDP) {
1197                 /* status from SDP block */
1198                 if (!(sdp_read(sd, 0x5A) & 0x01))
1199                         *status |= V4L2_IN_ST_NO_SIGNAL;
1200
1201                 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1202                                 __func__, *status);
1203                 return 0;
1204         }
1205         /* status from CP block */
1206         if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1207                         !(cp_read(sd, 0xb1) & 0x80))
1208                 /* TODO channel 2 */
1209                 *status |= V4L2_IN_ST_NO_SIGNAL;
1210
1211         if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1212                 *status |= V4L2_IN_ST_NO_SIGNAL;
1213
1214         v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1215                         __func__, *status);
1216
1217         return 0;
1218 }
1219
1220 struct stdi_readback {
1221         u16 bl, lcf, lcvs;
1222         u8 hs_pol, vs_pol;
1223         bool interlaced;
1224 };
1225
1226 static int stdi2dv_timings(struct v4l2_subdev *sd,
1227                 struct stdi_readback *stdi,
1228                 struct v4l2_dv_timings *timings)
1229 {
1230         struct adv7842_state *state = to_state(sd);
1231         u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1232         u32 pix_clk;
1233         int i;
1234
1235         for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1236                 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1237
1238                 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1239                                            adv7842_get_dv_timings_cap(sd),
1240                                            adv7842_check_dv_timings, NULL))
1241                         continue;
1242                 if (vtotal(bt) != stdi->lcf + 1)
1243                         continue;
1244                 if (bt->vsync != stdi->lcvs)
1245                         continue;
1246
1247                 pix_clk = hfreq * htotal(bt);
1248
1249                 if ((pix_clk < bt->pixelclock + 1000000) &&
1250                     (pix_clk > bt->pixelclock - 1000000)) {
1251                         *timings = v4l2_dv_timings_presets[i];
1252                         return 0;
1253                 }
1254         }
1255
1256         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1257                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1258                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1259                             timings))
1260                 return 0;
1261         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1262                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1263                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1264                             state->aspect_ratio, timings))
1265                 return 0;
1266
1267         v4l2_dbg(2, debug, sd,
1268                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1269                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1270                 stdi->hs_pol, stdi->vs_pol);
1271         return -1;
1272 }
1273
1274 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1275 {
1276         u32 status;
1277
1278         adv7842_g_input_status(sd, &status);
1279         if (status & V4L2_IN_ST_NO_SIGNAL) {
1280                 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1281                 return -ENOLINK;
1282         }
1283
1284         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1285         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1286         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1287
1288         if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1289                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1290                         ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1291                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1292                         ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1293         } else {
1294                 stdi->hs_pol = 'x';
1295                 stdi->vs_pol = 'x';
1296         }
1297         stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1298
1299         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1300                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1301                 return -ENOLINK;
1302         }
1303
1304         v4l2_dbg(2, debug, sd,
1305                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1306                  __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1307                  stdi->hs_pol, stdi->vs_pol,
1308                  stdi->interlaced ? "interlaced" : "progressive");
1309
1310         return 0;
1311 }
1312
1313 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1314                                    struct v4l2_enum_dv_timings *timings)
1315 {
1316         return v4l2_enum_dv_timings_cap(timings,
1317                 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1318 }
1319
1320 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1321                                   struct v4l2_dv_timings_cap *cap)
1322 {
1323         *cap = *adv7842_get_dv_timings_cap(sd);
1324         return 0;
1325 }
1326
1327 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1328    if the format is listed in adv7842_timings[] */
1329 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1330                 struct v4l2_dv_timings *timings)
1331 {
1332         v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1333                         is_digital_input(sd) ? 250000 : 1000000,
1334                         adv7842_check_dv_timings, NULL);
1335 }
1336
1337 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1338                                     struct v4l2_dv_timings *timings)
1339 {
1340         struct adv7842_state *state = to_state(sd);
1341         struct v4l2_bt_timings *bt = &timings->bt;
1342         struct stdi_readback stdi = { 0 };
1343
1344         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1345
1346         /* SDP block */
1347         if (state->mode == ADV7842_MODE_SDP)
1348                 return -ENODATA;
1349
1350         /* read STDI */
1351         if (read_stdi(sd, &stdi)) {
1352                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1353                 return -ENOLINK;
1354         }
1355         bt->interlaced = stdi.interlaced ?
1356                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1357
1358         if (is_digital_input(sd)) {
1359                 uint32_t freq;
1360
1361                 timings->type = V4L2_DV_BT_656_1120;
1362                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1363                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1364                 freq = (hdmi_read(sd, 0x06) * 1000000) +
1365                        ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1366
1367                 if (is_hdmi(sd)) {
1368                         /* adjust for deep color mode */
1369                         freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8);
1370                 }
1371                 bt->pixelclock = freq;
1372                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1373                         hdmi_read(sd, 0x21);
1374                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1375                         hdmi_read(sd, 0x23);
1376                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1377                         hdmi_read(sd, 0x25);
1378                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1379                         hdmi_read(sd, 0x2b)) / 2;
1380                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1381                         hdmi_read(sd, 0x2f)) / 2;
1382                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1383                         hdmi_read(sd, 0x33)) / 2;
1384                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1385                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1386                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1387                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1388                                         hdmi_read(sd, 0x0c);
1389                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1390                                         hdmi_read(sd, 0x2d)) / 2;
1391                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1392                                         hdmi_read(sd, 0x31)) / 2;
1393                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1394                                         hdmi_read(sd, 0x35)) / 2;
1395                 }
1396                 adv7842_fill_optional_dv_timings_fields(sd, timings);
1397         } else {
1398                 /* Interlaced? */
1399                 if (stdi.interlaced) {
1400                         v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__);
1401                         return -ERANGE;
1402                 }
1403
1404                 if (stdi2dv_timings(sd, &stdi, timings)) {
1405                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1406                         return -ERANGE;
1407                 }
1408         }
1409
1410         if (debug > 1)
1411                 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings: ",
1412                                       timings, true);
1413         return 0;
1414 }
1415
1416 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1417                                 struct v4l2_dv_timings *timings)
1418 {
1419         struct adv7842_state *state = to_state(sd);
1420         struct v4l2_bt_timings *bt;
1421         int err;
1422
1423         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1424
1425         if (state->mode == ADV7842_MODE_SDP)
1426                 return -ENODATA;
1427
1428         bt = &timings->bt;
1429
1430         if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1431                                    adv7842_check_dv_timings, NULL))
1432                 return -ERANGE;
1433
1434         adv7842_fill_optional_dv_timings_fields(sd, timings);
1435
1436         state->timings = *timings;
1437
1438         cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1439
1440         /* Use prim_mode and vid_std when available */
1441         err = configure_predefined_video_timings(sd, timings);
1442         if (err) {
1443                 /* custom settings when the video format
1444                   does not have prim_mode/vid_std */
1445                 configure_custom_video_timings(sd, bt);
1446         }
1447
1448         set_rgb_quantization_range(sd);
1449
1450
1451         if (debug > 1)
1452                 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1453                                       timings, true);
1454         return 0;
1455 }
1456
1457 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1458                                 struct v4l2_dv_timings *timings)
1459 {
1460         struct adv7842_state *state = to_state(sd);
1461
1462         if (state->mode == ADV7842_MODE_SDP)
1463                 return -ENODATA;
1464         *timings = state->timings;
1465         return 0;
1466 }
1467
1468 static void enable_input(struct v4l2_subdev *sd)
1469 {
1470         struct adv7842_state *state = to_state(sd);
1471
1472         set_rgb_quantization_range(sd);
1473         switch (state->mode) {
1474         case ADV7842_MODE_SDP:
1475         case ADV7842_MODE_COMP:
1476         case ADV7842_MODE_RGB:
1477                 /* enable */
1478                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1479                 break;
1480         case ADV7842_MODE_HDMI:
1481                 /* enable */
1482                 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1483                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1484                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1485                 break;
1486         default:
1487                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1488                          __func__, state->mode);
1489                 break;
1490         }
1491 }
1492
1493 static void disable_input(struct v4l2_subdev *sd)
1494 {
1495         /* disable */
1496         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1497         hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1498         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1499 }
1500
1501 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1502                           const struct adv7842_sdp_csc_coeff *c)
1503 {
1504         /* csc auto/manual */
1505         sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1506
1507         if (!c->manual)
1508                 return;
1509
1510         /* csc scaling */
1511         sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1512
1513         /* A coeff */
1514         sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1515         sdp_io_write(sd, 0xe1, c->A1);
1516         sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1517         sdp_io_write(sd, 0xe3, c->A2);
1518         sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1519         sdp_io_write(sd, 0xe5, c->A3);
1520
1521         /* A scale */
1522         sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1523         sdp_io_write(sd, 0xe7, c->A4);
1524
1525         /* B coeff */
1526         sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1527         sdp_io_write(sd, 0xe9, c->B1);
1528         sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1529         sdp_io_write(sd, 0xeb, c->B2);
1530         sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1531         sdp_io_write(sd, 0xed, c->B3);
1532
1533         /* B scale */
1534         sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1535         sdp_io_write(sd, 0xef, c->B4);
1536
1537         /* C coeff */
1538         sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1539         sdp_io_write(sd, 0xf1, c->C1);
1540         sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1541         sdp_io_write(sd, 0xf3, c->C2);
1542         sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1543         sdp_io_write(sd, 0xf5, c->C3);
1544
1545         /* C scale */
1546         sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1547         sdp_io_write(sd, 0xf7, c->C4);
1548 }
1549
1550 static void select_input(struct v4l2_subdev *sd,
1551                          enum adv7842_vid_std_select vid_std_select)
1552 {
1553         struct adv7842_state *state = to_state(sd);
1554
1555         switch (state->mode) {
1556         case ADV7842_MODE_SDP:
1557                 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1558                 io_write(sd, 0x01, 0); /* prim mode */
1559                 /* enable embedded syncs for auto graphics mode */
1560                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1561
1562                 afe_write(sd, 0x00, 0x00); /* power up ADC */
1563                 afe_write(sd, 0xc8, 0x00); /* phase control */
1564
1565                 io_write(sd, 0x19, 0x83); /* LLC DLL phase */
1566                 io_write(sd, 0x33, 0x40); /* LLC DLL enable */
1567
1568                 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1569                 /* script says register 0xde, which don't exist in manual */
1570
1571                 /* Manual analog input muxing mode, CVBS (6.4)*/
1572                 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1573                 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1574                         afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1575                         afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1576                 } else {
1577                         afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1578                         afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1579                 }
1580                 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1581                 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1582
1583                 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1584                 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1585
1586                 /* SDP recommended settings */
1587                 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1588                 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1589
1590                 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1591                 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1592                 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1593                 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1594                 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1595                 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1596                 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1597
1598                 /* deinterlacer enabled and 3D comb */
1599                 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1600
1601                 sdp_write(sd, 0xdd, 0x08); /* free run auto */
1602
1603                 break;
1604
1605         case ADV7842_MODE_COMP:
1606         case ADV7842_MODE_RGB:
1607                 /* Automatic analog input muxing mode */
1608                 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1609                 /* set mode and select free run resolution */
1610                 io_write(sd, 0x00, vid_std_select); /* video std */
1611                 io_write(sd, 0x01, 0x02); /* prim mode */
1612                 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1613                                                           for auto graphics mode */
1614
1615                 afe_write(sd, 0x00, 0x00); /* power up ADC */
1616                 afe_write(sd, 0xc8, 0x00); /* phase control */
1617                 if (state->mode == ADV7842_MODE_COMP) {
1618                         /* force to YCrCb */
1619                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1620                 } else {
1621                         /* force to RGB */
1622                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
1623                 }
1624
1625                 /* set ADI recommended settings for digitizer */
1626                 /* "ADV7842 Register Settings Recommendations
1627                  * (rev. 1.8, November 2010)" p. 9. */
1628                 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1629                 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1630
1631                 /* set to default gain for RGB */
1632                 cp_write(sd, 0x73, 0x10);
1633                 cp_write(sd, 0x74, 0x04);
1634                 cp_write(sd, 0x75, 0x01);
1635                 cp_write(sd, 0x76, 0x00);
1636
1637                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1638                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1639                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1640                 break;
1641
1642         case ADV7842_MODE_HDMI:
1643                 /* Automatic analog input muxing mode */
1644                 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1645                 /* set mode and select free run resolution */
1646                 if (state->hdmi_port_a)
1647                         hdmi_write(sd, 0x00, 0x02); /* select port A */
1648                 else
1649                         hdmi_write(sd, 0x00, 0x03); /* select port B */
1650                 io_write(sd, 0x00, vid_std_select); /* video std */
1651                 io_write(sd, 0x01, 5); /* prim mode */
1652                 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1653                                                           for auto graphics mode */
1654
1655                 /* set ADI recommended settings for HDMI: */
1656                 /* "ADV7842 Register Settings Recommendations
1657                  * (rev. 1.8, November 2010)" p. 3. */
1658                 hdmi_write(sd, 0xc0, 0x00);
1659                 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1660                 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1661                 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1662                 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1663                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1664                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1665                 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1666                 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1667                 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1668                                                Improve robustness */
1669                 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1670                 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1671                 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1672                 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1673                 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1674                 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1675                 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1676                 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1677                 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1678                 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1679
1680                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1681                 afe_write(sd, 0xc8, 0x40); /* phase control */
1682
1683                 /* set to default gain for HDMI */
1684                 cp_write(sd, 0x73, 0x10);
1685                 cp_write(sd, 0x74, 0x04);
1686                 cp_write(sd, 0x75, 0x01);
1687                 cp_write(sd, 0x76, 0x00);
1688
1689                 /* reset ADI recommended settings for digitizer */
1690                 /* "ADV7842 Register Settings Recommendations
1691                  * (rev. 2.5, June 2010)" p. 17. */
1692                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1693                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1694                 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control,
1695                                              enable color control */
1696                 /* CP coast control */
1697                 cp_write(sd, 0xc3, 0x33); /* Component mode */
1698
1699                 /* color space conversion, autodetect color space */
1700                 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1701                 break;
1702
1703         default:
1704                 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1705                          __func__, state->mode);
1706                 break;
1707         }
1708 }
1709
1710 static int adv7842_s_routing(struct v4l2_subdev *sd,
1711                 u32 input, u32 output, u32 config)
1712 {
1713         struct adv7842_state *state = to_state(sd);
1714
1715         v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1716
1717         switch (input) {
1718         case ADV7842_SELECT_HDMI_PORT_A:
1719                 state->mode = ADV7842_MODE_HDMI;
1720                 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1721                 state->hdmi_port_a = true;
1722                 break;
1723         case ADV7842_SELECT_HDMI_PORT_B:
1724                 state->mode = ADV7842_MODE_HDMI;
1725                 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1726                 state->hdmi_port_a = false;
1727                 break;
1728         case ADV7842_SELECT_VGA_COMP:
1729                 state->mode = ADV7842_MODE_COMP;
1730                 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1731                 break;
1732         case ADV7842_SELECT_VGA_RGB:
1733                 state->mode = ADV7842_MODE_RGB;
1734                 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1735                 break;
1736         case ADV7842_SELECT_SDP_CVBS:
1737                 state->mode = ADV7842_MODE_SDP;
1738                 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1739                 break;
1740         case ADV7842_SELECT_SDP_YC:
1741                 state->mode = ADV7842_MODE_SDP;
1742                 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1743                 break;
1744         default:
1745                 return -EINVAL;
1746         }
1747
1748         disable_input(sd);
1749         select_input(sd, state->vid_std_select);
1750         enable_input(sd);
1751
1752         v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1753
1754         return 0;
1755 }
1756
1757 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1758                                  enum v4l2_mbus_pixelcode *code)
1759 {
1760         if (index)
1761                 return -EINVAL;
1762         /* Good enough for now */
1763         *code = V4L2_MBUS_FMT_FIXED;
1764         return 0;
1765 }
1766
1767 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1768                               struct v4l2_mbus_framefmt *fmt)
1769 {
1770         struct adv7842_state *state = to_state(sd);
1771
1772         fmt->width = state->timings.bt.width;
1773         fmt->height = state->timings.bt.height;
1774         fmt->code = V4L2_MBUS_FMT_FIXED;
1775         fmt->field = V4L2_FIELD_NONE;
1776
1777         if (state->mode == ADV7842_MODE_SDP) {
1778                 /* SPD block */
1779                 if (!(sdp_read(sd, 0x5A) & 0x01))
1780                         return -EINVAL;
1781                 fmt->width = 720;
1782                 /* valid signal */
1783                 if (state->norm & V4L2_STD_525_60)
1784                         fmt->height = 480;
1785                 else
1786                         fmt->height = 576;
1787                 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1788                 return 0;
1789         }
1790
1791         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1792                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1793                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1794         }
1795         return 0;
1796 }
1797
1798 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1799 {
1800         if (enable) {
1801                 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1802                 io_write(sd, 0x46, 0x9c);
1803                 /* ESDP_50HZ_DET interrupt */
1804                 io_write(sd, 0x5a, 0x10);
1805                 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1806                 io_write(sd, 0x73, 0x03);
1807                 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1808                 io_write(sd, 0x78, 0x03);
1809                 /* Enable SDP Standard Detection Change and SDP Video Detected */
1810                 io_write(sd, 0xa0, 0x09);
1811         } else {
1812                 io_write(sd, 0x46, 0x0);
1813                 io_write(sd, 0x5a, 0x0);
1814                 io_write(sd, 0x73, 0x0);
1815                 io_write(sd, 0x78, 0x0);
1816                 io_write(sd, 0xa0, 0x0);
1817         }
1818 }
1819
1820 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1821 {
1822         struct adv7842_state *state = to_state(sd);
1823         u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1824         u8 irq_status[5];
1825
1826         adv7842_irq_enable(sd, false);
1827
1828         /* read status */
1829         irq_status[0] = io_read(sd, 0x43);
1830         irq_status[1] = io_read(sd, 0x57);
1831         irq_status[2] = io_read(sd, 0x70);
1832         irq_status[3] = io_read(sd, 0x75);
1833         irq_status[4] = io_read(sd, 0x9d);
1834
1835         /* and clear */
1836         if (irq_status[0])
1837                 io_write(sd, 0x44, irq_status[0]);
1838         if (irq_status[1])
1839                 io_write(sd, 0x58, irq_status[1]);
1840         if (irq_status[2])
1841                 io_write(sd, 0x71, irq_status[2]);
1842         if (irq_status[3])
1843                 io_write(sd, 0x76, irq_status[3]);
1844         if (irq_status[4])
1845                 io_write(sd, 0x9e, irq_status[4]);
1846
1847         adv7842_irq_enable(sd, true);
1848
1849         v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__,
1850                  irq_status[0], irq_status[1], irq_status[2],
1851                  irq_status[3], irq_status[4]);
1852
1853         /* format change CP */
1854         fmt_change_cp = irq_status[0] & 0x9c;
1855
1856         /* format change SDP */
1857         if (state->mode == ADV7842_MODE_SDP)
1858                 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1859         else
1860                 fmt_change_sdp = 0;
1861
1862         /* digital format CP */
1863         if (is_digital_input(sd))
1864                 fmt_change_digital = irq_status[3] & 0x03;
1865         else
1866                 fmt_change_digital = 0;
1867
1868         /* notify */
1869         if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1870                 v4l2_dbg(1, debug, sd,
1871                          "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1872                          __func__, fmt_change_cp, fmt_change_digital,
1873                          fmt_change_sdp);
1874                 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1875         }
1876
1877         /* 5v cable detect */
1878         if (irq_status[2])
1879                 adv7842_s_detect_tx_5v_ctrl(sd);
1880
1881         if (handled)
1882                 *handled = true;
1883
1884         return 0;
1885 }
1886
1887 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
1888 {
1889         struct adv7842_state *state = to_state(sd);
1890         int err = 0;
1891
1892         if (e->pad > 2)
1893                 return -EINVAL;
1894         if (e->start_block != 0)
1895                 return -EINVAL;
1896         if (e->blocks > 2)
1897                 return -E2BIG;
1898         if (!e->edid)
1899                 return -EINVAL;
1900
1901         /* todo, per edid */
1902         state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
1903                         e->edid[0x16]);
1904
1905         if (e->pad == 2) {
1906                 memset(&state->vga_edid.edid, 0, 256);
1907                 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
1908                 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
1909                 err = edid_write_vga_segment(sd);
1910         } else {
1911                 u32 mask = 0x1<<e->pad;
1912                 memset(&state->hdmi_edid.edid, 0, 256);
1913                 if (e->blocks)
1914                         state->hdmi_edid.present |= mask;
1915                 else
1916                         state->hdmi_edid.present &= ~mask;
1917                 memcpy(&state->hdmi_edid.edid, e->edid, 128*e->blocks);
1918                 err = edid_write_hdmi_segment(sd, e->pad);
1919         }
1920         if (err < 0)
1921                 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
1922         return err;
1923 }
1924
1925 /*********** avi info frame CEA-861-E **************/
1926 /* TODO move to common library */
1927
1928 struct avi_info_frame {
1929         uint8_t f17;
1930         uint8_t y10;
1931         uint8_t a0;
1932         uint8_t b10;
1933         uint8_t s10;
1934         uint8_t c10;
1935         uint8_t m10;
1936         uint8_t r3210;
1937         uint8_t itc;
1938         uint8_t ec210;
1939         uint8_t q10;
1940         uint8_t sc10;
1941         uint8_t f47;
1942         uint8_t vic;
1943         uint8_t yq10;
1944         uint8_t cn10;
1945         uint8_t pr3210;
1946         uint16_t etb;
1947         uint16_t sbb;
1948         uint16_t elb;
1949         uint16_t srb;
1950 };
1951
1952 static const char *y10_txt[4] = {
1953         "RGB",
1954         "YCbCr 4:2:2",
1955         "YCbCr 4:4:4",
1956         "Future",
1957 };
1958
1959 static const char *c10_txt[4] = {
1960         "No Data",
1961         "SMPTE 170M",
1962         "ITU-R 709",
1963         "Extended Colorimetry information valied",
1964 };
1965
1966 static const char *itc_txt[2] = {
1967         "No Data",
1968         "IT content",
1969 };
1970
1971 static const char *ec210_txt[8] = {
1972         "xvYCC601",
1973         "xvYCC709",
1974         "sYCC601",
1975         "AdobeYCC601",
1976         "AdobeRGB",
1977         "5 reserved",
1978         "6 reserved",
1979         "7 reserved",
1980 };
1981
1982 static const char *q10_txt[4] = {
1983         "Default",
1984         "Limited Range",
1985         "Full Range",
1986         "Reserved",
1987 };
1988
1989 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
1990                                 struct avi_info_frame *avi)
1991 {
1992         avi->f17 = (buf[1] >> 7) & 0x1;
1993         avi->y10 = (buf[1] >> 5) & 0x3;
1994         avi->a0 = (buf[1] >> 4) & 0x1;
1995         avi->b10 = (buf[1] >> 2) & 0x3;
1996         avi->s10 = buf[1] & 0x3;
1997         avi->c10 = (buf[2] >> 6) & 0x3;
1998         avi->m10 = (buf[2] >> 4) & 0x3;
1999         avi->r3210 = buf[2] & 0xf;
2000         avi->itc = (buf[3] >> 7) & 0x1;
2001         avi->ec210 = (buf[3] >> 4) & 0x7;
2002         avi->q10 = (buf[3] >> 2) & 0x3;
2003         avi->sc10 = buf[3] & 0x3;
2004         avi->f47 = (buf[4] >> 7) & 0x1;
2005         avi->vic = buf[4] & 0x7f;
2006         avi->yq10 = (buf[5] >> 6) & 0x3;
2007         avi->cn10 = (buf[5] >> 4) & 0x3;
2008         avi->pr3210 = buf[5] & 0xf;
2009         avi->etb = buf[6] + 256*buf[7];
2010         avi->sbb = buf[8] + 256*buf[9];
2011         avi->elb = buf[10] + 256*buf[11];
2012         avi->srb = buf[12] + 256*buf[13];
2013 }
2014
2015 static void print_avi_infoframe(struct v4l2_subdev *sd)
2016 {
2017         int i;
2018         uint8_t buf[14];
2019         uint8_t avi_inf_len;
2020         struct avi_info_frame avi;
2021
2022         if (!(hdmi_read(sd, 0x05) & 0x80)) {
2023                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2024                 return;
2025         }
2026         if (!(io_read(sd, 0x60) & 0x01)) {
2027                 v4l2_info(sd, "AVI infoframe not received\n");
2028                 return;
2029         }
2030
2031         if (io_read(sd, 0x88) & 0x10) {
2032                 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2033                    with a length of 14 or 15. See the ADV7842 Register Settings
2034                    Recommendations document for more details. */
2035                 v4l2_info(sd, "AVI infoframe checksum error\n");
2036                 return;
2037         }
2038
2039         avi_inf_len = infoframe_read(sd, 0xe2);
2040         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2041                   infoframe_read(sd, 0xe1), avi_inf_len);
2042
2043         if (infoframe_read(sd, 0xe1) != 0x02)
2044                 return;
2045
2046         for (i = 0; i < 14; i++)
2047                 buf[i] = infoframe_read(sd, i);
2048
2049         v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2050                   buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2051                   buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2052
2053         parse_avi_infoframe(sd, buf, &avi);
2054
2055         if (avi.vic)
2056                 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2057         if (avi.itc)
2058                 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2059
2060         if (avi.y10)
2061                 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2062                         (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2063         else
2064                 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2065 }
2066
2067 static const char * const prim_mode_txt[] = {
2068         "SDP",
2069         "Component",
2070         "Graphics",
2071         "Reserved",
2072         "CVBS & HDMI AUDIO",
2073         "HDMI-Comp",
2074         "HDMI-GR",
2075         "Reserved",
2076         "Reserved",
2077         "Reserved",
2078         "Reserved",
2079         "Reserved",
2080         "Reserved",
2081         "Reserved",
2082         "Reserved",
2083         "Reserved",
2084 };
2085
2086 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2087 {
2088         /* SDP (Standard definition processor) block */
2089         uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2090
2091         v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2092         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2093                   io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2094
2095         v4l2_info(sd, "SDP: free run: %s\n",
2096                 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2097         v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2098                 "valid SD/PR signal detected" : "invalid/no signal");
2099         if (sdp_signal_detected) {
2100                 static const char * const sdp_std_txt[] = {
2101                         "NTSC-M/J",
2102                         "1?",
2103                         "NTSC-443",
2104                         "60HzSECAM",
2105                         "PAL-M",
2106                         "5?",
2107                         "PAL-60",
2108                         "7?", "8?", "9?", "a?", "b?",
2109                         "PAL-CombN",
2110                         "d?",
2111                         "PAL-BGHID",
2112                         "SECAM"
2113                 };
2114                 v4l2_info(sd, "SDP: standard %s\n",
2115                         sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2116                 v4l2_info(sd, "SDP: %s\n",
2117                         (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2118                 v4l2_info(sd, "SDP: %s\n",
2119                         (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2120                 v4l2_info(sd, "SDP: deinterlacer %s\n",
2121                         (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2122                 v4l2_info(sd, "SDP: csc %s mode\n",
2123                         (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2124         }
2125         return 0;
2126 }
2127
2128 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2129 {
2130         /* CP block */
2131         struct adv7842_state *state = to_state(sd);
2132         struct v4l2_dv_timings timings;
2133         uint8_t reg_io_0x02 = io_read(sd, 0x02);
2134         uint8_t reg_io_0x21 = io_read(sd, 0x21);
2135         uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2136         uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2137         bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2138         bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2139         bool audio_mute = io_read(sd, 0x65) & 0x40;
2140
2141         static const char * const csc_coeff_sel_rb[16] = {
2142                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2143                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2144                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2145                 "reserved", "reserved", "reserved", "reserved", "manual"
2146         };
2147         static const char * const input_color_space_txt[16] = {
2148                 "RGB limited range (16-235)", "RGB full range (0-255)",
2149                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2150                 "xvYCC Bt.601", "xvYCC Bt.709",
2151                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2152                 "invalid", "invalid", "invalid", "invalid", "invalid",
2153                 "invalid", "invalid", "automatic"
2154         };
2155         static const char * const rgb_quantization_range_txt[] = {
2156                 "Automatic",
2157                 "RGB limited range (16-235)",
2158                 "RGB full range (0-255)",
2159         };
2160         static const char * const deep_color_mode_txt[4] = {
2161                 "8-bits per channel",
2162                 "10-bits per channel",
2163                 "12-bits per channel",
2164                 "16-bits per channel (not supported)"
2165         };
2166
2167         v4l2_info(sd, "-----Chip status-----\n");
2168         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2169         v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
2170                         "HDMI" : (is_digital_input(sd) ? "DVI-D" : "DVI-A"));
2171         v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2172                         state->hdmi_port_a ? "A" : "B");
2173         v4l2_info(sd, "EDID A %s, B %s\n",
2174                   ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2175                   "enabled" : "disabled",
2176                   ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2177                   "enabled" : "disabled");
2178         v4l2_info(sd, "HPD A %s, B %s\n",
2179                   reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2180                   reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2181         v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2182                         "enabled" : "disabled");
2183
2184         v4l2_info(sd, "-----Signal status-----\n");
2185         if (state->hdmi_port_a) {
2186                 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2187                           io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2188                 v4l2_info(sd, "TMDS signal detected: %s\n",
2189                           (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2190                 v4l2_info(sd, "TMDS signal locked: %s\n",
2191                           (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2192         } else {
2193                 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2194                           io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2195                 v4l2_info(sd, "TMDS signal detected: %s\n",
2196                           (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2197                 v4l2_info(sd, "TMDS signal locked: %s\n",
2198                           (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2199         }
2200         v4l2_info(sd, "CP free run: %s\n",
2201                   (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2202         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2203                   io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2204                   (io_read(sd, 0x01) & 0x70) >> 4);
2205
2206         v4l2_info(sd, "-----Video Timings-----\n");
2207         if (no_cp_signal(sd)) {
2208                 v4l2_info(sd, "STDI: not locked\n");
2209         } else {
2210                 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2211                 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2212                 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2213                 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2214                 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2215                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2216                 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2217                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2218                 v4l2_info(sd,
2219                         "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2220                         lcf, bl, lcvs, fcl,
2221                         (cp_read(sd, 0xb1) & 0x40) ?
2222                                 "interlaced" : "progressive",
2223                         hs_pol, vs_pol);
2224         }
2225         if (adv7842_query_dv_timings(sd, &timings))
2226                 v4l2_info(sd, "No video detected\n");
2227         else
2228                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2229                                       &timings, true);
2230         v4l2_print_dv_timings(sd->name, "Configured format: ",
2231                         &state->timings, true);
2232
2233         if (no_cp_signal(sd))
2234                 return 0;
2235
2236         v4l2_info(sd, "-----Color space-----\n");
2237         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2238                   rgb_quantization_range_txt[state->rgb_quantization_range]);
2239         v4l2_info(sd, "Input color space: %s\n",
2240                   input_color_space_txt[reg_io_0x02 >> 4]);
2241         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2242                   (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2243                   (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2244                   ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2245                                         "enabled" : "disabled");
2246         v4l2_info(sd, "Color space conversion: %s\n",
2247                   csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2248
2249         if (!is_digital_input(sd))
2250                 return 0;
2251
2252         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2253         v4l2_info(sd, "HDCP encrypted content: %s\n",
2254                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2255         v4l2_info(sd, "HDCP keys read: %s%s\n",
2256                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2257                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2258         if (!is_hdmi(sd))
2259                 return 0;
2260
2261         v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2262                         audio_pll_locked ? "locked" : "not locked",
2263                         audio_sample_packet_detect ? "detected" : "not detected",
2264                         audio_mute ? "muted" : "enabled");
2265         if (audio_pll_locked && audio_sample_packet_detect) {
2266                 v4l2_info(sd, "Audio format: %s\n",
2267                         (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2268         }
2269         v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2270                         (hdmi_read(sd, 0x5c) << 8) +
2271                         (hdmi_read(sd, 0x5d) & 0xf0));
2272         v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2273                         (hdmi_read(sd, 0x5e) << 8) +
2274                         hdmi_read(sd, 0x5f));
2275         v4l2_info(sd, "AV Mute: %s\n",
2276                         (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2277         v4l2_info(sd, "Deep color mode: %s\n",
2278                         deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2279
2280         print_avi_infoframe(sd);
2281         return 0;
2282 }
2283
2284 static int adv7842_log_status(struct v4l2_subdev *sd)
2285 {
2286         struct adv7842_state *state = to_state(sd);
2287
2288         if (state->mode == ADV7842_MODE_SDP)
2289                 return adv7842_sdp_log_status(sd);
2290         return adv7842_cp_log_status(sd);
2291 }
2292
2293 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2294 {
2295         struct adv7842_state *state = to_state(sd);
2296
2297         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2298
2299         if (state->mode != ADV7842_MODE_SDP)
2300                 return -ENODATA;
2301
2302         if (!(sdp_read(sd, 0x5A) & 0x01)) {
2303                 *std = 0;
2304                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2305                 return 0;
2306         }
2307
2308         switch (sdp_read(sd, 0x52) & 0x0f) {
2309         case 0:
2310                 /* NTSC-M/J */
2311                 *std &= V4L2_STD_NTSC;
2312                 break;
2313         case 2:
2314                 /* NTSC-443 */
2315                 *std &= V4L2_STD_NTSC_443;
2316                 break;
2317         case 3:
2318                 /* 60HzSECAM */
2319                 *std &= V4L2_STD_SECAM;
2320                 break;
2321         case 4:
2322                 /* PAL-M */
2323                 *std &= V4L2_STD_PAL_M;
2324                 break;
2325         case 6:
2326                 /* PAL-60 */
2327                 *std &= V4L2_STD_PAL_60;
2328                 break;
2329         case 0xc:
2330                 /* PAL-CombN */
2331                 *std &= V4L2_STD_PAL_Nc;
2332                 break;
2333         case 0xe:
2334                 /* PAL-BGHID */
2335                 *std &= V4L2_STD_PAL;
2336                 break;
2337         case 0xf:
2338                 /* SECAM */
2339                 *std &= V4L2_STD_SECAM;
2340                 break;
2341         default:
2342                 *std &= V4L2_STD_ALL;
2343                 break;
2344         }
2345         return 0;
2346 }
2347
2348 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2349 {
2350         if (s && s->adjust) {
2351                 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2352                 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2353                 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2354                 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2355                 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2356                 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2357                 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2358                 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2359                 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2360                 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2361                 sdp_io_write(sd, 0xae, s->de_v_end_o);
2362                 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2363         } else {
2364                 /* set to default */
2365                 sdp_io_write(sd, 0x94, 0x00);
2366                 sdp_io_write(sd, 0x95, 0x00);
2367                 sdp_io_write(sd, 0x96, 0x00);
2368                 sdp_io_write(sd, 0x97, 0x20);
2369                 sdp_io_write(sd, 0x98, 0x00);
2370                 sdp_io_write(sd, 0x99, 0x00);
2371                 sdp_io_write(sd, 0x9a, 0x00);
2372                 sdp_io_write(sd, 0x9b, 0x00);
2373                 sdp_io_write(sd, 0xac, 0x04);
2374                 sdp_io_write(sd, 0xad, 0x04);
2375                 sdp_io_write(sd, 0xae, 0x04);
2376                 sdp_io_write(sd, 0xaf, 0x04);
2377         }
2378 }
2379
2380 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2381 {
2382         struct adv7842_state *state = to_state(sd);
2383         struct adv7842_platform_data *pdata = &state->pdata;
2384
2385         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2386
2387         if (state->mode != ADV7842_MODE_SDP)
2388                 return -ENODATA;
2389
2390         if (norm & V4L2_STD_625_50)
2391                 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2392         else if (norm & V4L2_STD_525_60)
2393                 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2394         else
2395                 adv7842_s_sdp_io(sd, NULL);
2396
2397         if (norm & V4L2_STD_ALL) {
2398                 state->norm = norm;
2399                 return 0;
2400         }
2401         return -EINVAL;
2402 }
2403
2404 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2405 {
2406         struct adv7842_state *state = to_state(sd);
2407
2408         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2409
2410         if (state->mode != ADV7842_MODE_SDP)
2411                 return -ENODATA;
2412
2413         *norm = state->norm;
2414         return 0;
2415 }
2416
2417 /* ----------------------------------------------------------------------- */
2418
2419 static int adv7842_core_init(struct v4l2_subdev *sd)
2420 {
2421         struct adv7842_state *state = to_state(sd);
2422         struct adv7842_platform_data *pdata = &state->pdata;
2423         hdmi_write(sd, 0x48,
2424                    (pdata->disable_pwrdnb ? 0x80 : 0) |
2425                    (pdata->disable_cable_det_rst ? 0x40 : 0));
2426
2427         disable_input(sd);
2428
2429         /* power */
2430         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2431         io_write(sd, 0x15, 0x80);   /* Power up pads */
2432
2433         /* video format */
2434         io_write(sd, 0x02,
2435                  0xf0 |
2436                  pdata->alt_gamma << 3 |
2437                  pdata->op_656_range << 2 |
2438                  pdata->rgb_out << 1 |
2439                  pdata->alt_data_sat << 0);
2440         io_write(sd, 0x03, pdata->op_format_sel);
2441         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2442         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2443                         pdata->insert_av_codes << 2 |
2444                         pdata->replicate_av_codes << 1 |
2445                         pdata->invert_cbcr << 0);
2446
2447         /* Drive strength */
2448         io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
2449                         pdata->drive_strength.clock<<2 |
2450                         pdata->drive_strength.sync);
2451
2452         /* HDMI free run */
2453         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01);
2454
2455         /* TODO from platform data */
2456         cp_write(sd, 0x69, 0x14);   /* Enable CP CSC */
2457         io_write(sd, 0x06, 0xa6);   /* positive VS and HS and DE */
2458         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2459         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2460
2461         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2462         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2463
2464         sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2465
2466         /* todo, improve settings for sdram */
2467         if (pdata->sd_ram_size >= 128) {
2468                 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2469                 if (pdata->sd_ram_ddr) {
2470                         /* SDP setup for the AD eval board */
2471                         sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2472                         sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2473                         sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2474                         sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2475                         sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2476                 } else {
2477                         sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2478                         sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2479                         sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2480                                                          depends on memory */
2481                         sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2482                         sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2483                         sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2484                         sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2485                 }
2486         } else {
2487                 /*
2488                  * Manual UG-214, rev 0 is bit confusing on this bit
2489                  * but a '1' disables any signal if the Ram is active.
2490                  */
2491                 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2492         }
2493
2494         select_input(sd, pdata->vid_std_select);
2495
2496         enable_input(sd);
2497
2498         /* disable I2C access to internal EDID ram from HDMI DDC ports */
2499         rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2500
2501         hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2502         /* HPA disable on port A and B */
2503         io_write_and_or(sd, 0x20, 0xcf, 0x00);
2504
2505         /* LLC */
2506         /* Set phase to 16. TODO: get this from platform_data */
2507         io_write(sd, 0x19, 0x90);
2508         io_write(sd, 0x33, 0x40);
2509
2510         /* interrupts */
2511         io_write(sd, 0x40, 0xf2); /* Configure INT1 */
2512
2513         adv7842_irq_enable(sd, true);
2514
2515         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2516 }
2517
2518 /* ----------------------------------------------------------------------- */
2519
2520 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2521 {
2522         /*
2523          * From ADV784x external Memory test.pdf
2524          *
2525          * Reset must just been performed before running test.
2526          * Recommended to reset after test.
2527          */
2528         int i;
2529         int pass = 0;
2530         int fail = 0;
2531         int complete = 0;
2532
2533         io_write(sd, 0x00, 0x01);  /* Program SDP 4x1 */
2534         io_write(sd, 0x01, 0x00);  /* Program SDP mode */
2535         afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2536         afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2537         afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2538         afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2539         afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2540         afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2541         io_write(sd, 0x0C, 0x40);  /* Power up ADV7844 */
2542         io_write(sd, 0x15, 0xBA);  /* Enable outputs */
2543         sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2544         io_write(sd, 0xFF, 0x04);  /* Reset memory controller */
2545
2546         mdelay(5);
2547
2548         sdp_write(sd, 0x12, 0x00);    /* Disable 3D Comb, Frame TBC & 3DNR */
2549         sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2550         sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2551         sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2552         sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2553         sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2554         sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2555         sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2556         sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2557         sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2558         sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2559
2560         mdelay(5);
2561
2562         sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2563         sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2564
2565         mdelay(20);
2566
2567         for (i = 0; i < 10; i++) {
2568                 u8 result = sdp_io_read(sd, 0xdb);
2569                 if (result & 0x10) {
2570                         complete++;
2571                         if (result & 0x20)
2572                                 fail++;
2573                         else
2574                                 pass++;
2575                 }
2576                 mdelay(20);
2577         }
2578
2579         v4l2_dbg(1, debug, sd,
2580                 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2581                 complete, i, pass, fail);
2582
2583         if (!complete || fail)
2584                 return -EIO;
2585         return 0;
2586 }
2587
2588 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2589                 struct adv7842_platform_data *pdata)
2590 {
2591         io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2592         io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2593         io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2594         io_write(sd, 0xf4, pdata->i2c_cec << 1);
2595         io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2596
2597         io_write(sd, 0xf8, pdata->i2c_afe << 1);
2598         io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2599         io_write(sd, 0xfa, pdata->i2c_edid << 1);
2600         io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2601
2602         io_write(sd, 0xfd, pdata->i2c_cp << 1);
2603         io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2604 }
2605
2606 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2607 {
2608         struct i2c_client *client = v4l2_get_subdevdata(sd);
2609         struct adv7842_state *state = to_state(sd);
2610         struct adv7842_platform_data *pdata = client->dev.platform_data;
2611         int ret = 0;
2612
2613         if (!pdata)
2614                 return -ENODEV;
2615
2616         if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2617                 v4l2_info(sd, "no sdram or no ddr sdram\n");
2618                 return -EINVAL;
2619         }
2620
2621         main_reset(sd);
2622
2623         adv7842_rewrite_i2c_addresses(sd, pdata);
2624
2625         /* run ram test */
2626         ret = adv7842_ddr_ram_test(sd);
2627
2628         main_reset(sd);
2629
2630         adv7842_rewrite_i2c_addresses(sd, pdata);
2631
2632         /* and re-init chip and state */
2633         adv7842_core_init(sd);
2634
2635         disable_input(sd);
2636
2637         select_input(sd, state->vid_std_select);
2638
2639         enable_input(sd);
2640
2641         adv7842_s_dv_timings(sd, &state->timings);
2642
2643         edid_write_vga_segment(sd);
2644         edid_write_hdmi_segment(sd, 0);
2645         edid_write_hdmi_segment(sd, 1);
2646
2647         return ret;
2648 }
2649
2650 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2651 {
2652         switch (cmd) {
2653         case ADV7842_CMD_RAM_TEST:
2654                 return adv7842_command_ram_test(sd);
2655         }
2656         return -ENOTTY;
2657 }
2658
2659 /* ----------------------------------------------------------------------- */
2660
2661 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2662         .s_ctrl = adv7842_s_ctrl,
2663 };
2664
2665 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2666         .log_status = adv7842_log_status,
2667         .g_std = adv7842_g_std,
2668         .s_std = adv7842_s_std,
2669         .ioctl = adv7842_ioctl,
2670         .interrupt_service_routine = adv7842_isr,
2671 #ifdef CONFIG_VIDEO_ADV_DEBUG
2672         .g_register = adv7842_g_register,
2673         .s_register = adv7842_s_register,
2674 #endif
2675 };
2676
2677 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2678         .s_routing = adv7842_s_routing,
2679         .querystd = adv7842_querystd,
2680         .g_input_status = adv7842_g_input_status,
2681         .s_dv_timings = adv7842_s_dv_timings,
2682         .g_dv_timings = adv7842_g_dv_timings,
2683         .query_dv_timings = adv7842_query_dv_timings,
2684         .enum_dv_timings = adv7842_enum_dv_timings,
2685         .dv_timings_cap = adv7842_dv_timings_cap,
2686         .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2687         .g_mbus_fmt = adv7842_g_mbus_fmt,
2688         .try_mbus_fmt = adv7842_g_mbus_fmt,
2689         .s_mbus_fmt = adv7842_g_mbus_fmt,
2690 };
2691
2692 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2693         .set_edid = adv7842_set_edid,
2694 };
2695
2696 static const struct v4l2_subdev_ops adv7842_ops = {
2697         .core = &adv7842_core_ops,
2698         .video = &adv7842_video_ops,
2699         .pad = &adv7842_pad_ops,
2700 };
2701
2702 /* -------------------------- custom ctrls ---------------------------------- */
2703
2704 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2705         .ops = &adv7842_ctrl_ops,
2706         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2707         .name = "Analog Sampling Phase",
2708         .type = V4L2_CTRL_TYPE_INTEGER,
2709         .min = 0,
2710         .max = 0x1f,
2711         .step = 1,
2712         .def = 0,
2713 };
2714
2715 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2716         .ops = &adv7842_ctrl_ops,
2717         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2718         .name = "Free Running Color, Manual",
2719         .type = V4L2_CTRL_TYPE_BOOLEAN,
2720         .max = 1,
2721         .step = 1,
2722         .def = 1,
2723 };
2724
2725 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2726         .ops = &adv7842_ctrl_ops,
2727         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2728         .name = "Free Running Color",
2729         .type = V4L2_CTRL_TYPE_INTEGER,
2730         .max = 0xffffff,
2731         .step = 0x1,
2732 };
2733
2734
2735 static void adv7842_unregister_clients(struct adv7842_state *state)
2736 {
2737         if (state->i2c_avlink)
2738                 i2c_unregister_device(state->i2c_avlink);
2739         if (state->i2c_cec)
2740                 i2c_unregister_device(state->i2c_cec);
2741         if (state->i2c_infoframe)
2742                 i2c_unregister_device(state->i2c_infoframe);
2743         if (state->i2c_sdp_io)
2744                 i2c_unregister_device(state->i2c_sdp_io);
2745         if (state->i2c_sdp)
2746                 i2c_unregister_device(state->i2c_sdp);
2747         if (state->i2c_afe)
2748                 i2c_unregister_device(state->i2c_afe);
2749         if (state->i2c_repeater)
2750                 i2c_unregister_device(state->i2c_repeater);
2751         if (state->i2c_edid)
2752                 i2c_unregister_device(state->i2c_edid);
2753         if (state->i2c_hdmi)
2754                 i2c_unregister_device(state->i2c_hdmi);
2755         if (state->i2c_cp)
2756                 i2c_unregister_device(state->i2c_cp);
2757         if (state->i2c_vdp)
2758                 i2c_unregister_device(state->i2c_vdp);
2759 }
2760
2761 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd,
2762                                                u8 addr, u8 io_reg)
2763 {
2764         struct i2c_client *client = v4l2_get_subdevdata(sd);
2765
2766         io_write(sd, io_reg, addr << 1);
2767         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2768 }
2769
2770 static int adv7842_probe(struct i2c_client *client,
2771                          const struct i2c_device_id *id)
2772 {
2773         struct adv7842_state *state;
2774         struct adv7842_platform_data *pdata = client->dev.platform_data;
2775         struct v4l2_ctrl_handler *hdl;
2776         struct v4l2_subdev *sd;
2777         u16 rev;
2778         int err;
2779
2780         /* Check if the adapter supports the needed features */
2781         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2782                 return -EIO;
2783
2784         v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2785                 client->addr << 1);
2786
2787         if (!pdata) {
2788                 v4l_err(client, "No platform data!\n");
2789                 return -ENODEV;
2790         }
2791
2792         state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2793         if (!state) {
2794                 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2795                 return -ENOMEM;
2796         }
2797
2798         /* platform data */
2799         state->pdata = *pdata;
2800
2801         sd = &state->sd;
2802         v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2803         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2804         state->connector_hdmi = pdata->connector_hdmi;
2805         state->mode = pdata->mode;
2806
2807         state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
2808
2809         /* i2c access to adv7842? */
2810         rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2811                 adv_smbus_read_byte_data_check(client, 0xeb, false);
2812         if (rev != 0x2012) {
2813                 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
2814                 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2815                         adv_smbus_read_byte_data_check(client, 0xeb, false);
2816         }
2817         if (rev != 0x2012) {
2818                 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
2819                           client->addr << 1, rev);
2820                 return -ENODEV;
2821         }
2822
2823         if (pdata->chip_reset)
2824                 main_reset(sd);
2825
2826         /* control handlers */
2827         hdl = &state->hdl;
2828         v4l2_ctrl_handler_init(hdl, 6);
2829
2830         /* add in ascending ID order */
2831         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2832                           V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2833         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2834                           V4L2_CID_CONTRAST, 0, 255, 1, 128);
2835         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2836                           V4L2_CID_SATURATION, 0, 255, 1, 128);
2837         v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2838                           V4L2_CID_HUE, 0, 128, 1, 0);
2839
2840         /* custom controls */
2841         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2842                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
2843         state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
2844                         &adv7842_ctrl_analog_sampling_phase, NULL);
2845         state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
2846                         &adv7842_ctrl_free_run_color_manual, NULL);
2847         state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
2848                         &adv7842_ctrl_free_run_color, NULL);
2849         state->rgb_quantization_range_ctrl =
2850                 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
2851                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2852                         0, V4L2_DV_RGB_RANGE_AUTO);
2853         sd->ctrl_handler = hdl;
2854         if (hdl->error) {
2855                 err = hdl->error;
2856                 goto err_hdl;
2857         }
2858         state->detect_tx_5v_ctrl->is_private = true;
2859         state->rgb_quantization_range_ctrl->is_private = true;
2860         state->analog_sampling_phase_ctrl->is_private = true;
2861         state->free_run_color_ctrl_manual->is_private = true;
2862         state->free_run_color_ctrl->is_private = true;
2863
2864         if (adv7842_s_detect_tx_5v_ctrl(sd)) {
2865                 err = -ENODEV;
2866                 goto err_hdl;
2867         }
2868
2869         state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2870         state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4);
2871         state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2872         state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2);
2873         state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1);
2874         state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8);
2875         state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2876         state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa);
2877         state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2878         state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd);
2879         state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2880         if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2881             !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe ||
2882             !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2883             !state->i2c_cp || !state->i2c_vdp) {
2884                 err = -ENOMEM;
2885                 v4l2_err(sd, "failed to create all i2c clients\n");
2886                 goto err_i2c;
2887         }
2888
2889         /* work queues */
2890         state->work_queues = create_singlethread_workqueue(client->name);
2891         if (!state->work_queues) {
2892                 v4l2_err(sd, "Could not create work queue\n");
2893                 err = -ENOMEM;
2894                 goto err_i2c;
2895         }
2896
2897         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2898                         adv7842_delayed_work_enable_hotplug);
2899
2900         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2901         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2902         if (err)
2903                 goto err_work_queues;
2904
2905         err = adv7842_core_init(sd);
2906         if (err)
2907                 goto err_entity;
2908
2909         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2910                   client->addr << 1, client->adapter->name);
2911         return 0;
2912
2913 err_entity:
2914         media_entity_cleanup(&sd->entity);
2915 err_work_queues:
2916         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2917         destroy_workqueue(state->work_queues);
2918 err_i2c:
2919         adv7842_unregister_clients(state);
2920 err_hdl:
2921         v4l2_ctrl_handler_free(hdl);
2922         return err;
2923 }
2924
2925 /* ----------------------------------------------------------------------- */
2926
2927 static int adv7842_remove(struct i2c_client *client)
2928 {
2929         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2930         struct adv7842_state *state = to_state(sd);
2931
2932         adv7842_irq_enable(sd, false);
2933
2934         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2935         destroy_workqueue(state->work_queues);
2936         v4l2_device_unregister_subdev(sd);
2937         media_entity_cleanup(&sd->entity);
2938         adv7842_unregister_clients(to_state(sd));
2939         v4l2_ctrl_handler_free(sd->ctrl_handler);
2940         return 0;
2941 }
2942
2943 /* ----------------------------------------------------------------------- */
2944
2945 static struct i2c_device_id adv7842_id[] = {
2946         { "adv7842", 0 },
2947         { }
2948 };
2949 MODULE_DEVICE_TABLE(i2c, adv7842_id);
2950
2951 /* ----------------------------------------------------------------------- */
2952
2953 static struct i2c_driver adv7842_driver = {
2954         .driver = {
2955                 .owner = THIS_MODULE,
2956                 .name = "adv7842",
2957         },
2958         .probe = adv7842_probe,
2959         .remove = adv7842_remove,
2960         .id_table = adv7842_id,
2961 };
2962
2963 module_i2c_driver(adv7842_driver);