2 * Copyright (c) 2017 Intel Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License version
6 * 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/acpi.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
22 #define OV13858_REG_VALUE_08BIT 1
23 #define OV13858_REG_VALUE_16BIT 2
24 #define OV13858_REG_VALUE_24BIT 3
26 #define OV13858_REG_MODE_SELECT 0x0100
27 #define OV13858_MODE_STANDBY 0x00
28 #define OV13858_MODE_STREAMING 0x01
30 #define OV13858_REG_SOFTWARE_RST 0x0103
31 #define OV13858_SOFTWARE_RST 0x01
33 /* PLL1 generates PCLK and MIPI_PHY_CLK */
34 #define OV13858_REG_PLL1_CTRL_0 0x0300
35 #define OV13858_REG_PLL1_CTRL_1 0x0301
36 #define OV13858_REG_PLL1_CTRL_2 0x0302
37 #define OV13858_REG_PLL1_CTRL_3 0x0303
38 #define OV13858_REG_PLL1_CTRL_4 0x0304
39 #define OV13858_REG_PLL1_CTRL_5 0x0305
41 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
42 #define OV13858_REG_PLL2_CTRL_B 0x030b
43 #define OV13858_REG_PLL2_CTRL_C 0x030c
44 #define OV13858_REG_PLL2_CTRL_D 0x030d
45 #define OV13858_REG_PLL2_CTRL_E 0x030e
46 #define OV13858_REG_PLL2_CTRL_F 0x030f
47 #define OV13858_REG_PLL2_CTRL_12 0x0312
48 #define OV13858_REG_MIPI_SC_CTRL0 0x3016
49 #define OV13858_REG_MIPI_SC_CTRL1 0x3022
52 #define OV13858_REG_CHIP_ID 0x300a
53 #define OV13858_CHIP_ID 0x00d855
55 /* V_TIMING internal */
56 #define OV13858_REG_VTS 0x380e
57 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */
58 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */
59 #define OV13858_VTS_MAX 0x7fff
60 #define OV13858_VBLANK_MIN 56
62 /* HBLANK control - read only */
63 #define OV13858_PPL_540MHZ 2244
64 #define OV13858_PPL_1080MHZ 4488
66 /* Exposure control */
67 #define OV13858_REG_EXPOSURE 0x3500
68 #define OV13858_EXPOSURE_MIN 4
69 #define OV13858_EXPOSURE_MAX (OV13858_VTS_MAX - 8)
70 #define OV13858_EXPOSURE_STEP 1
71 #define OV13858_EXPOSURE_DEFAULT 0x640
73 /* Analog gain control */
74 #define OV13858_REG_ANALOG_GAIN 0x3508
75 #define OV13858_ANA_GAIN_MIN 0
76 #define OV13858_ANA_GAIN_MAX 0x1fff
77 #define OV13858_ANA_GAIN_STEP 1
78 #define OV13858_ANA_GAIN_DEFAULT 0x80
80 /* Digital gain control */
81 #define OV13858_REG_DIGITAL_GAIN 0x350a
82 #define OV13858_DGTL_GAIN_MASK 0xf3
83 #define OV13858_DGTL_GAIN_SHIFT 2
84 #define OV13858_DGTL_GAIN_MIN 1
85 #define OV13858_DGTL_GAIN_MAX 4
86 #define OV13858_DGTL_GAIN_STEP 1
87 #define OV13858_DGTL_GAIN_DEFAULT 1
89 /* Test Pattern Control */
90 #define OV13858_REG_TEST_PATTERN 0x4503
91 #define OV13858_TEST_PATTERN_ENABLE BIT(7)
92 #define OV13858_TEST_PATTERN_MASK 0xfc
94 /* Number of frames to skip */
95 #define OV13858_NUM_OF_SKIP_FRAMES 2
102 struct ov13858_reg_list {
104 const struct ov13858_reg *regs;
107 /* Link frequency config */
108 struct ov13858_link_freq_config {
112 /* PLL registers for this link frequency */
113 struct ov13858_reg_list reg_list;
116 /* Mode : resolution and related config&values */
117 struct ov13858_mode {
126 /* Index of Link frequency config to be used */
128 /* Default register values */
129 struct ov13858_reg_list reg_list;
132 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
133 static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
135 {OV13858_REG_PLL1_CTRL_0, 0x07},
136 {OV13858_REG_PLL1_CTRL_1, 0x01},
137 {OV13858_REG_PLL1_CTRL_2, 0xc2},
138 {OV13858_REG_PLL1_CTRL_3, 0x00},
139 {OV13858_REG_PLL1_CTRL_4, 0x00},
140 {OV13858_REG_PLL1_CTRL_5, 0x01},
143 {OV13858_REG_PLL2_CTRL_B, 0x05},
144 {OV13858_REG_PLL2_CTRL_C, 0x01},
145 {OV13858_REG_PLL2_CTRL_D, 0x0e},
146 {OV13858_REG_PLL2_CTRL_E, 0x05},
147 {OV13858_REG_PLL2_CTRL_F, 0x01},
148 {OV13858_REG_PLL2_CTRL_12, 0x01},
149 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
150 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
154 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
157 static const struct ov13858_reg mipi_data_rate_540mbps[] = {
159 {OV13858_REG_PLL1_CTRL_0, 0x07},
160 {OV13858_REG_PLL1_CTRL_1, 0x01},
161 {OV13858_REG_PLL1_CTRL_2, 0xc2},
162 {OV13858_REG_PLL1_CTRL_3, 0x01},
163 {OV13858_REG_PLL1_CTRL_4, 0x00},
164 {OV13858_REG_PLL1_CTRL_5, 0x01},
167 {OV13858_REG_PLL2_CTRL_B, 0x05},
168 {OV13858_REG_PLL2_CTRL_C, 0x01},
169 {OV13858_REG_PLL2_CTRL_D, 0x0e},
170 {OV13858_REG_PLL2_CTRL_E, 0x05},
171 {OV13858_REG_PLL2_CTRL_F, 0x01},
172 {OV13858_REG_PLL2_CTRL_12, 0x01},
173 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
174 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
177 static const struct ov13858_reg mode_4224x3136_regs[] = {
367 static const struct ov13858_reg mode_2112x1568_regs[] = {
557 static const struct ov13858_reg mode_2112x1188_regs[] = {
747 static const struct ov13858_reg mode_1056x784_regs[] = {
937 static const char * const ov13858_test_pattern_menu[] = {
939 "Vertical Color Bar Type 1",
940 "Vertical Color Bar Type 2",
941 "Vertical Color Bar Type 3",
942 "Vertical Color Bar Type 4"
945 /* Configurations for supported link frequencies */
946 #define OV13858_NUM_OF_LINK_FREQS 2
947 #define OV13858_LINK_FREQ_1080MBPS 1080000000
948 #define OV13858_LINK_FREQ_540MBPS 540000000
949 #define OV13858_LINK_FREQ_INDEX_0 0
950 #define OV13858_LINK_FREQ_INDEX_1 1
952 /* Menu items for LINK_FREQ V4L2 control */
953 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
954 OV13858_LINK_FREQ_1080MBPS,
955 OV13858_LINK_FREQ_540MBPS
958 /* Link frequency configs */
959 static const struct ov13858_link_freq_config
960 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
962 .pixel_rate = 864000000,
963 .pixels_per_line = OV13858_PPL_1080MHZ,
965 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
966 .regs = mipi_data_rate_1080mbps,
970 .pixel_rate = 432000000,
971 .pixels_per_line = OV13858_PPL_540MHZ,
973 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
974 .regs = mipi_data_rate_540mbps,
980 static const struct ov13858_mode supported_modes[] = {
984 .vts = OV13858_VTS_30FPS,
986 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
987 .regs = mode_4224x3136_regs,
989 .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
994 .vts = OV13858_VTS_30FPS,
996 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
997 .regs = mode_2112x1568_regs,
999 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1004 .vts = OV13858_VTS_30FPS,
1006 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1007 .regs = mode_2112x1188_regs,
1009 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1014 .vts = OV13858_VTS_30FPS,
1016 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1017 .regs = mode_1056x784_regs,
1019 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1024 struct v4l2_subdev sd;
1025 struct media_pad pad;
1027 struct v4l2_ctrl_handler ctrl_handler;
1029 struct v4l2_ctrl *link_freq;
1030 struct v4l2_ctrl *pixel_rate;
1031 struct v4l2_ctrl *vblank;
1032 struct v4l2_ctrl *hblank;
1033 struct v4l2_ctrl *exposure;
1036 const struct ov13858_mode *cur_mode;
1038 /* Mutex for serialized access */
1041 /* Streaming on/off */
1045 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
1047 /* Read registers up to 4 at a time */
1048 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 *val)
1050 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1051 struct i2c_msg msgs[2];
1055 u16 reg_addr_be = cpu_to_be16(reg);
1060 data_be_p = (u8 *)&data_be;
1061 /* Write register address */
1062 msgs[0].addr = client->addr;
1065 msgs[0].buf = (u8 *)®_addr_be;
1067 /* Read data from register */
1068 msgs[1].addr = client->addr;
1069 msgs[1].flags = I2C_M_RD;
1071 msgs[1].buf = &data_be_p[4 - len];
1073 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1074 if (ret != ARRAY_SIZE(msgs))
1077 *val = be32_to_cpu(data_be);
1082 /* Write registers up to 4 at a time */
1083 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 val)
1085 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1093 buf[1] = reg & 0xff;
1095 val = cpu_to_be32(val);
1101 buf[buf_i++] = val_p[val_i++];
1103 if (i2c_master_send(client, buf, len + 2) != len + 2)
1109 /* Write a list of registers */
1110 static int ov13858_write_regs(struct ov13858 *ov13858,
1111 const struct ov13858_reg *regs, u32 len)
1113 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1117 for (i = 0; i < len; i++) {
1118 ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1121 dev_err_ratelimited(
1123 "Failed to write reg 0x%4.4x. error = %d\n",
1124 regs[i].address, ret);
1133 static int ov13858_write_reg_list(struct ov13858 *ov13858,
1134 const struct ov13858_reg_list *r_list)
1136 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1139 /* Open sub-device */
1140 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1142 struct ov13858 *ov13858 = to_ov13858(sd);
1143 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
1147 mutex_lock(&ov13858->mutex);
1149 /* Initialize try_fmt */
1150 try_fmt->width = ov13858->cur_mode->width;
1151 try_fmt->height = ov13858->cur_mode->height;
1152 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1153 try_fmt->field = V4L2_FIELD_NONE;
1155 /* No crop or compose */
1156 mutex_unlock(&ov13858->mutex);
1161 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1169 ret = ov13858_read_reg(ov13858, OV13858_REG_DIGITAL_GAIN,
1170 OV13858_REG_VALUE_08BIT, &val);
1174 val &= OV13858_DGTL_GAIN_MASK;
1175 val |= (d_gain - 1) << OV13858_DGTL_GAIN_SHIFT;
1177 return ov13858_write_reg(ov13858, OV13858_REG_DIGITAL_GAIN,
1178 OV13858_REG_VALUE_08BIT, val);
1181 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1186 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1187 OV13858_REG_VALUE_08BIT, &val);
1192 val &= OV13858_TEST_PATTERN_MASK;
1193 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1195 val &= ~OV13858_TEST_PATTERN_ENABLE;
1198 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1199 OV13858_REG_VALUE_08BIT, val);
1202 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1204 struct ov13858 *ov13858 = container_of(ctrl->handler,
1205 struct ov13858, ctrl_handler);
1206 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1210 /* Propagate change of current control to all related controls */
1212 case V4L2_CID_VBLANK:
1213 /* Update max exposure while meeting expected vblanking */
1214 max = ov13858->cur_mode->height + ctrl->val - 8;
1215 __v4l2_ctrl_modify_range(ov13858->exposure,
1216 ov13858->exposure->minimum,
1217 max, ov13858->exposure->step, max);
1222 * Applying V4L2 control value only happens
1223 * when power is up for streaming
1225 if (pm_runtime_get_if_in_use(&client->dev) <= 0)
1230 case V4L2_CID_ANALOGUE_GAIN:
1231 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1232 OV13858_REG_VALUE_16BIT, ctrl->val);
1234 case V4L2_CID_DIGITAL_GAIN:
1235 ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1237 case V4L2_CID_EXPOSURE:
1238 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1239 OV13858_REG_VALUE_24BIT,
1242 case V4L2_CID_VBLANK:
1243 /* Update VTS that meets expected vertical blanking */
1244 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1245 OV13858_REG_VALUE_16BIT,
1246 ov13858->cur_mode->height
1249 case V4L2_CID_TEST_PATTERN:
1250 ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1253 dev_info(&client->dev,
1254 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1255 ctrl->id, ctrl->val);
1259 pm_runtime_put(&client->dev);
1264 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1265 .s_ctrl = ov13858_set_ctrl,
1268 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1269 struct v4l2_subdev_pad_config *cfg,
1270 struct v4l2_subdev_mbus_code_enum *code)
1272 /* Only one bayer order(GRBG) is supported */
1273 if (code->index > 0)
1276 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1281 static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1282 struct v4l2_subdev_pad_config *cfg,
1283 struct v4l2_subdev_frame_size_enum *fse)
1285 if (fse->index >= ARRAY_SIZE(supported_modes))
1288 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1291 fse->min_width = supported_modes[fse->index].width;
1292 fse->max_width = fse->min_width;
1293 fse->min_height = supported_modes[fse->index].height;
1294 fse->max_height = fse->min_height;
1299 static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1300 struct v4l2_subdev_format *fmt)
1302 fmt->format.width = mode->width;
1303 fmt->format.height = mode->height;
1304 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1305 fmt->format.field = V4L2_FIELD_NONE;
1308 static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1309 struct v4l2_subdev_pad_config *cfg,
1310 struct v4l2_subdev_format *fmt)
1312 struct v4l2_mbus_framefmt *framefmt;
1313 struct v4l2_subdev *sd = &ov13858->sd;
1315 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1316 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1317 fmt->format = *framefmt;
1319 ov13858_update_pad_format(ov13858->cur_mode, fmt);
1325 static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1326 struct v4l2_subdev_pad_config *cfg,
1327 struct v4l2_subdev_format *fmt)
1329 struct ov13858 *ov13858 = to_ov13858(sd);
1332 mutex_lock(&ov13858->mutex);
1333 ret = ov13858_do_get_pad_format(ov13858, cfg, fmt);
1334 mutex_unlock(&ov13858->mutex);
1340 * Calculate resolution distance
1343 ov13858_get_resolution_dist(const struct ov13858_mode *mode,
1344 struct v4l2_mbus_framefmt *framefmt)
1346 return abs(mode->width - framefmt->width) +
1347 abs(mode->height - framefmt->height);
1351 * Find the closest supported resolution to the requested resolution
1353 static const struct ov13858_mode *
1354 ov13858_find_best_fit(struct ov13858 *ov13858,
1355 struct v4l2_subdev_format *fmt)
1357 int i, dist, cur_best_fit = 0, cur_best_fit_dist = -1;
1358 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1360 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1361 dist = ov13858_get_resolution_dist(&supported_modes[i],
1363 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1364 cur_best_fit_dist = dist;
1369 return &supported_modes[cur_best_fit];
1373 ov13858_set_pad_format(struct v4l2_subdev *sd,
1374 struct v4l2_subdev_pad_config *cfg,
1375 struct v4l2_subdev_format *fmt)
1377 struct ov13858 *ov13858 = to_ov13858(sd);
1378 const struct ov13858_mode *mode;
1379 struct v4l2_mbus_framefmt *framefmt;
1382 mutex_lock(&ov13858->mutex);
1384 /* Only one raw bayer(GRBG) order is supported */
1385 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1386 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1388 mode = ov13858_find_best_fit(ov13858, fmt);
1389 ov13858_update_pad_format(mode, fmt);
1390 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1391 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1392 *framefmt = fmt->format;
1394 ov13858->cur_mode = mode;
1395 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1396 __v4l2_ctrl_s_ctrl_int64(
1397 ov13858->pixel_rate,
1398 link_freq_configs[mode->link_freq_index].pixel_rate);
1399 /* Update limits and set FPS to default */
1400 __v4l2_ctrl_modify_range(
1401 ov13858->vblank, OV13858_VBLANK_MIN,
1402 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1403 ov13858->cur_mode->vts - ov13858->cur_mode->height);
1405 link_freq_configs[mode->link_freq_index].pixels_per_line
1406 - ov13858->cur_mode->width;
1407 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1408 h_blank, 1, h_blank);
1411 mutex_unlock(&ov13858->mutex);
1416 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1418 *frames = OV13858_NUM_OF_SKIP_FRAMES;
1423 /* Start streaming */
1424 static int ov13858_start_streaming(struct ov13858 *ov13858)
1426 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1427 const struct ov13858_reg_list *reg_list;
1428 int ret, link_freq_index;
1430 /* Get out of from software reset */
1431 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1432 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1434 dev_err(&client->dev, "%s failed to set powerup registers\n",
1440 link_freq_index = ov13858->cur_mode->link_freq_index;
1441 reg_list = &link_freq_configs[link_freq_index].reg_list;
1442 ret = ov13858_write_reg_list(ov13858, reg_list);
1444 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1448 /* Apply default values of current mode */
1449 reg_list = &ov13858->cur_mode->reg_list;
1450 ret = ov13858_write_reg_list(ov13858, reg_list);
1452 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1456 /* Apply customized values from user */
1457 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1461 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1462 OV13858_REG_VALUE_08BIT,
1463 OV13858_MODE_STREAMING);
1466 /* Stop streaming */
1467 static int ov13858_stop_streaming(struct ov13858 *ov13858)
1469 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1470 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1473 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1475 struct ov13858 *ov13858 = to_ov13858(sd);
1476 struct i2c_client *client = v4l2_get_subdevdata(sd);
1479 mutex_lock(&ov13858->mutex);
1480 if (ov13858->streaming == enable) {
1481 mutex_unlock(&ov13858->mutex);
1486 ret = pm_runtime_get_sync(&client->dev);
1488 pm_runtime_put_noidle(&client->dev);
1493 * Apply default & customized values
1494 * and then start streaming.
1496 ret = ov13858_start_streaming(ov13858);
1500 ov13858_stop_streaming(ov13858);
1501 pm_runtime_put(&client->dev);
1504 ov13858->streaming = enable;
1505 mutex_unlock(&ov13858->mutex);
1510 pm_runtime_put(&client->dev);
1512 mutex_unlock(&ov13858->mutex);
1517 static int __maybe_unused ov13858_suspend(struct device *dev)
1519 struct i2c_client *client = to_i2c_client(dev);
1520 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1521 struct ov13858 *ov13858 = to_ov13858(sd);
1523 if (ov13858->streaming)
1524 ov13858_stop_streaming(ov13858);
1529 static int __maybe_unused ov13858_resume(struct device *dev)
1531 struct i2c_client *client = to_i2c_client(dev);
1532 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1533 struct ov13858 *ov13858 = to_ov13858(sd);
1536 if (ov13858->streaming) {
1537 ret = ov13858_start_streaming(ov13858);
1545 ov13858_stop_streaming(ov13858);
1546 ov13858->streaming = 0;
1550 /* Verify chip ID */
1551 static int ov13858_identify_module(struct ov13858 *ov13858)
1553 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1557 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1558 OV13858_REG_VALUE_24BIT, &val);
1562 if (val != OV13858_CHIP_ID) {
1563 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1564 OV13858_CHIP_ID, val);
1571 static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1572 .s_stream = ov13858_set_stream,
1575 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1576 .enum_mbus_code = ov13858_enum_mbus_code,
1577 .get_fmt = ov13858_get_pad_format,
1578 .set_fmt = ov13858_set_pad_format,
1579 .enum_frame_size = ov13858_enum_frame_size,
1582 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1583 .g_skip_frames = ov13858_get_skip_frames,
1586 static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1587 .video = &ov13858_video_ops,
1588 .pad = &ov13858_pad_ops,
1589 .sensor = &ov13858_sensor_ops,
1592 static const struct media_entity_operations ov13858_subdev_entity_ops = {
1593 .link_validate = v4l2_subdev_link_validate,
1596 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1597 .open = ov13858_open,
1600 /* Initialize control handlers */
1601 static int ov13858_init_controls(struct ov13858 *ov13858)
1603 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1604 struct v4l2_ctrl_handler *ctrl_hdlr;
1607 ctrl_hdlr = &ov13858->ctrl_handler;
1608 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
1612 mutex_init(&ov13858->mutex);
1613 ctrl_hdlr->lock = &ov13858->mutex;
1614 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1617 OV13858_NUM_OF_LINK_FREQS - 1,
1619 link_freq_menu_items);
1620 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1622 /* By default, PIXEL_RATE is read only */
1623 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1624 V4L2_CID_PIXEL_RATE, 0,
1625 link_freq_configs[0].pixel_rate, 1,
1626 link_freq_configs[0].pixel_rate);
1628 ov13858->vblank = v4l2_ctrl_new_std(
1629 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1631 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1632 ov13858->cur_mode->vts
1633 - ov13858->cur_mode->height);
1635 ov13858->hblank = v4l2_ctrl_new_std(
1636 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1637 OV13858_PPL_1080MHZ - ov13858->cur_mode->width,
1638 OV13858_PPL_1080MHZ - ov13858->cur_mode->width,
1640 OV13858_PPL_1080MHZ - ov13858->cur_mode->width);
1641 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1643 ov13858->exposure = v4l2_ctrl_new_std(
1644 ctrl_hdlr, &ov13858_ctrl_ops,
1645 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1646 OV13858_EXPOSURE_MAX, OV13858_EXPOSURE_STEP,
1647 OV13858_EXPOSURE_DEFAULT);
1649 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1650 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1651 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1654 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1655 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1656 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1658 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1659 V4L2_CID_TEST_PATTERN,
1660 ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1661 0, 0, ov13858_test_pattern_menu);
1662 if (ctrl_hdlr->error) {
1663 ret = ctrl_hdlr->error;
1664 dev_err(&client->dev, "%s control init failed (%d)\n",
1669 ov13858->sd.ctrl_handler = ctrl_hdlr;
1674 v4l2_ctrl_handler_free(ctrl_hdlr);
1675 mutex_destroy(&ov13858->mutex);
1680 static void ov13858_free_controls(struct ov13858 *ov13858)
1682 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1683 mutex_destroy(&ov13858->mutex);
1686 static int ov13858_probe(struct i2c_client *client,
1687 const struct i2c_device_id *devid)
1689 struct ov13858 *ov13858;
1693 device_property_read_u32(&client->dev, "clock-frequency", &val);
1694 if (val != 19200000)
1697 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1701 /* Initialize subdev */
1702 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1704 /* Check module identity */
1705 ret = ov13858_identify_module(ov13858);
1707 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1711 /* Set default mode to max resolution */
1712 ov13858->cur_mode = &supported_modes[0];
1714 ret = ov13858_init_controls(ov13858);
1718 /* Initialize subdev */
1719 ov13858->sd.internal_ops = &ov13858_internal_ops;
1720 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1721 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1722 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1724 /* Initialize source pad */
1725 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1726 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1728 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1729 goto error_handler_free;
1732 ret = v4l2_async_register_subdev(&ov13858->sd);
1734 goto error_media_entity;
1737 * Device is already turned on by i2c-core with ACPI domain PM.
1738 * Enable runtime PM and turn off the device.
1740 pm_runtime_get_noresume(&client->dev);
1741 pm_runtime_set_active(&client->dev);
1742 pm_runtime_enable(&client->dev);
1743 pm_runtime_put(&client->dev);
1748 media_entity_cleanup(&ov13858->sd.entity);
1751 ov13858_free_controls(ov13858);
1752 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1757 static int ov13858_remove(struct i2c_client *client)
1759 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1760 struct ov13858 *ov13858 = to_ov13858(sd);
1762 v4l2_async_unregister_subdev(sd);
1763 media_entity_cleanup(&sd->entity);
1764 ov13858_free_controls(ov13858);
1767 * Disable runtime PM but keep the device turned on.
1768 * i2c-core with ACPI domain PM will turn off the device.
1770 pm_runtime_get_sync(&client->dev);
1771 pm_runtime_disable(&client->dev);
1772 pm_runtime_set_suspended(&client->dev);
1773 pm_runtime_put_noidle(&client->dev);
1778 static const struct i2c_device_id ov13858_id_table[] = {
1783 MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1785 static const struct dev_pm_ops ov13858_pm_ops = {
1786 SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume)
1790 static const struct acpi_device_id ov13858_acpi_ids[] = {
1795 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1798 static struct i2c_driver ov13858_i2c_driver = {
1801 .owner = THIS_MODULE,
1802 .pm = &ov13858_pm_ops,
1803 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1805 .probe = ov13858_probe,
1806 .remove = ov13858_remove,
1807 .id_table = ov13858_id_table,
1810 module_i2c_driver(ov13858_i2c_driver);
1812 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1813 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
1814 MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>");
1815 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1816 MODULE_LICENSE("GPL v2");